08th week of 2014 patent applcation highlights part 13 |
Patent application number | Title | Published |
20140048814 | FILM SEMICONDUCTOR DEVICE, DISPLAY DEVICE USING SUCH THIN FILM SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A thin film semiconductor device formed as integrated circuits on an insulating substrate with bottom gate type thin film transistors stacked with gate electrodes, a gate insulating film and a semiconductor thin film in the order from below upward. The gate electrodes comprise metallic materials with thickness less than 100 nm. The gate insulating film has a thickness thicker than the gate electrodes. The semiconductor thin film comprises polycrystalline silicon crystallized by a laser beam. By reducing thickness of metallic gate electrodes, thermal capacity becomes small and difference in thermal condition on the metallic gate electrodes and on the insulating substrate made of glass or the like becomes small. This invention relates to the task of uniforming and optimizing recrystallization by a laser anneal treatment provided for the semiconductor thin film which works as an active layer of the bottom gate type thin film transistors. | 2014-02-20 |
20140048815 | SCHOTTKY BARRIER DIODE AND MANUFACTURING METHOD THEREOF - A Schottky barrier diode (SBD) is disclosed, which includes: a gallium nitride (GaN) layer, formed on a substrate; an aluminum gallium nitride (AlGaN), formed on the GaN layer; an insulation layer, formed on the AlGaN layer; an anode conducive layer, formed on the insulation layer, wherein Schottky contact is formed between a part of the anode conductive layer and the AlGaN layer or between a part of the anode conductive layer and the GaN layer, and another part of the anode conductive layer is separated from the AlGaN layer by the insulation layer; and a cathode conductive layer, formed on the AlGaN layer, wherein an ohmic contact is formed between the cathode conductive layer and the GaN layer or between the cathode conductive layer and the AlGaN layer, and wherein the anode conductive layer is not directly connected to the cathode conductive layer. | 2014-02-20 |
20140048816 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a metal substrate, a first semiconductor layer, a first semiconductor layer, a second semiconductor layer, a light emitting layer, a first intermediate layer and a second intermediate layer. The substrate has a coefficient of thermal expansion not more than 10×10 | 2014-02-20 |
20140048817 | LIGHT EMITTING DEVICE WITH IMPROVED EXTRACTION EFFICIENCY - In embodiments of the invention, a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown on a substrate. The substrate is a non-III-nitride material. The substrate has an in-plane lattice constant a | 2014-02-20 |
20140048818 | PHOTOELECTRIC CONVERSION ELEMENT, PHOTOELECTRIC CONVERSION SYSTEM, AND METHOD FOR PRODUCTION OF PHOTOELECTRIC CONVERSION ELEMENT - A photoelectric conversion element of an embodiment is a photoelectric conversion element which performs photoelectric conversion by receiving illumination light having n light emission peaks having a peak energy Ap (eV) (where 1≦p≦n and 2≦n) of 1.59≦Ap≦3.26 and a full width at half maximum Fp (eV) (where 1≦p≦n and 2≦n), wherein the photoelectric conversion element includes m photoelectric conversion layers having a band gap energy Bq (eV) (where 1≦q≦m and 2≦m≦n), and the m photoelectric conversion layers each satisfy the relationship of Ap−Fp2014-02-20 | |
20140048819 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - According to one embodiment, a semiconductor light-emitting device includes: a first conductivity type first semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in a (0001) surface; a second conductivity type second semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in the (0001) surface; a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, containing a nitride semiconductor crystal, and having an average lattice constant larger than the lattice constant of the first semiconductor layer; and a first stress application layer provided on a side opposite to the light emitting layer of the first semiconductor layer and applying a compressive stress to the first semiconductor layer. | 2014-02-20 |
20140048820 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light emitting device includes a first and second conductive semiconductor layers including an n-type dopant on active layer; a third and fourth conductive semiconductor layers including a p-type dopant under the active layer; wherein the first to fourth conductive semiconductor layers are formed of an AlGaN-based semiconductor, wherein the active layer includes a plurality of quantum barrier layers and a plurality of quantum well layers, wherein the plurality of quantum well layers include an InGaN semiconductor layer, wherein the plurality of quantum barrier layers include an AlGaN-based semiconductor layer, wherein at least two of the plurality barrier layers have a thickness of about 50 Å to about 300 Å, respectively, wherein a cycle of the quantum barrier layer and the quantum well layer includes a cycle of 2 to 10, wherein the second conductive semiconductor layer has a thickness thinner than a thickness of the third conductive semiconductor layer. | 2014-02-20 |
20140048821 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nitride semiconductor light-emitting device includes a nitride semiconductor light-emitting chip including an active layer for outputting polarized light, the active layer having a non-polar plane or a semi-polar plane as a growth plane; and a light-transmissive cover for transmitting light from the active layer. The light-transmissive cover includes a first light-transmissive member located in an area, among areas to the side of the nitride semiconductor light-emitting chip, and in a direction perpendicular to a polarization direction of the polarized light, and a second light-transmissive member located in an area above the nitride semiconductor light-emitting chip. The first light-transmissive member has a higher diffuse transmittance than the second light-transmissive member. | 2014-02-20 |
20140048822 | LIGHT EMITTING DIODES INCLUDING CURRENT SPREADING LAYER AND BARRIER SUBLAYERS - Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive stack including a current spreading layer, on the epitaxial region. A barrier layer is provided on the current spreading layer and extending on a sidewall of the current spreading layer. The multilayer conductive stack can also include an ohmic layer between the reflector and the epitaxial region. The barrier layer further extends on a sidewall of the ohmic layer. The barrier layer can also extend onto the epitaxial region outside the multilayer conductive stack. The barrier layer can be fabricated as a series of alternating first and second sublayers. | 2014-02-20 |
20140048823 | SEMICONDUCTOR STACKED BODY, METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR ELEMENT - A method for manufacturing a semiconductor stacked body, and a semiconductor element including the semiconductor stacked body includes a semiconductor stacked body, including a Ga | 2014-02-20 |
20140048824 | LIGHT-EMITTING DEVICE - A light-emitting device of an embodiment of the present application comprises optoelectronic units; a transparent structure having cavities configured to accommodate at least one of the optoelectronic units; and a conductive element connecting at least two of the optoelectronic units. | 2014-02-20 |
20140048825 | LIGHT-EMITTING DEVICE - This disclosure discloses a light-emitting display module display. The light-emitting display module comprises: a board; and a plurality of light-emitting diode modules arranged in an array configuration on the board; wherein one of the light-emitting diode modules comprises a plurality of encapsulated light-emitting units spaced apart from each other; and one of the encapsulated light-emitting units comprises a plurality of optoelectronic units, a first supporting, and a fence; and wherein the plurality of optoelectronic units are covered by the first supporting structure, and the fence surrounds the first supporting structure and the plurality of optoelectronic units. | 2014-02-20 |
20140048826 | ARRAY SUBSTRATE AND ITS MANUFACTURING METHOD - An array substrate comprises a substrate, a gate electrode, a source electrode and a drain electrode, the source electrode and the drain electrode being provided in different areas on the substrate and the vertical projections of the source electrode and the drain electrode on the substrate having an overlapping area; a semiconductor layer formed between the source electrode and the drain electrode, a vertical projection of the semiconductor layer on the substrate having overlapping areas with the vertical projections of the source electrode and the drain electrode on the substrate; a first insulating layer formed on the substrate while below the gate electrode and covering the source electrode or the drain electrode; a pixel electrode, a gate line, and a data line. A manufacturing method for the array substrate is also disclosed. | 2014-02-20 |
20140048827 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes: a semiconductor chip having a growth surface that is a nonpolar or semipolar plane, and emitting polarized light; and a reflector having a reflective surface. At least part of light in a plane L | 2014-02-20 |
20140048828 | LED DISPLAY PANEL AND LED DISPLAY APPARATUS - An LED display panel includes: a semiconductor wafer having a top surface; a plurality of LED elements disposed over the top surface of the semiconductor wafer, each of the LED elements having an electrode contact; and a plurality of driving circuits formed in the semiconductor wafer. Each of the driving circuits has an electrode-connecting contact that is disposed on the top surface of the semiconductor wafer and that is bonded to the electrode contact of a respective one of the LED elements. | 2014-02-20 |
20140048829 | LIGHT BLOCKING MEMBER AND DISPLAY PANEL INCLUDING THE SAME - A light blocking member including a metal particle and a ceramic material and a display device including the same. | 2014-02-20 |
20140048830 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A method of fabricating a light-emitting device comprising steps of: providing a substrate, an active layer, and a first semiconductor layer between the substrate and the active layer; removing part of the active layer; and forming a rough structure in the first semiconductor layer while keeping the active layer attached to the substrate. | 2014-02-20 |
20140048831 | GRADED FLUORESCENT MATERIAL - Some embodiments in the present disclosure generally relate to fluorescent structures such as fluorescent glass, fluorescent substrates, and/or light emitting devices, which can include a gradient of fluorescent molecules across the structure, substrate, and/or light emitting device. In some embodiments, the fluorescent glass, fluorescent substrates, and/or light emitting devices can be porous and include at least one fluorescent molecule within the one or more pore. In some embodiments, this can allow for the creation of a gradient fluorescent material throughout the material. | 2014-02-20 |
20140048832 | Micro-Bead Blasting Process for Removing a Silicone Flash Layer - Using compression molding to form lenses over LED arrays on a metal core printed circuit board leaves a flash layer of silicone covering the contact pads that are later required to connect the arrays to power. A method for removing the flash layer involves blasting particles of sodium bicarbonate at the flash layer. A nozzle is positioned within thirty millimeters of the top surface of the flash layer. The stream of air that exits from the nozzle is directed towards the top surface at an angle between five and thirty degrees away from normal to the top surface. The particles of sodium bicarbonate are added to the stream of air and then collide into the top surface of the silicone flash layer until the flash layer laterally above the contact pads is removed. The edge of silicone around the cleaned contact pad thereafter contains a trace amount of sodium bicarbonate. | 2014-02-20 |
20140048833 | LIGHT-EMITTING DEVICE WITH NARROW DOMINANT WAVELENGTH DISTRIBUTION AND METHOD OF MAKING THE SAME - This application discloses a light-emitting device with narrow dominant wavelength distribution and a method of making the same. The light-emitting device with narrow dominant wavelength distribution at least includes a substrate, a plurality of light-emitting stacked layers on the substrate, and a plurality of wavelength transforming layers on the light-emitting stacked layers, wherein the light-emitting stacked layer emits a first light with a first dominant wavelength variation; the wavelength transforming layer absorbs the first light and converts the first light into the second light with a second dominant wavelength variation; and the first dominant wavelength variation is larger than the second dominant wavelength variation. | 2014-02-20 |
20140048834 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE - A method for manufacturing a light emitting device that comprises a light emitting element and a phosphor layer to absorb at least a part of light emitted from the light emitting element to emit a light having a different wavelength from that of the absorbed light comprises a first resin layer forming step of forming a first resin layer with a first resin in which viscosity is adjusted to a first viscosity on a light emitting face of the light emitting element to define a predetermined shape of the phosphor layer; a second resin layer forming step of forming a second resin layer with a second resin containing a phosphor in which viscosity is adjusted to a second viscosity lower than the first viscosity on the first resin layer before curing the first resin layer; and a curing step of curing the first resin layer and the second resin layer. | 2014-02-20 |
20140048835 | REFLECTIVE DISPLAY DEVICES - A technique of producing a control component for a reflective display device, comprising: forming an array of electronic switching devices; forming over said array of electronic switching devices an insulator region defining a controlled surface topography; and forming on the patterned surface of the insulator region by a conformal deposition technique a substantially planar array of reflective pixel conductors each independently controllable via a respective one of the array of electronic switching devices, wherein each pixel conductor exhibits specular reflection at a range of reflection angles relative to the plane of the array of pixel conductors for a given incident angle relative to the plane of the array of pixel conductors. | 2014-02-20 |
20140048836 | LIGHTING EMITTING DEVICE WITH ALIGNED-BONDING AND THE MANUFACTURING METHOD THEREOF - A light-emitting device comprises a semiconductor light-emitting stacked layer having a first connecting surface, wherein the semiconductor light-emitting stacked layer comprises a first alignment pattern on the first connecting surface, and a substrate under the semiconductor light-emitting stacked layer, wherein the substrate has a second connecting surface being operable for connecting with the first connecting surface, wherein the substrate comprises a second alignment pattern on the second connecting surface, and the second alignment pattern is corresponding to the first alignment pattern. | 2014-02-20 |
20140048837 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display device includes a display panel, a driving circuit, and a connection terminal. The display panel includes a display area and a non-display area surrounding the display area and an electrode terminal disposed in the non-display area and extended in a direction. The driving circuit includes a signal terminal extended in the same direction as the electrode terminal and disposed adjacent to the electrode terminal. The connection terminal is disposed on the electrode terminal and the signal terminal to electrically connect the electrode terminal and the signal terminal. | 2014-02-20 |
20140048838 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND LIGHT EMITTING APPARATUS - A semiconductor light emitting device includes a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, a first internal electrode, a second internal electrode, an insulating part, and first and second pad electrodes. The active layer is disposed on a first portion of the first conductive semiconductor layer, and has the second conductive layer disposed thereon. The first internal electrode is disposed on a second portion of the first conductive semiconductor layer separate from the first portion. The second internal electrode is disposed on the second conductive semiconductor layer. The insulating part is disposed between the first and second internal electrodes, and the first and second pad electrodes are disposed on the insulating part to connect to a respective one of the first and second internal electrodes. | 2014-02-20 |
20140048839 | LIGHT EMITTING DEVICE - A light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer adjacent the active layer. A first electrode is electrically coupled to the first conductive semiconductor layer, and a second electrode is electrically coupled to the second conductive semiconductor layer. A channel layer is provided at a peripheral portion of a lower portion of the light emitting structure, and a conductive support member is provided adjacent to the second electrode. A first connection part is electrically coupled to the first electrode and the conductive support member, and a second connection part is electrically coupled to the second electrode. | 2014-02-20 |
20140048840 | LIGHT EMITTING DIODE AND LIGHT EMITTING DIODE PACKAGE - A light emitting diode includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on a substrate, and a first electrode connected to the first semiconductor layer. The first electrode includes an edge electrode including first and second edge portions opposite to each other, and a line electrode including first and second line portions respectively extending from the first and second edge portions. The edge electrode has a closed loop-shape. A distance between the first line portion and the second edge portion is equal to or less than a quarter of a length of the first line portion. A distance between the second line portion and the first edge portion is equal to or less than a quarter of a length of the second line portion. | 2014-02-20 |
20140048841 | POLYAMIDE COMPOSITION HAVING HIGH THERMAL CONDUCTIVITY - The present invention relates to a composition based on a polyamide matrix having a high thermal conductivity and comprising specific proportions of alumina and of graphite and also a flame-retardant system. This composition may in particular be used for producing components for lighting devices comprising light-emitting diodes. | 2014-02-20 |
20140048842 | LED LAMP AND MANUFACTURE METHOD THEREOF - An LED lamp comprises an LED light source ( | 2014-02-20 |
20140048843 | BOTH CARRIERS CONTROLLED THYRISTOR - The present invention relates to a technique of semiconductor devices, and provides a semiconductor device, which uses two controllable current sources to control the electron current and the hole current of the voltage-sustaining region of a thyristor under conduction state, making the sum of current between anode and cathode close to saturation under high voltage, thus avoiding the current crowding effect in local region and increasing the reliability of the device. Besides, it further provides a method of implementing the two current sources in the device and a method to improve the switching speed. | 2014-02-20 |
20140048844 | TRENCH GATE TYPE POWER SEMICONDUCTOR DEVICE - Disclosed herein is a trench gate type power semiconductor device including: a semiconductor substrate; a drift layer formed on the semiconductor substrate; a well layer formed on the drift layer; trenches formed to arrive at the drift layer while penetrating through the well layer in a thickness direction; first insulating films formed from bottom surfaces of the trenches up to a predetermined height; first electrodes formed at a height lower than that of the first insulating films in the trenches; interlayer dielectrics formed up to the same height as that of the first insulating films in the trenches; and a second electrode formed on the well layer, a portion of the first surface corresponding to the trenches being protruded into the trenches to contact the interlayer dielectrics. | 2014-02-20 |
20140048845 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a semiconductor device and a method for manufacturing the same, the semiconductor device including: trench gate electrodes formed in a semiconductor substrate; a gate insulating film covering an upper surface of the semiconductor substrate and lateral surfaces and lower surfaces of the trench gate electrodes; a base region formed between the trench gate electrodes; an emitter region formed between the trench gate electrodes and on the base region; interlayer insulating films formed on the trench gate electrodes and spaced apart from each other; an emitter metal layer formed on the interlayer insulating films and between the interlayer insulating films. | 2014-02-20 |
20140048846 | SELF ALIGNED TRENCH MOSFET WITH INTEGRATED DIODE - Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact. | 2014-02-20 |
20140048847 | DIODE, SEMICONDUCTOR DEVICE, AND MOSFET - Disclosed is a technique capable of reducing loss at the time of switching in a diode. A diode disclosed in the present specification includes a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, an anode region made of a second conductivity type semiconductor, an anode electrode made of metal, a barrier region formed between the drift region and the anode region and made of a first conductivity type semiconductor having a concentration higher than that of the drift region, and a pillar region formed so as to connect the barrier region to the anode electrode and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region. The pillar region and the anode are connected through a Schottky junction. | 2014-02-20 |
20140048848 | LAYERED SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING IT - A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant a | 2014-02-20 |
20140048849 | PACKAGE CONFIGURATIONS FOR LOW EMI CIRCUITS - An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion. | 2014-02-20 |
20140048850 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICE - According to example embodiments, a semiconductor device may include a high electron mobility transistor (HEMT) on a first region of a substrate, and a diode on a second region of the substrate. The HEMT may be electrically connected to the diode. The HEMT and the diode may be formed on an upper surface of the substrate such as to be spaced apart from each other in a horizontal direction. The HEMT may include a semiconductor layer. The diode may be formed on another portion of the substrate on which the semiconductor layer is not formed. The HEMT and the diode may be cascode-connected to each other. | 2014-02-20 |
20140048851 | SUBSTRATE COMPRISING SI-BASE AND INAS-LAYER - The present invention relates to a substrate ( | 2014-02-20 |
20140048852 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF THE SAME AND ELECTRONIC APPARATUS - Disclosed herein is a solid-state imaging device including: an opto-electrical conversion section provided inside a semiconductor substrate to receive incident light coming from one surface of the semiconductor substrate; a wiring layer provided on the other surface of the semiconductor substrate; and a light absorption layer provided between the other surface of the semiconductor substrate and the wiring layer to absorb transmitted light passing through the opto-electrical conversion section as part of the incident light. | 2014-02-20 |
20140048853 | Image Sensors - An image sensor includes a first substrate including a driving element, a first insulation layer on the first substrate and on the driving element, a second substrate including a photoelectric conversion element, and a second insulation layer on the second substrate and on the photoelectric conversion element. A surface of the second insulation layer is on an upper surface of the first insulation layer. The image sensor includes a conductive connector penetrating the second insulation layer and a portion of the first insulation layer. Methods of forming image sensors are also disclosed. | 2014-02-20 |
20140048854 | In-Cell Touch Panel - An embodiment of the disclosure discloses an in-cell touch panel having advantages such as a simple structure and a low cost. The in-cell touch panel comprises: a first substrate and a second substrate arranged oppositely, wherein a plurality of gate lines arranged horizontally are formed on the first substrate; the in-cell touch panel further comprises: a plurality of touch driving lines arranged horizontally; a plurality of touch sensing lines arranged vertically; and a plurality of touch scanning TFTs, wherein each touch scanning TFT has a gate connected to one gate line, a source connected to a touch driving circuit, and a drain connected to one touch driving line, the one gate line is only connected to the gate of one touch scanning TFT; wherein, the number of the gate lines≧the number of the touch scanning TFTs≧the number of the touch driving lines. | 2014-02-20 |
20140048855 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a substrate. A spacer is formed adjoining a sidewall of the gate stack. A recess is formed between the spacer and the substrate. Then, a strained feature is formed in the recess. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance. | 2014-02-20 |
20140048856 | SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS - A semiconductor device includes an active area defined by a device isolation layer and including a plurality of source/drain regions, a gate structure disposed on the active area and extending in a first direction, a stress layer contacting a side surface of each of the plurality of source/drain regions and a plurality of source/drain contacts disposed in the active area and connected to the plurality of source/drain regions. | 2014-02-20 |
20140048857 | BULK FIN-FIELD EFFECT TRANSISTORS WITH WELL DEFINED ISOLATION - A process fabricates a fin field-effect-transistor by implanting a dopant into an exposed portion of a semiconductor substrate within a cavity. The cavity is formed in a dielectric layer on the semiconductor substrate. The cavity exposes the portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate. A height of the cavity defines a height of the epitaxially grown semiconductor. | 2014-02-20 |
20140048858 | SEMICONDUCTOR DEVICE - A semiconductor device including a silicon substrate including a first region and a second region; a gate electrode above the first region and the second region; an insulation film extending from the gate electrode to the second region to cover part of the gate electrode and part of the second region; a source region and a drain region formed in the silicon substrate, silicide formed on the source region, on the drain region, and on the gate electrode; an interlayer insulation film formed above the gate electrode and the insulation film; a first electrically conductive via formed in the interlayer insulation film, a second electrically conductive via formed in the interlayer insulation, and a third electrically conductive via formed in the interlayer insulation and electrically connecting to the gate electrode; and at least one electrically conductive member formed on the insulation film in the interlayer insulation film. | 2014-02-20 |
20140048859 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - Disclosed is a semiconductor device including: a titanium nitride film formed over a semiconductor substrate and a tungsten film formed over the titanium nitride film. The titanium nitride film contains carbon and the tungsten film contains boron. A tungsten hexafluoride gas and a diborane gas are used in formation of the tungsten film. | 2014-02-20 |
20140048860 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR PILLAR - Disclosed herein is a device that includes: first to fourth conductive lines embedded in a semiconductor substrate; a first semiconductor pillar located between the first and second conductive lines; a second semiconductor pillar located between the second and third conductive lines; a third semiconductor pillar located between the third and fourth conductive lines; a first storage element connected to an upper portion of the first semiconductor pillar; a second storage element connected to an upper portion of the third semiconductor pillar; and a bit line embedded in the semiconductor substrate connected to lower portions of the first to third semiconductor pillars. At least one of the first and second conductive lines and at least one of the third and fourth conductive lines being supplied with a potential so as to form channels in the first and third semiconductor pillars. | 2014-02-20 |
20140048861 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity. | 2014-02-20 |
20140048862 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment, includes a first dielectric film, a floating gate, a second dielectric film, and a third dielectric film. The first dielectric film is formed above a semiconductor substrate. The floating gate is formed above the first dielectric film by using a silicon film. The third dielectric film is formed to cover an upper surface of the floating gate and a side face portion of the floating gate. The floating gate includes an impurity layer formed on an upper surface of the floating gate and a side face of the floating gate along an interface between the floating gate and the third dielectric film formed to cover the upper surface of the floating gate and a side face portion of the floating gate and containing at least one of carbon (C), nitrogen (N), and fluorine (F) as an impurity. | 2014-02-20 |
20140048863 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device including a first dielectric film, a floating gate portion, second and third dielectric films, a control gate portion, and a recess on the side face of the floating gate portion. The second dielectric film for element isolation is embedded between a height position of a lower portion of the side face of the floating gate portion and a height position inside the semiconductor substrate. The third dielectric film covers an upper surface and a side face portion of the floating gate portion up to a height position of an upper surface of the second dielectric film, and on the second dielectric film. A height position of an interface between the second and third dielectric films is between a height position of a center of the recess and a position in a predetermined range below the height position of the center of the recess. | 2014-02-20 |
20140048864 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - In accordance with an embodiment, a semiconductor memory device includes a substrate with a semiconductor layer and memory cells on the semiconductor layer. Each memory cell includes a laminated body on the semiconductor layer, a gate insulating film on the laminated body, and a control gate on the gate insulating film. The laminated body includes a tunnel insulating film and a floating gate subsequently laminated in a direction vertical to a front surface of the substrate for N (a natural number equal to or above 2) times. A dimension of a top face of any floating gate in a second or subsequent layer is smaller than a dimension of a bottom surface of the floating gate in the lowermost layer in at least one of a first direction parallel to the front surface of the substrate and a second direction crossing the first direction. | 2014-02-20 |
20140048865 | NOVEL COMPACT CHARGE TRAP MULTI-TIME PROGRAMMABLE MEMORY - A method for enabling fabrication of memory devices requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a charge-trapping spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack. | 2014-02-20 |
20140048866 | GATE STRUCTURE AND METHOD OF MANUFACTURING THEREOF - An improved gate structure is provided whereby the gate structure is defined by a trench, the trench having a first oxide layer and a second oxide layer. The invention also provides methods for fabricating the gate structure of the invention defined by a trench having a first oxide layer and a second oxide layer. | 2014-02-20 |
20140048867 | MULTI-TIME PROGRAMMABLE MEMORY - A device is disclosed. The device includes a substrate and a fin structure disposed on the substrate. The fin structure serves as a common body of n transistors. The transistors include separate charge storage layers and gate dielectric layers. The charge storage layers are disposed over a top surface of the fin structure and the gate dielectric layers are disposed on sidewalls of the fin structure. n=2 | 2014-02-20 |
20140048868 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME - A three-dimensional (3D) semiconductor memory device may include an electrode structure extending in a first direction and including insulating patterns and horizontal electrodes stacked on a substrate, a semiconductor pillar penetrating the electrode structure and connected to the substrate, a charge storage layer between the semiconductor pillar and the electrode structure, a tunnel insulating layer between the charge storage layer and the semiconductor pillar, and a blocking insulating layer between the charge storage layer and the electrode structure. A first horizontal electrode of the horizontal electrodes includes a gate electrode and a metal stopper between the gate electrode and the blocking insulating layer. | 2014-02-20 |
20140048869 | TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. | 2014-02-20 |
20140048870 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a trench defined by etching a semiconductor substrate including a device isolation film and an active region, an active region protruded from a side and bottom of the trench, and a gate electrode surrounding the active region simultaneously while being buried in the trench. | 2014-02-20 |
20140048871 | Trench Connection Between a Transistor and a Further Component - A semiconductor component arrangement includes a semiconductor body, a transistor structure, a further component, and at least a first electrode structure. The semiconductor body has a first side and a second side. The transistor structure is integrated in the semiconductor body, and includes a source and a drain. The further component is also integrated in the semiconductor body. The first electrode structure is disposed in at least a first trench, and includes at least one electrode. The first electrode structure electrically connects at least one of the source and the drain to the further component. | 2014-02-20 |
20140048872 | AVALANCHE CAPABILITY IMPROVEMENT IN POWER SEMICONDUCTOR DEVICES USING THREE MASKS PROCESS - A power semiconductor device with improved avalanche capability is disclosed by forming at least one avalanche capability enhancement doped region underneath an ohmic contact doped region. Moreover, a source mask is saved by using three masks process and the avalanche capability is further improved. | 2014-02-20 |
20140048873 | SEMICONDUCTOR DEVICES - A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively. | 2014-02-20 |
20140048874 | MOS WITH RECESSED LIGHTLY-DOPED DRAIN - LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches. | 2014-02-20 |
20140048875 | Asymmetrical Gate MOS Device and Method of Making - An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented. | 2014-02-20 |
20140048876 | SEMICONDUCTOR DEVICE INCLUDING A HIGH BREAKDOWN VOLTAGE DMOS AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a high breakdown voltage DMOS transistor formed on a first conductivity type semiconductor substrate. The semiconductor device includes: a DMOS second conductivity type well; a DMOS first conductivity body region; a DMOS second conductivity type source region; a DMOS second conductivity type drain region; a LOCOS oxide film formed between the DMOS second conductivity type drain region and the DMOS first conductivity type body region; and a DMOS gate insulating film formed in succession to the LOCOS oxide film to cover a DMOS channel region between the DMOS second conductivity type source region and the DMOS second conductivity type well, wherein the DMOS gate insulating film includes a first insulating film which is disposed outside the DMOS channel region and a second insulating film which is disposed in the DMOS channel region and is thinner than the first insulating film. | 2014-02-20 |
20140048877 | LATERAL DIFFUSION METAL OXIDE SEMICONDUCTOR TRANSISTOR STRUCTURE - A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source. | 2014-02-20 |
20140048878 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a P+ substrate; a P− epitaxial layer over the P+ substrate; a P-well and an N− drift region in the P− epitaxial layer and laterally adjacent to each other; an N+ source region in the P-well and connected to a front-side metal via a first contact electrode; an N+ drain region in the N− drift region and connected to the front-side metal via a second contact electrode; a gate structure on the P− epitaxial layer and connected to the front-side metal via a third contact electrode; and a metal plug through the P− epitaxial layer and having one end in contact with the P+ substrate and the other end connected to the front-side metal, the metal plug being adjacent to one side of the N+ source region that is farther from the N− drift region. A method for fabricating the semiconductor device is also disclosed. | 2014-02-20 |
20140048879 | LDMOS DEVICE WITH STEP-LIKE DRIFT REGION AND FABRICATION METHOD THEREOF - An LDMOS device is disclosed. The LDMOS device includes: a substrate having a first type of conductivity; a drift region having a second type of conductivity and a doped region having the first type of conductivity both formed in the substrate; a drain region having the second type of conductivity and being formed in the drift region, the drain region being located at an end of the drift region farther from the doped region; and a buried layer having the first type of conductivity and being formed in the drift region, the buried layer being in close proximity to the drain region and having a step-like bottom surface, and wherein a depth of the buried layer decreases progressively in a direction from the drain region to the doped region. A method of fabricating LDMOS device is also disclosed. | 2014-02-20 |
20140048880 | LDMOS WITH ACCUMULATION ENHANCEMENT IMPLANT - A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor device includes an enhancement implant region formed in a portion of an accumulation region proximate a P-N junction between body and drift drain regions. The enhancement implant region contains additional dopants of the same conductivity type as the drift drain region. There is a gap between the enhancement implant region and the P-N junction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2014-02-20 |
20140048881 | Method of Manufacturing a Body-Contacted SOI FINFET - A semiconductor structure including a body-contacted finFET device and methods form manufacturing the same. The method may include forming one or more semiconductor fins on a SOI substrate, forming a semiconductive body contact region connected to the bottom of the fin(s) in the buried insulator region, forming a sacrificial gate structure over the body region of the fin(s), forming a source region on one end of the fin(s), forming a drain region on the opposite end of the fin(s), replacing the sacrificial gate structure with a metal gate, and forming electrical contacts to the source, drain, metal gate, and body contact region. The method may further include forming a body contact fin contemporaneously with the finFET fins that is in contact with the body contact region, through which electrical contact to the body contact region is made. | 2014-02-20 |
20140048882 | TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES - In one aspect, a CMOS device is provided. The CMOS device includes a SOI wafer having a SOI layer over a BOX; one or more active areas formed in the SOI layer in which one or more FET devices are formed, each of the FET devices having an interfacial oxide on the SOI layer and a gate stack on the interfacial oxide layer, the gate stack having (i) a conformal gate dielectric layer present on a top and sides of the gate stack, (ii) a conformal gate metal layer lining the gate dielectric layer, and (iii) a conformal workfunction setting metal layer lining the conformal gate metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer present in the gate stack are/is proportional to a length of the gate stack. | 2014-02-20 |
20140048883 | THIN-FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - The organic thin-film transistor according to the present invention includes: a gate electrode line on a substrate in a first region: a first signal line layer in a second region; a gate insulating film covering the gate electrode line and the first signal line layer; bank layers on the gate insulating film; a second signal line layer on the bank layer over the first signal line; a drain electrode and a source electrode line which are located on the bank layers and in at least one opening between the bank layers in the first region; a semiconductor layer located at least in the opening and banked up by the bank layers, the drain electrode, and the source electrode line; and a protection film covering the semiconductor layer. | 2014-02-20 |
20140048884 | DISPOSABLE CARBON-BASED TEMPLATE LAYER FOR FORMATION OF BORDERLESS CONTACT STRUCTURES - After formation of gate stacks, a carbon-based template layer is deposited over the gate stacks, and is optionally planarized to provide a planar top surface. A hard mask layer and a photoresist layer are subsequently formed above the carbon-based template layer. A pattern including openings is formed within the photoresist layer. The pattern is subsequently transferred through the hard mask layer and the carbon-based template layer with high selectivity to gate spacers to form self-aligned cavities within the carbon-based template layer. Contact structures are formed within the carbon-based template layer by a damascene method. The hard mask layer and the carbon-based template layer are subsequently removed selective to the contact structures. The contact structures can be formed as contact bar structures or contact via structures. Optionally, a contact-level dielectric layer can be subsequently deposited. | 2014-02-20 |
20140048885 | DUAL WORKFUNCTION SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THEREOF - Embodiments of the invention provide dual workfunction semiconductor devices and methods for manufacturing thereof. According to one embodiment, the method includes providing a substrate containing first and second device regions, depositing a dielectric film on the substrate, and forming a first metal-containing gate electrode film on the dielectric film, wherein a thickness of the first metal-containing gate electrode film is less over the first device region than over the second device region. The method further includes depositing a second metal-containing gate electrode film on the first metal-containing gate electrode film, patterning the second metal-containing gate electrode film, the first metal-containing gate electrode film, and the dielectric film to form a first gate stack above the first device region and a second gate stack above the second device region. | 2014-02-20 |
20140048886 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of the gate stack, forming a stress film over the substrate, performing a process to form a dislocation with a pinchoff point in the substrate, removing at least a portion of the dislocation to form a recess cavity with a tip in the substrate, and forming a source/drain feature in the recess cavity. | 2014-02-20 |
20140048887 | INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY - An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; an n-well formed on the substrate; a p-well formed on the substrate; and a p-tap formed in the p-well adjacent to the n-well, wherein the p-tap extends between circuit elements formed in the n-well and circuit elements formed in the p-well, and is coupled to a ground potential. A method of forming an integrated circuit having improved radiation immunity is also described. | 2014-02-20 |
20140048888 | Strained Structure of a Semiconductor Device - A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region. | 2014-02-20 |
20140048889 | Layout Circuit Optimization For Deep Submicron Technologies - An integrated circuit is disclosed that has substantially continuous active diffusion regions within its diffusion layers. Active regions of semiconductor devices can be fabricated using portions of these substantially continuous active diffusion regions. Stress can be applied to these semiconductor devices during their fabrication which leads to substantially uniform stress patterns throughout the integrated circuit. The substantially uniform stress patterns can significantly improve performance of the integrated circuit. | 2014-02-20 |
20140048890 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and isolation regions are alternately defined, and a support region is defined in a direction crossing the active regions and the isolation regions, first trenches formed in the isolation regions, second trenches formed under the first trenches in the active regions and the isolation regions; and a support layer formed under the first trenches in the support region. | 2014-02-20 |
20140048891 | PMOS TRANSISTORS AND FABRICATION METHOD - A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate, and forming a dummy gate structure at least having a dummy gate, a high-K dielectric layer, and a sidewall spacer surrounding the high-K dielectric layer and the dummy gate on the semiconductor substrate. The method also includes forming a source region and a drain region in the semiconductor substrate at both sides of the dummy gate structure by an ion implantation process, and performing a first annealing process to enhance the ion diffusion. Further, the method includes forming an interlayer dielectric layer leveling with the surface of the dummy gate, and forming a trench by removing the dummy gate. Further, the method also includes performing a second annealing process, and forming a metal gate in the trench. | 2014-02-20 |
20140048892 | SELF ALIGNED MOS STRUCTURE WITH POLYSILICON CONTACT - An integrated circuit structure has a substrate comprising a well region and a surface region, an isolation region within the well region, a gate insulating layer overlying the surface region, first and second source/drain regions within the well region of the substrate. The structure also has a channel region formed between the first and second source/drain regions and within a vicinity of the gate insulating layer, and a gate layer overlying the gate insulating layer and coupled to the channel region. The structure has sidewall spacers on edges of the gate layer to isolate the gate layer, a local interconnect layer overlying the surface region of the substrate and having an edge region extending within a vicinity of the first source/drain region. A contact layer on the first source/drain region in contact with the edge region and has a portion abutting a portion of the sidewall spacers. | 2014-02-20 |
20140048893 | MAGNETORESISTIVE RANDOM ACCESS MEMORY CELL AND FABRICATING THE SAME - The present disclosure provides a semiconductor memory device. The device includes a pinning layer having an anti-ferromagnetic material and disposed over a first electrode; a pinned layer disposed over the pinning layer; a tunneling layer disposed over the pinned layer, a free layer disposed over the tunneling layer and a capping layer disposed over the free layer. The capping layer includes metal-oxide and metal-nitride materials. | 2014-02-20 |
20140048894 | MTP MTJ DEVICE - Systems and methods for multiple-time programmable (MTP) devices. An MTP device includes a magnetic tunnel junction (MTJ) device programmable to a plurality of states based on voltage applied across the MTJ device. The plurality of states include a first resistance state corresponding to a first binary value stored in the MTJ device based on a first voltage, a second resistance state corresponding to a second binary value stored in the MTJ device based on a second voltage, a third resistance state corresponding to a breakdown of a barrier layer of the MTJ device based on a third voltage, and a fourth resistance state corresponding to an open fuse based on a fourth voltage. | 2014-02-20 |
20140048895 | Magnetic Tunnel Junction Device - A magnetic tunnel junction (MTJ) device includes a reference layer having a surface, a tunnel insulating layer formed over the surface of the reference layer, and a free layer formed over the tunnel insulating layer. A magnetization direction in each of the reference layer and the free layer is substantially perpendicular to the surface. A dimension of the reference layer in a horizontal direction substantially parallel to the surface is larger than a dimension of the free layer in the horizontal direction. | 2014-02-20 |
20140048896 | Magnetic Tunnel Junction Device And Method Of Making Same - A magnetic tunnel junction (MTJ) device includes a reference layer having a surface, a tunnel insulating layer formed over the surface of the reference layer, a free layer formed over the tunnel insulating layer, and a magnetic field providing layer formed over the free layer. A magnetization direction in each of the reference layer and the free layer is substantially perpendicular to the surface. The magnetic field providing layer is configured to provide a lateral magnetic field in the free layer, the lateral magnetic field being substantially parallel to the surface. | 2014-02-20 |
20140048897 | PIXEL WITH NEGATIVELY-CHARGED SHALLOW TRENCH ISOLATION (STI) LINER - Embodiments of a pixel including a substrate having a front surface and a photosensitive region formed in or near the front surface of the substrate. An isolation trench is formed in the front surface of the substrate adjacent to the photosensitive region. The isolation trench includes a trench having a bottom and sidewalls, a passivation layer formed on the bottom and the sidewalls, and a filler to fill the portion of the trench not filled by the passivation layer. | 2014-02-20 |
20140048898 | BACKSIDE ILLUMINATED CMOS IMAGE SENSOR - A backside illuminated (BSI) CMOS image sensor is disclosed. The BSI CMOS image sensor includes: a substrate having a front side and a back side, the substrate including a photodiode formed therein, the photodiode being proximate the back side of the substrate; a metal shielding layer covering the back side of the substrate, the metal shielding layer including an opening formed therein, the opening being arranged in correspondence with the photodiode; and a light-absorbing layer formed on each side face of the opening. The light-absorbing layer coated on the side faces of the opening prevents the occurrence of photon cross-talk and hence improves imaging quality of the BSI CMOS image sensor. | 2014-02-20 |
20140048899 | LOW DAMAGE LASER-TEXTURED DEVICES AND ASSOCIATED METHODS - Methods for laser processing semiconductor materials for use in optoelectronic and other devices, including materials, devices, and systems associated therewith are provided. In one aspect, a method of minimizing laser-induced material damage while laser-texturing a semiconductor material can include delivering short pulse duration laser radiation to a target region of a semiconductor material to form a textured region having a reorganized surface layer, wherein the laser radiation has a wavelength from about 200 nm to about 600 nm and a pulse duration of from about 10 femtoseconds to about 400 picoseconds, and wherein defect density of the semiconductor material from beneath the reorganized surface layer up to a depth of about 1 micron is less than or equal to about 10 | 2014-02-20 |
20140048900 | INTEGRATED CIRCUIT COMBINATION OF A TARGET INTEGRATED CIRCUIT, PHOTOVOLTAIC CELLS AND LIGHT SENSITIVE DIODES CONNECTED TO ENABLE A SELF-SUFFICIENT LIGHT DETECTOR DEVICE - An integrated circuit (IC) comprises a plurality of photovoltaic (PV) cells formed over a passivation layer of a target integrated circuit (TIC), wherein at least one PV cell of the plurality of PV cells is usable as a light sensing device; an interface to an energy storage unit; the TIC comprising at least: a control unit; and a switching circuit, the switching circuit coupled to the plurality of PV cells, the energy storage, and the control unit; wherein the control unit is configured to control at least the switching circuit to configure a connection scheme, wherein the connection scheme devises at least one first PV cell of the plurality of PV cells to connect to the energy storage and at least one second PV cell to connect to the control unit for light detection. | 2014-02-20 |
20140048901 | RECTIFIER OF ALTERNATING-CURRENT GENERATOR FOR VEHICLE - In a rectifier device ( | 2014-02-20 |
20140048902 | METHOD OF FABRICATING A GALLIUM NITRIDE MERGED P-I-N SCHOTTKY (MPS) DIODE BY REGROWTH AND ETCH BACK - An MPS diode includes a III-nitride substrate characterized by a first conductivity type and a first dopant concentration and having a first side and a second side. The MPS diode also includes a III-nitride epitaxial structure comprising a first III-nitride epitaxial layer coupled to the first side of the substrate, wherein a region of the first III-nitride epitaxial layer comprises an array of protrusions. The III-nitride epitaxial structure also includes a plurality of III-nitride regions of a second conductivity type, each partially disposed between adjacent protrusions. Each of the plurality of III-nitride regions of the second conductivity type comprises a first section laterally positioned between adjacent protrusions and a second section extending in a direction normal to the first side of the substrate. The MPS diode further includes a first metallic structure electrically coupled to one or more of the protrusions and to one or more of the second sections. | 2014-02-20 |
20140048903 | METHOD AND SYSTEM FOR EDGE TERMINATION IN GAN MATERIALS BY SELECTIVE AREA IMPLANTATION DOPING - A method for fabricating edge termination structures in gallium nitride (GaN) materials includes providing an n-type GaN substrate having a first surface and a second surface, forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate, and forming one or more p-type regions in the n-type GaN epitaxial layer by using a first ion implantation. At least one of the one or more p-type regions includes an edge termination structure. | 2014-02-20 |
20140048904 | Semiconductor Device, Integrated Circuit and Manufacturing Method Thereof - One embodiment of a semiconductor device includes a semiconductor body with a first side and a second side opposite to the first side. The semiconductor device further includes a first contact trench extending into the semiconductor body at the first side. The first contact trench includes a first conductive material electrically coupled to the semiconductor body adjoining the first contact trench. The semiconductor further includes a second contact trench extending into the semiconductor body at the second side. The second contact trench includes a second conductive material electrically coupled to the semiconductor body adjoining the second contact trench. | 2014-02-20 |
20140048905 | LOW COST ANTI-FUSE STRUCTURE - An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure. | 2014-02-20 |
20140048906 | Semiconductor Device and Method of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units - A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters. | 2014-02-20 |
20140048907 | POWER TSVS OF SEMICONDUCTOR DEVICE - A semiconductor device including power TSVs for stably supplying a power source is described. A semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (TSVs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power TSVs. | 2014-02-20 |
20140048908 | SEMICONDUCTOR SUBSTRATE ASSEMBLY - A semiconductor substrate assembly is proposed. The semiconductor interposer comprises a substrate having a first surface and a second surface opposite to the first surface, a first conductive pad, a second conductive pad and a conductive pillar. The first conductive pad is formed at a predetermined location of the first surface of the substrate. The second conductive pad is formed at a predetermined location of the second surface of the substrate as compared with the position of the first conductive pad. The conductive pillar is formed in the substrate and contacts with one of the first conductive pad and the second conductive pad. | 2014-02-20 |
20140048909 | COMPLIANT BIPOLAR MICRO DEVICE TRANSFER HEAD - A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes. | 2014-02-20 |
20140048910 | SUBSTRATE STRUCTURE AND METHOD FOR MANUFACTURING SAME - Provided is a substrate structure, including: a first substrate and a second substrate arranged correspondingly. A first surface of the first substrate faces a second surface of the second substrate, wherein the first surface is successively arranged with a conductor interconnection layer and a bonding layer, with the bonding layer connecting the first substrate and the conductor interconnection layer to the second substrate. The substrate structure and a method for manufacturing the same. The second substrate can serve as a support substrate and the first substrate as a substrate for directly manufacturing a device. However, the first substrate is formed by the growth of a crystal without the problem of thickness and stress thereof, thereby avoiding unnecessary stress and further improving the performance of the device formed in the first substrate. | 2014-02-20 |
20140048911 | LATERAL SEMICONDUCTOR DEVICE - A lateral semiconductor device includes a semiconductor layer, an insulating layer, and a resistive field plate. The semiconductor layer includes a first semiconductor region and a second semiconductor region at a surface portion, and the second semiconductor region makes a circuit around the first semiconductor region. The insulating layer is formed on a surface of the semiconductor layer and is disposed between the first and second semiconductor regions. The resistive field plate is formed on a surface of the insulating layer. Between the first and second semiconductor regions, a first section and a second section are adjacent to each other along a circumferential direction around the first semiconductor region. The resistive field plate includes first and second resistive field plate sections respectively formed in the first and second sections, and the first and second resistive field plate sections are separated from each other. | 2014-02-20 |
20140048912 | COMPRESSIVE STRESS TRANSFER IN AN INTERLAYER DIELECTRIC OF A SEMICONDUCTOR DEVICE BY PROVIDING A BI-LAYER OF SUPERIOR ADHESION AND INTERNAL STRESS - The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer. | 2014-02-20 |
20140048913 | ELECTRONIC DEVICES INCLUDING EMI SHIELD STRUCTURES FOR SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - An electronic apparatus includes a main board, a semiconductor package, an upper conductive EMI shield member, and a lower conductive EMI shield member. The main board includes a first ground pad. The semiconductor package is spaced apart from and electrically connected to the main board. The upper conductive EMI shield member covers a top surface and a sidewall of the semiconductor package. The lower conductive EMI shield member surrounds a space between the main board and the semiconductor package, and is electrically connected to the upper conductive EMI shield member and the first ground pad. | 2014-02-20 |