08th week of 2009 patent applcation highlights part 50 |
Patent application number | Title | Published |
20090049215 | NETWORK UNIT AND PROGRAMMABLE CONTROLLER USING THE SAME - A network unit in a programmable controller of a building block mutually connects an information system network and a control system network. The network unit includes transfer analyzing units that judge to which of interface units received data received from the information system network and the control system network should be allocated. Moreover, received data that needs to be transferred is converted into predetermined data by conversion processing units included in the networks and output to the information system network or the control system network without being transmitted to a system bus. | 2009-02-19 |
20090049216 | Dynamically allocating lanes to a plurality of PCI express connectors - Method, apparatus, and computer program products for dynamically allocating lanes to a plurality of PCI Express connectors are disclosed that include identifying whether a PCI Express device is installed into each PCI Express connector, and assigning a portion of the lanes to each PCI Express connector having a PCI Express device installed into the PCI Express connector. Dynamically allocating lanes to a plurality of PCI Express connectors may also include identifying a device type for each PCI Express device installed into the plurality of PCI Express connectors. Dynamically allocating lanes to a plurality of PCI Express connectors may also include creating allocation rules that specify the allocation of lanes to the plurality of PCI Express connectors. Dynamically allocating lanes to a plurality of PCI Express connectors may also include receiving user allocation preferences that specify the allocation of lanes to the plurality of PCI Express connectors. | 2009-02-19 |
20090049217 | I/O-REQUEST PROCESSING SYSTEM AND METHOD - An I/O-request processing system which is capable of reducing the maximum value of the time required until the I/O request of each external device is registered. An I/O-request receiving section ( | 2009-02-19 |
20090049218 | RETRIEVING LOCK ATTENTION DATA - Provided are techniques for retrieving lock attention data. A group of attention connection paths configured to transmit lock attention interrupts and lock attention data between the host and the control unit are identified. A lock attention interrupt is received from the control unit. In response to receiving the lock attention interrupt, a connection path from the group of attention connection paths is selected and lock attention data is retrieved from the control unit using the selected connection path | 2009-02-19 |
20090049219 | INFORMATION PROCESSING APPARATUS AND EXCEPTION CONTROL CIRCUIT - To provide an information processing apparatus capable of performing switching between an exception handler and normal processing, the information processing apparatus comprising: An information processing apparatus comprising: a processor; a data processing unit operable to perform particular processing upon receiving a processing request from the processor; an interrupt controller operable to issue an interrupt request to the processor; and an exception control unit operable to control the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line, the data processing unit includes a notification unit operable to notify, via the dedicated line, the exception control unit of status information showing a current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor. | 2009-02-19 |
20090049220 | INTERRUPT-RELATED CIRCUITS, SYSTEMS, AND PROCESSES - An electronic interrupt circuit includes an interrupt-related input line ( | 2009-02-19 |
20090049221 | SYSTEM AND METHOD OF OBTAINING ERROR DATA WITHIN AN INFORMATION HANDLING SYSTEM - A system and method of obtaining error data within an information handling system is disclosed. According to one aspect, an interrupt handling system can include a first system management interrupt handler operable to initiate access to a first interrupt event message. The interrupt handling system can also include a first resource operable to generate the first interrupt event message. In one form, the first interrupt event message can identify a first interrupt event occurrence detectable by the first system management interrupt handler. The interrupt handling system can further include a memory including a first allocated memory location configured to store the first interrupt event message using the first system management interrupt handler. In one form, the first system management interrupt handler can be responsive to a second system management interrupt handler request to read the first interrupt event message. | 2009-02-19 |
20090049222 | PCI Express-Compatible Controller And Interface For Flash Memory - A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation. | 2009-02-19 |
20090049223 | INTERFACE WITH MULTIPLE PACKET PREEMPTION BASED ON START INDICATORS OF DIFFERENT TYPES - Preemption techniques are disclosed which permit multiple high-priority packets to preempt a single low-priority packet. In one aspect, a first device is configured for communication with a second device via an interface bus. The first device comprises interface circuitry configured to receive from the second device a start indicator of a first type and a start indicator of a second type, and to allow at least one data segment associated with the start indicator of the second type to preempt at least one data segment associated with the start indicator of the first type. The start indicator of the second type may have a longer pulse width than that of the start indicator of the first type, such as a double-length pulse width. The first and second devices may comprise physical layer and link layer devices of a communication system. | 2009-02-19 |
20090049224 | System and Method for Distributed Partitioned Library Mapping - Embodiments of the present invention provide a system and method of media library access that eliminates, or at least substantially reduces, the shortcomings of prior art media library access systems and methods. More particularly, embodiments of the present invention provide systems and methods of distributed mapping of media library partitions. According to one embodiment, the present invention can include a first controller connected to a data transport element of a media library and a second controller connected to a media changer of the media library. The first controller can maintain a media library partition representing a portion of the media library, receive a command from a host application based on the media library partition and forward the command to the second controller. The first controller can further translate logical addresses referenced in the command to physical addresses before forwarding the command to the second controller. The second controller can receive the command from the first controller and forward the command to the media changer. The second controller, according to another embodiment of the present invention, can also prioritize the command on a FIFO basis or according to other prioritization scheme known in the art. | 2009-02-19 |
20090049225 | Information processing apparatus, information processing method, program for executing the information processing method, storage medium storing the program, DMA controller, DMA transfer method, program for executing the DMA transfer method, and storage medium storing the program - Disclosed herein is an information processing apparatus that transfers information, using direct memory access (DMA), between a first storage section in an information processing system and a second storage section in an information transfer system. The information processing system includes the first storage section for storing the information, and a control section. The information transfer system includes: the second storage section for storing descriptor information indicating the location at which the information is stored in the first storage section and the size of the information; and a DMA transfer section for DMA transferring the information between the first storage section and the second storage section based on the descriptor information. The DMA transfer section DMA transfers the descriptor information concerning the DMA transferred information from the second storage section to the first storage section. The control section loads the descriptor information from the first storage section. | 2009-02-19 |
20090049226 | STALE TRACK INITIALIZATION IN A STORAGE CONTROLLER - Deleting a data volume from a storage system and freeing its storage space to make it available to be allocated to a new volume is accomplished by only zeroing associated metadata for the tracks contained in the freed storage space which is then reused in a new volume allocation and an attempt is made by the new volume to read a first record R | 2009-02-19 |
20090049227 | AVOIDING FAILURE OF AN INITIAL PROGRAM LOAD IN A LOGICAL PARTITION OF A DATA STORAGE SYSTEM - An initial program load (IPL) of a logical partition (LPAR) is managed by establishing a logical path to the LPAR from a storage controller. When a notice is received by the storage controller from the LPAR that the IPL has commenced, the LPAR address is stored in a data structure. After the storage controller initiates a pack change state interrupt, the stored address is compared with the addresses in a list of all LPARS to which the interrupt is directed. If the list of addresses includes the stored address, the stored address is removed from the list. Thus, the pack change state interrupt is transmitted only to the addresses in the list, leaving the LPAR to complete the IPL without interruption. After the storage controller receives a notice from the LPAR that the IPL has completed, the address of the LPAR is removed from the data structure. | 2009-02-19 |
20090049228 | AVOIDING FAILURE OF AN INITIAL PROGRAM LOAD IN A LOGICAL PARTITION OF A DATA STORAGE SYSTEM - An initial program load (IPL) of a logical partition (LPAR) is managed by establishing a logical path to the LPAR from a storage controller. When a notice is received by the storage controller from the LPAR that the IPL has commenced, the LPAR address is stored in a data structure. After the storage controller initiates a pack change state interrupt, the stored address is compared with the addresses in a list of all LPARS to which the interrupt is directed. If the list of addresses includes the stored address, the stored address is removed from the list. Thus, the pack change state interrupt is transmitted only to the addresses in the list, leaving the LPAR to complete the IPL without interruption. After the storage controller receives a notice from the LPAR that the IPL has completed, the address of the LPAR is removed from the data structure. | 2009-02-19 |
20090049229 | NONVOLATILE MEMORY DEVICE, METHOD OF WRITING DATA,AND METHOD OF READING OUT DATA - A nonvolatile memory device ( | 2009-02-19 |
20090049230 | FSA Context Switch Architecture for Programmable Intelligent Search Memory - Memory architecture provides capabilities for high performance content search. The architecture creates an innovative memory that can be programmed with content search rules which are used by the memory to evaluate presented content for matching with the programmed rules. When the content being searched matches any of the rules programmed in the Programmable Intelligent Search Memory (PRISM) action(s) associated with the matched rule(s) are taken. Content search rules comprise of regular expressions which are converted to finite state automata (FSA) and then programmed in PRISM for evaluating content with the search rules. PRISM architecture comprises of a plurality of programmable PRISM Search Engines (PSE) organized in PRISM memory clusters that are used simultaneously to search content presented to PRISM. A context switching architecture enables transitioning of PSE states between different input contexts. | 2009-02-19 |
20090049231 | EFFICIENT AND SYSTEMATIC MEASUREMENT FLOW ON DRAIN VOLTAGE FOR DIFFERENT TRIMMING IN FLASH SILICON CHARACTERIZATION - Systems and methods that facilitate characterization of a flash memory device are presented. A characterization component can be associated with a regulator component included in a memory device to facilitate setting and measuring respective drain voltage levels for programming, erase, and soft programming operations at address bit combinations available for the respective operations. The characterization component can utilize external address bits that can be fixed when performing the operations to minimize disruption to the drain voltage measurement flow. The characterization component can detect when a particular operation has already been performed based in part on an applicable portion of the address bit combination associated with such operation, and can bypass such operation at that address bit combination to proceed to the next operation that has yet to be performed thereby efficiently setting and measuring drain voltage levels for various operations and trim settings to characterize the memory device. | 2009-02-19 |
20090049232 | EXECUTE-IN-PLACE IMPLEMENTATION FOR A NAND DEVICE - An Execute-In-Place (XIP) implementation in a NAND controller of the kind that controls a NAND flash memory device. A page load command is provided to a predefined block and page address in a NAND device and identifies whether the boot read request received from the processor is a continuation of a previous boot read request. A read enable pin in the NAND device is toggled if the boot read request is a continuation of the previous boot read request. A random data output command sequence is sent to the NAND device and the read enable pin is toggled if the boot read request is not a continuation of the previous boot read address. | 2009-02-19 |
20090049233 | Flash Memory, and Method for Operating a Flash Memory - A method for operating a flash memory is provided. The flash memory comprises a controller, a cache, and a plurality of blocks. By using a cache to preload data from the host, the buffer of the controller can be smaller than the capacity of a single block or omitted entirely. Smooth data transmission is still maintained. | 2009-02-19 |
20090049234 | SOLID STATE MEMORY (SSM), COMPUTER SYSTEM INCLUDING AN SSM, AND METHOD OF OPERATING AN SSM - In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer. | 2009-02-19 |
20090049235 | ENABLING PARALLEL ACCESS VOLUMES IN VIRTUAL MACHINE ENVIRONMENTS - Parallel, coordinated, and optimized access of real Base and Alias DASDs by one or more virtual machines, each utilizing one or more virtual Base and Alias DASDs. Each of a plurality of virtual machines defines a virtual Base DASD device and a modified operating system may coordinate the virtual machine activity on real Base and Alias devices to maximize overall system throughput. In more complex embodiments, one or more virtual machines define one or more virtual Bases and associated virtual Alias devices in which case wherein the embodiments described coordinate their activity on one or more real Base and Alias devices to maximize overall system throughput. | 2009-02-19 |
20090049236 | SYSTEM AND METHOD FOR DATA PROTECTION MANAGEMENT FOR NETWORK STORAGE - A storage system is defined by multiple hard drives (HDDs) which are divided into several HDD Groups. Each HDD Group consists of one or several HDDs. A storage administrator can set security related attributes to each HDD Group. The storage system may have logical volumes mapped onto corresponding selected HDD Group. When the storage system assigns a logical volume to a host computer, the storage system receives security related requirements for the logical volume from the host computer. The storage system then compares the HDD Groups attributes and to the requirements and assigns an appropriate free space that meets requirements as a logical volume. | 2009-02-19 |
20090049237 | Methods and systems for multi-caching - Provided are methods and systems for multi-caching. The methods and systems provided can enhance network content delivery performance in terms of reduced response time and increased throughput, and can reduce communication overhead by decreasing the amount of data that have to be transmitted over the communication paths. | 2009-02-19 |
20090049238 | DISK DRIVE STORAGE DEFRAGMENTATION SYSTEM - The present invention provides a disk drive storage defragmentation system, comprising providing a cache buffer system coupled to a host system, coupling a disk drive storage system to the cache buffer system, performing a defragmentation process on the disk drive storage system utilizing the cache buffer system and servicing a data access request by the host system from the cache buffer system. | 2009-02-19 |
20090049239 | CONSISTENT DATA STORAGE SUBSYSTEM CONFIGURATION REPLICATION IN ACCORDANCE WITH PORT ENABLEMENT SEQUENCING OF A ZONEABLE SWITCH - Consistency for replicating data storage subsystem configurations in accordance with a “golden” configuration file. A data storage subsystem comprises a blade system configured to support a plurality of blades and a storage system, each arranged in a predetermined slot of the blade system, and at least one zoneable switch whose zoning is disabled at power on. A management module operates the blade system to power on all slots. The storage system, in accordance with a “golden” configuration file, transfers port enablement sequencing to the switch, and the switch enables and zones ports in sequence to allow the server blades to see the storage system in accordance with the port enablement sequence. The storage system is configured with the “golden” configuration file to log on the server blades in accordance with the port enablement sequence to logically configure the server blades in accordance with the “golden” configuration file. | 2009-02-19 |
20090049240 | APPARATUS AND METHOD FOR STORAGE MANAGEMENT SYSTEM - A storage apparatus, method and program are provided. The apparatus includes a management information storing unit that stores management information which defines storage nodes to allocate primary data used as a destination of access and secondary data used as a backup. The apparatus also includes data allocation unit that divides storage nodes | 2009-02-19 |
20090049241 | METHOD FOR CONTROLLING STORAGE SYSTEM, AND STORAGE CONTROL APPARATUS - A method for controlling a storage system including a host computer, and a first and a second storage control apparatuses each receiving a data input/output request from the host computer and executing a data input/output process for a storage device in response to the request, comprises connecting a first communication path between the host computer and the first apparatus; connecting a second communication path between the first apparatus and the second apparatus; receiving by the first apparatus a first data input/output request from the host computer through the first path; when the first apparatus has judged that the first request is not for the first apparatus, transmitting by the first apparatus a second data input/output request corresponding to the first request, to the second apparatus through the second path; and by the second apparatus, receiving the second request and executing a data input/output process corresponding to the second request received. | 2009-02-19 |
20090049242 | MEMORY CARD AUTHENTICATION SYSTEM, CAPACITY SWITCHING-TYPE MEMORY CARD HOST DEVICE, CAPACITY SWITCHING-TYPE MEMORY CARD, STORAGE CAPACITY SETTING METHOD, AND STORAGE CAPACITY SETTING PROGRAM - A system for authenticating a memory card including a capacity switching-type memory card host device including a capacity switch notification module which notifies a memory card targeted for exchanging information that the capacity switching-type memory card host device handles a capacity switching-type memory card, and a capacity switch authentication module which authenticates whether the targeted memory card is the capacity switching-type memory card, a capacity switching-type memory card including a capacity switching-type controller which flags the large-capacity expression register use flag on receipt of notification of being the capacity switching-type memory card host device, and a bus which transmits and receives data between the capacity switching-type memory card host device and the capacity switching-type memory card. | 2009-02-19 |
20090049243 | Caching Dynamic Content - Aspects of the subject matter described herein relate to caching dynamic content. In aspects, caching components on a requesting entity and on a content server cache requested content. When a request for content similar to cached content is received, the requesting entity sends a request for the content and an identifier of similar cached content to the content server. The content server obtains the requested content and determines the differences between the requested content and the cached content. The content server then sends the differences to the requesting entity. The requesting entity uses the differences and its cached content to construct the requested content and provides the requested content. | 2009-02-19 |
20090049244 | Data Displacement Bypass System - A data displacement bypass system is disclosed, wherein the data displacement bypass system comprises a CPU (Central Processing Unit), a first memory, a plurality of address lines, a plurality of data lines, an OE (Output Enable) line, a CS (Chip Select) line and a data displacement unit. The CPU could output a plurality of address characters, an OE signal and a CS signal, and receive a plurality of data characters. The first memory and the data displacement unit could output the plurality of data characters according to the plurality of address characters, the OE signal and the CS signal received by the first memory and the data displacement unit, wherein the data displacement unit could govern the plurality of data characters inputting to the CPU by outputting high or low voltage. | 2009-02-19 |
20090049245 | Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same - A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The cache system operates in a manner that can be transparent to a memory controller to which the memory device is connected. Alternatively, the memory controller can control the operation of the cache system. | 2009-02-19 |
20090049246 | APPARATUS AND METHOD OF CACHING FRAME - An apparatus and method of caching a frame is provided. The method of caching a frame includes receiving information on a frame to be cached from a main storage unit, setting an initial value of a specified mode using the received information, and caching the frame from the main storage unit using the specified mode. | 2009-02-19 |
20090049247 | MEDIA CACHE CONTROL INTERFACE - The apparent speed with which a media work is ripped to copy the work into a visible store is substantially reduced. When the media work is played, its content is cached onto a persistent, fast access storage media. If the user subsequently decides to rip the media work, the content of the cache is copied to a visible store in substantially less time than would be required to play the media work and convert it. The user thus perceives that the media work is ripped in a substantially shorter time, compared to that required for ripping the media work in a conventional manner. The ripping process may encode or transform the format of the content to a desired format for use within the visible store. Constraints may be imposed by the user to limit the cache, or the caching process may be hidden from the user. | 2009-02-19 |
20090049248 | Reducing Wiring Congestion in a Cache Subsystem Utilizing Sectored Caches with Discontiguous Addressing - A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector. | 2009-02-19 |
20090049249 | Transparent cache system and method - A transparent caching system and a method for transparent caching are provided. The system includes a cache for storing, a processor for executing instructions of the cache, and clone handlers that provide a copy of a cached object. A cache key, corresponding uniquely to the cached object, is configured to identify and lookup the cached object. A pluggable expiration handler is configured to authorize the transparent caching system to clean up the cached object, and a cache object helper determines whether information in the cached object is still valid. If a cache hit is received to retrieve the cached object corresponding to the cache key, a copy of the cached object is provided. To determine if the cached object is to be cleaned up, the expiration handler takes into account at least one of a cache hit count, a time since a last cache hit, and an available memory. | 2009-02-19 |
20090049250 | Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same - A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function. | 2009-02-19 |
20090049251 | SPLITTING WRITES BETWEEN A STORAGE CONTROLLER AND REPLICATION ENGINE - Provided are a method, system, and article of manufacture for splitting writes between a storage controller and replication engine. A splitter executing in a storage controller manages access to primary volumes. An initialization command is received to communicate with a replication engine. A replication command is received for one primary volume and the primary volume is indicated as subject to replication. A write request is received to write data to a target primary volume of the primary volumes that is indicated as subject to the replication. The data in the write request is written to the target primary volume. The data in the write request is sent to the replication engine. The replication engine executes a copy services function associated with the target primary volume to write the data to a replication engine volume. | 2009-02-19 |
20090049252 | REPLICATION ENGINE COMMUNICATING WITH A SPLITTER TO SPLIT WRITES BETWEEN A STORAGE CONTROLLER AND REPLICATION ENGINE - Provided are a method, system, and article of manufacture for a replication engine communicating with a splitter to split writes between a storage controller and replication engine. Communication is initiated with the splitter implemented in a storage controller managing access to primary volumes. A command is sent to the splitter to copy writes to one primary volume to the replication engine. Write data is received from the splitter to one of the primary volumes following the splitter receiving the command to copy the writes to the replication engine. A determination is made of a copy services function to use for the received data. The determined copy services function is invoked to transfer the received data to a secondary storage volume. | 2009-02-19 |
20090049253 | Program and erase diabling control of WPCAM by double controls - The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions that include nonvolatile memory cells; program prohibition information units, the program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in a plurality of memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state to a program allowing state with respect a memory region, the memory region is one of the plurality of corresponding memory regions, based on first prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, based on second prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region | 2009-02-19 |
20090049254 | MEMORY CONTROLLER AND PROCESSOR SYSTEM - A memory controller includes a memory diagnosing part for controlling access from a CPU to a memory, and accessing and diagnosing the memory, an information setting part for setting cycle information according to a loaded condition of the CPU, and a cycle adjusting part for adjusting a cycle for the memory diagnosing part to access the memory based on the cycle information of the information setting part. | 2009-02-19 |
20090049255 | System And Method To Reduce Disk Access Time During Predictable Loading Sequences - A method, software, and system for loading data from disk include comparing a current sequence of disk I/O requests to data indicative of a previous disk I/O request sequence. Responsive to detecting a match between the current disk I/O sequence and the previous disk I/O sequence, a copy of data blocks accessed during the I/O sequence is stored in a contiguous portion of the disk. Responsive to a subsequent request to data in the disk sequence, the request is mapped to and serviced from the sequential portion of the disk. In one embodiment, the disk sequence represents a boot sequence of the system. | 2009-02-19 |
20090049256 | MEMORY CONTROLLER PRIORITIZATION SCHEME - A system includes a processor coupled to a memory through a memory controller. The memory controller includes first and second queues. The memory controller receives memory requests from the processor, assigns a priority to each request, stores each request in the first queue, and schedules processing of the requests based on their priorities. The memory controller changes the priority of a request in the first queue in response to a trigger, sends a next scheduled request from the first queue to the second queue in response to detecting the next scheduled request has the highest priority of any request in the first queue, and sends requests from the second queue to the memory. The memory controller changes the priority of different types of requests in response to different types of triggers. The memory controller maintains a copy of each request sent to the second queue in the first queue. | 2009-02-19 |
20090049257 | System and Method for Implementing a Memory Defect Map - In accordance with the present disclosure, a system and method are herein disclosed for managing memory defects in an information handling system. In an information handling system, a first quantity of memory, such as RAM, may contain defective memory elements. A second quantity of memory is physically coupled to the first quantity of memory and is used to store a memory defect map containing information regarding the location of defective memory elements in the first quantity of memory. The memory defect map may then be referenced by the BIOS or the operating system to preclude use of regions of memory containing defective memory elements. | 2009-02-19 |
20090049258 | Method of verifying pseudo-code loaded in an embedded system, in particular a smart card - The invention relates to a verification of applications in interpreted language of the byte-code type (pseudo-code) loaded on portable electronic devices, in particular a chipcard and a method for verification of an application ( | 2009-02-19 |
20090049259 | CLUSTERED SNAPSHOTS IN NETWORKS - Apparatus, systems, and methods may operate to assign a plurality of managing nodes to manage a corresponding plurality of groups of blocks forming a portion of a snapshot volume for copy-on-write execution and snapshot write execution. Further operations include coordinating the copy-on-write execution and the snapshot write execution using a write completion map accessible to the managing nodes. Additional apparatus, systems, and methods are disclosed. | 2009-02-19 |
20090049260 | HIGH PERFORMANCE DATA DEDUPLICATION IN A VIRTUAL TAPE SYSTEM - Data deduplication in a storage system, achieving high performance due to minimal overhead during a backup operation, reduced disk read operations to locate duplicate data and minimal impact for restore operations involving deduplicated data. | 2009-02-19 |
20090049261 | Method to accelerate block level snapshots in archiving storage systems - A device and method for connection to a host and transferring data between the host and data storage assembly. The device is preferably a storage system which initializes a logical unit (LUN) in the storage assembly. A persistent memory stores a data representation of clean areas in the LUN. The storage system receives data to be written from the host to a destination area in the LUN, and determines if the destination area in the LUN is a clean area or a dirty area as indicated in the persistent memory. The storage system effects a snapshot copy of data from the destination area in the LUN to an archive storage device of the storage assembly only if the destination area is not entirely a clean area. Bandwidth is likewise reduced in LUN copy and reconstruction operations. | 2009-02-19 |
20090049262 | EXTERNAL STORAGE AND DATA RECOVERY METHOD FOR EXTERNAL STORAGE AS WELL AS PROGRAM - The data is automatically recovered to a desired arbitrary point in an external storage without imposing a burden on the host computer. An application on a host computer instructs data recovery control processing of a disk control apparatus to set a recovery opportunity. It is possible to register arbitrary plural points as a recoverable point by setting a recovery flag included in journal data. In the case in which data is recovered due to occurrence of a failure or the like, the application requests a list showing recovery opportunities which have already been set. The application designates a point to which data is recovered on the basis of the recovery opportunity list. The disk control apparatus recovers the data to the designated point on the basis of a backup disk and a journal disk. | 2009-02-19 |
20090049263 | METHOD OF MIRRORING DATA BETWEEN CLUSTERED NAS SYSTEMS - Data of a global file system spread over multiple local NAS systems may be consolidated as a copy into a single remote NAS system. When remote copy is set up, the local NAS systems replace referrals within the global file system with directories and send these in place of the referrals to the remote NAS system. Then, other local NAS systems referred to by the referrals send files and directories under the directories replacing the referrals on the remote NAS system. Alternatively, to split copy data of a locally-stored global file system amongst multiple remote NAS systems, the local NAS system replaces specified directories with referrals, and sends the referrals with the data to one of the remote NAS systems. Then, the local NAS system sends files and directories under the directories replaced with referrals to one or more other remote NAS systems as referred to by the referrals. | 2009-02-19 |
20090049264 | Memory device and method having on-board address protection system for facilitating interface with multiple processors, and computer system using same - A memory device includes an address protection system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The protection system is used to prevent at least some of a plurality of processors in a system from accessing addresses designated by one of the processors as a protected memory address. Until the processor releases the protection, only the designating processor can access the memory device at the protected address. If the memory device contains a cache memory, the protection system can alternatively or additionally be used to protect cache memory addresses. | 2009-02-19 |
20090049265 | STALE TRACK INITIALIZATION IN A STORAGE CONTROLLER - Deleting a data volume from a storage system and freeing its storage space to make it available to be allocated to a new volume is accomplished by only zeroing associated metadata for the tracks contained in the freed storage space which is then reused in a new volume allocation and an attempt is made by the new volume to read a first record R | 2009-02-19 |
20090049266 | MEMORY SYSTEM WITH SECTOR BUFFERS - The invention relates to a memory system which is connected to a host system by means of a host bus (HB). Said system contains a memory controller (FC) having an internal memory (IR) and flash memory chips (F | 2009-02-19 |
20090049267 | Buffer circuit for a memory module - The invention provides a buffer circuit for a memory module comprising at least one configuration register bank for storing configuration data of said memory module, an error check logic for performing an error check of input signals applied to the memory module via input pins of said memory module to generate a signature output by said memory module via at least one output pin of said memory module, and a controller which depending on an output request setting stored in a configuration register of said configuration register bank reads out information data said buffer circuit via said output pin of said memory module. | 2009-02-19 |
20090049268 | PORTABLE STORAGE DEVICE AND METHOD OF MANAGING RESOURCE OF THE PORTABLE STORAGE DEVICE - Provided are a portable storage device and a method of managing a resource of the portable storage device. The method includes converting a first DRM application into a ready status from an idle status if task processing of the first DRM application is required, and converting the first DRM application into a pending status and a second DRM application into the ready status from the idle status if task processing of the second DRM application is required. | 2009-02-19 |
20090049269 | HOST MEMORY INTERFACE FOR A PARALLEL PROCESSOR - A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory. | 2009-02-19 |
20090049270 | SYSTEM AND METHOD FOR USING A MEMORY MAPPING FUNCTION TO MAP MEMORY DEFECTS - A system and method are herein disclosed for managing memory defects in an information handling system. More particularly, a system and method are described for generating a usable memory map which excludes memory locations containing defect memory elements. In an information handling system, a memory defect map, which contains information about the location of defective memory elements, is coupled to the memory device. As a map of memory usable by the system is created, usable memory regions containing defective memory elements are excluded from the memory map. The memory map is passed to the operating system, which uses only those regions of memory designated as usable and non-defective. | 2009-02-19 |
20090049271 | Consolidation of matching memory pages - A method and apparatus for managing memory allocation using memory pages. A first physical memory page is compared with a second physical memory page, wherein the first physical memory page is associated with a first page table and the second physical memory page is associated with a second page table. If the second physical memory page matches the first physical memory page, the second physical memory page is deallocated, and the second page table is associated with the first physical memory page. | 2009-02-19 |
20090049272 | METHOD FOR IMPROVING THE PERFORMANCE OF SOFTWARE-MANAGED TLB - Exemplary embodiments of the present invention comprise a method for the utilization of entry-replacement index hint information within a software-managed TLB. The method comprises receiving an address translation request at a TLB and retrieving the address translation information from a page table in the event of a miss lookup event at the TLB. The method further comprises retrieving index replacement hint information from a hardware component, wherein the hardware component is configured to execute a predetermined replacement algorithm and writing the address translation information to a TLB index referenced within the index replacement hint information. | 2009-02-19 |
20090049273 | PHYSICALLY-TAGGED CACHE WITH VIRTUAL FILL BUFFERS - A virtually indexed, physically-tagged cache is combined with one or more virtually-tagged fill-buffers. | 2009-02-19 |
20090049274 | Circuitry and method for indicating a memory - Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 2009-02-19 |
20090049275 | PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR SYSTEM, PROCESSING METHOD BY PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR METHOD, PROCESSING PROGRAM BY PROCESSING ELEMENTS AND MIXED MODE PARALLEL PROCESSING PROGRAM - Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inherently belong to the PEs, where P2009-02-19 | |
20090049276 | Techniques for sourcing immediate values from a VLIW - Sourcing immediate values from a very long instruction word includes determining if a VLIW sub-instruction expansion condition exists. If the sub-instruction expansion condition exists, operation of a portion of a first arithmetic logic unit component is minimized. In addition, a part of a second arithmetic logic unit component is expanded by utilizing a block of a very long instruction word, which is normally utilized by the first arithmetic logic unit component, for the second arithmetic logic unit component if the sub-instruction expansion condition exists. | 2009-02-19 |
20090049277 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device is provided. The operating frequency generating component generates an operating frequency that is a timing that becomes a reference for synchronizing processing between each circuit when the semiconductor integrated circuit operates. The extracting component extracts a critical path that is the slowest path when a data signal propagates between predetermined terminals inside the semiconductor integrated circuit. The instruction prefetch executing component prefetches an instruction relating to the critical path that has been extracted by the extracting component. The processing configuration changing component changes the processing configuration so as to realize transmission of the data signal within a predetermined cycle of the operating frequency using the instruction prefetch executing component when the data signal passes through the path of the critical path. | 2009-02-19 |
20090049278 | EFFICIENT MEMORY UPDATE PROCESS FOR ON-THE-FLY INSTRUCTION TRANSLATION FOR WELL BEHAVED APPLICATIONS EXECUTING ON A WEAKLY-ORDERED PROCESSOR - A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of a well-behaved application. Instructions of a well-behaved application are translated and executed by a weakly-ordered processor. The processing logic includes a lock address tracking utility (LATU), which provides an algorithm and a table of lock addresses, within which each lock address is stored when the lock is acquired by the weakly-ordered processor. When a store instruction is encountered in the instruction stream, the LATU compares the target address of the store instruction against the table of lock addresses. If the target address matches one of the lock addresses, indicating that the store instruction is the corresponding unlock instruction (or lock release instruction), a sync instruction is issued ahead of the store operation. The sync causes all values updated by the intermediate store operations to be flushed out to the point of coherency and be visible to all processors. | 2009-02-19 |
20090049279 | THREAD INTERLEAVING IN A MULTITHREADED EMBEDDED PROCESSOR - The present invention provides a network multithreaded processor, such as a network processor, including a thread interleaver that implements fine-grained thread decisions to avoid underutilization of instruction execution resources in spite of large communication latencies. In an upper pipeline, an instruction unit determines an-instruction fetch sequence responsive to an instruction queue depth on a per thread basis. In a lower pipeline, a thread interleaver determines a thread interleave sequence responsive to thread conditions including thread latency conditions. The thread interleaver selects threads using a two-level round robin arbitration. Thread latency signals are active responsive to thread latencies such as thread stalls, cache misses, and interlocks. During the subsequent one or more clock cycles, the thread is ineligible for arbitration. In one embodiment, other thread conditions affect selection decisions such as local priority, global stalls, and late stalls. | 2009-02-19 |
20090049280 | SOFTWARE CONTROLLED CPU PIPELINE PROTECTION - A processor in a digital system executes instructions in an instruction execution pipeline. The processor detects a pipeline protection directive while executing instructions and sets a pipeline protection mode in accordance with the directive. The processor then continues to fetch and execute instructions in an unprotected manner if the pipeline protection mode is off and continues to fetch and execute instruction in a protected manner if the pipeline protection mode is on. | 2009-02-19 |
20090049281 | MULTIMEDIA DECODING METHOD AND MULTIMEDIA DECODING APPARATUS BASED ON MULTI-CORE PROCESSOR - Provided are a multimedia decoding method and multimedia decoding apparatus based on a multi-core platform including a central processor and a plurality of operation processors. The multimedia decoding method includes performing a queue generation operation on input multimedia data to generate queues of one or more operations of the multimedia data which are to be performed by the central processor and the operation processors, wherein the queue generation operation is performed by the central processor; performing motion compensation operations on partitioned data regions of the multimedia data by one or more motion compensation processors among the operation processors; and performing a deblocking operation on the multimedia data by a deblocking processor among the operation processors. | 2009-02-19 |
20090049282 | SYSTEM AND METHOD FOR MANAGING DATA - A method of performing data and pointer compression includes, in a buffer which is formed between a processor and a level one cache and stores plural tags and full-word values associated with the tags, when the buffer is presented with an address, breaking the address into a line number which indexes a set of the full-word values, and a tag which is used as a key to determine whether a value in the set of full-word values includes a value associated with the presented address, if a tag in the presented address matches a tag in the buffer, returning a full-word value in the buffer which is associated with the tag, and storing the returned full-word value in a destination register of an instruction which originated the presented address, and if a tag in the presented address does not match a tag in the buffer, generating a fault and branching control to a pre-defined handler. | 2009-02-19 |
20090049283 | INFORMATION PROCESSING DEVICE AND INSTRUCTION EXECUTING METHOD - An information processing device including registers ( | 2009-02-19 |
20090049284 | Parallel Subword Instructions With Distributed Results - The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify (implicitly or explicitly) a bit position and the result of each of the parallel subword compare operations can be stored at that bit position within the respective subword location of a result register. Alternatively, for a shifting-type instruction, pre-existing contents of a result register can be shifted one bit toward greater significance while the results are of the present operation are stored in the least-significant bits of respective result-register subword locations. This approach provides the results of multiple parallel subword compare instructions to be combined with relatively few instructions and reduces the maximum lateral movement of information—both of which can enhance performance. | 2009-02-19 |
20090049285 | INFORMATION DELIVERY APPARATUS, INFORMATION REPRODUCTION APPARATUS, AND INFORMATION PROCESSING METHOD - An information delivery apparatus includes an encoding information collection unit which collects information used to encode content information, a generation unit which predicts decode processes of the content information based on the collected information, and generates configuration information used to configure data paths required to execute the decode processes, an embedding unit which embeds the configuration information in the content information, and a delivery unit which delivers the content information embedded with the configuration information. | 2009-02-19 |
20090049286 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING IMPROVED BRANCH TARGET ADDRESS CACHE - A processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a level one branch target address cache (BTAC) and a level two BTAC each having a respective plurality of entries each associating at least a tag with a predicted branch target address. The branch logic accesses the level one and level two BTACs in parallel with a tag portion of a first instruction fetch address to obtain a first predicted branch target address from the level one BTAC for use as a second instruction fetch address in a first processor clock cycle and a second predicted branch target address from the level two BTAC for use as a third instruction fetch address in a later second processor clock cycle. | 2009-02-19 |
20090049287 | Stall-Free Pipelined Cache for Statically Scheduled and Dispatched Execution - This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled by a latency field in a load instruction or by a latency specification of a prior instruction. This invention is useful in the great majority of cases where the code can tolerate incremental increases in load latency for a reduction in cache miss penalty. | 2009-02-19 |
20090049288 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR RUNTIME INVOCATION OF AN APPROPRIATE VERSION OF PROGRAM INSTRUCTIONS IN AN ON-DEMAND DATABASE - In accordance with embodiments, there are provided mechanisms and methods for runtime invocation of an appropriate version of program instructions in an on-demand database service. These mechanisms and methods for providing such runtime invocation can enable embodiments to ensure that new versions of developed applications will operate in the same application environment of a previous version. The ability of embodiments to provide such runtime invocation may lead to an improved application migration development/runtime framework, etc. | 2009-02-19 |
20090049289 | Method and apparatus for Assigning devices to a partition - Devices in a processing system may be managed by performing a first scan of a bus of the processing system from a first partition. In one embodiment, the first scan may discover location information for devices on the bus. A communications hub of the processing system may be programmed to hide at least one of the devices on the bus. After the communications hub is so programmed, the first partition may scan the bus again. A second partition of the processing system may receive location information for one or more of the devices detected in the first scan but not detected in the second scan. In one embodiment, the second partition may boot, and then the communications hub may again be programmed to hide at least one of the devices on the bus. An operating system may then boot on the first partition. Other embodiments are described and claimed. | 2009-02-19 |
20090049290 | CONSISTENT DATA STORAGE SUBSYSTEM CONFIGURATION REPLICATION - Consistency for replicating data storage subsystem configurations in accordance with a “golden” configuration file. A data storage subsystem comprises a blade system with a plurality of slots, the blade system configured to support a plurality of blades and a storage system, each arranged in a predetermined slot of the blade system. A management module operates the blade system to first power on the storage system, and subsequently to power on the plurality of server blades in a sequential order that matches a blade system natural boot sequence order, skipping the storage system, and the storage system is configured with the “golden” configuration file to log on the server blades in accordance with the power on sequence to logically configure the server blades in accordance with the “golden” configuration file. | 2009-02-19 |
20090049291 | CONSISTENT DATA STORAGE SUBSYSTEM CONFIGURATION REPLICATION IN ACCORDANCE WITH SEQUENCE INFORMATION - Consistency for replicating data storage subsystem configurations in accordance with a “golden” configuration file. A data storage subsystem comprises a blade system with a plurality of slots, the blade system configured to support a plurality of blades and a storage system, each arranged in a predetermined slot of the blade system. A management module operates the blade system to first power on the storage system. In accordance with a “golden” configuration file, the storage system passes sequence information to the management module. The management module powers on the plurality of server blades in accordance with the sequence information. The storage system is configured with the “golden” configuration file to log on the server blades in accordance with the power on sequence to logically configure the server blades in accordance with the “golden” configuration file. | 2009-02-19 |
20090049292 | Computer with Extensible Firmware Interface Implementing Parallel Storage-Device Enumeration - A computer includes an extensible firmware interface with a storage device enumeration function that performs storage device enumeration operations in parallel. | 2009-02-19 |
20090049293 | BOOTING A COMPUTER USING A BOOT LIST WHEN A NON-VOLATILE MEMORY ON THE COMPUTER DOES NOT CONTAIN THE BOOT LIST - A computer implemented method, apparatus, and computer program product for booting a computer using a boot list. A determination is made as to whether a boot list is present in a non-volatile memory of the computer. The boot list is a set of paths, in which each path in the boot list is a path of a storage device. If the boot list is not present, a search is performed for the boot list in a reserved area of each storage device in a set of storage devices. When the boot list is found in the reserved area of a storage device in the set of storage devices, the boot list is copied from the reserved area of the storage device in the set of storage devices to form a copied boot list. The copied boot list is stored in the non-volatile memory to form a stored boot list. The computer is booted using the stored boot list in the non-volatile memory. | 2009-02-19 |
20090049294 | METHOD FOR BOOTING COMPUTER SYSTEM - The invention relates to a method for booting a computer system. The method includes the steps of executing a hardware initialization process, starting a setting interface according to a trigger signal, determining whether a specific setting option belongs to a specific option group when the value of the specific setting option in the setting interface is changed and loading an operating system to the computer system when the specific setting option belongs to the specific option group. | 2009-02-19 |
20090049295 | Determining a boot image based on a requesting client address - A method, computer-readable storage medium, and boot server that, in an embodiment, receive a command that requests a name of a boot image and a network address of a boot server that contains the boot image, invoke a plug-in to determine the name of the boot image based on an address of a client that sent the command, and send the name of the boot image and the network address of the boot server to a client that sent the command. In various embodiments, the address of the client may be a network address or a MAC (Media Access Control) address. The client retrieves the boot image via the name, and the boot image initializes the client when executed at the client. The name of the boot image is changed to a second name and sent to the client in response to another command. | 2009-02-19 |
20090049296 | Customizable instant messaging private tags - Systems for customizing the privatizing of instant messages preferably comprise a processing device configured to detect a marking of select portions of an instant message as sensitive data. The instant message is parsed for marked sensitive data. An encryption engine encrypts the sensitive data. A modified unencoder is also preferably included for converting the encrypted sensitive data into a data stream that complies with an XML format. Other systems and methods are also provided. | 2009-02-19 |
20090049297 | SYSTEMS AND METHODS FOR VERIFYING THE AUTHENTICITY OF A REMOTE DEVICE - Some embodiments of the invention are directed to, among other things, systems, computer readable media, methods and any other means for verifying the authenticity of a client device. In some embodiments, a token is issued by one or more remote media servers that allows the client device to download video, media or other data from one or more remote media servers. | 2009-02-19 |
20090049298 | System for remote electronic notarization and signatory verification and authentication/ interface/ interlinked with an advanced steganographic cryptographic protocol - A method for remote electronic verification and authentication and screening of potential signatories for remote electronic notary transactions via remote pc encrypted platform to a broadband digitally or WIFI cellular/PDA device or portable pc device. The system implements the following electronic components, but not limited to, electronic signature device, digital certificates, electronic document, electronic biometric devices, electronic audio/visual software/hardware, and electronic payment systems and devices, all electronically synchronized to afford capable notary publics in executing remote electronic notary transactions via a satellite kiosk network or on-line virtual kiosk application. | 2009-02-19 |
20090049299 | Data Integrity and Non-Repudiation System - A system is disclosed for establishing data integrity and non-repudiation without hashing and without performing a bit to bit comparison of the message. The system includes necessary hardware and/or software to generate a random symmetric key for use with a symmetric encryption algorithm; generate a random sequence having a plurality of elements; separate a message into a plurality of blocks, wherein each block has a size less than or equal to the block size of the symmetric algorithm less the size of a digital signature of one of the plurality of elements; generate a signature for each of the plurality of elements; encrypt a concatenation of each of the plurality of blocks of the message with a corresponding signature, the encryption being performed using the symmetric encryption algorithm and the random symmetric key; and communicating the encrypted concatenation from the gaming server to a gaming device. | 2009-02-19 |
20090049300 | Method and system for user attestation-signatures with attributes - The present invention discloses a method for generating and verifying a user attestation-signature value (DAA′) and issuing an attestation value (cert) for the generation of the user attestation-signature value (DAA′). Further, the invention is related to a system for using a user attestation-signature value (DAA′) that corresponds to at least one attribute (A, B, C, D), each with an attribute value (w, x, y, z), none, one or more of the attribute values (x, y) remaining anonymous for transactions, the system comprising: a user device ( | 2009-02-19 |
20090049301 | Method of Providing Assured Transactions by Watermarked File Display Verification - Electronic transactions employing prior art approaches of digital certificates and authentification are subject to attacks resulting in fraudulent transactions and abuse of identity information. Disclosed is a method of improving electronic security by establishing a secure trusted path between a user and an institution seeking an electronic signature to verify a transaction before any request for signature and completing electronic transaction activities occurs. The secure trusted path providing the user with a predetermined portion of the request from the institution for a signature upon a personalized device that cannot be intercepted or manipulated by malware to verify that the request as displayed upon the user's primary computing device is valid. | 2009-02-19 |
20090049302 | System And Method For Processing Conent For Later Insertion Of Digital Watermark And Other Data - A method and system for processing content are described including generating a dummy value, inserting the dummy value into encoded content, selecting a position in the encoded content where the dummy value in the encoded content is to be replaced by a real value, generating the real value and replacing the dummy value with the real value in the encoded content. | 2009-02-19 |
20090049303 | METHOD AND SYSTEM FOR DATA DELIVERY AND REPRODUCTION - Methods and apparatus for processing title data watermarked with a code. At least a portion of the title data may be watermarked at a plurality of locations within the title data with customer information data, so that the title data provided to a customer includes the watermark information. To obtain the code from the watermarked title data, watermarking information associated with the watermarked title data is first received. The watermarking information identifies a plurality of locations and a number to frequency modulation relationship at each of the locations. A different modulation scheme may be used at each location. The watermarked title data is demodulated at each of the plurality of placement locations based on the number to frequency modulation relationship. The code is then generated from the demodulated watermarked title data. A verification indication is output based in part on the generated code. | 2009-02-19 |
20090049304 | DIGITAL WATERMARK EMBEDDING APPARATUS AND METHOD, AND DIGITAL WATERMARK ANALYSIS APPARATUS, METHOD AND PROGRAM - A digital watermark embedding apparatus comprises below units. A first generation unit generates a plurality of symbol sequences each of which includes a plurality of symbols including ranks, each of the ranks being uniquely numbered among each of the symbol sequences, each of the symbol sequences uniquely corresponding to each of a plurality of identification information items to be embedded as digital watermark information into each of copies of digital contents. A second generation generates a plurality of to-be-embedded codes corresponding to each of the symbols in each of the symbol sequences. An embedding unit embeds the to-be-embedded codes in each of the copies. | 2009-02-19 |
20090049305 | METHOD AND SYSTEM FOR HIERARCHICAL PLATFORM BOOT MEASUREMENTS IN A TRUSTED COMPUTING ENVIRONMENT - An architecture for a distributed data processing system comprises a system-level service processor along with one or more node-level service processors; each are uniquely associated with a node, and each is extended to comprise any components that are necessary for operating the nodes as trusted platforms, such as a TPM and a CRTM in accordance with the security model of the Trusted Computing Group. These node-level service processors then inter-operate with the system-level service processor, which also contains any components that are necessary for operating the system as a whole as a trusted platform. A TPM within the system-level service processor aggregates integrity metrics that are gathered by the node-level service processors, thereafter reporting integrity metrics as requested, e.g., to a hypervisor, thereby allowing a large distributed data processing system to be validated as a trusted computing environment while allowing its highly parallelized initialization process to proceed. | 2009-02-19 |
20090049306 | Method, Computer System, and Computer Program Product for Password Generation - The generation of a unique password using a secret key and an application name is disclosed. Other passwords may be generated for other applications using the same key. A user provides a key that is not easily able to be guessed by third parties. The user also inputs a name of an application for which a password is desired. The system utilises the application name and the secret key to generate a unique password for that application, using standard encryption techniques. The system generates the same password for that application and secret key combination every time. Alternate embodiments generate a user identifier from the same secret key and application name. | 2009-02-19 |
20090049307 | System and Method for Providing a Multifunction Computer Security USB Token Device - The invention discloses a small token device, ideally about the size of a key, which can plug into the USB interface of a host computer, which need not be fully trusted, and handle a variety of different security functions. The device is capable of serving as a secure USB hub, and thus can function on a host computer that only has one available USB port. Among the multiple functions that the device can perform include communicating through the internet in a secure manner, storing data in a secure manner, and access secure information through public key (PKI) methods. The invention also allows secure USB peripherals to maintain security while being hooked up to either a non-secure host computer or other non-secure USB peripherals. | 2009-02-19 |
20090049308 | Method for Effective Tamper Resistance - A system, method, and computer program product for preventing a malicious user from analyzing and modifying software content. The one-way functions used in prior art systems using dynamically evolving audit logs or self-modifying applications are replaced with a one-way function based on group theory. With this modification, untampered key evolution will occur inside a defined mathematical group such that all valid key values form a subgroup. However, if the program is altered, the key will evolve incorrectly and will no longer be a member of the subgroup. Once the key value is outside of the subgroup, it is not possible to return it to the subgroup. The present invention provides a limited total number of valid keys. The key evolution points are not restricted to locations along the deterministic path, so the key can be used in various novel ways to regulate the program's behavior, including in non-deterministic execution paths. | 2009-02-19 |
20090049309 | Method and Apparatus for Verifying Integrity of Computer System Vital Data Components - Vital data components of a computer system are protected by a mechanism for detecting unauthorized alteration, preferably in the form of digital signatures to detect unauthorized alteration. A vital data validation mechanism is provided to verify that vital data modules have not been tampered with. The vital data validation mechanism verifies the current state of each vital data module, preferably by decrypting the digital signature. The validation mechanism also checks an alteration log to verify that no alterations have been made to the corresponding memory locations. The second verification is intended to detect whether a vital data module has been altered temporarily, and then restored to its initial state. | 2009-02-19 |
20090049310 | Efficient Elimination of Access to Data on a Writable Storage Media - A method and computer program product are provided for eliminating access to data within a writable storage media cartridge. If it is determined if at least a first portion of data on the writable storage media is encrypted then a second portion of data within the writable storage media cartridge related to said encrypted first portion of data is shredded. The first portion of data and the second portion are not the same portions of the writable storage media cartridge. | 2009-02-19 |
20090049311 | Efficient Elimination of Access to Data on a Writable Storage Media - A system provided for eliminating access to data within a writable storage media cartridge. The system comprises a writable storage media drive, such as a tape drive. The writable storage drive determines if at least a first portion of data on the writable storage media is encrypted. If it is determined that the first portion of data is encrypted then the writable storage drive shreds a second portion of data within the writable storage media cartridge related to said encrypted first portion of data. The first portion of data and the second portion are not the same portions of the writable storage media cartridge. | 2009-02-19 |
20090049312 | Power Management for System Having One or More Integrated Circuits - Power management control software including power management policies is provided with those policies divided into observation code and response code. When predetermined execution points within the operating system | 2009-02-19 |
20090049313 | Proactive Power Management in a Parallel Computer - Proactive power management in a parallel computer, the parallel computer including a service node and a plurality of compute nodes, the service node connected to the compute nodes through an out-of-band service network, each compute node including a computer processor and a computer memory operatively coupled to the computer processor. Embodiments include receiving, by the service node, a user instruction to initiate a job on an operational group of compute nodes in the parallel computer, the instruction including power management attributes for the compute nodes; setting, by the service node in accordance with the power management attributes for the compute nodes of the operational group, power consumption ratios for each compute node of the operational group including a computer processor power consumption ratio and a computer memory power consumption ratio; and initiating, by the service node, the job on the compute nodes of the operational group of the parallel computer. | 2009-02-19 |
20090049314 | Method and System for Dynamic Voltage and Frequency Scaling (DVFS) - Methods and systems for dynamic voltage and frequency scaling (DVFS) may include monitoring change in resource utilization of an electronic device. If the change is greater than a threshold amount, a frequency of at least one clock and/or voltage for at least one voltage island may be adjusted. The resource utilization may be measured as, for example, a number of instructions executed per second. The frequency and/or voltage adjustment may depend on one or more operating points that may correspond to a power management state. An interrupt received in a power management state may also indicate an operating point. If resource utilization has increased, the frequency/voltage may be increased. Similarly, in cases where resource utilization has decreased, the frequency/voltage may be decreased. Voltage to circuits using the clock may be increased prior to increasing the clock frequency, and the voltage may be decreased after decreasing the clock frequency. | 2009-02-19 |