07th week of 2011 patent applcation highlights part 6 |
Patent application number | Title | Published |
20110037030 | NANOPARTICULATE COMPOSITION AND METHOD FOR ITS PRODUCTION - The present invention relates to a nanoparticulate composition comprising nanoparticles with a particle-size distribution of d | 2011-02-17 |
20110037031 | CATION DEFICIENT MATERIALS FOR ELECTRICAL ENERGY STORAGE - A composition comprising: a metal oxide of a first metal ions and second metal ions; an electrically conductive material; and a binder material. The second metal ions have a higher oxidation state than the first metal ions. The presence of the second metal ion increases the number of metal cation vacancies. A method of: dissolving salts of a first metal ion and a second metal ion in water to form a solution; heating the solution to a temperature of about 80-90° C.; and adding a base to the solution to precipitate nanoparticles of a metal oxide of the first metal ion and the second metal ion. | 2011-02-17 |
20110037032 | PROCESS FOR THE PREPARATION OF CRYSTALLINE LITHIUM-, IRON- AND PHOSPHATE-COMPRISING MATERIALS - The present invention relates to a Process for the preparation of compounds of general formula (I), Li | 2011-02-17 |
20110037033 | Sorting Two-Dimensional Nanomaterials By Thickness - The present teachings provide, in part, methods of separating two-dimensional nanomaterials by atomic layer thickness. In certain embodiments, the present teachings provide methods of generating graphene nanomaterials having a controlled number of atomic layer(s). | 2011-02-17 |
20110037034 | METHOD FOR PRODUCING AN ANTISTATIC ARTICLE MADE FROM AGGLOMERATED STONE AND RESULTING ARTICLE - The invention relates to a method for producing an article from agglomerated stone, for example a slab for construction or decoration, comprising the following steps: bringing into contact (i) an inorganic filler, (ii) a polyester resin precursor composition and (iii) a powdered electrically conductive component; mixing same to produce a uniform mass; distributing part of the mass on a substrate; pressing the distributed mass in a vibro-compaction press under vacuum conditions; and hardening the mass by means of polymerisation of the polyester resin. | 2011-02-17 |
20110037035 | METHOD OF PREPARING CONDUCTIVE NANO INK COMPOSITION - A method of preparing a conductive nano ink composition. The method includes mixing a metal precursor in a solution of a multi-functional polymer having a chemical reduction function and a particle growth suppression function to form a mixture solution, forming primary particles by stirring the mixture solution at about 800 to about 1,200 rpm for about 10 to about 20 minutes, and forming secondary particles by leaving the mixture solution at room temperature. | 2011-02-17 |
20110037036 | DISPERSION, COMPOSITION FOR TRANSPARENT ELECTROCONDUCTIVE FILM FORMATION, TRANSPARENT ELECTROCONDUCTIVE FILM, AND DISPLAY - Disclosed is composition providing high refractive index to form a transparent conductive film having excellent transparency and high refractive index, a transparent conductive film produced thereby, a display having the transparent conductive film, and a dispersion having high storage stability for use in preparation of the composition. LCDs employ an anti-reflection film produced from the composition containing a metal complex in a resin solution or a solvent and a high refractive index metal oxide and a conductive metal oxide dispersed therein. However, conventional dispersion has problems such as corroding an apparatus and a material employed in a dispersion step and poor storage stability. Disclosed is a dispersion which contains a high refractive index metal oxide having a refractive index of 1.8 or higher, a conductive metal oxide, an alkoxide-free metal complex, and a dispersion medium, and which has a water content of 3 mass % or less. | 2011-02-17 |
20110037037 | COMPOSITE OF METAL SULFIDE AND METAL OXIDE AND PROCESS FOR PRODUCING THE COMPOSITE - The present invention provides a process for producing a composite of metal sulfide and metal oxide obtained by dispersing a metal sulfide, which is nickel sulfide, copper sulfide, iron sulfide or a mixture thereof, in a metal salt-containing aqueous solution, and depositing metal salt on the metal sulfide by drying the aqueous solution; and heat-treating the metal sulfide comprising a metal salt deposited thereon at 400 to 900° C. in a sulfur-containing atmosphere. Also disclosed is a composite obtained by the aforementioned process, comprising a metal sulfide having a surface partially covered with a metal oxide. The composite of the present invention has improved cycle characteristics while maintaining a high charge/discharge capacity and excellent electrical conductivity inherently possessed by metal sulfide, which is usable as a material having a high theoretical capacity and excellent electrical conductivity when used as a positive-electrode material for a lithium secondary battery. | 2011-02-17 |
20110037038 | Thermosetting Resin Composition for Producing Color Filter for CMOS Image Sensor, Color Filter Comprising Transparent Film Formed Using the Composition and CMOS Image Sensor Using the Color Filter - A thermosetting resin composition for producing a color filter for a CMOS image sensor is provided. The thermosetting resin composition comprises an organic solvent and a self-curing copolymer having structural units represented by Formulae 1, 2, 3 and 4, which are described in the specification. | 2011-02-17 |
20110037039 | ELEVATION MECHANISM - An elevation mechanism includes a platform, a base assembly, a scissor lift assembly and a sliding assembly. The base assembly includes a threaded rod having two threaded portions and two threaded members threadedly engaging with the threaded rod. Rotation directions of the two threaded portion are opposite to each other. The scissor lift assembly includes a plurality of articulated first scissor legs and a plurality of articulated second scissor legs pivotedly coupled to the respective second scissor legs. The sliding assembly includes two fixing members fixed to the platform, a sliding rod fixed between the two fixing members, and two sliding members slidablely connected to the sliding rod. The two sliding members are correspondingly pivotedly connected to the upmost first and second scissor leg. The two threaded members are pivotedly connected to the lowermost first and second scissor legs. | 2011-02-17 |
20110037040 | Fluid shear actuated hoist brake - A fluid shear actuated brake mechanism includes an outer hub secured to a hoist frame, a main brake disc stack engaged between the outer hub and a hoist drum shaft, an actuator hub helically engaged with the outer hub, and an actuator disc stack engaged between the actuator hub and the shaft. The main disc stack and the actuator disc stack are immersed in a fluid. Rotation of the shaft in a load lowering direction generates fluid shear in the actuator disc stack which rotates the actuator hub in a lowering direction and advances it toward the main disc stack, compressing it and the actuator disc stack. Rotation of the shaft in an opposite load lift direction retract the actuator hub from the main disc stack. | 2011-02-17 |
20110037041 | System with Position-Determination for Lifting Columns, and Method Therefor - A system and method for lifting and lowering an object such as a vehicle, comprising: at least two lifting columns; communication means for communication with the at least two lifting columns; position-determining means for carrying out a position determination for each of the at least two lifting columns; selection means for selecting at least one of the lifting columns on the basis of the position determinations; and at least one control unit co-acting with the communication means during use for the purpose of controlling the lifting columns selected with the selection means. | 2011-02-17 |
20110037042 | PHASE CHANGE MEMORY DEVICE WITH PLATED PHASE CHANGE MATERIAL - A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell. | 2011-02-17 |
20110037043 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile memory device includes a first wire, a second wire and a nonvolatile memory cell. The first wire is formed to extend in a first direction, and the second wire is formed at height different from height of the first wire and to extend in a second direction. The nonvolatile memory cell is arranged to be held between the first wire and the second wire in a poison where the first wire and the second wire cross. The nonvolatile memory cell includes a nonvolatile storage layer and a current limiting resistance layer connected in series to the nonvolatile storage layer and having resistance of 1 kilo-ohm to 1 mega-ohm. | 2011-02-17 |
20110037044 | INFORMATION RECORDING DEVICE AND INFORMATION RECORDING/REPRODUCTION SYSTEM INCLUDING THE SAME - This disclosure provides an information recording device for use in a non-volatile information recording/reproduction system having a high recording density, the device including a resistive material having less phase separation or the like during switching. This disclosure also provides an information recording/reproduction system including the device. This disclosure provides an information recording device including: a pair of electrodes; and a recording layer between the electrodes, the recording layer recording information by its resistance change, the recording layer including at least one of (a) M | 2011-02-17 |
20110037045 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile memory device includes a substrate, a first electrode, a second electrode, and a memory. The first electrode is provided on the substrate. The second electrode crosses on the first electrode. The memory portion is provided between the first electrode and the second electrode. At least one of an area of a first memory portion surface of the memory portion opposed to the first electrode and an area of a second memory portion surface of the memory portion opposed to the second electrode is smaller than an area of a cross surface of the first electrode and the second electrode opposed to each other by the crossing. | 2011-02-17 |
20110037046 | RESISTANCE-CHANGE MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a resistance-change memory includes a laminated structure in which a lower electrode, an insulating film and an upper electrode are stacked, and a resistance-change film provided on a side surface of the laminated structure, and configured to store data in accordance with an electric resistance change. | 2011-02-17 |
20110037047 | PROGRAMMABLE METALLIZATION CELLS AND METHODS OF FORMING THE SAME - A programmable metallization cell (PMC) that includes an active electrode; a nanoporous layer disposed on the active electrode, the nanoporous layer comprising a plurality of nanopores and a dielectric material; and an inert electrode disposed on the nanoporous layer. Other embodiments include forming the active electrode from silver iodide, copper iodide, silver sulfide, copper sulfide, silver selenide, or copper selenide and applying a positive bias to the active electrode that causes silver or copper to migrate into the nanopores. Methods of formation are also disclosed. | 2011-02-17 |
20110037048 | Composition Comprising Rare-earth Dielectric - Compositions comprising a single-phase rare-earth dielectric disposed on a substrate. Embodiments of the present invention provide the basis for high-K gate dielectrics in conventional integrated circuits and high-K buried dielectrics as part of a semiconductor-on-insulator wafer structure. | 2011-02-17 |
20110037049 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - Disclosed is a nitride semiconductor light-emitting device including a substrate, a pair of p-type and n-type clad layers formed on the substrate, and an active layer having a single quantum well structure or a multiple quantum well structure, which is sandwiched between the p-type clad layer and the n-type clad layer, and includes a quantum well layer and a pair of barrier layers each having a larger bandgap than that of the quantum well layer, the quantum well layer being sandwiched between the pair of barrier layers. Each of the pair of barrier layers has a multi-layer structure including, starting from the quantum well layer side, a first subbarrier layer having a composition of In | 2011-02-17 |
20110037050 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - A light emitting device (LED) includes a light emitting structure and a reflective layer. The light emitting structure includes a semiconductor layer of a first conductivity type, a light emitting layer, and a semiconductor layer of a second conductivity type, and the reflective layer is provided adjacent to the semiconductor layer of the second conductivity-type. The light emitting layer includes multiple quantum wells, and a distance between adjacent quantum wells is about λ/2n±Δ, where λ represents a wavelength of emitted light, n represents an average refractive index of a medium disposed between the reflective layer and the light emitting layer, and Δ≦λ/8n. | 2011-02-17 |
20110037051 | OPTIMIZATION OF POLISHING STOP DESIGN - The present invention provides a method of fabricating vertical LED structures in which the substrate used for epitaxial layer growth is removed through polishing. The polishing technique used in an exemplary embodiment is chemical mechanical polishing using polish stops to provide a sufficiently level plane. Polish stops are provided in the multilayer structure before polishing the surface, the hardness of the polish stop material being greater than the hardness of the material that needs to be removed. Consequently, vertical LEDs can be produced at a lower cost and higher yield compared to either laser lift-off or conventional polishing. Exemplary vertical LEDs are GaN LEDs. The polish stops may be removed by saw dicing, laser dicing or plasma etching. | 2011-02-17 |
20110037052 | METALORGANIC CHEMICAL VAPOR DEPOSITION (MOCVD) GROWTH OF HIGH PERFORMANCE NON-POLAR III-NITRIDE OPTICAL DEVICES - A method of device growth and p-contact processing that produces improved performance for non-polar III-nitride light emitting diodes and laser diodes. Key components using a low defect density substrate or template, thick quantum wells, a low temperature p-type III-nitride growth technique, and a transparent conducting oxide for the electrodes. | 2011-02-17 |
20110037053 | HIGH QUANTUM EFFICIENCY LIGHTING DEVICE WITH LIGHT INFLUENCING ELEMENT - The present invention relates to a high quantum efficiency lighting device comprising a solid state light source ( | 2011-02-17 |
20110037054 | AMOLED WITH CASCADED OLED STRUCTURES - An active matrix organic light emitting display includes a plurality of pixels with each pixel including at least one organic light emitting diode circuit. Each diode circuit producing a predetermined amount of light lm in response to power W applied to the circuit and including n organic light emitting diodes cascaded in series so as to increase voltage dropped across the cascaded diodes by the factor of n, where n is an integer greater than one. Each diode of the n organic light emitting diodes produces approximately 1/n of the predetermined amount of light lm so as to reduce current flowing in the diodes by 1/n. The organic light emitting diode circuit of each pixel includes a thin film transistor current driver with the cascaded diodes connected in the source/drain circuit so the current driver provides the current flowing in the diodes. | 2011-02-17 |
20110037055 | Flexible Optoelectronic Device Having Inverted Electrode Structure and Method for Making the same - A flexible optoelectronic device having inverted electrode structure is disclosed. The flexible optoelectronic device having inverted electrode structure includes a flexible plastic substrate having a cathode structure, an n-type oxide semiconductor layer, an organic layer, and an anode. The n-type oxide semiconductor layer is disposed on the cathode structure. The organic layer is disposed on the n-type oxide semiconductor layer. The anode is electrically connected with the organic layer. | 2011-02-17 |
20110037056 | PHOTOACTIVE COMPOSITION AND ELECTRONIC DEVICE MADE WITH THE COMPOSITION - There is provided a photoactive composition including: (a) a first host material having a HOMO energy level shallower than or equal to −5.6 eV and having a Tg greater than 95° C.; (b) a second host material having a LUMO deeper than −2.0 eV; and (c) an electroluminescent dopant material. The weight ratio of first host material to second host material is in the range of 99:1 to 1.5:1. | 2011-02-17 |
20110037057 | DEUTERATED COMPOUNDS FOR ELECTRONIC APPLICATIONS - This invention relates to deuterated aryl-anthracene compounds that are useful in electronic applications. It also relates to electronic devices in which the active layer includes such a deuterated compound. | 2011-02-17 |
20110037058 | OPTOELECTRONIC DEVICE - The present invention relates to an opto-electronic device comprising a layer comprising a polymer containing fluorine-containing groups, where an adhesive fluorine-fluorine interaction exists at least between some of the fluorine-containing groups of the layer. The invention is furthermore directed to the use of the opto-electronic device and to a process for the production thereof. | 2011-02-17 |
20110037059 | ELECTRO-OPTIC APPARATUS, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING ELECTRO-OPTIC APPARATUS - An electro-optic apparatus has an electro-optic panel, driver semiconductor chips bonded onto the terminal portion of the electro-optic panel, and two protection films either or both of which are transparent, wherein the electro-optic panel is sealed by being sandwiched between the two protection films, and one protection film that covers the terminal portion has openings for exposing the driver semiconductor chips. | 2011-02-17 |
20110037060 | ORGANIC LIGHT EMITTING DEVICE - Embodiments of the present invention are directed to a heterocyclic compound and an organic light-emitting device including the heterocyclic compound. The organic light-emitting devices using the heterocyclic compounds have high-efficiency, low driving voltage, high luminance and long lifespan. | 2011-02-17 |
20110037061 | Light Emitting Device, Electronic Equipment and Apparatus For Manufacturing the Same - To provide an aspect of a novel display device using a light emitting element which is composed of a cathode, an EL layer and an anode, and a manufacturing device of the display device. According to the present invention, dual-sided emission display can be performed in one sheet white color light emitting panel | 2011-02-17 |
20110037062 | ORGANIC ELECTROLUMINESCENT DEVICE - Disclosed is an organic electroluminescent device (organic EL device) which can achieve high efficiency and long lifetime even when driven at low voltage. The organic El device comprises at least a light-emitting layer and an electron-transporting layer between an anode and a cathode facing each other. The electron-transporting layer consists of two layers, namely, a first electron-transporting layer and a second electron-transporting layer and the first electron-transporting layer and the second electron-transporting layer are arranged sequentially in this order from the light-emitting layer side to the cathode side. The first electron-transporting layer contains an indole derivative in which the ring nitrogen atom is substituted with an aromatic group and an aromatic ring is fused to the indole ring. | 2011-02-17 |
20110037063 | NOVEL MATERILS FOR ORGANIC ELECTROLUMINESCENCE DEVICE - The present invention relates to a compound of the formula (1) and (2) | 2011-02-17 |
20110037064 | ELECTRONIC DEVICE - The invention relates to an organic electronic (OE) device, in particular a transistor, comprising an interlayer between the gate insulator and the gate electrode, to novel processes for preparing the device, and to dielectric materials for use in the interlayer. | 2011-02-17 |
20110037065 | DEVICE COMPRISING POSITIVE HOLE INJECTION TRANSPORT LAYER, METHOD FOR PRODUCING THE SAME AND INK FOR FORMING POSITIVE HOLE INJECTION TRANSPORT LAYER - A device having an easy production process and capable of achieving a long lifetime. The device has a substrate, two or more electrodes facing each other disposed on the substrate and a positive hole injection transport layer disposed between two electrodes among the two or more electrodes. The positive hole injection transport layer contains a reaction product of a molybdenum complex or tungsten complex. | 2011-02-17 |
20110037066 | ORGANIC PHOTOELECTRIC CONVERSION ELEMENT AND MANUFACTURING METHOD THEREOF - An organic photoelectric conversion element comprising a plurality of active layers and a junction positioned between the active layers which are laminated between a pair of electrodes, wherein the junction is formed from a plurality of layers including a positive hole transport layer, and the positive hole transport layer is formed first by a coating method when the junction is formed. | 2011-02-17 |
20110037067 | ZNO-GROUP SEMICONDUCTOR ELEMENT - Provided is a ZnO-based semiconductor device in which flat ZnO-based semiconductor layers can be grown on a MgZnO substrate having a laminate-side principal surface including a C-plane. With an Mg | 2011-02-17 |
20110037068 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - One object is to provide a semiconductor device with a structure which enables reduction in parasitic capacitance sufficiently between wirings. In a bottom-gate type thin film transistor including a stacked layer of a first layer which is a metal thin film oxidized partly or entirely and an oxide semiconductor layer, the following oxide insulating layers are formed together: an oxide insulating layer serving as a channel protective layer which is over and in contact with a part of the oxide semiconductor layer overlapping with a gate electrode layer; and an oxide insulating layer which covers a peripheral portion and a side surface of the stacked oxide semiconductor layer. | 2011-02-17 |
20110037069 | METHOD AND APPARATUS FOR VISUALLY DETERMINING ETCH DEPTH - Etch depth of a material in a semiconductor wafer may be determined by forming a production region and a test region of the wafer, the test region having a test pattern for determining etch depth on a the wafer. The semiconductor wafer is comprised of a base layer, an intermediate layer above and visually distinguishable from the base layer, and a mask of photoresist material formed atop the intermediate layer. The mask of photoresist material has an areal photoresist coverage that varies across a horizontal axis. When the wafer is etched, a visible boundary can be seen between a region where the intermediate layer has been entirely etched away, and a region where at least some of the intermediate layer remains. The horizontal position of this visible boundary corresponds to the vertical etch depth in the production region., after etching of the semiconductor wafer. | 2011-02-17 |
20110037070 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor substrate includes a substrate including a display area and a peripheral area surrounding the display area, gate lines formed on the substrate including gate electrodes, an auxiliary insulating layer formed on the gate lines, a gate insulating layer formed on the auxiliary insulating layer and the gate lines, a semiconductor layer formed on the gate insulating layer, data lines formed on the semiconductor layer including source electrodes and drain electrodes, a passivation layer formed on the data lines, pixel electrodes formed on the passivation layer and electrically connected to the drain electrode, wherein the boundary line of the auxiliary insulating layer is located at or within the boundary of the gate line. | 2011-02-17 |
20110037071 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes: a pixel including a plurality of light emitting elements each formed by sequentially stacking a first electrode layer, an organic layer, and a second electrode layer, spaced apart from each other in a first direction orthogonal to the stacking direction thereof, and emitting light emission colors different from each other; and an auxiliary wiring layer electrically connected to the second electrode layer. A plurality of the pixels are aligned in the first direction so as to include a gap which is larger than a gap between the light emitting elements adjacent to each other, and the auxiliary wiring layer is provided between the pixels adjacent to each other. | 2011-02-17 |
20110037072 | MULTILAYER WIRING, SEMICONDUCTOR DEVICE, SUBSTRATE FOR DISPLAY AND DISPLAY DEVICE - The present invention provides a multilayer wiring capable of reducing the area of the wiring layer while preventing the property deterioration due to the parasitic capacitance, a semiconductor device, a substrate for display device, and a display device. The multilayer wiring of the present invention includes: a first conductor; a second conductor; and a third conductor. The first conductor is positioned in a (n+1)th conductive layer. The second conductor is positioned in a (n+2)th conductive layer, is electrically connected to a conductor in a layer below the (n+1)th conductive layer through at least a first connection hole in a (n+1)th insulating layer directly below the (n+2)th conductive layer, and is positioned so as not to overlap with the first conductor in a plan view of the main face of the substrate. The third conductor is positioned in a (n+3)th conductive layer, is electrically connected to a second conductor through a second connection hole in a (n+2)th insulating layer directly below the (n+3)th conductive layer, and is positioned on the second connection hole toward the first conductor. The second connection hole overlaps with the first connection hole in a plan view of the main face of the substrate. | 2011-02-17 |
20110037073 | METHODS OF FABRICATING THIN FILM TRANSISTOR AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING THE SAME - A thin film transistor (TFT), an OLED device having the TFT and a method of fabricating the same and a method of fabricating an organic light emitting diode (OLED) display device that includes the TFT. The method of fabricating a TFT includes providing a substrate, forming a buffer layer on the substrate, forming an amorphous silicon layer pattern on the buffer layer, forming a metal layer on an entire surface of the substrate, forming a semiconductor layer by applying an electrical field to the metal layer to crystallize the amorphous silicon layer pattern, forming source and drain electrodes connected to the semiconductor layer by patterning the metal layer, forming a gate insulating layer on the entire surface of the substrate, forming a gate electrode on the gate insulating layer to correspond to the semiconductor layer and forming a protective layer on the entire surface of the substrate. | 2011-02-17 |
20110037074 | Thin film transistor method of fabricating the same, and organic light emitting diode dislplay device having the same - A thin film transistor includes a substrate, a buffer layer on the substrate, a semiconductor layer on the buffer layer, source and drain electrodes directly on the semiconductor layer, each of the source and drain electrodes including at least one hole therethrough, a gate insulating layer on the substrate, and a gate electrode on the gate insulating layer and corresponding to the semiconductor layer. | 2011-02-17 |
20110037075 | PROCESS FOR FABRICATING A STRUCTURE FOR EPITAXY WITHOUT AN EXCLUSION ZONE - A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone. The process includes at least one step of wafer bonding the crystalline growth seed layer directly onto the support substrate and at least one step of thinning the crystalline growth seed layer. After thinning, the crystalline growth seed layer has a diameter identical to its initial diameter. | 2011-02-17 |
20110037076 | DIAMOND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention is contemplated for providing a diamond semiconductor device where an impurity-doped diamond semiconductor is buried in a selected area, and a method of manufacturing the same. | 2011-02-17 |
20110037077 | LIGHT DETECTING CHIP AND LIGHT DETECTING DEVICE PROVIDED WITH LIGHT DETECTING CHIP - A light detecting chip includes at least one detection region configured to accommodate a sample that is capable of emitting fluorescent light, and a light reflecting section configured to reflect at least a portion of the fluorescent light emitted from the sample in a direction toward a light detector. | 2011-02-17 |
20110037078 | OPTICAL INTERCONNECTION DEVICE - Provided is an optical interconnection device. The optical interconnection device include: a first semiconductor chip disposed on a germanium-on-insulator (GOI) substrate; a light emitter on the GOI substrate, the light emitter receiving an electrical signal from the first semiconductor chip and outputting a light signal; a light detector on the GOI substrate, the light detector sensing the light signal and converting the sensed light signal into an electrical signal; and a second semiconductor chip on the GOI substrate, the second semiconductor chip receiving the electrical signal from the light detector. | 2011-02-17 |
20110037079 | Structure and method for fabricating fluorescent powder gel light emitting module - The present invention relates to a structure and a method for fabricating a fluorescent powder gel light emitting module. A circuit is arranged on a surface of the circuit board, and a plurality of wire connection points is arranged thereon for providing the electrical connection to the electronic components and the light emitting diodes respectively with the circuit board. A plastic ring is formed on an outer portion of the light emitting diodes on the surface of the circuit board to form a specific region and coat the fluorescent powder gel onto the surface of the circuit board in the specific region between every visible light emitting face of the plurality of light emitting diodes and the adjacent region of every light emitting diode, and further to bake for forming a light emitting module to produce light overlapping region by the side light between every adjacent light emitting diode to further produce an extended light source plane to effectively gain a high light emitting efficiency, higher brightness and even irradiation of the radiated light. | 2011-02-17 |
20110037080 | METHODS FOR COMBINING LIGHT EMITTING DEVICES IN A PACKAGE AND PACKAGES INCLUDING COMBINED LIGHT EMITTING DEVICES - Methods of forming a light emitting device package assembly include defining a chromaticity region in a two dimensional chromaticity space within a 10-step MacAdam ellipse of a target chromaticity point, and subdividing the defined chromaticity region into at least three chromaticity subregions, providing a plurality of light emitting devices that emit light having a chromaticity that falls within the defined chromaticity region, selecting at least three of the plurality of light emitting devices, wherein each of the three light emitting devices emits light from a different one of the chromaticity subregions. The at least three light emitting devices are selected from chromaticity subregions that are complementary relative to the target chromaticity point to at least one other chromaticity subregion from which a light emitting device is selected. | 2011-02-17 |
20110037081 | WHITE LIGHT-EMITTING DIODE PACKAGES WITH TUNABLE COLOR TEMPERATURE - A white light-emitting diode package with tunable color temperature is provided, including a package substrate with a first light emitting diode (first LED) disposed over a first portion of the substrate and a second light emitting diode (second LED) disposed over a second portion different from the first portion of the substrate. A phosphor layer is coated around the first and second LED, wherein the phosphor layer is formed by blending at least one colored phosphor grain with a transparent optical resin, and the at least one colored phosphor grain in the transparent optical resin is excited by light from the first and second LED to react and emit white light. In one embodiment, the first and second LED are both blue LEDs for emitting blue light of different wavelengths or ultraviolet (UV) LEDs for emitting UV light of different wavelengths. | 2011-02-17 |
20110037082 | Smart Integrated Semiconductor Light Emitting System Including Light Emitting Diodes And Application Specific Integrated Circuits (ASIC) - A light emitting diode (LED) system includes a substrate, an application specific integrated circuit (ASIC) on the substrate, and at least one light emitting diode (LED) on the substrate in electrical communication with the application specific integrated circuit (ASIC). The light emitting diode (LED) system can also include a polymer lens, and a phosphor layer on the lens or light emitting diode (LED) for producing white light. In addition, multiple light emitting diodes (LEDs) can be mounted on the substrate, and can have different colors for smart color control lighting. The substrate and the application specific integrated circuit (ASIC) are configured to provide an integrated system having smart functionality. In addition, the substrate is configured to compliment and expand the functions of the application specific integrated circuit (ASIC), and can also include built in integrated circuits for performing additional electrical functions. | 2011-02-17 |
20110037083 | LED PACKAGE WITH CONTRASTING FACE - LED packages and LED displays utilizing the LED packages are disclosed, with the LED packages arranged to provide good contrast between the different pixels in an LED display while not reducing the perceived luminous flux or brightness of the display. One embodiment of an LED package comprises an LED chip and conversion material arranged to convert at least some light emitted from the LED chip. The package emits light from the conversion material or a combination of light from the conversion material and the LED chip. A reflective area is included around the LED chip that substantially reflects the package light and a contrasting area is included outside the reflective area and has a color that contrasts with the package light. LED displays according to the present invention comprise a plurality of LED packages arranged in relation to one another to produce messages or images, with the package providing improved pixel contrast. | 2011-02-17 |
20110037084 | LENS-MOUNTED LIGHT EMITTING UNIT - In a lens-mounted light emitting unit comprising LED elements of multiple light colors, narrow-angle light distribution is enabled, and color mixing properties are improved. The lens-mounted light emitting unit | 2011-02-17 |
20110037085 | THIN P-TYPE GALLIUM NITRIDE AND ALUMINUM GALLIUM NITRIDE ELECTRON-BLOCKING LAYER FREE GALLIUM NITRIDE-BASED LIGHT EMITTING DIODES - A light emitting diode (LED) having a p-type layer having a thickness of 100 nm or less, an n-type layer, and an active layer, positioned between the p-type layer and the n-type layer, for emitting light, wherein the LED does not include a separate electron blocking layer. | 2011-02-17 |
20110037086 | NITRIDE BASED SEMICONDUCTOR LIGHT-EMITTING DEVICE - Disclosed herein is a nitride-based semiconductor light-emitting device. The nitride-based semiconductor light-emitting device comprises an n-type clad layer made of n-type Al | 2011-02-17 |
20110037087 | COMPOUND SEMICONDUCTOR LIGHT-EMITTING DIODE AND METHOD FOR FABRICATION THEREOF - A compound semiconductor light-emitting diode includes a light-emitting layer ( | 2011-02-17 |
20110037088 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride-based semiconductor light-emitting device | 2011-02-17 |
20110037089 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride-based semiconductor light-emitting device | 2011-02-17 |
20110037090 | LIGHT EMITTING DIODE - A light emitting diode includes an epitaxial layer, an electroder electrically conductive members, a light incident layer, a light reflecting layer, an adhesive, and an electrically conductive permanent substrate. The epitaxial layer has first and second surfaces. The electrode is disposed on the second surface of the epitaxial layer. The electrically conductive members are formed on the first surface of the epitaxial layer and are spaced apart from each other. The light incident layer is formed on the first surface of the epitaxial layer at regions where none of the electrically conductive members are formed. The light reflecting layer is formed on the light incident layer and the electrically conductive members, and has indented parts and non-indented parts. The adhesive is disposed in the indented parts of the light reflecting layer. The permanent substrate is bonded to the light reflecting layer through the adhesive and through wafer bonding. | 2011-02-17 |
20110037091 | PACKAGE FOR LIGHT EMITTING DIODE, LIGHT EMITTING DEVICE, AND LIGHT EMITTING DEVICE MANUFACTURING METHOD - The present invention relates to a light emitting diode package for mounting a light emitting diode, a light emitting diode device with the light emitting diode package mounting a vertical electrode type light emitting diode thereon and a manufacturing method for manufacturing the light emitting device. | 2011-02-17 |
20110037092 | LIGHT-EMITTING ELEMENT - A light-emitting device includes an n-type semiconductor layer | 2011-02-17 |
20110037093 | LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING ELEMENT FABRICATION METHOD - According to an aspect of the invention, a light-emitting element includes a semiconductor layer, a gold electrode layer, an insulator, a barrier metal layer, and an aluminum wiring layer. The gold electrode layer is formed on a part of the semiconductor layer and is electrically connected to the semiconductor layer. The gold electrode layer being made of metal including gold. The insulator film covers the semiconductor layer and has a contact opening corresponding to the gold electrode layer. The barrier metal layer covers a an upper face of the gold electrode layer and the insulator film in a vicinity of the contact opening. The aluminum wiring layer is formed on the barrier metal layer and electrically connected to the barrier metal layer. | 2011-02-17 |
20110037094 | SEMICONDUCTOR CHIP ASSEMBLY WITH BUMP/BASE HEAT SPREADER AND CAVITY IN BUMP - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a bump, a base and a flange. The conductive trace includes a pad and a terminal. The semiconductor device extends into a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal. | 2011-02-17 |
20110037095 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode (OLED) display includes a display substrate assembly including an organic light emitting structure, an encapsulation substrate assembly disposed facing the display substrate assembly, a sealant disposed between the display substrate assembly and the encapsulation substrate assembly to seal the display substrate assembly and the encapsulation substrate assembly with each other, and a substrate deformation protection body disposed between the sealant and the organic light emitting structure. | 2011-02-17 |
20110037096 | Heterojunction Bipolar Transistors and Methods of Manufacture - Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures. | 2011-02-17 |
20110037097 | EXTENDED WAVELENGTH DIGITAL ALLOY NBN DETECTOR - A strain-balanced photodetector is provided for detecting infrared light at an extended cutoff wavelength in the range of 4.5 μm or more. An InAsSb absorber layer has an Sb content is grown in a lattice-mismatched condition to a GaSb substrate, and a plurality of GaAs strain-compensating layers are interspersed within the absorber layer to balance the strain of the absorber layer due to the lattice mismatch. The strain-compensation layers allow the absorber to achieve a thickness exhibiting sufficient absorption efficiency while extending the cutoff wavelength beyond that possible in a lattice-matched state. Additionally, the strain-compensation layers are sufficiently thin to be substantially quantum-mechanically transparent such that they do not substantially affect the transmission efficiency of the absorber. The photodetector is preferably formed as a majority carrier filter photodetector exhibiting minimal dark current, and may be provided individually or in a focal plane array. | 2011-02-17 |
20110037098 | Substrate structures and methods of manufacturing the same - Substrate structures and methods of manufacturing the substrate structures. A substrate structure is manufactured by forming a protrusion area of a substrate under a buffer layer, and forming a semiconductor layer on the buffer layer, thereby separating the substrate from the buffer layer except in an area where the protrusion is formed. The semiconductor layer on the buffer layer not contacting the substrate has freestanding characteristics, and dislocation or cracks may be reduced and/or prevented. | 2011-02-17 |
20110037099 | SEMICONDUCTOR WAFER, SEMICONDUCTOR WAFER MANUFACTURING METHOD, AND ELECTRONIC DEVICE - A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; a Ge layer that is crystal-grown on the wafer and shaped as an isolated island; a butler layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be shaped as an island having a size that does not exceed double a distance moved by crystal defects as a result of annealing the Ge layer at a certain temperature for a certain time. The Ge layer may be shaped as an island having a size for which stress due to a difference relative to a thermal expansion coefficient of Si, which is material of the wafer, does not cause crystal defects when the Ge layer is annealed at a certain temperature. | 2011-02-17 |
20110037100 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride semiconductor device includes: first through third nitride semiconductor layers formed in sequence over a substrate. The second nitride semiconductor layer has a band gap energy larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer has an opening. A p-type fourth nitride semiconductor layer is formed so that the opening is filled therewith. A gate electrode is formed on the fourth nitride semiconductor layer. | 2011-02-17 |
20110037101 | SEMICONDUCTOR DEVICE - A semiconductor device includes an undoped GaN layer ( | 2011-02-17 |
20110037102 | HYBRID PLASMA-SEMICONDUCTOR OPTOELECTRONIC DEVICES AND TRANSISTORS - The invention provides combination semiconductor and plasma devices, including transistors and phototransistors. A preferred embodiment hybrid plasma semiconductor device has active solid state semiconductor regions; and a plasma generated in proximity to the active solid state semiconductor regions. Devices of the invention are referred to as hybrid plasma-semiconductor devices, in which a plasma, preferably a microplasma, cooperates with conventional solid state semiconductor device regions to influence or perform a semiconducting function, such as that provided by a transistor. The invention provides a family of hybrid plasma electronic/photonic devices having properties previously unavailable. In transistor devices of the invention, a low temperature, glow discharge is integral to the hybrid transistor. Example preferred devices include hybrid BJT and MOSFET devices. | 2011-02-17 |
20110037103 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To improve performance of a semiconductor device. Over a semiconductor substrate, a plurality of p-channel type MISFETs for logic, a plurality of n-channel type MISFETs for logic, a plurality of p-channel type MISFETs for memory, and a plurality of n-channel type MISFETs for memory are mixedly mounted. At least a part of the p-channel type MISFETs for logic have each a source/drain region constituted by silicon-germanium, and all the n-channel type MISFETs for logic have each a source/drain region constituted by silicon. All the p-channel type MISFETs for memory have each a source/drain region constituted by silicon, and all the n-channel type MISFETs for memory have each a source/drain region constituted by silicon. | 2011-02-17 |
20110037104 | VERTICAL SPACER FORMING AND RELATED TRANSISTOR - Methods include, for example, forming a vertically disposed active region on a substrate; forming a first gate over a portion of the vertically disposed active region; forming a dielectric over the portion; exposing an upper surface of the first gate; forming a second gate over the upper surface; and forming a spacer pocket region between the vertically disposed active region, the first gate and the dielectric, wherein the spacer pocket region is self-aligned to a lower surface of the second gate and has a substantially uniform thickness from an upper to a lower extent thereof. | 2011-02-17 |
20110037105 | SELF-ALIGNED SELECTIVE METAL CONTACT TO SOURCE/DRAIN DIFFUSION REGION - A transistor structure includes a semiconductor substrate with a first surface, a diffusion region at the first surface of the substrate, a sacrificial gate formed on the diffusion region, and insulating side walls formed adjacent to the sacrificial gate. A metal gate is formed by etching out the sacrificial gate and filling in the space between the insulating side walls with gate metals. Silicided source and drain contacts are formed over the diffusion region between the side walls of two adjacent aluminum gates. One or more oxide layers are formed over the substrate. Vias are formed in the oxide layers by plasma etching to expose the silicided source and drain contacts, which simultaneously oxidizes the aluminum gate metal. A first metal is selectively formed over the silicided contact by electroless deposition, but does not deposit on the oxidized aluminum gate. | 2011-02-17 |
20110037106 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor device improves a Schottky-barrier field-effect transistor. In a semiconductor device including a gate electrode formed with interposition of a gate insulating film on a channel formed on a semiconductor substrate, and a Schottky source/drain formed within a top surface of the substrate to be positioned on both sides of the gate insulating film so that end portions of the Schottky source and the Schottky drain do not cover a lower end portion of the gate insulating film and so as to form Schottky junctions with the semiconductor substrate, a Schottky barrier height at an interface between the end portion of the Schottky source and the semiconductor substrate and a Schottky barrier height at an interface between the end portion of the Schottky drain and the semiconductor substrate are different from Schottky barrier heights at interfaces between portions except the end portions of the Schottky source/drain and the substrate. | 2011-02-17 |
20110037107 | Silicon Photon Detector - A silicon photon detector device and methodology are provided for detecting incident photons in a partially depleted floating body SOI field-effect transistor ( | 2011-02-17 |
20110037108 | MAGNETORESISTIVE MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a magnetoresistive memory includes first and second contact plugs in a first interlayer insulating film, a lower electrode on the first interlayer insulating film, a magnetoresistive effect element on the lower electrode, and an upper electrode on the magnetoresistive effect element. The lower electrode has a tapered cross-sectional shape in which a dimension of a bottom surface of the lower electrode is longer than a dimension of an upper surface of the lower electrode, one end of the lower electrode is in contact with an upper surface of the first contact plug. The magnetoresistive effect element is provided at a position shifted from a position immediately above the first contact plug in a direction parallel to a surface of the semiconductor substrate. | 2011-02-17 |
20110037109 | SEMICONDUCTOR DEVICES INCLUDING LOWER AND UPPER DEVICE ISOLATION PATTERNS - In some embodiments, a semiconductor substrate includes trenches defining active regions. The semiconductor device further includes lower and upper device isolation patterns disposed in the trenches. An intergate insulation pattern and a control gate electrode are disposed on the semiconductor substrate to cross over the active regions. A charge storage electrode is between the control gate electrode and the active regions. A gate insulation pattern is between the charge storage electrode and the active regions, and the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions. | 2011-02-17 |
20110037110 | CAPACITOR AND METHOD FOR FABRICATIONG THE SAME, AND SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The semiconductor device comprises a device isolation region | 2011-02-17 |
20110037111 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The invention relates to a semiconductor device and a method of fabricating the same, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resistance, and the SAC process is eliminated at the time of the bit line formation. A method of fabricating a semiconductor device according to the invention comprises: forming a device isolation film for defining a multiplicity of active regions in a semiconductor substrate; forming a multiplicity of buried word lines in the semiconductor substrate; forming a storage node contact hole for exposing a storage node contact region of two adjoining active regions; filling the storage node contact hole with a storage node contact plug material; forming a bit-line groove for exposing a bit-line contact region of the active region and splitting the storage node contact plug material into two; and burying the bit line into the bit-line groove. | 2011-02-17 |
20110037112 | NONVOLATILE MEMORY DEVICES WITH OBLIQUE CHARGE STORAGE REGIONS AND METHODS OF FORMING THE SAME - A nonvolatile memory device includes an active region defined by a device isolation layer in a semiconductor substrate, a word line passing over the active region and a charge storage region defined by a crossing of the active region and the word line and disposed between the active region and the word line. The charge storage region is disposed at an oblique angle with respect to the word line. | 2011-02-17 |
20110037113 | SEMICONDUCTOR STRUTURE AND METHOD OF FORMING THE SAME - A semiconductor structure including a substrate, at least one power MOSFET, a floating diode or a body diode, and at least one Schottky diode is provided. The substrate has a first area, a second area and a third area. The second area is between the first area and the third area. The at least one power MOSFET is in the first area. The floating diode or the body diode is in the second area. The at least one Schottky diode is in the third area. Further, the contact plugs of the power MOSFET and the Schottky diode include tungsten and are electronically connected to each other. | 2011-02-17 |
20110037114 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is formed to include: a substrate; a floating gate formed on the substrate via a gate insulating film; a control gate formed on an adjacent position to the floating gate via a tunnel insulating film; a spacer insulating film formed on the floating gate; and a protection film formed between the spacer insulating film and the control gate. In such a semiconductor memory device (MC), the protection film functions as a stopper of a side surface of the spacer insulating film when a part other than the spacer insulating film is etched. | 2011-02-17 |
20110037115 | SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE - A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench. | 2011-02-17 |
20110037116 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The method of manufacturing a semiconductor device, including a first region where a transistor including a gate electrode of a stacked structure is formed, a second region where a transistor including a gate electrode of a single-layer structure is formed, and a third region positioned in a boundary part between the first region and the second region, includes: depositing a first conductive film, patterning the first conductive film in the first region and the third region so that the outer edge is positioned in the third region, depositing the second conductive film, patterning the second conductive film to form a control gate in the first region while leaving the second conductive film, covering the second region and having the inner edge positioned inner of the outer edge of the first conductive film, and patterning the second conductive film in the second region to form the gate electrode. | 2011-02-17 |
20110037117 | LANTHANUM-METAL OXIDE DIELECTRIC APPARATUS, METHODS, AND SYSTEMS - Lanthanum-metal oxide dielectrics and methods of fabricating such dielectrics provide an insulating layer in a variety of structures for use in a wide range of electronic devices and systems. In an embodiment, a lanthanum-metal oxide dielectric is formed using a trisethylcyclopentadionatolanthanum precursor and/or a trisdipyvaloylmethanatolanthanum precursor. Additional apparatus, systems, and methods are disclosed. | 2011-02-17 |
20110037118 | Nonvolatile memory device having cell and peripheral regions and method of making the same - A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance. | 2011-02-17 |
20110037119 | MEMORY - A memory includes: a semiconductor substrate ( | 2011-02-17 |
20110037120 | Shielded gate trench MOSFET device and fabrication - A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode. | 2011-02-17 |
20110037121 | INPUT/OUTPUT ELECTROSTATIC DISCHARGE DEVICE WITH REDUCED JUNCTION BREAKDOWN VOLTAGE - An I/O electrostatic discharge (ESD) device having a gate electrode over a substrate, a gate dielectric layer between the gate electrode and the substrate, a pair of sidewall spacers respectively disposed on two opposite sidewalls of the gate electrode, a first lightly doped drain (LDD) region disposed under one of the sidewall spacers, a source region disposed next to the first LDD region, a second LDD region disposed under the other sidewall spacer, and a drain region disposed next to the second LDD region, wherein a doping concentration of the second LDD region is larger than a doping concentration of the first LDD region. | 2011-02-17 |
20110037122 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor fabrication process according to the present invention defines an auxiliary structure with a plurality of spaces with a predetermined line-width in the oxide layer to prevent the conductive material in the spaces from being removed by etching or defined an auxiliary structure to rise the conductive structure so as to have the conductive structure being exposed by chemical mechanical polishing. Thus, the transmitting circuit can be defined without requiring an additional mask. Hence, the semiconductor fabrication process can reduce the number of required masks to lower the cost. | 2011-02-17 |
20110037123 | SOI SUBSTRATE AND MANUFACTURING METHOD OF THE SAME, AND SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor substrate is provided, in which a bonding strength can be increased even when a substrate having low heat resistant temperature, e.g., a glass substrate, is used. Heat treatment is conducted at a temperature higher than or equal to a strain point of a support substrate in an oxidation atmosphere containing halogen, so that a surface of a semiconductor substrate is covered with an insulating film. A separation layer is formed in the semiconductor substrate. A blocking layer is provided. Then, heat treatment is conducted in a state in which the semiconductor substrate and the support substrate are superposed with the silicon oxide film therebetween, at a temperature lower than or equal to the support substrate, so that a part of the semiconductor substrate is separated at the separation layer. In this manner, a single crystal semiconductor layer is formed on the support substrate. | 2011-02-17 |
20110037124 | THIN FILM TRANSISTOR - The present disclosure provides a thin film transistor which includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The semiconducting layer is electrically connected with the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by the insulating layer. At least one of the gate electrode, the drain electrode, the source electrode includes a carbon nanotube composite layer. | 2011-02-17 |
20110037125 | EXTREMELY THIN SILICON ON INSULATOR (ETSOI) COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) WITH IN-SITU DOPED SOURCE AND DRAIN REGIONS FORMED BY A SINGLE MASK - A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions. | 2011-02-17 |
20110037126 | SEMICONDUCTOR ARRANGEMENT INCLUDING A LOAD TRANSISTOR AND SENSE TRANSISTOR - A semiconductor arrangement including a load transistor and a sense transistor that are integrated in a semiconductor body. One embodiment provides a number of transistor cells integrated in the semiconductor body, each transistor cell including a first active transistor region. A number of first contact electrodes, each of the contact electrodes contacting the first active transistor regions through contact plugs. A second contact electrode contacts a first group of the first contact electrodes, but not contacting a second group of the first contact electrodes. The transistor cells being contacted by first contact electrodes of the first group form a load transistor, with the second electrode forming a load terminal of the load transistor. The transistor cells being contacted by first contact electrodes of the second group form a sense transistor. | 2011-02-17 |
20110037127 | CMOS INTEGRATED CIRCUIT - A MOS integrated circuit including an N-type silicide MOS transistor, an N-type non-silicide MOS transistor simultaneously formed with the N-type silicide MOS transistor, and an isolation film having an N conductivity type impurity formed on the N-type non-silicide MOS transistor. | 2011-02-17 |
20110037128 | METHOD AND STRUCTURE FOR IMPROVING UNIFORMITY OF PASSIVE DEVICES IN METAL GATE TECHNOLOGY - Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers from the logic region; applying a second layer of silicon on the semiconductor substrate such that the logic region has layers of high K material, metal gate and second silicon and the STI region has layers of high K material, metal gate, first silicon, hardmask and second silicon. There may also be a second hardmask layer between the metal gate layer and the first silicon layer in the STI region. There may also be a hardmask layer between the metal gate layer and the first silicon layer in the STI region but no hardmask layer between the first and second layers of silicon in the STI region. | 2011-02-17 |
20110037129 | Semiconductor Device Having Multiple Fin Heights - A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal. | 2011-02-17 |