07th week of 2012 patent applcation highlights part 14 |
Patent application number | Title | Published |
20120037910 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes; a gate pattern including a gate electrode disposed on a substrate, a gate insulation layer disposed on the substrate and the gate pattern, an insulation pattern including; a first thickness part disposed on a first area of the gate insulation layer overlapping the gate electrode and a second thickness part disposed on a second area of the gate insulation layer adjacent to the first area, an oxide semiconductor pattern disposed on the first thickness part of the first area, an etch stopper disposed on the oxide semiconductor pattern, a source pattern including a source electrode and a drain electrode which contact the oxide semiconductor pattern, and a pixel electrode which contacts the drain electrode. | 2012-02-16 |
20120037911 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a gate wire formed on an insulating substrate, a semiconductor pattern formed on the gate wire and containing a metal oxynitride compound, and a data wire formed on the semiconductor pattern to cross the gate wire. The semiconductor pattern has a carrier number density ranging from 10 | 2012-02-16 |
20120037912 | VISIBLE SENSING TRANSISTOR, DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A display device includes an infrared sensing transistor and a visible sensing transistor. The visible sensing transistor includes a semiconductor on a substrate; an ohmic contact on the semiconductor; an etch stopping layer on the ohmic contact; a source electrode and a drain electrode on the etch stopping layer; a passivation layer on the source electrode and the drain electrode; and a gate electrode on the passivation layer. The etch stopping layer may be composed of the same material as the source electrode and the drain electrode. The infrared sensing transistor is similar to the visible sensing transistor except the etch stopping layer is absent. | 2012-02-16 |
20120037913 | THIN-FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin-film transistor (TFT) and a method of manufacturing the same are disclosed herein. The TFT may include a gate electrode disposed on an insulating substrate, an insulating layer disposed on the insulating substrate and the gate electrode, an active layer pattern disposed on the insulating layer to overlap the gate electrode, a source electrode disposed on the insulating layer and at least part of which overlaps the active layer pattern, and a drain electrode which is separated from the source electrode and at least part of which overlaps the active layer pattern. A first ohmic contact layer pattern may be disposed between the active layer pattern and the source electrode and between the active layer pattern and the drain electrode. The first ohmic contact layer may have higher nitrogen content on its surface than in other portions of the first ohmic contact layer. | 2012-02-16 |
20120037914 | HETEROJUNCTION BIOPOLAR TRANSISTOR AND MANUFACTURING METHOD - A method of manufacturing a heterojunction bipolar transistor, including providing a substrate comprising an active region bordered by shallow trench insulation regions; depositing a stack of a dielectric layer and a polysilicon layer over the substrate; forming a base window in the stack, the base window extending over the active region and part of the shallow trench insulation regions, the base window having a trench extending vertically between the active region and one of the shallow trench insulation regions; growing an epitaxial base material inside the base window; forming a spacer on the exposed side walls of the base material; and filling the base window with an emitter material. A HBT manufactured in this manner and an IC including such an HBT. | 2012-02-16 |
20120037915 | Method of Making an Organic Thin Film Transistor - A method of forming an organic thin film transistor the method comprising:
| 2012-02-16 |
20120037916 | Organic light-emitting diode display device and method of manufacturing the same - An organic light-emitting diode display device includes a substrate, a display unit on the substrate, a touch unit facing the substrate, and a sealing portion surrounding the display unit. The sealing portion couples the substrate to the touch unit and includes glass frit. The touch unit includes an encapsulation substrate, a first conductive layer on the encapsulation substrate, an insulating layer on a portion of the first conductive layer and the encapsulation substrate, and a second conductive layer on the first conductive layer and the insulating layer. The insulating layer of the touch unit includes an organosilicon compound and has a thermal decomposition temperature of about 360° C. or more. | 2012-02-16 |
20120037917 | LOW INTERCONNECT RESISTANCE INTEGRATED SWITCHES - Circuits and systems comprising one or more switches are provided. A circuit includes a first switch formed on a substrate; and a second switch formed on the substrate, the second switch including a first terminal coupled to a third terminal of the first switch. A system includes a supply; a first switch formed on a substrate, the first switch coupled to the supply; a second switch formed on the substrate, the second switch coupled to the first switch; a third switch formed on the substrate, the third switch coupled to the supply; a fourth switch formed on the substrate, the fourth switch coupled to the third switch; and a driver coupled to respective second terminals of the first, second, third, and fourth switches. | 2012-02-16 |
20120037918 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME - A semiconductor device includes a semiconductor layer ( | 2012-02-16 |
20120037919 | NANOPORE ELECTRICAL SENSOR - A nanopore electrical sensor is provided. The sensor has layered structure, including a substrate ( | 2012-02-16 |
20120037920 | Silicone Carbide Trench Semiconductor Device - A semiconductor device as described herein includes a silicon carbide semiconductor body. A trench extends into the silicon carbide semiconductor body at a first surface. A gate dielectric and a gate electrode are formed within the trench. A body zone of a first conductivity type adjoins to a sidewall of the trench, the body zone being electrically coupled to a contact via a body contact zone including a higher maximum concentration of dopants than the body zone. An extension zone of the first conductivity type is electrically coupled to the contact via the body zone, wherein a maximum concentration of dopants of the extension zone along a vertical direction perpendicular to the first surface is higher than the maximum concentration of dopants of the body zone along the vertical direction. A distance between the first surface and a bottom side of the extension zone is larger than the distance between the first surface and the bottom side of the trench. | 2012-02-16 |
20120037921 | Electrical Devices With Enhanced Electrochemical Activity and Manufacturing Methods Thereof - In some aspects, a device is provided having a member with a region of enhanced electrochemical activity. In one aspect, a sensor of enhanced electrochemical activity is provided for detecting an analyte concentration level in a bio-fluid sample. The sensor may include a sensor member of a semiconductor material wherein the sensor member has a surface region of enhanced electrochemical activity. In other aspects, the member may be made of semiconducting foam having a surface region of enhanced electrochemical activity. In some embodiments, the region may be thermally-induced. Manufacturing methods and apparatus are also provided, as are numerous other aspects. | 2012-02-16 |
20120037922 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method. A semiconductor device includes: a silicon carbide substrate; a first-conductive-type first silicon carbide layer provided on a first principal surface of the silicon carbide substrate; a second-conductive-type first silicon carbide region formed at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region formed at a surface of the first silicon carbide region; a second-conductive-type third silicon carbide region formed below the second silicon carbide region; a trench piercing through the second silicon carbide region to reach the third silicon carbide region; a gate insulating film; a gate electrode; an interlayer insulating film with which the gate electrode is covered; a first electrode that is formed on the second silicon carbide region and the interlayer insulating film in a side surface of the trench while containing a metallic element selected from a group consisting of Ni, Ti, Ta, Mo, and W; a second electrode that is formed on the third silicon carbide region in a bottom portion of the trench and the first electrode while containing Al; a first main electrode formed on the second electrode; and a second main electrode formed on a second principal surface of the silicon carbide substrate. | 2012-02-16 |
20120037923 | LIGHT EMITTING DIODE ELEMENT AND METHOD FOR PRODUCING THE SAME - [PROBLEM] To provide a light emitting diode which can obtain emission at shorter wavelength side of emission range of normal 6H-type SiC doped with B and N, and a method for manufacturing the same. | 2012-02-16 |
20120037924 | Junction Field-Effect Transistor - A junction field-effect transistor ( | 2012-02-16 |
20120037925 | Engineered Substrate for Light Emitting Diodes - A diode substrate including a crystalline aluminum oxide window, a silicon oxide layer on the crystalline aluminum oxide window, and a silicon layer on the silicon oxide layer, the silicon layer being implanted with ions at a predetermined depth. | 2012-02-16 |
20120037926 | SOLID STATE LIGHTS WITH COOLING STRUCTURES - A solid state lighting (SSL) with a solid state emitter (SSE) having thermally conductive projections extending into an air channel, and methods of making and using such SSLs. The thermally conductive projections can be fins, posts, or other structures configured to transfer heat into a fluid medium, such as air. The projections can be electrical contacts between the SSE and a power source. The air channel can be oriented generally vertically such that air in the channel warmed by the SSE flows upward through the channel. | 2012-02-16 |
20120037927 | LIGHT EMITTING DIODE PACKAGE STRUCTURE - A light emitting diode package structure includes a substrate ( | 2012-02-16 |
20120037928 | ANTI-REFLECTION FILM AND FOLDABLE DISPLAY DEVICE EMPLOYING THE SAME - A anti-reflection film includes a light phase delay film which changes a phase of incident light, a polarizing film on the light phase delay film and transmitting light with a polarization component in a particular direction, and a protective film on the polarizing film and protecting the polarizing film. All of the polarizing film, the light phase delay film, and the protective film include flexible materials. | 2012-02-16 |
20120037929 | OPTOELECTRONIC COMPONENT - An optoelectronic component has an optoelectronic semiconductor chip, a contact frame, a contact carrier, a first electrical connection zone and a second electrical connection zone electrically insulated from the first electrical connection zone, which each have a part of the contact frame and a part of the contact carrier, wherein the contact frame has a recess which separates the first electrical connection zone at least in places from the second electrical connection zone and into which the optoelectronic semiconductor chip projects, and wherein the contact frame has a contact element which connects the contact frame electrically with the optoelectronic semiconductor chip. | 2012-02-16 |
20120037930 | METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT, OPTOELECTRONIC COMPONENT, AND COMPONENT ARRANGEMENT HAVING A PLURALITY OF OPTOELECTRONIC COMPONENTS - A method for producing optoelectronic components including A) providing a growth substrate with a semiconductor layer arranged thereon that produces a zone which is active during operation, B) applying separating structures on the semiconductor layer, C) applying a multiplicity of copper layers on the semiconductor layer in regions delimited by the separating structures, D) removing the separating structures, E) applying, a protective layer at least on lateral areas of copper layers, F) applying an auxiliary substrate on the copper layers, G) removing the growth substrate, H) singulating a composite assembly comprising the semiconductor layer, the copper layers and the auxiliary substrate to form components which are separated from one another. | 2012-02-16 |
20120037931 | SEMICONDUCTOR LIGHT EMITTING DEVICES INCLUDING AN OPTICALLY TRANSMISSIVE ELEMENT AND METHODS FOR PACKAGING THE SAME - Methods of packaging a semiconductor light emitting device include dispensing a first quantity of encapsulant material into a cavity including the light emitting device. The first quantity of encapsulant material in the cavity is treated to form a hardened upper surface thereof having a shape. A luminescent conversion element is provided on the upper surface of the treated first quantity of encapsulant material. The luminescent conversion element includes a wavelength conversion material and has a thickness at a middle region of the cavity greater than proximate a sidewall of the cavity. | 2012-02-16 |
20120037932 | Display Device and Driving Method of the Same - A problem in that a light emitting element slightly emits light is solved by an off current of a thin film transistor connected in series to the light emitting element, thereby a display device which can perform a clear display by increasing contrast, and a driving method thereof are provided. When the thin film transistor connected in series to the light emitting element is turned off, a charge held in the capacitance of the light emitting element itself is discharged. Even when an off current is generated at the thin film transistor connected in series to the light emitting element, this off current charges this capacitance until the capacitance of the light emitting element itself holds a predetermined voltage again. Accordingly, the off current of the thin film transistor does not contribute to light emission. In this manner, a slight light emission of the light emitting element can be reduced. | 2012-02-16 |
20120037933 | LIGHT EMITTING DEVICE AND LIGHTING SYSTEM HAVING THE SAME - The present invention provides a light emitting device comprising a first light emitting portion that emits white light at a color temperature of 6000K or more and a second light emitting portion that emits white light at a color temperature of 3000K or less, which include light emitting diode chips and phosphors and are independently driven. The present invention has an advantage in that a light emitting device can be diversely applied in a desired atmosphere and use by realizing white light with different light spectrums and color temperatures. Particularly, the present invention has the effect on health by adjusting the wavelength of light or the color temperature according to the circadian rhythm of humans. | 2012-02-16 |
20120037934 | Pre-molded LED light bulb package - The present invention relates to a pre-molded LED light bulb package with its main improvements being: the chip and gold wire outside the chip cup at the top of the traditional conducting bracket is covered with an appropriate quantity of epoxy resin colloid and then baked to form an oblate spheroid, which is inserted into the mold and filled with injection PC or ordinary resin to rapidly condense into LED enclosure package, wherein the special effect of multiple amplified or integrated light source whereby the light source is amplified internally and then gathered externally can be achieved by means of an internal optical amplifying light source effect through the pre-molded oblate spheroid and the convex or concave structure on the upper part of the external injection molded LED enclosure, significantly improving the existing single lighting deflection technology, therefore reducing the time of the packaging process and increasing the output capacity of mass production significantly. | 2012-02-16 |
20120037935 | Substrate Structure of LED (light emitting diode) Packaging and Method of the same - The present invention provides a substrate for LED packaging and a fabrication method thereof. The substrate can dissipate heat quickly and enhance light emitting efficiency. For this purpose, several via holes are formed in the substrate and metal layers are coated to act as light reflector. In the substrate, the via holes are filled with the material with high thermal conductivity, such as Copper, to conduct the heat efficiently; and the reflector are coated the metal with high reflection factor to visible light, such as Ag, Au, Al, to enhance the light emitting efficiency. | 2012-02-16 |
20120037936 | LED PACKAGE - A LED package includes a substrate, at least one LED chip, a transparent adhesive and a lens. The at least one LED chip is mounted on the substrate. The transparent adhesive is filled between the LED chip and the lens. A number of through holes is regularly defined in an optical non-effective portion of the lens. The through holes are configured for increasing the air convection between inside and outside of the lens. | 2012-02-16 |
20120037937 | LED PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME - An LED package structure includes a substrate unit, a conductive unit, a heat-dissipating unit, a light-emitting unit and a package unit. The substrate unit includes an insulating substrate. The conductive unit includes two top conductive pads disposed on top surface of the insulating substrate, two bottom conductive pads disposed on bottom surface of the insulating substrate, and a plurality of penetrating conductive posts passing the insulating substrate. The two top conducive pads respectively electrically connect the two bottom conductive pads through the penetrating conductive posts. The heat-dissipating unit includes a top heat-dissipating block and a bottom heat-dissipating block respectively disposed on top and bottom surfaces of the insulating substrate. The light-emitting unit includes a light-emitting element on the top heat-dissipating block and electrically connected between the two top conductive pads. The package unit includes a package resin on the conductive unit and the heat-dissipating unit to cover the light-emitting element. | 2012-02-16 |
20120037939 | LIGHT EMITTING DIODE - A light emitting diode comprises a LED chip, a package in which the LED chip is housed, and a connection electrode electrically connected to an element electrode with which the LED chip is provided. The package is a laminated body comprising at least a submount substrate and a frame body, and the LED chip is fixedly-mounted on one surface of the submount substrate, and the frame body is laminated on the one surface of the submount substrate and is provided with a through-hole in which the LED chip is stored. The connection electrode is formed on at least either the one surface of the submount substrate or one surface of the frame body facing toward a light irradiation direction, while being exposed in the light irradiation direction. Therefore, the light emitting diode can improve both heat dissipation performance and density of LED placement together. | 2012-02-16 |
20120037940 | LIGHT-EMITTING DEVICE, METHOD FOR ADJUSTING OPTICAL PROPERTIES, AND METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICES - Provided are a light-emitting tube and lamp that can maintain a high lamp efficiency even if the lamp power fluctuate. The light-emitting tube ( | 2012-02-16 |
20120037941 | Red Emitting Luminescent Materials - The invention relates to an improved red light emitting material of the formula ML | 2012-02-16 |
20120037942 | LIGHT EMITTING DEVICE - A light emitting device is provided with a base member, an interconnect pattern disposed on an upper surface of the base member, a light reflecting layer comprising a first layer disposed on a part of the interconnect pattern and formed from a metal material, and a second layer made of a dielectric multilayer reflecting film made with stacked layers of dielectric films having different refractive indices and covering an upper surface and side surfaces of the first layer, a light emitting element chip fixed so as to face at least a part of the light reflecting layer, and a light transmissive sealing member sealing the light reflecting layer and the light emitting element chip. | 2012-02-16 |
20120037943 | ILLUMINATION SYSTEM COMPRISING BEAM SHAPING ELEMENT - The invention relates to an illumination system ( | 2012-02-16 |
20120037944 | LIGHT EMITTING DEVICE - A light emitting device, which has: a light emitting element; a package that comprises a concavity for holding the light emitting element, and that has on its side wall where the concavity is integrally formed a light reflector for reflecting light from the light emitting element and a light transmitter for transmitting light from the light emitting element to the outside. | 2012-02-16 |
20120037945 | LIGHT EMITTING DEVICE - Disclosed is a light emitting structure comprising a first semiconductor layer, a substrate, a reflection electrode disposed on the substrate, a light transmitting electrode disposed on the reflection electrode, and a light emitting structure disposed on the light transmitting electrode, the light emitting structure comprising a first semiconductor layer, a second semiconductor layer, and an active layer interposed between the first and second semiconductor layer. The light transmitting electrode has a thickness of 20 to 200 A. | 2012-02-16 |
20120037946 | LIGHT EMITTING DEVICES - In one aspect of the invention, a light emitting device includes a substrate, and a multilayered structure having an n-type semiconductor layer formed in a light emitting region and a non-emission region on the substrate, an active layer formed in the light emitting region on the n-type semiconductor layer, and a p-type semiconductor layer formed in the light emitting region on the active layer. The light emitting device also includes a p-electrode formed in the light emitting region and electrically coupled to the p-type semiconductor layer, and an n-electrode formed in the non-emission region and electrically coupled to the n-type semiconductor layer. Further, the light emitting device also includes an insulator formed between the n-electrode and the n-type semiconductor layer in the first portion of the non-emission region to define at least one ohmic contact such that the n-electrode in the first portion of the non-emission region is electrically coupled to the n-type semiconductor layer through the at least one ohmic contact. | 2012-02-16 |
20120037947 | LIGHT EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF - A light emitting diode package comprises a substrate with a first surface and a second surface opposite to each other, a circuit on the substrate, a support on the substrate for reinforcing strength of the substrate, a plurality of light emitting diodes on the substrate and electrically connected to the circuit, and a cover layer on the plurality of light emitting diodes. A method for manufacturing a light-emitting diode package is further provided. | 2012-02-16 |
20120037948 | ORGANIC LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - An exemplary embodiment of the present invention provides an organic light emitting diode, comprising a substrate, a first electrode, an organic material layer, and a second electrode, wherein a trench comprising a concave part and a convex part is provided on the substrate, the first electrode is provided on the substrate on which the trench is formed by being deposited, and an auxiliary electrode is provided on the first electrode. The organic light emitting diode according to the exemplary embodiment of the present invention may increase surface areas of the first electrode and the auxiliary electrode formed on the substrate, thereby implementing a low resistance electrode. In addition, since a line width of the electrode is not increased, it is possible to prevent a decrease of an opening ratio of the organic light emitting diode. | 2012-02-16 |
20120037949 | LIGHT EMITTING DEVICE, METHOD FOR FABRICATING THE LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM - Provided is a light emitting device. The light emitting device includes a light emitting structure layer including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer, a first electrode electrically connected to the first conductive type semiconductor layer, an insulating support member under the light emitting structure layer, and a plurality of conductive layers between the light emitting structure layer and the insulating support member. At least one of the plurality of conductive layers has a width greater than that of the light emitting structure layer and includes a contact part disposed further outward from a sidewall of the light emitting structure layer. | 2012-02-16 |
20120037950 | LED WITH LOCAL PASSIVATION LAYERS - A LED with local passivation layers comprises a substrate, a light-emitting stack layer formed on the substrate, an electrode group formed on the light-emitting stack layer, and a first passivation layer formed on a side wall of the light-emitting stack layer. The light-emitting stack layer at least includes an n-type semiconductor layer, an active layer and a p-type semiconductor layer. The electrode group includes an n-type electrode and a p-type electrode. The n-type semiconductor layer has an exposed area where the n-type electrode is formed. The first passivation layer is distributed on a side wall of the light-emitting stack layer, which neighbors the exposed area, to protect the PN junction that is between the n-type semiconductor layer and the p-type semiconductor layer and is on the abovementioned side wall. | 2012-02-16 |
20120037951 | Optical Device And Method Of Producing The Same - An optical device of the present invention comprises a light-emitting element or a light-receiving element mounted on a support and a cured silicone material unified into a single article onto the support by the sealing of the element with a hydrosilylation reaction curable silicone composition, and is characterized in that the surface of the cured silicone material has been treated with an organopolysiloxane that has at least three silicon-bonded hydrogen atoms in one molecule. The optical device is resistant to the adherence of dust and dirt due to an inhibition of the stickiness of the surface of a cured silicone material that seals a light-emitting element or a light-receiving element mounted on a support and has thereby been unified into a single body onto the support. | 2012-02-16 |
20120037952 | LIGHT EMITTING DIODE AND FABRICATING METHOD THEREOF - A light emitting diode and a fabricating method thereof are provided. A first-type semiconductor layer, a light emitting layer and a second-type semiconductor layer with a first surface are sequentially formed a substrate. Next, the first surface is treated during a surface treatment process to form a current-blocking region which extends from the first surface to the light emitting layer to a depth of 1000 angstroms. Afterward, a first electrode is formed above the current-blocking region of the second-type semiconductor layer, and a second electrode is formed to electrically contact to the first-type semiconductor layer. Since the current-blocking region is formed with a determined depth within the second-type semiconductor layer, the light extraction efficiency of the light emitting diode may be increased. | 2012-02-16 |
20120037953 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a vertical MOS transistor including a semiconductor substrate having a silicon pillar, a gate electrode formed along a sidewall of the silicon pillar, a gate insulating film formed between the gate electrode and the silicon pillar, an upper diffusion layer formed on the top of the silicon pillar, and a lower diffusion layer formed lower than the upper diffusion layer in the semiconductor substrate; and a pad electrically connected to the lower diffusion layer. Breakdown occurs between the lower diffusion layer and the semiconductor substrate when a surge voltage is applied. | 2012-02-16 |
20120037954 | Equal Potential Ring Structures of Power Semiconductor with Trenched Contact - A semiconductor power device with trenched contact having improved equal potential ring (EPR) structures for device die size shrinkage and yield enhancement are disclosed. The invented semiconductor power device comprising a termination area including an equal potential ring (EPR) formed with EPR contact metal plug penetrating through an insulation layer covering top surface of epitaxial layer and extended downward into an epitaxial layer. To prevent the semiconductor power device from EPR damage induced by die pick-up nozzle at assembly stage in prior art, some preferred embodiments of the present invention without having EPR front metal. | 2012-02-16 |
20120037955 | Transistor Component with Reduced Short-Circuit Current - A transistor component includes in a semiconductor body a source zone and a drift zone of a first conduction type, and a body zone of a second conduction type complementary to the first conduction type, the body zone arranged between the drift zone and the source zone. The transistor component further includes a source electrode in contact with the source zone and the body zone, a gate electrode adjacent the body zone and dielectrically insulated from the body zone by a gate dielectric layer, and a diode structure connected between the drift zone and the source electrode. The diode structure includes a first emitter zone adjoining the drift zone in the semiconductor body, and a second emitter zone of the first conduction type adjoining the first emitter zone. The second emitter zone is connected to the source electrode and has an emitter efficiency γ of less than 0.7. | 2012-02-16 |
20120037956 | Circuit and Method for Power Clamp Triggered Dual SCR ESD Protection - Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit. | 2012-02-16 |
20120037957 | SEMICONDUCTOR DEVICES GROWN ON INDIUM-CONTAINING SUBSTRATES UTILIZING INDIUM DEPLETION MECHANISMS - We have observed anomalous behavior of II-VI semiconductor devices grown on certain semiconductor substrates, and have determined that the anomalous behavior is likely the result of indium atoms from the substrate migrating into the II-V layers during growth. The indium can thus become an unintended dopant in one or more of the II-VI layers grown on the substrate, particularly layers that are close to the growth substrate, and can detrimentally impact device performance. We describe a variety of semiconductor constructions and techniques effective to deplete the migrating indium within a short distance in the growth layers, or to substantially prevent indium from migrating out of the substrate, or to otherwise substantially isolate functional II-VI layers from the migrating indium, so as to maintain good device performance. | 2012-02-16 |
20120037958 | POWER ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an example embodiment, a power electronic device includes a first semiconductor layer, a second semiconductor layer on a first surface of the first semiconductor layer, and a source, a drain, and a gate on the second semiconductor layer. The source, drain and gate are separate from one another. The power electronic device further includes a 2-dimensional electron gas (2DEG) region at an interface between the first semiconductor layer and the second semiconductor layer, a first insulating layer on the gate and a second insulating layer adjacent to the first insulating layer. The first insulating layer has a first dielectric constant and the second insulating layer has a second dielectric constant less than the first dielectric constant. | 2012-02-16 |
20120037959 | SEMICONDUCTOR DEVICE WITH LESS POWER SUPPLY NOISE - A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line. | 2012-02-16 |
20120037960 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device according to the present invention is of a MOS type and includes a plurality of pixels arranged in rows and columns, and includes: a semiconductor substrate; a photodiode which is formed in the semiconductor substrate and converts, into a signal charge, light that is incident from a first main surface of the semiconductor substrate; a transfer transistor which is formed in a second main surface of the semiconductor substrate and transfers the signal charge converted by the photodiode; a light shielding film which is conductive and formed on a boundary between the pixels, above the first main surface of the semiconductor substrate; an overflow drain region electrically connected to the light shielding film and formed in the first main surface of the semiconductor substrate; and an overflow barrier region formed between the overflow drain region and the photodiode. | 2012-02-16 |
20120037961 | Methods and Apparatus for Measuring Analytes Using Large Scale FET Arrays - Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis. | 2012-02-16 |
20120037962 | SEMICONDUCTOR STRUCTURE HAVING A CONTACT-LEVEL AIR GAP WITHIN THE INTERLAYER DIELECTRICS ABOVE A SEMICONDUCTOR DEVICE AND A METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE USING A SELF-ASSEMBLY APPROACH - Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach. | 2012-02-16 |
20120037963 | SEMICONDUCTOR DEVICE WITH PROTECTIVE FILMS AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate having a drain region, a source region and an impurity diffusion region; an oxide film formed on the impurity diffusion region; a first protective film including a SiN film as a principle component and being formed on the oxide film; and a second protective film containing carbon and being formed on the first protective film. A method of manufacturing the semiconductor device, includes doping an impurity into a semiconductor substrate, thereby forming a drain region, a source region and an impurity diffusion region; forming an oxide film on the impurity diffusion region; forming a first protective film including a SiN film as a principle component on the oxide film; and forming a second protective film containing carbon on the first protective film. | 2012-02-16 |
20120037964 | ILLUMINATION APPARATUS - A point light source is converted into a plane light source having a satisfactory uniformity. The point light source is converted into a line light source by means of a linear light guiding plate, and further into the plane light source by means of a plane-like light guiding plate. Light from the point light source is reflected at a lamp reflector to be incident on at least two side surfaces of the plane-like light guiding plate. | 2012-02-16 |
20120037965 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET. | 2012-02-16 |
20120037966 | MINUTE STRUCTURE, MICROMACHINE, ORGANIC TRANSISTOR, ELECTRIC APPLIANCE, AND MANUFACTURING METHOD THEREOF - A micromachine is generally formed using a semiconductor substrate such as a silicon wafer. One of the objects of the present invention is to realize further reduction in cost by integrating a minute structure and a semiconductor element controlling the minute structure over one insulating surface in one step. A minute structure has a structure in which a first layer formed into a frame-shape are provided over an insulating surface, a space is formed inside the frame, and a second layer is formed to cross over the first layer. Such a minute structure and a thin film transistor can be integrated over one insulating surface in one step. | 2012-02-16 |
20120037967 | CMOS PIXEL SENSOR CELLS WITH POLY SPACER TRANSFER GATES AND METHODS OF MANUFACTURE - CMOS pixel sensor cells with spacer transfer gates and methods of manufacture are provided herein. The method includes forming a middle gate structure on a gate dielectric. The method further includes forming insulation sidewalls on the middle gate structure. The method further includes forming spacer transfer gates on the gate dielectric on opposing sides of the middle gate, adjacent to the insulation sidewalls which isolate the middle gate structure from the spacer transfer gates. The method further includes forming a photo-diode region in electrical contact with one of the spacer transfer gates and a floating diffusion in electrical contact with another of the spacer transfer gates. | 2012-02-16 |
20120037968 | SOLID-STATE IMAGE SENSING DEVICE AND METHOD OF MANUFACTURING THE SAME - By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other. | 2012-02-16 |
20120037969 | MONOLITHIC MICROWAVE INTEGRATED CIRCUIT - Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates ( | 2012-02-16 |
20120037970 | MICROELECTRONIC MEMORY DEVICES HAVING FLAT STOPPER LAYERS AND METHODS OF FABRICATING THE SAME - Memory devices comprise a microelectronic substrate including a cell array region and a peripheral region adjacent the cell array region, the cell array region including therein an array of memory cells and the peripheral region including therein peripheral circuits for the array of memory cells, the microelectronic substrate including a lower layer that extends across the cell array region and across the peripheral region and that includes a flat outer surface from the cell array region to the peripheral region. A signal transfer conductor layer extends in the cell array region beneath the flat outer surface of the lower layer and extends in the peripheral region above the flat outer surface of the lower layer. An insulating layer is provided on the lower layer, the insulating layer extending across the cell array region and the peripheral region and also including a flat outer surface from the cell array region to the peripheral region. A flat stopper layer is provided on the flat outer surface of the insulating layer and extending across the cell array region and the peripheral region. Finally, an array of memory cell capacitor storage nodes is provided in the cell array region that extend beyond the flat stopper layer and that penetrate through the flat stopper layer and the insulating layer. Related methods are also provided. | 2012-02-16 |
20120037971 | NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME - A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region. | 2012-02-16 |
20120037972 | SEMICONDUCTOR DEVICE - It is an object to give excellent data retention characteristics to a semiconductor device in which stored data is judged in accordance with the potential of a gate of a specified transistor, by achieving both reduction in variation of the threshold voltage of the transistor and data retention for a long time. Charge is held (data is stored) in a node electrically connected only to a source or a drain of a transistor whose channel region is formed using an oxide semiconductor. There may be a plurality of transistors whose sources or drains are electrically connected to the node. The oxide semiconductor has a wider band gap and a lower intrinsic carrier density than silicon. By using such an oxide semiconductor for the channel region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized. | 2012-02-16 |
20120037973 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure. | 2012-02-16 |
20120037974 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a resistor element and a stacked-gate type memory cell transistor. The resistor element includes a first conductive layer which is formed on a second conductive layer via a first insulating layer, and is electrically connected to an interconnect, the second conductive layer being on a substrate and in a floating state. The stacked-gate type memory cell transistor is on the substrate, and includes a floating gate formed of the same material as the second conductive layer. | 2012-02-16 |
20120037975 | SEMICONDUCTOR DEVICES - A semiconductor device has an isolation layer pattern, a plurality of gate structures, and a first insulation layer pattern. The isolation layer pattern is formed on a substrate and has a recess thereon. The gate structures are spaced apart from each other on the substrate and the isolation layer pattern. The first insulation layer pattern is formed on the substrate and covers the gate structures and an inner wall of the recess. The first insulation layer pattern has a first air gap therein. | 2012-02-16 |
20120037976 | NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME - A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor. | 2012-02-16 |
20120037977 | SEMICONDUCTOR DEVICES INCLUDING VERTICAL CHANNEL PATTERN - An insulating pattern is disposed on a surface of a semiconductor substrate and includes a silicon oxynitride film. A conductive pattern is disposed on the insulating pattern. A data storage pattern and a vertical channel pattern are disposed within a channel hole formed to vertically penetrate the insulating pattern and the conductive pattern. The data storage pattern and the vertical channel pattern are conformally stacked along sidewalls of the insulating pattern and the conductive pattern. A concave portion is formed in the semiconductor substrate adjacent to the insulating pattern. The concave portion is recessed relative to a bottom surface of the insulating pattern. | 2012-02-16 |
20120037978 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device is provided in such a manner that a semiconductor layer is formed over a substrate, a charge accumulating layer is formed over the semiconductor layer with a first insulating layer interposed therebetween, and a gate electrode is provided over the charge accumulating layer with a second insulating layer interposed therebetween. The semiconductor layer includes a channel formation region provided in a region overlapping with the gate electrode, a first impurity region for forming a source region or drain region, which is provided to be adjacent to the channel formation region, and a second impurity region provided to be adjacent to the channel formation region and the first impurity region. A conductivity type of the first impurity region is different from that of the second impurity region. | 2012-02-16 |
20120037979 | METHOD FOR PRODUCING AN INSULATION LAYER BETWEEN TWO ELECTRODES - Method for producing an insulation layer between a first electrode and a second electrode in a trench of a semiconductor body, wherein the method comprises the following features: providing a semiconductor body with a trench formed therein, wherein a first electrode is formed in a lower part of the trench, producing an insulation layer on the first electrode and at the sidewalls of the trench in an upper part of the trench in such a way that the insulation layer is formed in a U-shaped fashion in the trench, producing a protective layer on the insulation layer at least at the bottom of the remaining void in the trench, removing the insulation layer at the sidewalls of the trench in the upper part of the trench, removing the protective layer, producing a second electrode at least on the insulation layer above the first electrode. | 2012-02-16 |
20120037980 | EDGE TERMINATION REGION - An isolation region ( | 2012-02-16 |
20120037981 | Power Semiconductor Chip with a Formed Patterned Thick Metallization Atop - A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK | 2012-02-16 |
20120037982 | REDUCED PROCESS SENSITIVITY OF ELECTRODE-SEMICONDUCTOR RECTIFIERS - Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion. | 2012-02-16 |
20120037983 | Trench mosfet with integrated schottky rectifier in same cell - A semiconductor power device comprising a plurality of trench MOSFETs integrated with Schottky rectifier in same cell is disclosed. The invented semiconductor power device comprises a tilt-angle implanted drift region having higher doping concentration than epitaxial layer to reduce Vf in Schottky rectifier portion and to reduce Rds in trench MOSFET portion while maintaining a higher breakdown voltage by implementation of thick gate oxide in trench bottom of trenched gates. Furthermore, the invented semiconductor power device further comprises a Schottky barrier height enhancement region to enhance the barrier layer covered in trench bottom of trenched source-body-Schottky contact in Schottky rectifier portion. | 2012-02-16 |
20120037984 | LDMOS Structure - A LDMOS structure includes a gate, a source, a drain and a bulk. The gate includes a polycrystalline silicon layer, the source includes a P-implanted layer, the drain includes the P-implanted layer, a P-well layer, and a deep P-well layer. A bulk terminal is connected through the P-implanted layer, the P-well layer, the deep P-well layer, and a P-type buried layer to the bulk. The LDMOS structure is able to be produced without any extra masking step, and it has compact structure, low on-resistance, and is able to withstand high current and high voltage. | 2012-02-16 |
20120037985 | APPARATUS WITH CAPACITIVE COUPLING AND ASSOCIATED METHODS - Transistors are described, along with methods and systems that include them. In one such transistor, a field plate is capacitively coupled between a first terminal and a second terminal. A potential in the field plate modulates dopant in a diffusion region in a semiconductor material of the transistor. Additional embodiments are also described. | 2012-02-16 |
20120037986 | SEMICONDUCTOR DEVICE - A semiconductor device includes a body region of a first conductivity type and a gate pattern disposed on the body region. The gate pattern has a linear portion extending in a first direction and having a uniform width and a bending portion extending from one end of the linear portion. The portion of a channel region located beneath the bending portion constitutes a channel whose length is greater than the length of the channel constituted by the portion of the channel region located beneath the linear portion. | 2012-02-16 |
20120037987 | Coupling Well Structure for Improving HVMOS Performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 2012-02-16 |
20120037988 | RESURF DEVICE INCLUDING INCREASED BREAKDOWN VOLTAGE - A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate. | 2012-02-16 |
20120037989 | LDMOS HAVING SINGLE-STRIP SOURCE CONTACT AND METHOD FOR MANUFACTURING SAME - LDMOS devices having a single-strip contact pad in the source region, and related methods of manufacturing are disclosed. The LDMOS may comprise a first well lightly doped with a first dopant and formed into a portion of a substrate, the first well having a drain region at its surface heavily doped with the first dopant, and a second well lightly doped with a second dopant formed in another portion of the substrate, the second well having a source region at its surface comprising first portions heavily doped with the first dopant directly adjacent second portions heavily doped with the second dopant. Also, the LDMOS device may comprise a field oxide at the upper surface of the substrate between the source and drain regions, and contacting the first well but separated from the second well, and a gate formed partially over the field oxide and partially over the source region. The LDMOS may also comprise contact pads in contact with the gate, and source and drain regions, wherein the contact pad in contact with the source regions comprises a single-strip of conductive material extending across the source region. | 2012-02-16 |
20120037990 | Method and system for pre-migration of metal ions in a semiconductor package - According to an embodiment of the present disclosure, a method of pre-migrating metal ions is disclosed. A metal in a semiconductor configuration is exposed to water and oxygen to yield metal ions. The metal couples a conductor to another material. The metal and the conductor are exposed to an electrical field in such a manner that one or both of the metal and the conductor becomes an anode to a corresponding cathode. The metal ions are then allowed to migrate from the anode to the cathode to form a migrated metal. Finally, a migration inhibitor is applied on top of the migrated metal to prevent further migration. | 2012-02-16 |
20120037991 | Silicon on Insulator Field Effect Device - A field effect transistor device includes a silicon on insulator (SOI) body portion disposed on a buried oxide (BOX) substrate, a gate stack portion disposed on the SOI body portion, a first silicide material disposed on the BOX substrate arranged adjacent to the gate stack portion, a second silicide material arranged on the first silicide material, a source region including a portion of the first silicide material and the second silicide material, and a drain region including a portion of the first silicide material and the second silicide material. | 2012-02-16 |
20120037992 | PRINTED TFT AND TFT ARRAY WITH SELF-ALIGNED GATE - A method is used to form a self-aligning thin film transistor. The thin film transistor includes a gate contact formed with a state-switchable material, and a dielectric layer to isolate the gate contact. A source-drain layer, which includes a source contact, and a drain contact are formed with a source-drain material. An area of the gate contact is exposed to a form of energy, wherein the energy transforms a portion of the state switchable material from a non-conductive material to a conductive material, the conductive portion defining the gate contact. A semiconductor material is formed between the source contact and the drain contact. | 2012-02-16 |
20120037993 | SEMICONDUCTOR DEVICE - A semiconductor device in which damages to an element such as a transistor are reduced even when external force such as bending is applied and stress is generated in the semiconductor device. The semiconductor device includes a first island-like reinforcement film over a substrate having flexibility; a semiconductor film including a channel formation region and an impurity region over the first island-like reinforcement film; a first conductive film over the channel formation region with a gate insulating film interposed therebetween; a second island-like reinforcement film covering the first conductive film and the gate insulating film. | 2012-02-16 |
20120037994 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME - A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed. | 2012-02-16 |
20120037995 | SEMICONDUCTOR DEVICE AND RELATED METHOD OF FABRICATION - A semiconductor device comprises a device isolation pattern, an active region, a gate pattern, a first source/drain region, and a first barrier region. The device isolation pattern defines an active portion in a semiconductor substrate and the active portion comprises first and second sidewalls extending in a first direction and doped with a first conductive type dopant. The gate pattern extends in a second direction perpendicular to the first direction to cross over the active portion. The first source/drain region and the first barrier region are disposed in the active portion at one side of the gate pattern. The first barrier region is disposed between the first source/drain region and the first sidewall and contacts the first sidewall. The first barrier region is doped with the first conductive type dopant and the first source/drain region is doped with a second conductive type dopant. | 2012-02-16 |
20120037996 | SRAM BIT CELL WITH SELF-ALIGNED BIDIRECTIONAL LOCAL INTERCONNECTS - Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects. | 2012-02-16 |
20120037997 | METHOD AND APPARATUS FOR WORD LINE DRIVER WITH DECREASED GATE RESISTANCE - A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor. | 2012-02-16 |
20120037998 | CMOS TRANSISTORS WITH STRESSED HIGH MOBILITY CHANNELS - A p-type field effect transistor (PFET) having a compressively stressed channel and an n-type field effect transistor (NFET) having a tensilely stressed channel are formed. In one embodiment, a silicon-germanium alloy is employed as a device layer, and the source and drain regions of the PFET are formed employing embedded germanium-containing regions, and source and drain regions of the NFET are formed employing embedded silicon-containing regions. In another embodiment, a germanium layer is employed as a device layer, and the source and drain regions of the PFET are formed by implanting a Group IIIA element having an atomic radius greater than the atomic radius of germanium into portions of the germanium layer, and source and drain regions of the NFET are formed employing embedded silicon-germanium alloy regions. The compressive stress and the tensile stress enhance the mobility of charge carriers in the PFET and the NFET, respectively. | 2012-02-16 |
20120037999 | DIFFERENTIAL STOICHIOMETRIES BY INFUSION THRU GCIB FOR MULTIPLE WORK FUNCTION METAL GATE CMOS - A method of modulating the work function of a metal layer in a localized manner is provided. Metal gate electrodes having multiple work functions may then be formed from this metal layer. Although the metal layer and metal gate electrodes over both the nFET and pFET regions of the instant substrates are made from only a single metal, they exhibit different electrical performances. The variation of electrical performances is achieved by infusing stoichiometrically-altering atoms into the metal layer, from which the metal gate electrodes are made, via a Gas Cluster Ion Beam process. The resulting metal gate electrodes have the necessary threshold voltages for both nFET and pFET, and are ideal for use in CMOS devices. | 2012-02-16 |
20120038000 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes forming a first stopper film and a second stopper film over a first stress film; etching, with a first mask covering a first region and with the first stopper film, the second stopper film in a second region while side-etching the second stopper film in a part of the first region near the second region; forming a second stress film whose etching characteristic is different from the second stopper film; etching, with a second mask covering the second region and having an end face located over the second stopper film and with the second stopper film, the second stress film so that a part of the second stress film overlaps a part of the first stress film and a part of the second stopper film; and forming a contact hole down to the gate interconnect. | 2012-02-16 |
20120038001 | P-CHANNEL MOS TRANSISTOR AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A p-channel MOS transistor includes a gate electrode formed on a silicon substrate via a gate insulating film, a channel region formed below the gate electrode within the silicon substrate, and a p-type source region and a p-type drain region formed at opposite sides of the channel region within the silicon substrate. In the p-channel MOS transistor, first and second sidewall insulating films are arranged on opposing sidewall faces of the gate electrode. First and second p-type epitaxial regions are respectively formed at outer sides of the first and second sidewall insulating films on the silicon substrate, and the first and second p-type epitaxial regions are arranged to be higher than the gate electrode. A stress film that stores tensile stress and covers the gate electrode via the first and second sidewall insulating films is continuously arranged over the first and second p-type epitaxial regions. | 2012-02-16 |
20120038002 | IC AND IC MANUFACTURING METHOD - Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate ( | 2012-02-16 |
20120038003 | Semiconductor device - A second conduction-type MIS transistor in which a source is coupled to a second power source over the surface of a first conduction-type well and a drain is coupled to the open-drain signal terminal is provided. A second conduction-type first region is provided at both sides of the MIS transistor in parallel with a direction where the electric current of the MIS transistor flows and coupled to the open-drain signal terminal. The whole these components are surrounded by a first conduction-type guard ring coupled to the second power source and the outside surrounded by the first conduction-type guard ring is further surrounded by a second conduction-type guard ring coupled to a first power source. Thereby, the semiconductor device is capable of achieving ESD protection of an open-drain signal terminal having a small area and not providing a protection element between power source terminals. | 2012-02-16 |
20120038004 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A first insulating film is formed above a semiconductor substrate with a device isolation insulating film defining a device region, a gate electrode and source/drain region formed. The first insulating film is etched, leaving the first insulating film in a recess formed in an edge of the device isolation insulating film. A second insulating film applying a stress to the semiconductor substrate is formed after etching the first insulating film. | 2012-02-16 |
20120038005 | DISPOSABLE PILLARS FOR CONTACT FORMATION - Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts. | 2012-02-16 |
20120038006 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor device comprising a fin of semiconductive material formed from a semiconductor layer over a semiconductor substrate and having two opposing sides perpendicular to the main surface of the semiconductor substrate; a source region and a drain region provided in the semiconductor substrate adjacent to two ends of the fin and being bridged by the fin; a channel region provided at the central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, and wherein the stack of gate dielectric and gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the semiconductor substrate, and insulated from the semiconductor substrate by an insulating layer. The semiconductor device has an improved short channel effect and a reduced parasitic capacitance and resistance, which contributes to an improved electrical property and facilitates scaling down of the transistor. | 2012-02-16 |
20120038007 | Field Effect Transistor Device With Self-Aligned Junction - A method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, the source extension portion extending from the source region into the first portion of the substrate, forming an ion doped drain extension portion in the substrate, the drain extension portion extending from the drain region into the first portion of the substrate, removing a portion of the dummy gate stack to expose an interfacial layer of the dummy gate stack, implanting ions in the source extension portion and the drain extension portion to form a channel region in the first portion of the substrate, removing the interfacial layer, and forming a gate stack on the channel region of the substrate. | 2012-02-16 |
20120038008 | Field Effect Transistor Device with Self-Aligned Junction and Spacer - In one aspect of the present invention, a method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, forming an ion doped drain extension portion in the substrate, forming a first spacer portion adjacent to the dummy gate stack, removing the dummy gate stack to expose a channel region of the substrate, a portion of the ion doped source extension portion, and a portion of the ion doped drain extension portion, forming a second spacer portion on the exposed portion of the ion doped source extension portion and on the exposed portion of the ion doped drain extension portion, and forming a gate stack on the exposed channel region of the substrate. | 2012-02-16 |
20120038009 | Novel methods to reduce gate contact resistance for AC reff reduction - A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff. | 2012-02-16 |
20120038010 | FILM STRESS MANAGEMENT FOR MEMS THROUGH SELECTIVE RELAXATION - An apparatus comprising a microelectromechanical system. The microelectromechanical system includes a crystalline structural element having dislocations therein. For at least about 60 percent of adjacent pairs of the dislocations, direction vectors of the dislocations form acute angles of less than about 45 degrees. | 2012-02-16 |