| 07th week of 2013 patent applcation highlights part 14 |
| Patent application number | Title | Published |
|---|
| 20130037823 | SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer. | 2013-02-14 |
| 20130037824 | POWER SEMICONDUCTOR DEVICE - Cell electrodes are provided respectively for cell structures on a semiconductor substrate. The cell electrodes are divided into groups each including two or more cell electrodes. Conductive members are respectively electrically connected to the groups. The conductive members have a used portion and an unused portion. The used portion has two or more conductive members electrically connected to each other. The unused portion has at least one of the conductive members and is electrically insulated from the used portion. | 2013-02-14 |
| 20130037825 | SEMICONDUCTOR LIGHT EMITTING CHIP AND METHOD FOR PROCESSING SUBSTRATE - Disclosed is a semiconductor light emitting chip ( | 2013-02-14 |
| 20130037826 | LED PACKAGE MODULE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) package module and the manufacturing method thereof are presented. A plurality of LEDs and a plurality of semiconductor elements are disposed on a silicon substrate, and then a plurality of lenses is formed above the positions of the plurality of the LEDs, and the plurality of the lenses is corresponding to the plurality of the LEDs. Then, a plurality of package units is defined on the silicon substrate, and each package unit has a semiconductor element and at least one LED. After that, the silicon substrate is cut to form a plurality of LED package modules, and each LED package module has at least one package unit. | 2013-02-14 |
| 20130037827 | OLED LIGHT PANEL WITH CONTROLLED BRIGHTNESS VARIATION - Embodiments may provide a light source with a controlled brightness variation. A first device is provided that includes a substrate and a plurality of OLEDs disposed on the substrate. Each of the OLEDs includes a first electrode, a second electrode, and an organic electroluminescent (EL) material disposed between the first and the second electrodes. The plurality of OLEDs comprise a first group and a second group where a first current density is supplied to the first group of the plurality of OLEDs and a second current density that is different from the first current density is supplied to the second group of the plurality of OLEDs. Each of the plurality of OLEDs is commonly addressable and at least one of the OLEDs in the first group of OLEDs has substantially the same device structure as at least one of the OLEDs in the second group of OLEDs. | 2013-02-14 |
| 20130037828 | ORGANIC LIGHT-EMITTING DISPLAY AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display and a method of manufacturing the organic light-emitting display are disclosed. In one embodiment, the organic light-emitting display includes: i) a pixel electrode disposed on a substrate, ii) an opposite electrode disposed opposite to the pixel electrode, iii) an organic emission layer disposed between the pixel electrode and the opposite electrode; a light-scattering portion disposed between the substrate and the organic emission layer, including a plurality of scattering patterns for scattering light emitted from the organic emission layer in insulating layers having different refractive indexes. The display may further include a plurality of light absorption portions disposed between the light-scattering portion and the organic emission layer to correspond to the scattering patterns. | 2013-02-14 |
| 20130037829 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a base substrate; a first metal pattern disposed on the base substrate and comprising a first signal line and a first electrode electrically connected to the first signal line; and a buffer pattern disposed at a corner between a sidewall surface of the first metal pattern and the base substrate. | 2013-02-14 |
| 20130037830 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode package includes a heat-dissipating substrate including a reflective groove having a lower bottom surface, an upper opening having a width greater than the lower bottom surface, and an inclined surface formed between the upper opening and the lower bottom surface and mounting grooves, each formed in the reflective groove and having a lower bottom surface, an upper opening having a width greater than the lower bottom surface, and an inclined surface formed between the upper opening and the lower bottom surface; an insulating layer selectively formed on the heat-dissipating substrate; wiring pattern layers formed on the insulating layer and extending to bottom surfaces of the mounting grooves to be selectively formed thereon; a light emitting diode chip mounted in each of the mounting grooves; and a molding layer formed around the light emitting diode chip. | 2013-02-14 |
| 20130037831 | Opto-Electronic Module and Method for Manufacturing The Same - A method for manufacturing a device that includes an opto-electronic module includes creating a wafer stack including multiple active optical components mounted on a substrate wafer, and an optics wafer including multiple passive optical components. The optics wafer can include a blocking portion, which is substantially non-transparent for at least a specific wavelength range, and a transparent portion, which is substantially non-transparent for the specific wavelength range. Each opto-electronic module includes a substrate member, an optics member, an active optical component mounted on the substrate member, and a passive optical component. The optics member is directly or indirectly fixed to the substrate member. The opto-electronic modules can have excellent manufacturability, small dimensions and high alignment accuracy. | 2013-02-14 |
| 20130037832 | FOLDABLE DISPLAY STRUCTURES - One embodiment provides a structure, comprising: a display; at least one structural component disposed over a portion of the display, wherein the at least on structural component comprises at least one amorphous alloy; and wherein a portion of the display is foldable. | 2013-02-14 |
| 20130037833 | Optical Device and Method for Manufacturing Same - The present invention relates to an optical device and a method for manufacturing the same. The technical object of the invention is to realize a surface emitting body which allows heat generated from a light-emitting chip to be easily dissipated, eliminates the need for an additional wiring layer, and allows a singular light emitting chips or a plurality of light emitting chips to be arranged in series, in parallel, or in series-parallel. The present invention discloses an optical device comprising: a substrate; a plurality of light emitting chips disposed on the substrate; a plurality of conductive wires which electrically connect the substrate with the light emitting chips such that the plurality of light emitting chips are connected to each other in series, in parallel or in series-parallel; and a protective layer which covers the plurality of light emitting chips and the plurality of conductive wires on the substrate. | 2013-02-14 |
| 20130037834 | LIGHT EMITTING ELEMENT MODULE SUBSTRATE, LIGHT EMITTING ELEMENT MODULE, AND ILLUMINATING DEVICE - According to an aspect of the invention, there is provided a light emitting element module substrate including: a laminated plate; and a metal layer. The laminated plate includes a base metal plate and an insulating layer provided on the base metal plate. The metal layer is provided on the insulating layer. The metal layer includes a mounting section on which a light emitting element is to be mounted, and a bonding section to which a wiring electrically connected to the light emitting element is to be bonded. The metal layer includes a silver layer which is an uppermost layer of at least one of the mounting section and the bonding section and is formed by electrolytic plating. The mounting section and the bonding section are electrically isolated from a periphery of the laminated plate. | 2013-02-14 |
| 20130037835 | Display Device with Reinforced Power Lines - A display device is provided with a reinforced power line. The display device includes a common power line. A light emission layer is interposed between a first and a second electrode. A passivation layer is formed over the second electrode and has a stepped shape. An auxiliary metal layer is coupled to a common power line. At least a portion of the auxiliary metal layer is formed over the passivation layer and has a shape that follows the stepped shape of the passivation layer. | 2013-02-14 |
| 20130037836 | LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - A light emitting device that includes a conductive substrate, an insulating layer on the conductive substrate, a plurality of light emitting device cells on the insulating layer, a connection layer electrically interconnecting the light emitting device cells, a first contact section electrically connecting the conductive substrate with at least one light emitting device cell, and a second contact section on the at least one light emitting device cell. | 2013-02-14 |
| 20130037837 | MINIATURE LEADLESS SURFACE MOUNT LAMP WITH DOME AND REFLECTOR CUP - A package for a light source is disclosed. In particular, a Plastic Leaded Chip Carrier (PLCC) is described which provides many features offered by traditional surface mount technology lamps, but also has a decreased height, increased light output, and enables a smaller viewing angle as compared to traditional surface mount technology lamps. | 2013-02-14 |
| 20130037838 | Method and Apparatus for Coupling Light-Emitting Elements with Light-Converting Material - Light-emitting elements such as LEDs are associated with light-converting material such as phosphor and/or other material. A donor substrate comprising the light-converting and/or other material is suitably placed relative to a target substrate associated with the light-emitting elements. A laser or other energy source is then used to transfer the light-converting and/or other material in a pattern via writing or masking from the donor substrate to the target substrate in accordance with the pattern. Addressability and targetability of the transfer process facilitates precise patterning of the target substrate. | 2013-02-14 |
| 20130037839 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element of the present invention includes a support substrate, a semiconductor film including a light emitting layer, a surface electrode provided on the surface on a light-extraction-surface side of the semiconductor film, and a light reflecting layer. The surface electrode includes first electrode pieces that form ohmic contact with the semiconductor film and a second electrode piece electrically connected to the first electrode pieces. The light reflecting layer includes a reflecting electrode, and the reflecting electrode includes third electrode pieces that form ohmic contact with the semiconductor film and a fourth electrode piece electrically connected to the third electrode pieces and placed opposite to the second electrode piece. Both the second electrode piece and the fourth electrode piece form Schottky contact with the semiconductor film so as to form barriers to prevent forward current in the semiconductor film. | 2013-02-14 |
| 20130037840 | EPOXY RESIN COMPOSITION FOR OPTICAL SEMICONDUCTOR DEVICE AND OPTICAL SEMICONDUCTOR DEVICE USING THE SAME - The present invention relates to an epoxy resin composition for an optical semiconductor device having an optical semiconductor element mounting region and having a reflector that surrounds at least a part of the region, the epoxy resin composition being an epoxy resin composition for forming the reflector, the epoxy resin composition including the following ingredients (A) to (E): (A) an epoxy resin; (B) a curing agent; (C) a white pigment; (D) an inorganic filler; and (E) a specific release agent. | 2013-02-14 |
| 20130037841 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed is a semiconductor light emitting device. The semiconductor light emitting device comprises a substrate; a light emitting structure comprising a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer on the substrate; an electrode layer on the second conductive semiconductor layer; and an electrode on the electrode layer, wherein the substrate comprises a plurality of convex portions, wherein the electrode layer comprises a plurality of holes corresponding to a region of at least one of the plurality of convex portions of the substrate, wherein an insulating material is disposed in the plurality of holes on the light emitting structure. | 2013-02-14 |
| 20130037842 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - A light emitting device ( | 2013-02-14 |
| 20130037843 | LIGHT EMITTING TRANSISTOR - A light emitting transistor of the present invention has a light emitting layer, both a source electrode and a drain electrode both of which are connected with the light emitting layer electrically, an insulation layer arranged on the light emitting layer, a gate electrode arranged on the insulation layer. The light emitting layer is made from an organic semiconductor material. The light emitting transistor has also a periodic structure and the gate electrode to which an AC voltage is applied. And the emission intensity can be high, and width of the emission spectrum can be reduced. In addition, it is easy to control the amplitude of the emitting light and the width of emission spectrum reproducibly. | 2013-02-14 |
| 20130037844 | Light-Emitting Device and Method for Manufacturing Same - A light-emitting device ( | 2013-02-14 |
| 20130037845 | LEAD FRAME, AND LIGHT EMITTING DIODE MODULE HAVING THE SAME - A light emitting diode (LED) module includes a lead frame having a number (N) of conducting arms spaced apart from each other, where N≧3, and at least one LED die mounted on one of any two neighbor conducting arms. Any two neighbor conducting arms are electrically coupled each other. | 2013-02-14 |
| 20130037846 | RED LIGHT EMITTING PHOSPHOR, METHOD FOR MANUFACTURING THE SAME AND LIGHT EMITTING APPARATUS EMPLOYING RED LIGHT EMITTING PHOSPHOR - The present invention relates to a divalent europium-activated nitride red light emitting phosphor substantially represented by a general formula: (MI | 2013-02-14 |
| 20130037847 | LAYERED SUBSTRATE, LIGHT-EMITTING DIODE INCLUDING THE LAYERED SUBSTRATE AND LIGHTING DEVICE USING THE LIGHT-EMITTING DIODE - A layered substrate includes a first substrate including an upper surface, a lower surface, a peripheral surface between peripheral edges of the upper surface and the lower surface, and a cut portion cut into the peripheral surface and passing through the upper surface and the lower surface, and a second substrate including an upper surface, a lower surface, and a peripheral surface between peripheral edges of the upper surface and the lower surface, and the lower surface of the second substrate layered on the upper surface of the first substrate and closing the cut portion of the first substrate from above. The second substrate includes a heat conductor that is thermally connected to an element to be mounted on the upper surface of the second substrate, the heat conductor configured to thermally extend to the cut portion of the first substrate. | 2013-02-14 |
| 20130037848 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE HAVING THE SAME - Disclosed are a light emitting device and a light emitting device package having the same. The light emitting device includes a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, a first electrode disposed in an opening portion of the light emitting structure and contacted with a portion of the first conductive type semiconductor layer, an insulating layer covering the first electrode, a second electrode disposed on the insulating layer and connected to the second conductive type semiconductor layer, a first electrode layer under the second electrode. | 2013-02-14 |
| 20130037849 | VERTICAL STRUCTURE LED DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a vertical structure light emitting diode device, the method including: sequentially forming a first conductivity type III-V group compound semiconductor layer, an active layer, and a second conductivity type III-V group compound semiconductor layer on a substrate for growth; bonding a conductive substrate to the second conductivity type III-V group compound semiconductor layer; removing the substrate for growth from the first conductivity type III-V group compound semiconductor layer; and forming an electrode on an exposed portion of the first conductive III-V group compound semiconductor layer due to the removing the substrate for growth, wherein the bonding a conductive substrate comprises partially heating a metal bonding layer by applying microwaves to a bonding interface while bringing the metal bonding layer into contact with the bonding interface. | 2013-02-14 |
| 20130037850 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT, PROTECTIVE FILM OF SEMICONDUCTOR LIGHT-EMITTING ELEMENT, AND METHOD FOR FABRICATING SAME - Disclosed are: a semiconductor light-emitting element that fulfills all of having high migration prevention, high transmittance, and low film-production cost; the protective film of the semiconductor light-emitting element; and a method for fabricating same. To this end, in the semiconductor light-emitting element-which has: a plurality of semiconductor layers ( | 2013-02-14 |
| 20130037851 | SEMICONDUCTOR DEVICE - A semiconductor device including a base semiconductor layer of a first conductivity type, a cell portion including a diffusion region of a second conductivity type formed on a surface of the base semiconductor layer, a plurality of guard ring semiconductor layers of the second conductivity type formed on the surface of the base semiconductor layer, each guard ring semiconductor layer being formed to surround the cell portion, a plurality of first RESURF semiconductor layers of the first conductivity type provided on the surface of the base semiconductor layer inside the plurality of guard ring semiconductor layers and having a higher concentration than the base semiconductor layer and a second RESURF semiconductor layer of the first conductivity type provided on the surface of the base semiconductor layer between the outermost guard ring semiconductor layer and the EQPR semiconductor layer. | 2013-02-14 |
| 20130037852 | POWER MOSFET, AN IGBT, AND A POWER DIODE - Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed. | 2013-02-14 |
| 20130037853 | SEMICONDUCTOR DEVICE - A semiconductor device includes a stripe-shaped gate trench formed in one major surface of n-type drift layer, a gate trench including gate polysilicon formed therein, and a gate polysilicon connected to a gate electrode. A p-type base layer is formed selectively in mesa region between adjacent gate trenches and a p-type base layer including an n-type emitter layer and connected to emitter electrode. One or more dummy trenches are formed between p-type base layers adjoining to each other in the extending direction of gate trenches. An electrically conductive dummy polysilicon is formed on an inner side wall of dummy trench with a gate oxide film interposed between the dummy polysilicon and dummy trench. The dummy polysilicon is spaced apart from the gate polysilicon and may be connected to the emitter electrode. | 2013-02-14 |
| 20130037854 | PHOTODETECTOR - A photodetector is provided, comprising: a radiation-absorbing semiconductor region and a collection semiconductor region separated by and each in contact with a barrier semiconductor region; wherein, at least in the absence of an applied bias voltage, the band gap between the valence band energy and the conduction band energy of the barrier semiconductor region is offset from the band gap between the valence band energy and the conduction band energy of the radiation-absorbing semiconductor region so as to form an energy barrier between the radiation-absorbing semiconductor region and the collection semiconductor region which resists the flow of minority carriers from the radiation-absorbing semiconductor region to the collection semiconductor region. Also provided is a method of manufacturing a photodetector. | 2013-02-14 |
| 20130037855 | SI-GE LAMINATED THIN FILM AND INFRARED SENSOR USING SAME - Provided is a Si—Ge laminated thin film including at least one Si layer and at least one Ge layer, which are alternately laminated on a substrate ( | 2013-02-14 |
| 20130037856 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention relates to a semiconductor device and a manufacturing method therefor for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A SiGe seed layer is formed on sidewalls of the recess, and a first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom. A second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer, and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer. | 2013-02-14 |
| 20130037857 | DISLOCATION AND STRESS MANAGEMENT BY MASK-LESS PROCESSES USING SUBSTRATE PATTERNING AND METHODS FOR DEVICE FABRICATION - Structures and methods for producing active layer stacks of lattice matched, lattice mismatched and thermally mismatched semiconductor materials, with low threading dislocation densities, no layer cracking and minimized wafer bowing, by using epitaxial growth onto elevated substrate regions in a mask-less process. | 2013-02-14 |
| 20130037858 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention relates to a semiconductor device and a manufacturing method thereof for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom, a SiGe seed layer is formed on sidewalls of the recess and a second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer. | 2013-02-14 |
| 20130037859 | SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD THEREOF - A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application. | 2013-02-14 |
| 20130037860 | 3D MEMORY ARRAY - A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line. | 2013-02-14 |
| 20130037861 | IMAGE SENSOR FOR SEMICONDUCTOR LIGHT-SENSITIVE DEVICE, MANUFACTURING METHOD THEREOF, IMAGE PROCESSING APPARATUS USING THE SAME, AND METHOD FOR DETECTING COLOR SIGNAL - An image sensor for a semiconductor light-sensitive device including a semiconductor substrate and a light receiving device configured to receive light and generate a signal from the light. The image sensor may include an electron collecting device formed in the semiconductor substrate to receive at least a portion of the electrons generated by the light in the light receiving device. The image sensor may include a first type device isolation film configured to isolate the light receiving device from the electron collecting device. The image sensor may include a shielding film formed over the semiconductor substrate and configured to shield the first electron collecting device from the light. | 2013-02-14 |
| 20130037862 | MAGNETIC RANDOM ACCESS MEMORY - According to one embodiment, a magnetic random access memory includes a plurality of magnetoresistance elements. The plurality of magnetoresistance elements each include a recording layer having magnetic anisotropy perpendicular to a film surface, and a variable magnetization direction, a reference layer having magnetic anisotropy perpendicular to a film surface, and an invariable magnetization direction, and a first nonmagnetic layer formed between the recording layer and the reference layer. The recording layer is physically separated for each of the plurality of magnetoresistance elements. The reference layer and the first nonmagnetic layer continuously extend over the plurality of magnetoresistance elements. | 2013-02-14 |
| 20130037863 | MECHANISMS FOR FORMING ULTRA SHALLOW JUNCTION - The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures. | 2013-02-14 |
| 20130037864 | CROSS-COUPLING OF GATE CONDUCTOR LINE AND ACTIVE REGION IN SEMICONDUCTOR DEVICES - Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme. | 2013-02-14 |
| 20130037865 | SEMICONDUCTOR STRUCTURE HAVING A WETTING LAYER - A semiconductor structure which includes a semiconductor substrate and a metal gate structure formed in a trench or via on the semiconductor substrate. The metal gate structure includes a gate dielectric; a wetting layer selected from the group consisting of cobalt and nickel on the gate dielectric lining the trench or via and having an oxygen content of no more than about 200 ppm (parts per million) oxygen; and an aluminum layer to fill the remainder of the trench or via. There is also disclosed a method of forming a semiconductor structure in which a wetting layer is formed from cobalt amidinate or nickel amidinate deposited by a chemical vapor deposition process. | 2013-02-14 |
| 20130037866 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes providing a substrate and depositing a gate stack having a side periphery on the substrate. A first liner dielectric layer is deposited on the substrate and the gate stack. A first spacer dielectric layer is deposited on the first liner dielectric layer. The first spacer dielectric layer is selectively etched such that the first spacer dielectric layer remains adjacent at least a portion of the side periphery of the gate stack. A first resist mask is disposed on a first portion of the first spacer dielectric layer such that the first portion of the first spacer dielectric layer is protected by the resist mask and a second portion of the first spacer dielectric layer is not protected by the resist mask. The first spacer dielectric layer is etched such that the second portion is removed and the first portion remains. | 2013-02-14 |
| 20130037867 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a substrate, a gate electrode, a channel region, a source region and a drain region. The source region forms a first boundary with the channel region, and the drain region forms a second boundary with the channel region. A side of the gate electrode at the side of the source region has a plurality of convex portions extending along a gate length direction, a side of the gate electrode at the side of the drain region is parallel to a gate width direction, the first boundary and the second boundary have shapes corresponding to the side of the gate electrode at the side of the source region and the side of the gate electrode at the side of the drain region, and the length of the first boundary is more than the length of the second boundary. | 2013-02-14 |
| 20130037868 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization. In other words, the intensities of polarization of the semiconductor layers change with an inclination based on their distances from the gate electrode so that, at each interface between two semiconductor layers, the amount of negative charge becomes larger than that of positive charge. | 2013-02-14 |
| 20130037869 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a manufacturing method of a semiconductor device includes a step of forming a dummy-fin semiconductor on a semiconductor substrate; a step of forming an insulating layer, into which a lower part of the dummy-fin semiconductor is buried, on the semiconductor substrate; a step of forming a fin semiconductor, which is bonded to a side face at an upper part of the dummy-fin semiconductor, on the insulating layer; and a step of removing the dummy-fin semiconductor on the insulating layer with the fin semiconductor being left on the insulating layer. | 2013-02-14 |
| 20130037870 | SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD FOR SAME - Disclosed is a manufacturing method for a semiconductor device that prevents excessive etching of a conductive layer, even if the section where a conductive layer contact hole is formed is etched a plurality of times. A light-shielding film | 2013-02-14 |
| 20130037871 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SAME - An integrated circuit device includes a plurality of fins on an upper surface of a semiconductor substrate and extending in a first direction, a device isolation insulating film placed between the fins, a gate electrode extending in a second direction crossing the first direction on the insulating film; and an insulating film insulating the fin from the gate electrode. In a first region where a plurality of the fins are consecutively arranged, an upper surface of the device isolation insulating film is located at a first position below an upper end of the fin. In a second region located in the second direction as viewed from the first region, the upper surface of the device isolation insulating film is located at a second position above the upper end of the fin. In the second region, the device isolation insulating film covers entirely a side surface of the fin. | 2013-02-14 |
| 20130037872 | METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) HAVING A FERROELECTRIC CAPACITOR ALIGNED WITH A THREE DIMENSIONAL TRANSISTOR STRUCTURE - Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure. | 2013-02-14 |
| 20130037873 | FILM FORMING METHOD, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME, FILM FORMING APPARATUS, AND SEMICONDUCTOR DEVICE - Provided is a semiconductor device capable of preventing destruction of an electrode having a pillar shape and densely arranged. The semiconductor device having a field-effect transistor and a capacitor having a pillar shape, the semiconductor device includes: a first electrode having a pillar shape and electrically connected to an impurity diffusion region of the field-effect transistor; a dielectric film formed at least on a side of the first electrode; a second electrode formed on the dielectric film; and a support film extending in a direction crossing a length direction of the first electrode having the pillar shape, and formed by a boron-added silicon nitride film connected to the first electrode by penetrating through at least a part of the second electrode. | 2013-02-14 |
| 20130037874 | NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-in change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other. | 2013-02-14 |
| 20130037875 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MULTI-LAYER GATE STRUCTURE - A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion. | 2013-02-14 |
| 20130037876 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a polysilicon film formed above a semiconductor substrate, and a silicide film of a metal formed on the polysilicon film. The semiconductor device of the embodiment includes an oxide film of the metal formed above the silicide film, and a film containing tungsten or molybdenum formed on the oxide film. | 2013-02-14 |
| 20130037877 | DOUBLE GATED FLASH MEMORY - A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate. | 2013-02-14 |
| 20130037878 | VDMOS DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating VDMOS devices includes providing a semiconductor substrate; forming a first N-type epitaxial layer on the semiconductor substrate; forming a hard mask layer with an opening on the first N-type epitaxial layer; etching the first N-type epitaxial layer along the opening until the semiconductor substrate is exposed, to form P-type barrier figures; forming a P-type barrier layer in the P-type barrier figures, the P-type barrier layer having a same thickness as that of the first N-type epitaxial layer; removing the hard mask layer; forming a second N-type epitaxial layer on the first N-type epitaxial layer and the P-type barrier layer; forming a gate on the second N-type epitaxial layer; forming a source in the second N-type epitaxial layer on both side of the gate; and forming a drain on the back of the semiconductor substrate relative to the gate and the source. | 2013-02-14 |
| 20130037879 | VERTICAL DEVICES AND METHODS OF FORMING - Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch. | 2013-02-14 |
| 20130037880 | TRENCH-GATE METAL OXIDE SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A trench-gate metal oxide semiconductor device includes a substrate, a first gate dielectric layer, a first gate electrode and a first source/drain structure. The substrate has a first doping region, a second doping region and at least one trench. A P/N junction is formed between the first doping region and the second doping region. The trench extends from a surface of the substrate to the first doping region through the second doping region and the P/N junction. The first gate dielectric layer is formed on a sidewall of the second trench. The first gate electrode is disposed within the trench. A height difference between the top surface of the first gate electrode and the surface of the substrate is substantially smaller than 1500 Å. The first source/drain structure is formed in the substrate and adjacent to the first gate dielectric layer. | 2013-02-14 |
| 20130037881 | SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD OF MANUFACTURING THE SAME - A gate electrode is formed in a trench reaching a drain region so as to leave a concave portion on the top of the trench. A first insulating film is formed, which fills the concave portion and of which the thickness increases as the distance from an end of the trench increases on the substrate surface on both sides of the trench. First and second source regions are formed in a self-alignment manner by introduction of impurities through the first insulating film. | 2013-02-14 |
| 20130037882 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench. | 2013-02-14 |
| 20130037883 | LDPMOS STRUCTURE FOR ENHANCING BREAKDOWN VOLTAGE AND SPECIFIC ON RESISTANCE IN BICMOS-DMOS PROCESS - An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a tightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance. | 2013-02-14 |
| 20130037884 | NONVOLATILE MEMORY AND ELECTRONIC APPARATUS - An active region, a source region, and a drain region are formed on a single crystal semiconductor substrate or a single crystal semiconductor thin film. Impurity regions called pinning regions are formed in striped form in the active region so as to reach both of the source region and the drain region. Regions interposed between the pinning regions serve as channel forming regions. A tunnel oxide film, a floating gate, a control gate, etc. are formed on the above structure. The impurity regions prevent a depletion layer from expanding from the source region toward the drain region. | 2013-02-14 |
| 20130037885 | SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX) - A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer. | 2013-02-14 |
| 20130037886 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME - A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate. | 2013-02-14 |
| 20130037887 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a source region having p-type conductivity, a drain region having p-type conductivity, a channel region provided between the source region and the drain region and having n-type conductivity, a lower gate insulating film provided on the channel region, a lower gate electrode provided on the lower gate insulating film, an upper gate insulating film provided on the lower gate electrode, an upper gate electrode provided on the upper gate insulating film, and a switching element connected between the lower gate electrode and the source region. | 2013-02-14 |
| 20130037888 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active region defined by a device isolation layer and including first and second sections or regions, a gate electrode extending in a first direction across the active region over a channel between the first region and the second region and including at least one first gate tab protruding in a second direction toward the first region, and first and second contact plugs. The first gate tab covers and extends along a boundary between the active region and the device isolation layer. The first contact plug is disposed over the first region, the second contact plug is disposed over the second region, and the second contact plug has an effective width, as measured in the first direction, greater than that of the first contact plug. | 2013-02-14 |
| 20130037889 | SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF - A fabricating method of semiconductor structure is provided. First, a substrate with a dielectric layer formed thereon is provided. The dielectric layer has a first opening and a second opening exposing a portion of the substrate. Further, a gate dielectric layer including a high-k dielectric layer and a barrier layer stacked thereon had been formed on the bottoms of the first opening and the second opening. Next, a sacrificial layer is formed on the portion of the gate dielectric layer within the second opening. Next, a first work function metal layer is formed to cover the portion of the gate dielectric layer within the first opening and the sacrificial layer. Then, the portion of the first work function metal layer and the sacrificial layer within the second opening are removed. | 2013-02-14 |
| 20130037890 | MULTIPLE GATE DIELECTRIC STRUCTURES AND METHODS OF FORMING THE SAME - The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness. | 2013-02-14 |
| 20130037891 | MEMS DEVICE AND METHOD OF FORMATION THEREOF - The present disclosure provides a method including providing a first substrate; and forming a microelectromechanical system (MEMS) device on a first surface of the first substrate. A bond pad is formed on at least one bonding site on the first surface of the first substrate. The bonding site is recessed from the first surface. Thus, a top surface of the bond pad may lie below the plane of the top surface of the substrate. A device with recessed connective element(s) (e.g., bond pad) is also described. In further embodiments, a protective layer is formed on the recessed connective element during dicing of a substrate. | 2013-02-14 |
| 20130037892 | SEMICONDCUTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a pinned layer having a magnetic direction permanently set to a first direction, a tunnel insulating layer arranged on the pinned layer, a free layer arranged on the tunnel insulating layer and having a changeable magnetic direction, and a magnetic induction layer formed to surround the pinned layer and have a magnetic direction permanently set to a second direction different from the first direction. | 2013-02-14 |
| 20130037893 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first free layer having a magnetic direction that changes according to a direction and an amount of a first current, a first tunnel insulating layer arranged on the first free layer, a pinned layer, arranged on the first tunnel insulating layer, having a magnetic direction set to a first direction, a second tunnel insulating layer arranged on the pinned layer, and a second free layer, arranged on the second tunnel insulating layer, having a magnetic direction that changes according to a direction and an amount of a second current. | 2013-02-14 |
| 20130037894 | METHOD FOR FABRICATING MAGNETIC TUNNEL JUNCTION - In a method for fabricating a magnetic tunnel junction, a fixed layer, a tunnel insulating layer, a free layer, and an anti-etch layer are formed on a substrate. A sacrificial layer having a hole is formed on the anti-etch layer. An upper electrode is buried in the hole. The sacrificial layer is removed. The anti-etch layer, the free layer, the tunnel insulating layer, and the fixed layer are etched using the upper electrode as a mask. | 2013-02-14 |
| 20130037895 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. The magnetic tunnel junction layer is patterned using an etching gas containing oxygen. An insulating layer is formed by oxidizing the conductive layer exposed outside the patterned magnetic tunnel junction layer using the etching gas. | 2013-02-14 |
| 20130037896 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a magnetic tunnel junction (MTJ) element on a substrate, forming a first capping layer along the shape of the MTJ element, forming an insulating layer on the first capping layer, forming a trench exposing a portion of the first capping layer above the MTJ element by selectively etching the insulating layer, forming a second capping layer on sidewalls of the trench, removing the exposed portion of the first capping layer using the second capping layer as an etching mask to expose an upper surface of the MTJ element, and forming a conductive layer in the trench, wherein the conductive layer contacts the upper surface of the MTJ element. | 2013-02-14 |
| 20130037897 | METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) DEVICE STRUCTURE EMPLOYING REDUCED PROCESSING STEPS - Disclosed is a novel non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM device structure on a planar surface using a reduced number of masks and etching steps. | 2013-02-14 |
| 20130037898 | Memory Array Including Magnetic Random Access Memory Cells and Oblique Field Lines - A memory device includes a first plurality of magnetic random access memory (MRAM) cells positioned along a first direction, and a first bit line electrically connected to the first plurality of MRAM cells, the bit line oriented in the first direction. The device includes a first plurality of field lines oriented in a second direction different from the first direction, the first plurality of field lines being spaced such that only a corresponding first one of the first plurality of MRAM cells is configurable by each of the first plurality of field lines. The device includes a second plurality of field lines oriented in a third direction different from the first direction and the second direction, the second plurality of field lines being spaced such that only a corresponding second one of the first plurality of MRAM cells is configurable by each of the second plurality of field lines. | 2013-02-14 |
| 20130037899 | SEMICONDUCTOR STRUCTURE FOR PHOTON DETECTION - A semiconductor structure for photon detection, comprising a substrate composed of a semiconductor material having a first doping, a contact region fitted at the frontside of the substrate, a bias layer composed of a semiconductor material having a second doping, which is arranged on the backside of the substrate at a distance from the contact region, wherein the contact region at least partly lies opposite the bias layer, such that an overlap region is present in a lateral direction, a guard ring, which is arranged at the frontside of the substrate and surrounds the contact region, wherein a reverse voltage can be applied between the contact region and the guard ring. In order to enable more cost-effective production, the overlap region has a lateral extent amounting to at least one quarter of the distance between contact region and bias layer. | 2013-02-14 |
| 20130037900 | SOLID-STATE IMAGING ELEMENT, MANUFACTURING METHOD, AND ELECTRONIC DEVICE - A solid-state imaging element includes a pixel having a photoelectric conversion section and a side pinning layer. The photoelectric conversion section is formed in a semiconductor substrate. The side pinning layer is formed on a side of the photoelectric conversion section. The side pinning layer is formed by performing ion implantation in a state of a trench being open, the trench being formed in a part on a side of a region in which the photoelectric conversion section is formed. | 2013-02-14 |
| 20130037901 | PHOTOELECTRIC CONVERSION DEVICE - It is an object to provide a photoelectric conversion device with high photoelectric conversion efficiency that improves reliability by increasing contact force between a light absorbing layer and an electrode layer. The photoelectric conversion device includes an electrode layer, and a light absorbing layer located on the electrode layer. The light absorbing layer contains a compound semiconductor. The light absorbing layer comprises a first layer close to the electrode layer and a second layer located on the first layer. The first layer has a void ratio lower than that of the second layer. | 2013-02-14 |
| 20130037902 | IMAGE SENSING DEVICE, IMAGE SENSING SYSTEM, AND METHOD FOR MANUFACTURING IMAGE SENSING DEVICE - An image sensing device includes a light-shielding film having transit portions, a first film and a second film. The second film comprises a first layer having a different refractive index from the first film. The first layer lies within at least the transit portions, and forms interfaces with the first film. The distance between the interface and the corresponding photoelectric conversion portion is greater than the distance between the photoelectric conversion portion and the lower end of the corresponding transit portion. | 2013-02-14 |
| 20130037903 | DISPLAY DEVICE - Disclosed is a display device that is configured such that light that is emitted from a backlight or the like and that illuminates a display panel is prevented from being transmitted through a light-shielding layer that is provided between a light sensor element and a substrate. A liquid crystal display device | 2013-02-14 |
| 20130037904 | PTC ELEMENT AND HEATING-ELEMENT MODULE - An object is to provide a PTC element that can be made thinner, using a Pb-free semiconductor ceramic composition. | 2013-02-14 |
| 20130037905 | HYBRID SUBSTRATELESS DEVICE WITH ENHANCED TUNING EFFICIENCY - In a hybrid integrated module, a semiconductor die is mechanically coupled face-to-face to an integrated device in which the substrate has been removed. For example, the integrated circuit may include an optical device fabricated on a silicon-on-insulator (SOI) wafer in which the backside silicon handler has been completely removed, thereby facilitating improved device performance and highly efficient thermal tuning of the operating wavelength of the optical device. Moreover, the semiconductor die may be a VLSI chip that provides power, and serves as a mechanical handler and/or an electrical driver. The thermal tuning efficiency of the substrateless optical device may be enhanced by over 100× relative to an optical device with an intact substrate, and by 5× relative to an optical device in which the substrate has only been removed in proximity to the optical device. | 2013-02-14 |
| 20130037906 | Semiconductor Device and a Method for Forming a Semiconductor Device - A semiconductor device having a semiconductor die is provided. The semiconductor die includes a main horizontal surface, an outer edge, an active area, and a peripheral area. The peripheral area includes a dielectric structure surrounding the active area and extending from the main horizontal surface into the semiconductor die. The dielectric structure includes, in a horizontal cross-section, at least one substantially L-shaped portion that is inclined against the outer edge. Further, a method for forming a semiconductor device is provided. | 2013-02-14 |
| 20130037907 | OPTOELECTRONIC INTEGRATED CIRCUIT SUBSTRATE AND METHOD OF FABRICATING THE SAME - An optoelectronic integrated circuit substrate may include a first region and a second region. The first region and the second region each include at least two buried insulation layers having different thicknesses. The at least two buried insulation layers of the first region are formed at a greater depth and have a greater thickness as compared to the at least two buried insulation layers of the second region. A micro-electromechanical systems (MEMS) structure may be formed in a third region that does not include a buried insulation layer. | 2013-02-14 |
| 20130037908 | Galvanic Isolation Fuse and Method of Forming the Fuse - The spikes in current and voltage that result from the failure of a galvanic dielectric layer are safely contained by a galvanic isolation fuse that pops and forms and open circuit between a high-voltage die and a low-voltage die in response to the failure of the galvanic dielectric layer. | 2013-02-14 |
| 20130037909 | Semiconductor Structure with Galvanic Isolation - Galvanic isolation between a high-voltage die and a low-voltage die in a multi-die chip is provided by a galvanic isolation die that physically supports the high-voltage die and the low-voltage die, and provides capacitive structures with high breakdown voltages that allow the high-voltage die to capacitively communicate with the low-voltage die. | 2013-02-14 |
| 20130037910 | Decoupling MIM Capacitor Designs for Interposers and Methods of Manufacture Thereof - Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device. | 2013-02-14 |
| 20130037911 | CHIP-COMPONENT STRUCTURE AND METHOD OF PRODUCING SAME - In a chip-component structure, a monolithic ceramic capacitor is a structure including a predetermined number of substantially flat internal electrodes stacked on each other. An interposer includes a substrate larger than the outer shape of the monolithic ceramic capacitor. The substrate includes a first major surface on which first front electrodes for use in mounting the monolithic ceramic capacitor are disposed and a second major surface on which first back electrodes for use in connecting to an external circuit board are disposed. The interposer includes a depression in its side surface. The depression includes a wall surface on which a connection conductor is disposed. The front surface of the substrate is overlaid with resist films extending along its edges. | 2013-02-14 |
| 20130037912 | METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) WITH SIMULTANEOUS FORMATION OF SIDEWALL FERROELECTRIC CAPACITORS - Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating the same in the form of a damascene self-aligned F-RAM device comprising a PZT capacitor built on the sidewalls of an oxide trench, while allowing for the simultaneous formation of two ferroelectric sidewall capacitors. | 2013-02-14 |
| 20130037913 | Inexpensive electrode materials to facilitate rutile phase titanium oxide - This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO | 2013-02-14 |
| 20130037914 | NOVEL STRUCTURE OF NPN-BJT FOR IMPROVING PUNCH THROUGH BETWEEN COLLECTOR AND EMITTER - A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode. | 2013-02-14 |
| 20130037915 | Method and Apparatus for Providing a Layout Defining a Structure to be Patterned onto a Substrate - A method provides a layout defining a structure to be patterned onto a substrate. The structure is registered with a predefined grid of the layout. The method includes locally stretching the grid in a first portion of a layout causing a problematic spot on the substrate. | 2013-02-14 |
| 20130037916 | BREAK PATTERN OF SILICON WAFER, SILICON WAFER, AND SILICON SUBSTRATE - A break pattern of a silicon wafer includes a line to be cut which is set in the silicon wafer assuming a surface as a (110) face in a surface direction of a first (111) face perpendicular to the (110) face; and through holes which are provided in a plurality of rows on the line to be cut, wherein each of the through holes has a first (111) face, a second (111) face which intersects the first (111) face, and a third (111) face which intersects the second (111) face and the first (111) face, an intersecting point with end edges of the second (111) face and the third (111) face is assumed as a point closest to the adjacent through holes. | 2013-02-14 |
| 20130037917 | WAFER LEVEL CHIP SCALE PACKAGE WITH THICK BOTTOM METAL EXPOSED AND PREPARATION METHOD THEREOF - A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices. | 2013-02-14 |
| 20130037918 | Semiconductor Structure and Manufacturing Method Thereof - A semiconductor structure is provided in the present invention. The semiconductor structure includes a substrate, a first material layer and a second material layer. A trench region is defined on the substrate. The trench region includes two separated first regions and a second region, wherein the second region is adjacent to and between the two first regions. The first material layer is disposed on the substrate outside the trench region. The second material layer is disposed in the second region and is level with the first material layer. | 2013-02-14 |
| 20130037919 | METHODS OF FORMING TRENCHES IN SILICON AND A SEMICONDUCTOR DEVICE INCLUDING SAME - A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed. | 2013-02-14 |
| 20130037920 | SILICON EPITAXIAL WAFER AND METHOD FOR MANUFACTURING THE SAME - The present invention includes a method for manufacturing a silicon epitaxial wafer having a silicon homoepitaxial layer formed on a surface of a silicon single crystal wafer, including the steps of: preparing the silicon single crystal wafer such that a plane orientation of the silicon single crystal wafer is tilted at an angle in the range from 0.1° to 8° in a <112> direction from a {110} plane; and growing the silicon homoepitaxial layer on the prepared silicon single crystal wafer. According to the present invention, a silicon epitaxial wafer using the {110} substrate with improved surface quality, such as Haze and surface roughness and a method for manufacturing the silicon epitaxial wafer are provided. | 2013-02-14 |
| 20130037921 | RESIST UNDERLAYER COMPOSITION AND PROCESS OF PRODUCING INTEGRATED CIRCUIT DEVICES USING SAME - A resist underlayer composition, including a solvent, and an organosilane condensation polymerization product of hydrolyzed products produced from a compound represented by Chemical Formula 1, a compound represented by Chemical Formula 2, and a compound represented by Chemical Formula 3. | 2013-02-14 |
| 20130037922 | Trap Rich Layer with Through-Silicon-Vias in Semiconductor Devices - An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias. | 2013-02-14 |
