07th week of 2014 patent applcation highlights part 62 |
Patent application number | Title | Published |
20140047204 | PROVIDING SERVICE ADDRESS SPACE FOR DIAGNOSTICS COLLECTION - A method and system are provided for providing a service address space for diagnostics collection. The system includes: a service co-processor attached to a main processor, wherein the service co-processor maintains an independent copy of the main processor's address space in the form of a service address space; and a storage update receiving component for updating the service address space by receiving storage update packets from the main processor and applying these to the service address space. An instruction pipe may be provided between the main processor and the service co-processor. The main processor may include: a service delegation component for delegating collection of diagnostic data to the co-processor by sending a collection command from the main processor to the service co-processor for collection of data from the service address space. | 2014-02-13 |
20140047205 | INTERACTION OF TRANSACTIONAL STORAGE ACCESSES WITH OTHER ATOMIC SEMANTICS - In a processor, an instruction sequence including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block is detected. In response to detecting the instruction sequence, the processor causes the conditional write access to the target memory block to fail. | 2014-02-13 |
20140047206 | INFORMATION PROCESSING APPARATUS, MEMORY CONTROL APPARATUS, AND CONTROL METHOD THEREOF - A memory control circuit is configured to take a priority for each transfer instruction into account but not the priority in a memory access unit, and thus processing of a high-priority transfer instruction received during a memory access needs to wait for a long time. The memory control apparatus divides the received transfer instruction into a memory access unit and, when the transfer instruction having a higher priority is received during the memory access, the memory access based on a low-priority transfer instruction is interrupted and starts the memory access based on the high-priority transfer instruction. | 2014-02-13 |
20140047207 | METHODS AND SYSTEMS FOR DATA CLEANUP USING PHYSICAL IMAGE OF FILES ON STORAGE DEVICES - Systems and computer program products are provided for optimizing selection of files for eviction from a first storage pool to free up a predetermined amount of space in the first storage pool. A method includes analyzing an effective space occupied by each file of a plurality of files in the first storage pool, identifying, from the plurality of files, one or more data blocks making up a file to free up the predetermined amount of space based on the analysis of the effective space of each file of the plurality of files, selecting one or more of the plurality of files as one or more candidate files for eviction, based on the identified one or more data blocks, and evicting the one or more candidate files for eviction from the first storage pool to a second storage pool. | 2014-02-13 |
20140047208 | METHOD OF CONTROLLING THE CAPACITY OF A VIRTUAL STORAGE SYSTEM, AND A VIRTUAL STORAGE SYSTEM - A method of controlling the capacity of a virtual storage system provided on a physical storage system, the method including: providing a control program on the physical storage system; coupling additional virtual storage to the virtual storage system on the physical storage system; providing control data on the additional virtual storage; with the control program, reading the control data and configuring the virtual storage system accordingly. A corresponding virtual storage system is also provided. | 2014-02-13 |
20140047209 | Split Heap Garbage Collection - A method and an apparatus to scan a stack for references to a heap used in executing a code via the heap are described. The heap may be allocated with fixed and varied sized slots. Each varied sized slot may be referenced by at most one fixed sized slot. Which slots are live may be identified based on the references in the stack. A fixed slot can be live if referenced by the stack. A fixed or varied slot referenced by a live slot can also be live. Varied sized slots referenced by the stack may be identified as pinned. The heap may be de-fragmented to reclaim fixed sized slots which are not live without moving live fixed sized slots and to reclaim varied sized slots which are neither live nor pinned by moving live varied slots. | 2014-02-13 |
20140047210 | TRIM MECHANISM USING MULTI-LEVEL MAPPING IN A SOLID-STATE MEDIA - Described embodiments provide a media controller that receives requests that include a logical address and address range. In response to the request, the media controller determines whether the received request is an invalidating request. If the received request type is an invalidating request, the media controller uses a map to determine one or more entries of the map associated with the logical address and range. Indicators in the map associated with each of the map entries are set to indicate that the map entries are to be invalidated. The media controller acknowledges to a host device that the invaliding request is complete and updates, in an idle mode of the media controller, a free space count based on the map entries that are to be invalidated. The physical addresses associated with the invalidated map entries are made available to be reused for subsequent requests from the host device. | 2014-02-13 |
20140047211 | VECTOR REGISTER FILE - An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector register includes a plurality of elements. A read command is received at a read port of the vector register file. The read command specifies a vector register address. The vector register address is decoded by an address decoder to determine a selected vector register of the vector register file. An element address is determined for one of the plurality of elements associated with the selected vector register based on a read element counter of the selected vector register. A word is selected in a memory array of the selected vector register as read data based on the element address. The read data is output from the selected vector register based on the decoding of the vector register address by the address decoder. | 2014-02-13 |
20140047212 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has processor elements each of which divides data that is contiguous in one direction into multiple data groups and processes them, a processor element control unit that issues a data shift instruction, and a data transfer network that performs data transfer between adjacent processor elements. The processor elements each have a data storage unit that stores one of the multiple data groups, a data selector that outputs transfer data obtained by selecting either of head data or end data of one data group according to a data shift instruction into a data transfer network, a data shifter that shifts a position at which the data group is stored to the right or to the left according to the data shift instruction, and a data connector that connects the data group which is shifted and the transfer data obtained through the data transfer network. | 2014-02-13 |
20140047213 | METHOD AND SYSTEM FOR MEMORY OVERLAYS FOR PORTABLE FUNCTION POINTERS - A system and method for implementing memory overlays for portable pointer variables. The method includes providing a program executable by a heterogeneous processing system comprising a plurality of a processors running a plurality of instruction set architectures (ISAs). The method also includes providing a plurality of processor specific functions associated with a function pointer in the program. The method includes executing the program by a first processor. The method includes dereferencing the function pointer by mapping the function pointer to a corresponding processor specific feature based on which processor in the plurality of processors is executing the program. | 2014-02-13 |
20140047214 | VECTOR REGISTER FILE - An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector register includes a plurality of elements. A read command is received at a read port of the vector register file. The read command specifies a vector register address. The vector register address is decoded by an address decoder to determine a selected vector register of the vector register file. An element address is determined for one of the plurality of elements associated with the selected vector register based on a read element counter of the selected vector register. A word is selected in a memory array of the selected vector register as read data based on the element address. The read data is output from the selected vector register based on the decoding of the vector register address by the address decoder. | 2014-02-13 |
20140047215 | STALL REDUCING METHOD, DEVICE AND PROGRAM FOR PIPELINE OF PROCESSOR WITH SIMULTANEOUS MULTITHREADING FUNCTION - The disclosure provides a technique for suppressing the occurrence of stalling caused by data dependency other than register dependency in an out-of-order processor. A stall reducing program includes a handler for detecting a stall occurring during execution of execution code using a PMU, and identifying, based on dependencies, a second instruction dependent on data of a first instruction causing the stall based on this dependency; a profiler registering the second instruction as profile information; and an optimization module for inserting a thread yield instruction in the appropriate position inside the execution code or original code file based on the profile information, and outputting the optimized execution code. | 2014-02-13 |
20140047216 | Scalable Decode-Time Instruction Sequence Optimization of Dependent Instructions - Producer-consumer instructions, comprising a first instruction and a second instruction in program order, are fetched requiring in-order execution, the second instruction is modified by the processor so that the first instruction and second instruction can be completed out-of-order, the modification comprising any one of extending an immediate field of the second instruction using immediate field information of the first instruction or providing a source location of the first instruction as an additional source location to source locations of the second instruction. | 2014-02-13 |
20140047217 | SATISFIABILITY CHECKING - A satisfiability checking system may include a single instruction, multiple data (SIMD) machine configured to execute multiple threads in parallel. The multiple threads may be divided among multiple blocks. The SIMD machine may be further configured to perform satisfiability checking of a formula including multiple parts. The satisfiability checking may include assigning one or more of the parts to one or more threads of the multiple threads of a first block of the multiple blocks. The satisfiability checking may further include processing the assigned one or more parts in the first block such that first results are calculated based on a first proposition. The satisfiability checking may further include synchronizing the results among the one or more threads of the first block. | 2014-02-13 |
20140047218 | MULTI-STAGE REGISTER RENAMING USING DEPENDENCY REMOVAL - Multi-stage register renaming using dependency removal is described. In an embodiment, the registers are renamed in two stages. The first stage involves removing all the dependencies within a set of instructions which are being renamed together. The final stage then renames all registers in parallel using a renaming map. In various embodiments, the dependencies are removed in the first stage using a fixed mapping to rename destination registers in each instruction and in some embodiments the fixed mapping is based on the position of a destination register within the set of instructions. Dependent registers, which are those registers which are read in an instruction but have been written in a previous instruction in the set, are also renamed in the first stage. In addition to performing the renaming in the final stage, the renaming map is updated. | 2014-02-13 |
20140047219 | Managing A Register Cache Based on an Architected Computer Instruction Set having Operand Last-User Information - A multi-level register hierarchy is disclosed comprising a first level pool of registers for caching registers of a second level pool of registers in a system wherein programs can dynamically release and re-enable architected registers such that released architected registers need not be maintained by the processor, the processor accessing operands from the first level pool of registers, wherein a last-use instruction is identified as having a last use of an architected register before being released, the last-use architected register being released causes the multi-level register hierarchy to discard any correspondence of an entry to said last use architected register. | 2014-02-13 |
20140047220 | Residual Addition for Video Software Techniques - According to some embodiments, a technique provides for the execution of an instruction that includes receiving residual data of a first image and decoded pixels of a second image, zero-extending a plurality of unsigned data operands of the decoded pixels producing a plurality of unpacked data operands, adding a plurality of signed data operands of the residual data to the plurality of unpacked data operands producing a plurality of signed results; and saturating the plurality of signed results producing a plurality of unsigned results. | 2014-02-13 |
20140047221 | FUSING FLAG-PRODUCING AND FLAG-CONSUMING INSTRUCTIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA - Fusing flag-producing and flag-consuming instructions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a flag-producing instruction indicating a first operation generating a first flag result is detected in an instruction stream by an instruction processing circuit. The instruction processing circuit also detects a flag-consuming instruction in the instruction stream indicating a second operation consuming the first flag result as an input. The instruction processing circuit generates a fused instruction indicating the first operation generating the first flag result and indicating the second operation consuming the first flag result as the input. In this manner, as a non-limiting example, the fused instruction eliminates a potential for a read-after-write hazard between the flag-producing instruction and the flag-consuming instruction. | 2014-02-13 |
20140047222 | METHOD AND DEVICE FOR RECOMBINING RUNTIME INSTRUCTION - A method for recombining runtime instruction comprising: an instruction running environment is buffered; the machine instruction segment to be scheduled is obtained; the second jump instruction which directs an entry address of an instruction recombining platform is inserted before the last instruction of the obtained machine instruction segment to generate the recombined instruction segment comprising the address A″; the value A of the address register of the buffered instruction running environment is modified to the address A″; the instruction running environment is recovered. A device for recombining the runtime instruction comprising: an instruction running environment buffering and recovering unit suitable for buffering and recovering the instruction running environment; an instruction obtaining unit suitable for obtaining the machine instruction segment to be scheduled; an instruction recombining unit suitable for generating the recombined instruction segment comprised the address A″; and an instruction replacing unit suitable for modifying the value of the address register of the buffered instruction running environment to the address of the recombined instruction segment. The monitoring and control of the runtime instruction of the computing device is completed. | 2014-02-13 |
20140047223 | SELECTIVELY ACTIVATING A RESUME CHECK OPERATION IN A MULTI-THREADED PROCESSING SYSTEM - This disclosure describes techniques for selectively activating a resume check operation in a single instruction, multiple data (SIMD) processing system. A processor is described that is configured to selectively enable or disable a resume check operation for a particular instruction based on information included in the instruction that indicates whether a resume check operation is to be performed for the instruction. A compiler is also described that is configured to generate compiled code which, when executed, causes a resume check operation to be selectively enabled or disabled for particular instructions. The compiled code may include one or more instructions that each specify whether a resume check operation is to be performed for the respective instruction. The techniques of this disclosure may be used to reduce the power consumption of and/or improve the performance of a SIMD system that utilizes a resume check operation to manage the reactivation of deactivated threads. | 2014-02-13 |
20140047224 | METHOD OF FLASHING BIOS USING SERVICE PROCESSOR AND COMPUTER SYSTEM USING THE SAME - A method of flashing a BIOS memory of a computer system is described herein. The method includes executing a kernel of baseboard management controller (BMC) to create a partition for the BMC memory and a second partition for the BIOS memory; detecting whether the host processor is accessing the BIOS memory; controlling a multiplexer (MUX) to allow the first processor to access the BIOS memory when the host processor is not accessing the BIOS memory; and retrieving first BIOS software from the BMC memory and writing the first BIOS software to the BIOS memory. | 2014-02-13 |
20140047225 | METHOD AND SYSTEM FOR IMPLEMENTING PRIMARY AND SECONDARY ZONES IN A VIRTUALIZED ENVIRONMENT - A system including a processor and a host operating system (OS) executing on the processor. The Host OS including a global zone, a first primary non-global (NG) zone associated with a first label and a first internet protocol (IP) address, where the first primary NG zone is accessible by a desktop layer of the system. The Host OS further including a second primary NG zone associated with a second label and the first IP address, wherein the second primary NG zone is accessible by the desktop layer of system. The global zone is configured to receive a first request to create a secondary NG zone with the first label, and in response to the first request, create the secondary NG zone associated with the first label and a second IP address, where the secondary NG zone is not accessible by the desktop layer of the system. | 2014-02-13 |
20140047226 | MANAGING HARDWARE CONFIGURATION OF A COMPUTER NODE - A method and computer program product for configuring the hardware devices of a computer node are disclosed. The method comprises the computer node receiving a user identification, and identifying a hardware configuration of the computer node that is stored in association with the user identification, wherein the hardware configuration identifies a subset of the hardware devices within the computer node that are not to receive power. The hardware configuration may be stored in associated with the user identification, for example by an administrator during setup. In one option, the computer node receives the user identification during user logon to the computer node. The method further comprises controlling power to the hardware devices of the computer node to implement the identified hardware configuration without physically removing the subset of hardware devices. Power is provided to the computer node except for the subset of the hardware devices. | 2014-02-13 |
20140047227 | SYSTEM AND METHOD FOR CONFIGURING BOOT-TIME PARAMETERS OF NODES OF A CLOUD COMPUTING SYSTEM - The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes providing a user interface comprising selectable boot-time configuration data and selecting, based on at least one user selection of the boot-time configuration data, a boot-time configuration for at least one node of a cluster of nodes of the computing system. The method further includes configuring the at least one node of the cluster of nodes with the selected boot-time configuration to modify at least one boot-time parameter of the at least one node. | 2014-02-13 |
20140047228 | Configuring a System with Various System Components Utilizing a Configuration Profile - According to an embodiment of the present invention, a computer system for configuring a system with at least two different system components based on a target computing environment includes at least one processor. The computer system generates a profile to configure each of the different system components for the target computing environment. The profile identifies the corresponding tasks to be performed and properties to configure each of the different system components for the target computing environment. The computer system processes the profile and performs the tasks in the order listed in the profile and in accordance with the properties to configure the system for the target computing environment. Embodiments of the present invention further include a method and computer program product for configuring a system with at least two different system components based on a target computing environment in substantially the same manner described above. | 2014-02-13 |
20140047229 | USING A TRUSTED PLATFORM MODULE FOR BOOT POLICY AND SECURE FIRMWARE - Embodiments of apparatuses and methods for using a trusted platform module for boot policy and secure firmware are disclosed. In one embodiment, a trusted platform module includes a non-volatile memory, a port, and a mapping structure. The port is to receive an input/output transaction from a serial bus. The transaction includes a system memory address in the address space of a processor. The mapping structure is to map the system memory address to a first location in non-volatile memory. | 2014-02-13 |
20140047230 | COMPUTING DEVICE AND METHOD FOR WIRELESS REMOTE BOOT IN A NETWORKED ENVIRONMENT - In some embodiments, a secure authenticated remote boot of computing device over a wireless network is performed in a pre-boot execution environment (PXE) using active management technology (AMT) for remote discovery. In these embodiments, a management engine (ME) may maintain full control of a wireless interface and a wireless connection as booting begins. The ME may relinquish control of the wireless interface after a PXE timeout, in response to a shutdown command, or once the device has booted. The ME controls the use of an operating system received from a remote location. | 2014-02-13 |
20140047231 | Secure Sub-Joined Computing Device - A system includes a sleeve capable of allowing a host-computing device to be positioned therein. The sleeve itself includes a processing device and a serial interface adapter to allow communication between the secure sub-joined computing device and the host communication device. The secure sub-joined computing device will include an authentication device to authenticate the identity of the user. The secure sub-joined computing device will be able to accommodate a wide variety of host devices and provide an exclusive computing environment where strong authentication and encryption can be performed with or without the knowledge of the host device and host means to communicate the data from the device. The secure sub joined computing device can be configured to be limited to operate within a configured geographic boundary. The system includes software such as the source or executable files necessary to perform the instructions or algorithms. | 2014-02-13 |
20140047232 | Query Interface to Policy Server - A scalable access filter that is used together with others like it in a virtual private network to control access by users at clients in the network to information resources provided by servers in the network. Each access filter uses a local copy of an access control data base to determine whether an access request is made by a user. Each user belongs to one or more user groups and each information resource belongs to one or more information sets. Access is permitted or denied according to access policies which define access in terms of the user groups and information sets. The first access filter in the path performs the access check, encrypts and authenticates the request; the other access filters in the path do not repeat the access check. The interface used by applications to determine whether a user has access to an entity is now an SQL entity. The policy server assembles the information needed for the response to the query from various information sources, including source external to the policy server. | 2014-02-13 |
20140047233 | SYSTEM AND METHODS FOR AUTOMATED TRANSACTION KEY GENERATION AND AUTHENTICATION - An independent, centralized token service that generates and authenticates transactions keys. The keys may be exchanged amongst registered users for use in a versatile variety of transactions and/or as a means of identification, authentication, and/or authorization. The service enables customization and recipient designation of the keys, as well as multi-party, multi-directional, multi-key exchanges. | 2014-02-13 |
20140047234 | ADAPTIVE DOCUMENT REDACTION - Described are computer-based methods and apparatuses, including computer program products, for adaptive document redaction. A container is generated comprising a set of redacted documents corresponding to an original document, each redacted document having a level of redaction corresponding to a viewing location, and a header comprising encryption information for each redacted document in the set of redacted documents. A request to view the original document is received from a requesting device. The container is transmitted to the requesting device. A request for additional encryption information for a redacted document from the set of redacted documents is received from the requesting device, wherein the redacted document comprises a level of redaction for a viewing location that is equal to a location of the requesting device. The additional encryption information is transmitted to the requesting device. | 2014-02-13 |
20140047235 | LOCAL TRUSTED SERVICE MANAGER - A method for managing a secure element which is embedded into a host unit. The described method comprises (a) transmitting a request for a management script from the host unit to a program element of the secure element, (b) at the program element, generating a management script in accordance with the request and encrypting the generated management script, (c) transmitting the encrypted management script from the program element to the host unit, (d) transmitting the encrypted management script from the host unit to a secure domain of the secure element, and (e) at the secure domain, decrypting and executing the management script. | 2014-02-13 |
20140047236 | AUTHENTICATED FILE HANDLES FOR NETWORK FILE SYSTEMS - One or more file sharing computers receives a client request including an IP address and port number used by the client (computer). The one or more computers respond by creating an enhanced file handle from a hash on a combination of the IP address, port number, restricted key, and a standard file handle, and concatenating the hash with the standard file handle. The enhanced file handle is sent to the client and used by the client in a second request. The one or more computers uncouple the standard file handle and hash combination. Using the client IP address, port number, restricted key and standard file handle from the client second request, the one or more computers create a second combination. The second combination hash is compared to the first combination hash and in response to determining a match, the second request is accepted, and otherwise denied. | 2014-02-13 |
20140047237 | Method and System for Establishing Secure Communications Using Composite Key Cryptography - A method is disclosed for establishing a secure communication session using composite key cryptography. The method comprises generating a first plurality of secret keys all of which are known only to a first communicating party and each one of which is shared with exactly one of a plurality of stewards, and generating a second plurality of secret keys all of which are known only to a second communicating party and each one of which is shared with exactly one of the plurality of stewards. The first and second communicating parties each send information to the other through different stewards, each communication leg being encrypted using a secret key known only to the respective communicating party and steward. These communications are usable to distribute cryptographic seeds to the communicating parties for use in generating a temporary session key that can be used to encrypt direct communications between the parties. | 2014-02-13 |
20140047238 | DEVICE IDENTIFICATION USING SYNTHETIC DEVICE KEYS - A device authentication server assigns unique synthetic device attributes to a device such that the device can use actual hardware and system configuration attributes and the assigned synthetic device attributes to form a device identifier that is unique, even among homogeneous devices for which actual, accessible hardware and system configuration attributes are not distinct. | 2014-02-13 |
20140047239 | AUTHENTICATOR, AUTHENTICATEE AND AUTHENTICATION METHOD - According to one embodiment, an authenticatee includes a memory configured to store a plurality of pieces of secret information XY and a plurality of pieces of secret information XY | 2014-02-13 |
20140047240 | DATA RECORDING DEVICE, AND METHOD OF PROCESSING DATA RECORDING DEVICE - A controller is provided with a controller key and a first controller identification information unique to the controller. The controller generates a controller unique key unique to a respective controller based on the controller key and the first controller identification information, and a second controller identification information based on the first controller identification information. A decryptor decrypts the encrypted medium device key using the controller unique key to obtain a medium device key. An authentication/key exchange process unit performs authentication/key exchange process with the host device through an interface unit using the medium device key, the medium device key certificate and the second controller identification information to establish a secure channel. | 2014-02-13 |
20140047241 | DATA RECORDING DEVICE, HOST DEVICE AND METHOD OF PROCESSING DATA RECORDING DEVICE - A data storage unit can store an encrypted medium device key Enc (Kcu, Kmd_i), and a medium device key certificate (Certmedia). A controller can include an information recording unit to store a controller key (Kc) and first controller identification information (IDcu). A key generation unit executes a one-way function calculation based on the controller key and the first controller identification information to generate a controller unique key (Kcu). An identification information generating unit executes a one-way function calculation based on the controller key and the first controller identification information to generate second controller identification information (IDcntr). A key encryption unit encrypts the medium device key (Kmd_i) by the controller unique key (Kcu) to generate encrypted medium device key Enc (Kcu, Kmd_i). A key exchange unit executes an authentication key exchange process with a host device using the medium device key (Kmd_i) and the medium device key certificate (Certmedia). | 2014-02-13 |
20140047242 | METHOD AND SYSTEM FOR PRESERVING PRIVACY DURING DATA AGGREGATION IN A WIRELESS SENSOR NETWORK - A computer-based system and method for secured privacy preservation scheme while data aggregation in a non-hierarchical wireless sensor network that lacks peer-to-peer communication between the communicating sensor nodes is disclosed. The method and system adopts formation of self-adaptive efficient cluster formation for robust privacy preservation in the network by grouping the multiple sensor nodes in the network to form multiple clusters that enables low computation overhead and high scalability in the network. The method and system of the invention discloses an effective twin-key management scheme that provides establishment of secure communication among the sensor nodes and the secure communication between at least one sensor node with the sever node performing the function data aggregation of the data collected by the sensor nodes. | 2014-02-13 |
20140047243 | System and Method for Pre-Boot Authentication of a Secure Client Hosted Virtualization in an Information Handling System - A client hosted virtualization system (CHVS) includes a processor to execute code, a component, and a non-volatile memory. The non volatile memory includes BIOS code and code to implement a virtualization manager. The virtualization manager is operable to initialize the CHVS, launch a virtual machine on the CHVS, and assign the component to the virtual machine, such that the virtual machine has control of the component. The CHVS is configurable to execute the BIOS and not the virtualization manager, or to execute the virtualization manager and not the BIOS. | 2014-02-13 |
20140047244 | PROTECTION OF INTERPRETED SOURCE CODE IN VIRTUAL APPLIANCES - Protection of interpreted programming language code filesystem files from access and alteration may be provided by encrypting a file to be protected in a boot sequence. Run-time examination of a virtual appliance may be deterred by hiding the boot sequence in a restricted virtual appliance platform. No shell or filesystem access may be provided. Thus, permissions on a read-only filesystem (for example) may be kept from being altered. The permissions may be set along with filesystem access control lists to prevent unauthorized examination of the source files. | 2014-02-13 |
20140047245 | IDENTIFICATION AND EXECUTION OF SUBSETS OF A PLURALITY OF INSTRUCTIONS IN A MORE SECURE EXECUTION ENVIRONMENT - Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for identifying and encrypting a subset of a plurality of instructions, for execution in a more secure execution environment. In various embodiments, the subset may include a single entry point and a single exit point. In various embodiments, one or more instructions of the plurality of instructions that precede or follow the subset may be executed in a first execution environment with a first security level. In various embodiments, the subset may be executed in a second execution environment with a second security level that is more secure than the first security level. | 2014-02-13 |
20140047246 | FLASH MEMORY DEVICE INCLUDING KEY CONTROL LOGIC AND ENCRYPTION KEY STORING METHOD - A flash memory device is provided which includes a plurality of memory cells connected with a word line and including a key cell to store an encryption key; a data input/output circuit configured to receive the encryption key; and key control logic configured to control a program operation on the key cell and to use a column address of the key cell as the encryption key. | 2014-02-13 |
20140047247 | Microprocessor Unit Capable of Multiple Power Modes - A power mode control system for microprocessors offers an unlimited variety of hardware-supported power modes that may satisfy any operating scenario. The microprocessor unit comprises a register that contains particular bit fields for defining selectable power modes. The particular bit fields in the register define pointers to a power mode defining register. Each pointer selects a corresponding bit field in the power mode defining register. The bits in the bit fields of the power mode defining register either directly control a power mode of at least one functional or peripheral blocks of the unit; or they are pointers to a further power mode defining register and the bits in the bit fields of the further power mode defining register directly control a power mode of at least one functional or peripheral blocks of the unit. | 2014-02-13 |
20140047248 | METHOD OF CONTROLLING A LOAD CURRENT, LOAD CURRENT CONTROL DEVICE, AND MOBILE DEVICE HAVING THE SAME - A method of controlling a load current is provided. By the method, a battery voltage control operation is begun when a battery voltage becomes lower than a first threshold value, whether a gradient of the battery voltage is a positive gradient or a negative gradient is determined at an interval of a reference or, alternatively, predetermined control time, the load current is controlled based on the gradient of the battery voltage at an interval of the reference or, alternatively, predetermined control time, and the battery voltage control operation is finished when the battery voltage becomes higher than a second threshold value. | 2014-02-13 |
20140047249 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD THEREOF, AND STORAGE MEDIUM - An information processing apparatus (MFP) according to this invention cyclically inquires, of a server, whether to activate the power source during the stop of the second power source functioning as the main power source of the MFP. The NIC of the MFP that operates by using the first power source as a power source establishes a link for an inquiry to the server, and calculates an electric energy consumed for the inquiry based on the link rate of the established link and the time taken for the inquiry. Further, the NIC adjusts the cycle of the inquiry so that the average power consumption of the MFP in the state in which the second power source is stopped, that is determined by the calculated consumed electric energy, does not exceed a threshold corresponding to a target power. | 2014-02-13 |
20140047250 | SINGLE PIN COMMUNICATION MECHANISM - A method and device include a power pin, a ground pin, and a communications pin. A communications module receives power from the power pin and utilizes an edge counting communication protocol over the communication pin. | 2014-02-13 |
20140047251 | METHODS, SYSTEMS AND DEVICES FOR HYBRID MEMORY MANAGEMENT - In the various aspects, virtualization techniques may be used to improve performance and reduce the amount of power consumed by translating virtual memory addresses into physical addresses on a computing system having hybrid memory. In a first stage of memory translation, an operating system translates virtual addresses to intermediate physical addresses. In a second stage of memory translation, a chip or virtualization software translates the intermediate physical address to physical addresses based on the characteristics of the physical memory and the characteristics of the processes associated with the physical memory. | 2014-02-13 |
20140047252 | HIERARCHICAL ENERGY OPTIMIZATION FOR DATACENTER NETWORKS - Technologies are presented for power optimization of datacenter networks in a hierarchical perspective. In some examples, a two-level power optimization model may be established to reduce the power consumption of datacenter networks by switching off network switches and links while still guaranteeing full connectivity and maximum link utilization. The model may be implemented by solving a capacitated constraint multi-commodity flow (CMCF) problem employing simple heuristic techniques. A power status of network switches may be determined according to a network traffic matrix and the CMCF optimization determined at core-level and at pod-level. A complementary process to provision whole network connectivity and to meet quality of service (QoS) goals may also be performed. | 2014-02-13 |
20140047253 | MULTIMEDIA PROCESSING SYSTEM AND METHOD OF OPERATING THE SAME - The multimedia processing system includes a plurality of first units including a CPU and a top domain; a storage domain configured to store a plurality of multimedia data; a multimedia codec domain configured to decode segments of target multimedia data received from the storage domain and to output decoded segments according to control of the CPU or the top domain; a system bus configured to connect the plurality of first units, the storage domain, and the multimedia codec domain with one another; and an alive domain configured to control power supply to the plurality of first units, the storage domain, the multimedia codec domain, and the system bus and to receive a signal from a user. | 2014-02-13 |
20140047254 | Sleep Mode Operation for Networked End Devices - A technique provides apparatuses, methods, and computer readable media for sending sleep information from an end device to a central unit of a network, in which the wake-up time of the end device is aligned to the scanning time for the central unit. The technique addresses at least two considerations: the clock accuracy of the end device is accounted for, and the reason that the end device requests sleep mode operation is provided. To address the above considerations, the end device may send its clock tolerance information and/or request for sleep mode (RSM) command to the central unit once the end device is connected via the network. The central unit may then adjust the scanning time based on the clock tolerance information. If the central unit receives a response from the end device during the adjusted scanning time, the central unit deems that the end device is still connected. | 2014-02-13 |
20140047255 | ON-BOARD NETWORK SYSTEM - An on-board network system is presented. The on-board network system sends a sleep-entered message to a communication bus. The sleep-entered message is sent under a condition that a sleep condition is satisfied on a basis that a network management (NM) message is ceased during state transition process in which node's state transfers from a normal state to a power-saving state. A monitoring ECU corresponding to a master performs an abnormality detection process. In the abnormality detection process, the monitoring ECU detects an abnormality state of the state transition process based on whether or not the sleep-entered message is sent from any one of nodes, thereby it is possible to detect the abnormality state not only during each node is a normal state but also during a bus-sleep state. | 2014-02-13 |
20140047256 | TERMINAL DEVICE AND METHOD FOR OPERATING THE SAME - The present disclosure discloses terminal devices and a method of operating the same, and relates to the field of terminal technology. The method includes: obtaining a current load occupancy parameter of a terminal device; and adjusting a working parameter of the terminal device's processing unit based on the current load occupancy parameter of the terminal device. The present disclosure can estimate the actual occupancy of a terminal device based on the load occupancy parameter of the terminal device, and can adjust a working parameter of the processing unit in real-time based on the load occupancy parameter, thereby controlling and reducing power usage from the bottom layer of the terminal device. In contrast to existing technologies, the disclosure does not require stopping certain services on the terminal device to achieve the goal of saving power, and power can be saved without affecting the normal operations of the terminal device. | 2014-02-13 |
20140047257 | POWER MANAGEMENT TECHNIQUES FOR USB INTERFACES - Power management techniques for a Universal Serial Bus (USB) include determining an idle period on one or more USB ports by a main controller circuit of a USB host controller. The main controller circuit signals a suspend to a Power Management Controller (PMC) sub-circuit of the USB host controller, in response to the determined idle period. The PMC sub-circuit stores one or more operating parameters of the one or more USB ports in response to the suspend signal. The PMC sub-circuit also maintains the idle state on the one or more USB ports in response to the suspend signal. Thereafter, the main controller circuit is placed in a low energy state while the PMC sub-circuit maintains the idle state. | 2014-02-13 |
20140047258 | AUTONOMOUS MICROPROCESSOR RE-CONFIGURABILITY VIA POWER GATING EXECUTION UNITS USING INSTRUCTION DECODING - In an embodiment, a functional unit control system includes an instruction decoder of a processor comprising a pipeline, the instruction decoder being configured to decode an instruction to be performed by the processor. The system further includes a power controller unit coupled to the instruction decoder, and a functional unit which may operate during execution stages of the processor's pipeline coupled to the power controller unit and the instruction decode stage. The power controller unit is configured to determine whether the functional unit should be used to perform at least part of the instruction based on data of the instruction decoder. The power controller unit is further configured to perform at least one of activating and deactivating the functional unit in accordance with the determination of whether the functional unit should be used. | 2014-02-13 |
20140047259 | Methods and Apparatus for Mobile Device Power Management Using Accelerometer Data - A computer-implemented method for power management in a portable device includes receiving sensor information from a sensor in the portable device, associating the sensor information with one of a plurality of states of the portable device, and reducing electrical power consumption in one or more parts in the portable device according to the associated state of the portable device. In some embodiments, the method also includes collecting, from the accelerometer in the portable device, electrical signals associated with a plurality of known motion states of the portable device, and analyzing the collected electrical signals. The method also includes identifying attributes of the electrical signal with the known motion states of the portable device. | 2014-02-13 |
20140047260 | NETWORK MANAGEMENT SYSTEM, NETWORK MANAGEMENT COMPUTER AND NETWORK MANAGEMENT METHOD - A network management system comprising: a network including a plurality of packet relay apparatuses; wherein the plurality of packet relay apparatuses include first packet relay apparatuses, second packet relay apparatuses, and third packet relay apparatuses located downstream of the first packet relay apparatuses and the second packet relay apparatuses, wherein each of the third packet relay apparatuses has a first path coupled to one of the first packet relay apparatuses to send and receive traffic and a second path coupled to one of the second packet relay apparatuses and being in a blocking state, a management computer includes: a state information collection unit for acquiring state information on the first to the third packet relay apparatuses; and a power management unit for selecting a candidate packet relay apparatus to be deactivated satisfying predetermined conditions based on the state information. | 2014-02-13 |
20140047261 | DATA STORAGE POWER MANAGEMENT - Embodiments of the present disclosure are directed to, among other things, managing power of one or more data storage devices. In some examples, a storage service may obtain a schedule associated with enabling different storage devices at different times. The storage service may also identify a request of a batch of requests for accessing the storage devices. In some cases, the storage service may also determine which storage device to activate based at least in part on the schedule and/or the request. Further, the storage service may manage power of a storage device based at least in part on the determination of which storage device to activate. | 2014-02-13 |
20140047262 | MULTIPLE CLOCK DOMAIN TRACING - An integrated circuit with multiple clock domain tracing capability includes a debug module including a global time stamp counter for counting pulses of a reference clock signal to provide a global time stamp, a first granularity counter for counting pulses of a first clock signal to provide a first granularity count, a second granularity counter fir counting pulses of a second clock signal to provide a second granularity count and a trace cache buffer for selectively storing in a first partition the global time stamp, the first granularity count, and first data synchronous to the first clock signal, and for selectively storing in a second partition the global time stamp, the second granularity count, and second data synchronous to the second clock signal. | 2014-02-13 |
20140047263 | SYNCHRONOUS LOCAL AND CROSS-SITE FAILOVER IN CLUSTERED STORAGE SYSTEMS - Synchronous local and cross-site switchover and switchback operations of a node in a disaster recovery (DR) group are described. In one embodiment, during switchover, a takeover node receives a failover request and responsively identifies a first partner node in a first cluster and a second partner node in a second cluster. The first partner node and the takeover node form a first high-availability (HA) group and the second partner node and a third partner node in the second cluster form a second HA group. The first and second HA groups form the DR group and share a storage fabric. The takeover node synchronously restores client access requests associated with a failed partner node at the takeover node. | 2014-02-13 |
20140047264 | COMPUTER INFORMATION SYSTEM AND DYNAMIC DISASTER RECOVERY METHOD THEREFOR - The method is performed as a client device and includes receiving a first message that includes a first data usage value. The first message is formatted according to a respective format. After receiving the first message, the method further includes acquiring a data usage template corresponding to the respective format. The method further includes receiving a second message that includes a second data usage value. The second message is formatted according to the respective format. The method further includes parsing the second message according to the data usage template so as to obtain a second data usage value. | 2014-02-13 |
20140047265 | ENHANCED STORAGE OF METADATA UTILIZING IMPROVED ERROR DETECTION AND CORRECTION IN COMPUTER MEMORY - A novel ECC scheme is disclosed that offers an error protection level that is at least the same as (if not better than) that of the conventional ECC scheme without negatively impacting latency and design complexity. Embodiments of the present disclosure utilize an ECC scheme which leaves up to extra 2B for metadata storage by changing the error detection and correction process flow. The scheme adopts an early error detection mechanism, and tailors the need for subsequent error correction based on the results of the early detection. | 2014-02-13 |
20140047266 | Distributed System for Fault-Tolerant Data Storage - Fault-tolerant storage is provided using a distributed data storage system that receives input data from clients and divides that data into data blocks for storage. The data blocks are processed using a coding scheme that generates redundant level one error correction blocks (L1EC Blocks). The L1EC blocks enable the reconstruction of one or more damaged or inaccessible data blocks, and the L1EC blocks and the data blocks are divided into distribution sets and stored at a plurality of data storage locations. At each data storage location additional level two error correction blocks (L2EC blocks) are generated that provide local data redundancy. Upon detecting a data disruption event, an inaccessible data storage location is identified and the elements that were stored at the inaccessible data storage location are reconstructed. | 2014-02-13 |
20140047267 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR RECONSTRUCTING DATA RECEIVED BY A COMPUTER IN A MANNER THAT IS INDEPENDENT OF THE COMPUTER - A data reconstruction system, method and computer program product are provided. In use, one of a plurality of computers receiving data over a network is identified. In addition, the data received by the computer is reconstructed in a manner that is independent of the computer. | 2014-02-13 |
20140047268 | Systems, Methods, and Computer Program Products for Instant Recovery of Image Level Backups - Systems, methods, and computer program products are provided for instant recovery of a virtual machine (VM) from a compressed image level backup without fully extracting the image level backup file's contents to production storage. The method receives restore parameters and initializes a virtual storage. The method attaches the virtual storage to a hypervisor configured to launch a recovered VM. The method stores virtual disk data changes inflicted by a running operating system (OS), applications, and users in a changes storage. The method provides the ability to migrate the actual VM disk state (taking into account changed disk data blocks accumulated in changes storage) so as to prevent data loss resulting from the VM running during the recovery and accessing virtual storage, to production storage without downtime. In embodiments, the method displays receives restore parameters in an interactive interface and delivers the recovery results via an automated message, such as an email message. | 2014-02-13 |
20140047269 | OPERATING METHOD FOR MEMORY SYSTEM INCLUDING NONVOLATILE RAM AND NAND FLASH MEMORY - An operating method for a memory system including a nonvolatile random access memory (NVRAM) and a NAND flash memory includes; performing a normal read operation directed to the target memory cell in response to a read request, determining that a read fail has occurred as a result of the normal read operation, then performing a read retry operation by iterations directed to the target memory cell according to a first read retry scheme until a pass read retry iteration successfully reads the target memory cell, and storing pass information associated with the pass read retry iteration in the NVRAM. | 2014-02-13 |
20140047270 | DATA SOURCE INTERFACE ENHANCED ERROR RECOVERY - The invention provides for the connection of a plurality of remote applications with a data source, to maximize the speed and reliability of data transfer. An interface module interfaces with a remote application such as a web browser. A port module interfaces between interface module and a data source. A connection manager facilitates the interface between the interface module and the port module. The port module detects the unavailability of the data source in response to an initial request for the data source by the remote application. The port module may then dynamically detect the availability of the data source in response to a subsequent request for the data source and re-connect to the data source to the remote application in response to the subsequent request without having to reinitialize the connection manager. | 2014-02-13 |
20140047271 | METHOD FOR TESTING THE RELIABILITY OF COMPLEX SYSTEMS - A method for testing the reliability of complex systems, and includes the evaluation and optimisation of the availability of such systems. | 2014-02-13 |
20140047272 | SYSTEM AND METHOD FOR CONFIGURING A CLOUD COMPUTING SYSTEM WITH A SYNTHETIC TEST WORKLOAD - The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes selecting, based on a user selection received via a user interface, a workload for execution on a cluster of nodes of the computing system. The workload is selected from a plurality of available workloads including an actual workload and a synthetic test workload. The method further includes configuring the cluster of nodes of the computing system to execute the selected workload such that processing of the selected workload is distributed across the cluster of nodes. The synthetic test workload may be generated by a code synthesizer based on a set of user-defined workload parameters provided via a user interface that identify execution characteristics of the synthetic test workload. | 2014-02-13 |
20140047273 | Administering Checkpoints For Incident Analysis - Methods, apparatuses, and computer program products for administering checkpoints for incident analysis are provided. Embodiments include a checkpoint manager receiving from each incident analyzer of a plurality of incident analyzers, a checkpoint indicating an incident having the oldest identification number still in analysis by the incident analyzer at the time associated with the checkpoint. The checkpoint manager examines each received checkpoint to identify, as a restore incident, an incident having the oldest identification number indicated in any of the received checkpoints. A monitor sends to the incident analyzers, a stream of incidents beginning with the identified restore incident and continuing with any incidents having a newer identification number than the identified restore incident. Each incident analyzer processes from the stream of incidents only the incident indicated in the last checkpoint of the incident analyzer and any subsequent incidents having a newer identification number than the indicated incident. | 2014-02-13 |
20140047274 | Network Debugging - A debugging system used for a data center in a network is disclosed. The system includes a monitoring engine to monitor network traffic by collecting traffic information from a network controller, a modeling engine to model an application signature, an infrastructure signature, and a task signature using a monitored log, a debugging engine to detect a change in the application signature between a working status and a non-working status using a reference log and a problem log, and to validate the change using the task signature, and a providing unit to provide toubleshooting information, wherein an unknown change in the application signature is correlated to a known problem class by considering a dependency to a change in the infrastructure signature. Other methods and systems also are disclosed. | 2014-02-13 |
20140047275 | FLOW BASED FAULT TESTING - Flow based fault testing is provided. A logical constraint model or a state model (LS model) can be generated based on logic/state characteristics of a system under test (SUT). The LS model can be generated from logical constraint grammar statements. The logical constraint grammar can be parsed as part of a pre-test analysis to seek faults related to the logic or states of the model. The inputs and outputs related to the SUT can be employed to determine faults, including post-test analysis for faults. The disclosed subject matter can capture in an automated or semi-automated manner faults that can be missed in more conventional fuzz testing. Further, flow based fault testing can be employed alone, along with, or in combination with conventional fuzz testing. | 2014-02-13 |
20140047276 | MODEL-BASED TESTING OF A GRAPHICAL USER INTERFACE - This invention provides a method, computer program and system for updating of a model of a system under test for use in model-based testing. In one embodiment, the system includes a rules engine, a comparator and a message dictionary. The rules engine runs an action against the system under test and runs the action against a model under test. The comparator compares an output from the system under test with a corresponding output from the model under test, wherein the output from the model under test is selected from one of a plurality of output message records. The dictionary engine updates the output message record by changing the message record if the output of the model under test is different from the output of the system under test. If the output message record is empty, the dictionary engine adds an output message record based on the system under test. | 2014-02-13 |
20140047277 | COMPUTER HARDWARE AND SOFTWARE DIAGNOSTIC AND REPORT SYSTEM INCORPORATING AN EXPERT SYSTEM AND AGENTS - The diagnostic and report system tests computer systems for defects that are able to cause performance and functional problems. An agent application is first installed on a user's system. The agent application then retrieves problem data from the expert system library pertinent to the user's operating environment. The agent application tests the user's system for each problem description within a downloaded data structure from the expert system library. If a problem is discovered, a script attempts to remediate the problem and/or notifies the user, describing the issue. The agent application utilizes discrete programs and/or scripts to send data to a knowledge base so that the knowledge base is able to generate new discrete programs and/or scripts using artificial intelligence which are sent to the expert system library. With additional discrete programs and/or scripts, the user's system is better protected. | 2014-02-13 |
20140047278 | AUTOMATIC TESTING OF A COMPUTER SOFTWARE SYSTEM - The invention relates to a method of automatic testing of a software system through test driver code that classifies test data into equivalence classes and updates the available test data after using it against the software system. One embodiment of the invention is a Test Runner that monitors the effect of calling the software system on the available test data and uses this information to automatically determine the execution order of test cases to meet a number of objectives including to: Reuse data between calls, ensure all test cases are executed, perform parallelized testing, perform time dependent testing, perform continuous testing according to a probability distribution on test cases, perform automated management of complex test data and finally to provide an easy and concise way for a user to define a large sets of test cases. | 2014-02-13 |
20140047279 | Fault Localization in Distributed Systems Using Invariant Relationships - A computer implemented method for temporal ranking in invariant networks includes considering an invariant network and a set of broken invariants in the invariant network, assuming, for each time point inside a window W, that each metric with broken invariants is affected by a fault at that time point, computing an expected pattern for each invariant of a metric with assumed fault, said pattern indicative of time points at which an invariant will be broken given that its associated metric was affected by a fault at time t, comparing the expected pattern with the pattern observed over the time window W; and determining a temporal score based on a match from the prior comparing | 2014-02-13 |
20140047280 | Second Failure Data Capture in Co-Operating Multi-Image Systems - A method, computer system, and computer program captures diagnostic trace information in a computer system having a plurality of software images. Information is received that is associated with a first failure in a first one of the plurality of software images. The received information is distributed to others of the plurality of software images. Further information is captured that is associated with a second failure in another one of the plurality of software images. The information associated with a first failure in a first one of said plurality of software images is combined with the information associated with a second failure in another of said plurality of software images, and the combined information is analyzed in order to determine a cause of the first failure. | 2014-02-13 |
20140047281 | MEMORY SYSTEM AND MEMORY CONTROLLER - According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. The memory controller includes a monitoring module and a determination module. The monitoring module acquires an elapsed time from the start of data erase of a first block in the NAND-type flash memory. The determination module determines whether the elapsed time has exceeded a reference time before completion of the data write in the first block. | 2014-02-13 |
20140047282 | FLEXRAY NETWORK RUNTIME ERROR DETECTION AND CONTAINMENT - A FlexRay network guardian including: a resetting leading coldstart node (RLCN) detector configured to detect a RLCN failure; a deaf coldstart node (DCN) detector configured to detect a DCN failure; a babbling idiot (BI) detector configured to detect a BI failure; and a FlexRay network decoder configured to output a signal regarding the status of the FlexRay network to the RLCN detector, DCN detector, and BI detector, wherein the RLCN detector, DCN detector, and BI detector are configured to send an indication of a failure to a containment module. | 2014-02-13 |
20140047283 | APPARATUSES, SYSTEMS, DEVICES, AND METHODS OF REPLACING AT LEAST PARTIALLY NON-FUNCTIONAL PORTIONS OF MEMORY - Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory. | 2014-02-13 |
20140047284 | COMBO STATIC FLOP WITH FULL TEST - A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master storage node and a multiplexer. The slave latch circuit includes a slave storage node driven by the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from the master latch circuit and a slave driver driven from the slave latch circuit. | 2014-02-13 |
20140047285 | MEMORY MANAGER - An embodiment of a manager includes at least one input node configured to receive information regarding a region of an integrated circuit, and a determiner configured to determine, in response to the information, a likelihood that the region will cause an error. For example, the region may include a memory, and contents of the memory may be transferred to another, more reliable memory, if the likelihood that the memory will cause an error in the data that it stores equals or exceeds a likelihood threshold. | 2014-02-13 |
20140047286 | SOLID STATE DRIVE TESTER - Disclosed is a solid state drive tester which reduces the size of the tester and easily changes a function without changing hardware (H/W) by implementing a plurality of devices for testing an SSD as one chip using a Field Programmable Gate Array (FPGA). The solid state drive tester includes: a host terminal receiving a test condition for testing a storage from a user; and a test control unit generating a test pattern corresponding to the test condition, adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, and storing fail data generated during the test in an internal memory. The test control unit is implemented by an FPGA to reduce the size of the tester and easily change a function without hardware. | 2014-02-13 |
20140047287 | SOLID STATE DRIVE TESTER - Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time. | 2014-02-13 |
20140047288 | STORAGE INTERFACE APPARATUS FOR SOLID STATE DRIVE TESTER - Disclosed is a storage interface apparatus for a solid state drive (SSD) tester which allows a plurality of interfaces to share a single protocol in parts where the protocol is commonly used in a multiple interface for interfacing a storage. The storage interface apparatus for the solid state driver tester includes: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit for generating a test pattern corresponding to the test condition to test the storage. The test control unit includes a storage interface unit for interfacing the storage, and the storage interface unit includes a plurality of interfaces that share a protocol in parts where the protocol is commonly used. | 2014-02-13 |
20140047289 | FAILURE DETECTION APPARATUS FOR SOLID STATE DRIVE TESTER - Disclosed is a failure detection apparatus for a solid state driver tester, the failure detection apparatus including: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit for creating a test pattern according to the test condition or creating a test pattern at random, and adaptively selecting an interface according to a type of the storage to be tested to test the storage with the test pattern. The test control unit includes a plurality of buffer memories for storing readout data of the storage, stores the readout data in the buffer memories in an interleaving manner, and endows comparison of the created test pattern and the readout data stored in the buffer memories with continuity to test the storage in real time. | 2014-02-13 |
20140047290 | ERROR GENERATING APPARATUS FOR SOLID STATE DRIVE TESTER - Disclosed is an error generating apparatus of a solid state drive tester. The error processing operation of the storage is tested by inserting errors into a specific instruction to be transmitted to the storage, and detecting the results of the error processing operation of the storage when testing the storage. The error generating apparatus includes a host terminal for receiving a test condition for a test of a storage from a user, and a test control unit for generating a test pattern according to the test condition or generating a test pattern randomly, generating error data used to test an error characteristic of the storage, and testing the storage based on the test pattern and a normal instruction or an error instruction which is formed by inserting the error data into the normal instruction. | 2014-02-13 |
20140047291 | AUTOMATIC DEFECT MANAGEMENT IN MEMORY DEVICES - A method for data storage in a memory including multiple memory cells arranged in blocks, includes storing first and second pages in respective first and second groups of the memory cells within a given block of the memory. A pattern of respective positions of one or more defective memory cells is identified in the first group. The second page is recovered by applying the pattern identified in the first group to the second group of the memory cells. | 2014-02-13 |
20140047292 | SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS - A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols. | 2014-02-13 |
20140047293 | SEMICONDUCTOR CIRCUIT AND METHODOLOGY FOR IN-SYSTEM SCAN TESTING - A semiconductor circuit comprising a digital circuit portion, which comprises a combinatorial logic block. The semiconductor circuit further comprises a scan chain for loading and applying a predefined digital test pattern to inputs of the combinatorial logic block. A bi-directional communication port is adapted for writing incoming data to an address space of the digital circuit portion. Scan control hardware comprises a plurality of individually addressable scan control registers which are mapped to the address space of the bi-directional communication port. A method of testing the digital circuit portion involves, using the scan chain, writing bit values to inputs of the individually addressable scan control registers, and reading bit values from at least one output of an individually addressable scan control register. The method and semiconductor circuit allow thorough testing and diagnosing of failing semiconductor devices, including core logic thereof, while mounted on a printed circuit board. | 2014-02-13 |
20140047294 | LOW POWER TESTING OF VERY LARGE CIRCUITS - Plural scan test paths ( | 2014-02-13 |
20140047295 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present technique relates to data processing devices and data processing methods that can increase tolerance for data errors. | 2014-02-13 |
20140047296 | Error Correcting Code Design For A Parity Enabled Memory - A memory system provides Error Correcting Code (ECC) protection for data stored in a parity enabled memory. The memory may include designated parity locations for data stored in the memory. During write operations, the system may obtain data to write into the memory, compute ECC protection bits for the data, and store the ECC protection bits in locations in the memory designated as parity locations for the data. During read operations, the system may read data from the memory. The system may also read protection bits for the data from locations designated as parity locations for the data. Then, the system may interpret the protection bits as ECC protection bits instead of as parity bits. The system may provide ECC protection for data without additional overhead or memory configuration changes to the parity enabled memory. | 2014-02-13 |
20140047297 | TRANSMITTING/RECEIVING SYSTEM AND BROADCAST SIGNAL PROCESSING METHOD - The invention relates to a transmitting system, comprising an SNS client that receives SNS messages from at least one SNS server, and a transmitter which transmits a broadcast signal, including the SNS messages and mobile service data, for a mobile broadcast. The transmitter includes: an RS frame encoder, which performs RS encoding and CRC encoding on the mobile service data for the mobile broadcast so as to build RS frames, and divides each RS frame into a plurality of portions; a group-forming unit, which forms data groups that contain each of the plurality of portions, and which adds known data sequences and signaling data to each data group; an inter-leaver for interleaving data of the data groups; and a trellis encoding unit for trellis-encoding the interleaved data. | 2014-02-13 |
20140047298 | MEMORY DEVICES FACILITATING DIFFERING DEPTHS OF ERROR DETECTION AND/OR ERROR CORRECTION COVERAGE - Memory devices facilitating differing depths of error detection and/or error correction coverage for differing portions of a memory array. | 2014-02-13 |
20140047299 | CONTROL DEVICE FOR VEHICLE AND ERROR PROCESSING METHOD IN CONTROL DEVICE FOR VEHICLE - A control device for a vehicle including a nonvolatile memory which is electrically erasable and writable detects, on start-up, whether or not an error occurs in updated data read from the nonvolatile memory, and when an error has been detected, performs a reset after saving error information. When being restarted by the reset, the control device for a vehicle determines on the basis of the error information whether or not there is updated data in which an error has occurred, and when there is updated data in which an error has occurred, overwrites the updated data with a fixed value prior to the error detection. Accordingly, there can be suppressed a case in which the error detection is performed while the updated data with an abnormality is present causing the reset and the error detection to be repeated. | 2014-02-13 |
20140047300 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROCESSING DATA THEREOF - A data processing method adapted for a rewritable non-volatile memory module is provided. The method includes receiving a first data stream and performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting (ECC) code corresponding to the first data stream. The method also includes converting the original ECC code into a second ECC code according to a second rearrangement rule, and the original ECC code is different from the second ECC code. The method further includes respectively writing the first data stream and the second ECC code into a data bit area and an error-correction code bit area of the same or different physical programming units in the rewritable non-volatile memory module. | 2014-02-13 |
20140047301 | SEMICONDUCTOR MEMORY DEVICE AND A METHOD THEREIN - The disclosed semiconductor memory device includes an operating environment information storing unit for storing memory characteristics representing a correlation between an operating environment of a first memory unit and a data error rate; first and second error correction units making a stepwise correction of a bit error in data, based on data stored in the first memory unit; an error rate estimation unit that compares each of parameters retained in an access counts retaining unit, a temperature information retaining unit, and a data retention period retaining unit with relevant memory characteristics and estimates an error rate of data to be accessed within the memory, and a power supply controller that controls power supply to the second error correction unit depending on an error correction step, based on the estimated error rate. | 2014-02-13 |
20140047302 | CYCLING ENDURANCE EXTENDING FOR MEMORY CELLS OF A NON-VOLATILE MEMORY ARRAY - Examples are disclosed for cycling endurance extending for memory cells of a non-volatile memory array. The examples include implementing one or more endurance extending schemes based on program/erase cycle counts or a failure trigger. The one or more endurance extending schemes may include a gradual read window expansion, a gradual read window shift, an erase blank check algorithm, a dynamic soft-program or a dynamic pre-program. | 2014-02-13 |
20140047303 | CORRECTION DATA - Correction data units for data packets of a data stream are generated. A correction data unit is based on a set of the data packets of the stream. The stream is transmitted over a lossy communication channel. A performance measure to be optimized is selected, which relates to the recovery of lost data packets of the stream. A coding requirement is determined. For the generation of the correction data units, it is determined, within the constraints of the coding requirement and based on previously generated correction data units, which of the data packets in the stream to include in the set on which the generation of the correction data unit is to be based to thereby optimize the selected performance measure. A generated correction data unit is generated based on a respective set of the data packets of the stream. The generated correction data units are included in the stream. | 2014-02-13 |