06th week of 2011 patent applcation highlights part 15 |
Patent application number | Title | Published |
20110031518 | LED DEVICE - A LED device includes a LED having a light-emitting surface and adapted for emitting light through the light-emitting surface, and a reflector formed of three or more than three reflecting layers having the peripheral surfaces thereof sloping at different angles and arranged in a stack on the light-emitting surface of the LED for letting the light emitted by the LED pass and/or reflecting and/or refracting the light to enhance luminous uniformity and luminous brightness and to avoid light concentration at the center or the formation of a corona. | 2011-02-10 |
20110031519 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light emitting device includes a light emitting portion, and an electrode formed on the light emitting portion. The electrode includes: a light reflecting layer configured to reflect light emitted from the light emitting portion and including a first metal; a first seed layer formed directly on the light reflecting layer and including a second metal; a second seed layer coating at least side surfaces of the light reflecting layer and the first seed layer, the second seed layer including a third metal; and a plating layer coating at least top and side surfaces of the second seed layer, the plating layer including a fourth metal. | 2011-02-10 |
20110031520 | LIGHT EMITTING MODULE - A light emitting module includes: a light emitting element including: a first light emitting surface, and second light emitting surfaces bordering the first light emitting surface; an optical wavelength conversion member that converts a wavelength of light emitted from the light emitting element, wherein the optical wavelength conversion member is plate-shaped and is disposed such that an incident surface of the optical wavelength conversion member faces the first light emitting surface; and a reflecting member disposed to face the incident surface of the optical wavelength conversion member, the reflecting member comprising a reflecting surface. The reflecting surface faces the second light emitting surfaces, and the reflecting surface is inclined such that a distance between the reflecting surface and the second light emitting surfaces is gradually increased toward the incident surface of the optical wavelength conversion member. | 2011-02-10 |
20110031521 | COMPOSITE PHOSPHOR POWDER, LIGHT EMITTING DEVICE USING THE SAME AND METHOD FOR MANUFACTURING COMPOSITE PHOSHPOR POWDER - The invention provides a high quality composite phosphor powder which ensures diversity in emission spectrum, color reproduction index, color temperature and color, a light emitting device using the same and a method for manufacturing the composite phosphor powder. The composite phosphor powder comprises composite particles. Each of the composite particles includes at least two types of phosphor particles and a light transmitting binder. The phosphor particles have different emission spectrums. In addition, the light transmitting binder is formed between the phosphor particles and binds them together. | 2011-02-10 |
20110031522 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride-based semiconductor light-emitting device | 2011-02-10 |
20110031523 | WHITE LIGHT EMITTING DEVICE, BACKLIGHT, LIQUID CRYSTAL DISPLAY DEVICE, AND ILLUMINATING DEVICE - A white light emitting device includes a blue light emitting diode chip that emits blue light in a specific wavelength band, a first resin layer that seals the blue light emitting diode chip and includes a cured product of silicone resin, and a second resin layer that covers the first resin layer and includes phosphor powder, which absorbs the blue light and emits light in a specific wavelength band, and a cured product of transparent resin. The phosphor powder has a composition represented by the following Formula (1): | 2011-02-10 |
20110031524 | LIGHT EMITTING DIODE - The invention provides a light emitting diode. The light emitting diode includes a ceramic substrate having a first surface and an opposite second surface. A first conductive trace metal layer and a second conductive trace metal layer are disposed on the first surface of the ceramic substrate. At least one light emitting diode chip is disposed on the first surface of the ceramic substrate, respectively and electrically connected to the first and second conductive trace metal layers. A plurality of thermal metal pads is disposed on the second surface of the ceramic substrate, wherein the thermal metal pads are electrically isolated from the light emitting diode chip. | 2011-02-10 |
20110031525 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - A light emitting device includes a light emitting diode chip, and a first lead terminal in which a bottom portion including a mounting region for the light emitting diode chip is formed, and a side wall continuing to the bottom portion and having an inner surface serving as a reflecting surface for light emitted from the light emitting diode chip is continuously formed. Further, the light emitting device includes a second lead terminal provided to be spaced from the first lead terminal. Furthermore, the light emitting device includes a resin portion which supports the first lead terminal and the second lead terminal, and in which a cavity exposing a portion of the second lead terminal and the mounting region in the first lead terminal is formed. | 2011-02-10 |
20110031526 | LIGHT EMITTING DIODE PACKAGE AND FABRICATION METHOD THEREOF - An LED package and a fabrication method therefor. The LED package includes first and second lead frames made of heat and electric conductors, each of the lead frames comprising a planar base and extensions extending in opposed directions and upward directions from the base. The package also includes a package body made of a resin and configured to surround the extensions of the first and second lead frames to fix the first and second lead frames while exposing underside surfaces of the first and second lead frames. The LED package further includes a light emitting diode chip disposed on an upper surface of the base of the first lead frame and electrically connected to the bases of the first and second lead frames, and a transparent encapsulant for encapsulating the light emitting diode chip. | 2011-02-10 |
20110031527 | Thermosetting resin composition, epoxy resin molding material, and polyvalent carboxylic acid condensate - The epoxy resin molding material of the invention comprises (A) an epoxy resin and (B) a curing agent, wherein the (B) curing agent contains a polyvalent carboxylic acid condensate. The thermosetting resin composition of the invention comprises (A) an epoxy resin and (B) a curing agent, wherein the viscosity of the (B) curing agent is 1.0-1000 mPa·s at 150° C., as measured with an ICI cone-plate Brookfield viscometer. | 2011-02-10 |
20110031528 | Semiconductor light emitting device - A semiconductor light emitting device with which a driving voltage is able to be kept low is provided. The semiconductor light emitting device includes: an n-type cladding layer; an active layer; a p-type cladding layer containing AlGaInP; an intermediate layer; and a contact layer containing GaP in this order, wherein the intermediate layer contains Ga | 2011-02-10 |
20110031529 | SEMICONDUCTOR PHOTODIODE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor photodiode device includes a semiconductor substrate, a first buffer layer containing a material different from that of the semiconductor substrate in a portion thereof, a first semiconductor layer formed above the buffer layer and having a lattice constant different from that of the semiconductor substrate, a second buffer layer formed above the first semiconductor layer and containing an element identical with that of the first semiconductor layer in a portion thereof, and a second semiconductor layer formed above the buffer layer in which a portion of the first semiconductor layer is formed of a plurality of island shape portions each surrounded with an insulating film, and the second buffer layer allows adjacent islands of the first semiconductor layer to coalesce with each other and is in contact with the insulating film. | 2011-02-10 |
20110031530 | FIELD EFFECT TRANSISTOR WITH A HETEROSTRUCTURE - A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized. | 2011-02-10 |
20110031531 | PROCESS FOR FORMING LOW DEFECT DENSITY HETEROJUNCTIONS - A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound. | 2011-02-10 |
20110031532 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device is provided with a substrate, an AlN layer formed over the substrate, an AlGaN layer formed over the AlN layer and larger in electron affinity than the AlN layer, another AlGaN layer formed over the AlGaN layer and smaller in electron affinity than the AlGaN layer. Furthermore, there are provided an i-GaN layer formed over the latter AlGaN layer, and an i-AlGaN layer and an n-AlGaN layer formed over the i-GaN layer. | 2011-02-10 |
20110031533 | SEMICONDUCTOR DEVICE - The present invention miniaturizes a HEMT element used as a switching element in a radio frequency module. A single gate electrode | 2011-02-10 |
20110031534 | PROCESS FOR PRODUCING Si(1-v-w-x)CwAlxNv BASE MATERIAL, PROCESS FOR PRODUCING EPITAXIAL WAFER, Si(1-v-w-x)CwAlxNv BASE MATERIAL, AND EPITAXIAL WAFER - There are provided a Si | 2011-02-10 |
20110031535 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A finger length al of a transistor P | 2011-02-10 |
20110031536 | LAYOUT STRUCTURE OF STANDARD CELL, STANDARD CELL LIBRARY, AND LAYOUT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT - In a layout structure of a standard cell including off transistors | 2011-02-10 |
20110031537 | SENSOR ELEMENT OF A GAS SENSOR - A sensor element of a gas sensor for determining gas components in gas mixtures is provided, which includes a field-effect transistor having a source electrode, a drain electrode, and a gate electrode. The gate electrode includes a gate metallization, which is in contact with an insulation layer or a semiconductor substrate of the field-effect transistor via a boundary layer, the boundary layer being formed by modifying the surface of the insulation layer or the semiconductor substrate using metal alkoxides, metal amides, metal halogenides and/or metal alkyls. Furthermore, a method for producing said sensor element is provided. | 2011-02-10 |
20110031538 | CMOS STRUCTURE WITH MULTIPLE SPACERS - A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer. | 2011-02-10 |
20110031539 | SEMICONDUCTOR DEVICES HAVING LINE TYPE ACTIVE REGIONS AND METHODS OF FABRICATING THE SAME - In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a plan type device isolation gate electrode, and a width of the plan type device isolation gate electrode greater than a width of the device gate electrode. | 2011-02-10 |
20110031540 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a field effect transistor and a strain generating layer to apply a stress to a channel region of the field effect transistor. The strain generating layer contains at least one of oxygen and nitrogen of 1.0×10 | 2011-02-10 |
20110031541 | Two-Step STI Formation Process - A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate. | 2011-02-10 |
20110031542 | METHOD TO OPTIMIZE SUBSTRATE THICKNESS FOR IMAGE SENSOR DEVICE - Provided is a method for fabricating an image sensor device that includes providing a substrate having a front side and a back side; patterning a photoresist on the front side of the substrate to define an opening having a first width, the photoresist having a first thickness correlated to the first width; performing an implantation process through the opening using an implantation energy correlated to the first thickness thereby forming a first doped isolation feature; forming a light sensing feature adjacent to the first doped isolation feature, the light sensing feature having a second width; and thinning the substrate from the back side so that the substrate has a second thickness that does not exceed twice a depth of the first doped isolation feature. A pixel size is substantially equal to the first and second widths. | 2011-02-10 |
20110031543 | IMAGING DEVICE BY BURIED PHOTODIODE STRUCTURE - An n-type region as a charge storage region of a photodiode is buried in a substrate. The interface between silicon and a silicon oxide film is covered with a high concentration p-layer and a lower concentration p-layer is formed only in the portion immediately below a floating electrode for signal extraction. Electrons generated by light are stored in the charge storage region, thereby changing the potential of the portion of the p-layer at the surface of the semiconductor region. The change is transmitted through a thin insulating film to the floating electrode by capacitive coupling and read out by a buffer transistor. Initialization of charges is executed by adding a positive high voltage to the gate electrode of a first transfer transistor such that the electrons stored in the charge storage region are transferred to the n+ region and generation of reset noise is protected. | 2011-02-10 |
20110031544 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME - According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; an element isolation region formed in the semiconductor substrate so as to extend in a first direction; a gate electrode formed in the semiconductor substrate so as to extend in a second direction crossing the first direction and to penetrate through the element isolation region; a gate insulating film interposed between the gate electrode and the semiconductor substrate; an interlayer dielectric film formed on the gate electrode; a ferroelectric capacitor including: first and second electrodes disposed on the interlayer dielectric film and a ferroelectric between the first and second electrodes; and first and second semiconductor pillars being in contact respectively with the first and second electrodes. | 2011-02-10 |
20110031545 | Spin transistor based on the spin-filter effect, and non-volatile memory using spin transistors - A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due to spin-splitting at the band edge of a second ferromagnetic barrier layer, the spin-polarized hot carriers are transported to a third nonmagnetic electrode when the direction of the spin of the carriers injected into the second nonmagnetic electrode is parallel to that of the spin of the spin band at the band edge of the second ferromagnetic barrier layer, whereas the hot carriers are not transported to the third nonmagnetic electrode in the case of antiparallel spin. A memory element is also provided that comprises such a spin transistor. | 2011-02-10 |
20110031546 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SAME - A method for manufacturing a semiconductor device includes: forming a first layer on a substrate; forming a first contact hole in the first layer; burying a sacrificial film in the first contact hole; forming a second layer on the first layer and the first contact hole after burying; forming a second contact hole reaching the sacrificial film in the second layer; removing the sacrificial film from the first contact hole via the second contact hole; and providing a contact electrode in the first contact hole and the second contact hole. | 2011-02-10 |
20110031547 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a substrate; a plurality of gate electrodes provided on the substrate, extended in a first direction parallel to an upper surface of the substrate, arranged in a matrix in an up-to-down direction perpendicular to the upper surface and a second direction, and having a through-hole respectively extended in the up-to-down direction, the second direction being orthogonal to both the first direction and the up-to-down direction; an insulation plate provided between the gate electrodes in the second direction and extended in the first direction and the up-to-down direction; a block insulation film provided on an interior surface of the through-hole and on an upper surface and a lower surface of the gate electrodes and being contact with the insulation plate; a charge storage film provided on the block insulation film; a tunnel insulation film provided on the charge storage film; and a semiconductor pillar provided in the through-hole and extended in the up-to-down direction. | 2011-02-10 |
20110031548 | SPLIT GATE NON-VOLATILE MEMORY CELL WITH IMPROVED ENDURANCE AND METHOD THEREFOR - A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5. | 2011-02-10 |
20110031549 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A memory includes active areas and an isolation on a semiconductor substrate. A tunnel dielectric film is on active areas. Floating gates include lower gate parts and upper gate parts. An upper gate part has a larger width than that of a lower gate part on a cross section perpendicular to an extension direction of an active area, and is provided on the lower gate part. An intermediate dielectric film is on an upper surface and a side surface of each floating gate. The control gate is on an upper surface and a side surface of each floating gate via the intermediate dielectric film. A height of a lower end of each control gate from a surface of the semiconductor substrate is lower than a height of an interface between the upper gate part and the lower gate part from the surface of the semiconductor substrate. | 2011-02-10 |
20110031550 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a stacked structural unit including a plurality of electrode films and a plurality of inter-electrode insulating films alternately stacked in a first direction; a first selection gate electrode stacked on the stacked structural unit in the first direction; a first semiconductor pillar piercing the stacked structural unit and the first selection gate electrode in the first direction; a first memory unit provided at an intersection of each of the electrode films and the first semiconductor pillar; and a first selection gate insulating film provided between the first semiconductor pillar and the first selection gate electrode, the first selection gate electrode including a first silicide layer provided on a face of the first selection gate electrode perpendicular to the first direction. | 2011-02-10 |
20110031551 | Structure and Method For Forming Laterally Extending Dielectric Layer in a Trench-Gate FET - A FET is formed as follows. A trench is formed in a silicon region. A shield electrode is formed in a bottom portion of the trench. The shield electrode is insulated from adjacent silicon region by a shield dielectric. A silicon nitride layer is formed over a surface of the silicon region adjacent the trench, along the trench sidewalls, and over the shield electrode and shield dielectric. A layer of LTO is formed over the silicon nitride layer such that those portions of the LTO layer extending over the surface of the silicon region adjacent the trench are thicker than the portion of the LTO layer extending over the shield electrode. The LTO layer is uniformly etched back such that a portion of the silicon nitride layer becomes exposed while portions of the silicon nitride layer remain covered. | 2011-02-10 |
20110031552 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide, in FINFET whose threshold voltage is determined essentially by the work function of a gate electrode, a technology capable of adjusting the threshold voltage of FINFET without changing the material of the gate electrode. FINFET is formed over an SOI substrate comprised of a substrate layer, a buried insulating layer formed over the substrate layer, and a silicon layer formed over the buried insulating layer. The substrate layer has therein a first semiconductor region contiguous to the buried insulating layer. The silicon layer of the SOI substrate is processed into a fin. A ratio of the height of the fin to the width of the fin is adjusted to fall within a range of from 1 or greater but not greater than 2. In addition, a voltage can be applied to the first semiconductor region. | 2011-02-10 |
20110031553 | Semiconductor device having transistors each having gate electrode of different metal ratio and production process thereof - A semiconductor device with integrated MIS field-effect transistors includes a first transistor including a first gate electrode having a composition represented by MAx, and a second transistor including a second gate electrode having a composition represented by MAy, in which M includes at least one metal element selected from the group consisting of W, Mo, Ni, Pt, Ta, Pd, Co, and Ti, A includes at least one of silicon and germanium, and 02011-02-10 | |
20110031554 | STRUCTURE AND METHOD TO IMPROVE THRESHOLD VOLTAGE OF MOSFETS INCLUDING A HIGH K DIELECTRIC - A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process. | 2011-02-10 |
20110031555 | METAL OXIDE SEMICONDUCTOR TRANSISTOR - A metal oxide semiconductor transistor includes a substrate including a first well, a second well, and an insulation between the first well and the second well, a first gate structure disposed on the first well, a second gate structure disposed on the second well, four first dopant regions disposed in the substrate at two sides of the first gate structure, and in the substrate at two sides of the second gate structure respectively, two second dopant regions disposed in the substrate at two sides of the first gate structure respectively, two first epitaxial layers disposed in the substrate at two sides of the first gate structure respectively and two first source/drain regions disposed in the substrate at two sides of the first gate structure respectively, wherein each of the first source/drain regions overlaps with one of the first epitaxial layers and one of the second dopant regions simultaneously. | 2011-02-10 |
20110031556 | FIN INTERCONNECTS FOR MULTIGATE FET CIRCUIT BLOCKS - In an embodiment, an apparatus includes a first field effect transistor including a first source contact region, a first drain contact region and a first plurality of fins overlying a substrate, a first gate overlying the first plurality of fins, the first source contact region coupled to first ends of the first plurality of fins, and a second field effect transistor including a second source contact region, a second drain contact region, and a second plurality of fins overlying the substrate, a second gate overlying the second plurality of fins, and an interconnection contact region overlying the substrate, electrically coupling the first drain contact region and the second source contact region and abutting the first and the second pluralities of fins. | 2011-02-10 |
20110031557 | GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIRCUITS THEREFROM - A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed. | 2011-02-10 |
20110031558 | GATE STRUCTURE OF SEMICONDUCTOR DEVICE - A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer. | 2011-02-10 |
20110031559 | SEMICONDUCTOR DEVICES IN WHICH A CELL GATE PATTERN AND A RESISTOR PATTERN ARE FORMED OF A SAME MATERIAL AND METHODS OF FORMING THE SAME - A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active region of the peripheral circuit region, forming a second insulating layer, a charge storage layer, and a third insulating layer on the active region of the cell region, farming a conductive layer on the semiconductor substrate, and patterning the conductive layer to form conductive patterns on the third insulating layer of the cell region, the polysilicon pattern of the active region of peripheral circuit region, and the semiconductor substrate of the resistor region, respectively. | 2011-02-10 |
20110031560 | READ-ONLY MEMORY AND METHOD OF MANUFACTURE THEREOF - A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor. | 2011-02-10 |
20110031561 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The present invention provides a semiconductor device which suppresses a short circuit and a leakage current between a semiconductor film and a gate electrode generated by a break or thin thickness of a gate insulating film in an end portion of a channel region of the semiconductor film, and the manufacturing method of the semiconductor device. Plural thin film transistors which each have semiconductor film provided over a substrate continuously, conductive films provided over the semiconductor film through a gate insulating film, source and drain regions provided in the semiconductor film which are not overlapped with the conductive films, and channel regions provided in the semiconductor film existing under the conductive films and between the source and drain regions. And impurity regions provided in the semiconductor film which is not overlapped with the conductive film and provided adjacent to the source and drain regions. Further, the conductive films are provided over the channel regions and regions of the semiconductor film which are provided adjacent to the channel regions. | 2011-02-10 |
20110031562 | SEALING LAYER OF A FIELD EFFECT TRANSISTOR - An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface. | 2011-02-10 |
20110031563 | Method for Manufacturing a Semiconductor Device Having Doped and Undoped Polysilicon Layers - Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein. | 2011-02-10 |
20110031564 | MEMS DEVICE AND FABRICATION METHOD THEREOF - A micro electro mechanical system (MEMS) device includes: a fixed electrode made of silicon and provided above a semiconductor substrate; a movable electrode made of silicon and arranged in a mechanically movable manner by having a gap from the semiconductor substrate; and a wiring layered part that is provided around the movable electrode, covers a portion of the fixed electrode and includes wiring. One of the fixed electrode and the movable electrode is implanted with an impurity ion and at least a part of the portion of the fixed electrode covered by the wiring layered part is silicidized. | 2011-02-10 |
20110031565 | MICROMACHINED DEVICES AND FABRICATING THE SAME - Micromachined devices and methods for making the devices. The device includes: a first wafer having at least one via; and a second wafer having a micro-electromechanical-systems (MEMS) layer. The first wafer is bonded to the second wafer. The via forms a closed loop when viewed in a direction normal to the top surface of the first wafer to thereby define an island electrically isolated. The method for fabricating the device includes: providing a first wafer having at least one via; bonding a second wafer having a substantially uniform thickness to the first wafer; and etching the bonded second wafer to form a micro-electromechanical-systems (MEMS) layer. | 2011-02-10 |
20110031566 | CONDUCTIVE NANOMEMBRANE, AND MEMS SENSOR OF USING THE SAME - The present invention relates to a conductive nanomembrane and a Micro Electro Mechanical System sensor using the same, and more particularly, a conductive nanomembrane that is formed by stacking a polymer electrolyte film and a carbon nanotube layer, and a MEMS sensor using the same. | 2011-02-10 |
20110031567 | PROCESS FOR MANUFACTURING MEMS DEVICES HAVING BURIED CAVITIES AND MEMS DEVICE OBTAINED THEREBY - A process for manufacturing a MEMS device, wherein a bottom silicon region is formed on a substrate and on an insulating layer; a sacrificial region of dielectric is formed on the bottom region; a membrane region, of semiconductor material, is epitaxially grown on the sacrificial region; the membrane region is dug down to the sacrificial region so as to form through apertures; the side wall and the bottom of the apertures are completely coated in a conformal way with a porous material layer; at least one portion of the sacrificial region is selectively removed through the porous material layer and forms a cavity; and the apertures are filled with filling material so as to form a monolithic membrane suspended above the cavity. | 2011-02-10 |
20110031568 | STRUCTURE HAVING PLURAL CONDUCTIVE REGIONS AND PROCESS FOR PRODUCTION THEREOF - A structure having a plurality of conductive regions insulated electrically from each other comprises a movable piece supported movably above the upper face of the conductive region, the movable piece having an electrode in opposition to the conductive region, the structure being constructed to be capable of emitting and receiving electric signals through the lower face of the conductive region, the plural conductive regions being insulated by sequentially connected oxidized regions formed from an oxide of a material having through-holes or grooves. | 2011-02-10 |
20110031569 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC TUNNELING JUNCTION ELEMENTS HAVING IMPROVED PERFORMANCE THROUGH CAPPING LAYER INDUCED PERPENDICULAR ANISOTROPY AND MEMORIES USING SUCH MAGNETIC ELEMENTS - A method and system for providing a magnetic element and a magnetic memory utilizing the magnetic element are described. The magnetic element is used in a magnetic device that includes a contact electrically coupled to the magnetic element. The method and system include providing pinned, nonmagnetic spacer, and free layers. The free layer has an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy corresponding to a perpendicular anisotropy energy that is less than the out-of-plane demagnetization energy. The nonmagnetic spacer layer is between the pinned and free layers. The method and system also include providing a perpendicular capping layer adjoining the free layer and the contact. The perpendicular capping layer induces at least part of the perpendicular magnetic anisotropy in the free layer. The magnetic element is configured to allow the free layer to be switched between magnetic states when a write current is passed through the magnetic element. | 2011-02-10 |
20110031570 | Magnetic tunnel junction device and method of manufacturing the same - The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared by the following steps. A single-crystalline MgO (001) substrate | 2011-02-10 |
20110031571 | WIRELESS COMMUNICATION UNIT AND SEMICONDUCTOR DEVICE HAVING A POWER AMPLIFIER THEREFOR - A semiconductor package device comprises a radio frequency power transistor having an output port operably coupled to a single de-coupling capacitance located within the semiconductor package device. The single de-coupling capacitance is arranged to provide both high frequency decoupling and low frequency decoupling of signals output from the radio frequency power transistor. | 2011-02-10 |
20110031572 | HIGH POWER DENSITY BETAVOLTAIC BATTERY - To increase total power in a betavoltaic device, it is desirable to have greater radioisotope material and/or semiconductor surface area, rather than greater radioisotope material volume. An example of this invention is a high power density betavoltaic battery. In one example of this invention, tritium is used as a fuel source. In other examples, radioisotopes, such as Nickel-63, Phosphorus-33 or promethium, may be used. The semiconductor used in this invention may include, but is not limited to, Si, GaAs, GaP, GaN, diamond, and SiC. For example (for purposes of illustration/example, only), tritium will be referenced as an exemplary fuel source, and SiC will be referenced as an exemplary semiconductor material. Other variations and examples are also discussed and given. | 2011-02-10 |
20110031573 | SOLID-STATE IMAGING DEVICE, IMAGING APPARATUS, AND MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes: photodetection cells formed in a semiconductor substrate and including respective photodetection photoelectric conversion elements for detecting light coming form a subject; black level detection cells formed in the semiconductor substrate, for detecting a black level; and a light shield layer which is formed over an area where the photodetection cells and the black level detection cells are formed, has openings over the respective photodetection photoelectric conversion elements of the photodetection cells, has no openings over the black level detection cells, and has contact portions that are in contact with the semiconductor substrate, the contact portions being formed only in or in the vicinity of plan-view areas of the black level detection cells, respectively. | 2011-02-10 |
20110031574 | SOLID-STATE IMAGING DEVICE, IMAGING APPARATUS, AND MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes: a first well layer which is provided in a semiconductor substrate, has a conductivity type that is opposite to a conductivity type of the semiconductor substrate, and includes photoelectric conversion elements and a reading unit for reading signals corresponding to charges generated in the respective photoelectric conversion elements; a second well layer provided in the semiconductor substrate and having the conductivity type that is opposite to the conductivity type of the semiconductor substrate; and a light shield layer which is provided over an area where the photoelectric conversion elements are provided, has openings over the respective photoelectric conversion elements, and has contact portions that are in contact with the second well layer. | 2011-02-10 |
20110031575 | SOLID-STATE IMAGE SENSOR - A solid-state image sensor includes first and second pixels formed on a semiconductor substrate. The first pixel includes: a first photoelectric conversion region located in an upper portion of the semiconductor substrate; a first transfer electrode; a light-shield film covering the first transfer electrode and having a first opening on the first photoelectric conversion region; and a first anti-reflection film located on the first photoelectric conversion region and, when viewed in plan, within the first opening so as not to overlap the first light-shield film. The second pixel includes: a second photoelectric conversion region located in an upper portion of the semiconductor substrate; a second transfer electrode; the light-shield film covering the second transfer electrode and having a second opening on the second photoelectric conversion region; and a second anti-reflection film located on the second photoelectric conversion region and continuously extending to a portion on the second transfer electrode. | 2011-02-10 |
20110031576 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF - A solid-state imaging device includes a first-conductive semiconductor layer, a second-conductive semiconductor layer that is provided on the first-conductive semiconductor layer, a light receiving element that is formed in the second-conductive semiconductor layer, and an element isolation region that is formed to surround the light receiving element in an in-plane direction of the second-conductive semiconductor layer, in which the element isolation region includes a first-conductive first element isolation unit that is connected to the first-conductive semiconductor layer, a hollow that is formed on the first-conductive first element isolation unit, and a first-conductive second element isolation unit that is formed on the hollow. | 2011-02-10 |
20110031577 | Photodiode Array - A photodiode array for near infrared rays that includes photodiodes having a uniform size and a uniform shape, has high selectivity for the wavelength of received light between the photodiodes, and has high sensitivity with the aid of a high-quality semiconducting crystal containing a large amount of nitrogen, a method for manufacturing the photodiode array, and an optical measurement system are provided. The steps of forming a mask layer | 2011-02-10 |
20110031578 | SEMICONDUCTOR PHOTODIODE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor photodiode includes a semiconductor substrate; a first conduction type first semiconductor layer formed above the semiconductor substrate; a high resistance second semiconductor layer formed above the first semiconductor layer; a first conduction type third semiconductor layer formed above the second semiconductor layer; and a second conduction type fourth semiconductor layer buried in the second semiconductor layer, in which the fourth semiconductor layer is separated at a predetermined distance in a direction horizontal to the surface of the semiconductor substrate. | 2011-02-10 |
20110031579 | LOW VOLTAGE DIODE WITH REDUCED PARASITIC RESISTANCE AND METHOD FOR FABRICATING - A method of making a diode begins by depositing an Al | 2011-02-10 |
20110031580 | METHOD FOR MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - An isolation oxide film whose upper surface is higher than a surface of a substrate is formed in the substrate. A silicon oxide film is formed on the substrate between the isolation oxide films. A self-aligned polysilicon film is formed on the silicon oxide film between the isolation oxide films. After forming a resist pattern covering the peripheral circuitry, the isolation oxide films in the memory cell are etched by a predetermined thickness. An ONO film is formed on the entire surface of the substrate, a second resist pattern covering the memory cell is formed. Then, the ONO film, the polysilicon film | 2011-02-10 |
20110031581 | INTEGRATED CIRCUIT (IC) HAVING TSVS WITH DIELECTRIC CRACK SUPPRESSION STRUCTURES - An IC includes a substrate having a semiconductor top surface, a plurality of metal interconnect levels having inter-level dielectric (ILD) layers therebetween on the top surface, and a bottom surface. A plurality of through substrate vias (TSVs) extend from a TSV terminating metal interconnect level downward to the bottom surface. The plurality of TSVs include an electrically conductive filler material surrounded by a dielectric liner that define a projected volume. The projected volume includes a projected area over the electrically conductive filler material and a projected height extending upwards from the TSV terminating metal interconnect level to a metal interconnect level above, and a projected sidewall surface along sidewalls of the projected volume. A crack suppression structure (CSS) protects TSVs and includes a lateral CSS portion that is positioned lateral to the projected volume and encloses at least 80% of the projected sidewall surface. | 2011-02-10 |
20110031582 | FIN ANTI-FUSE WITH REDUCED PROGRAMMING VOLTAGE - A method forms an anti-fuse structure comprises a plurality of parallel conductive fins positioned on a substrate, each of the fins has a first end and a second end. A second electrical conductor is electrically connected to the second end of the fins. An insulator covers the first end of the fins and a first electrical conductor is positioned on the insulator. The first electrical conductor is electrically insulated from the first end of the fins by the insulator. The insulator is formed to a thickness sufficient to break down on the application of a predetermined voltage between the second electrical conductor and the first electrical conductor and thereby form an uninterrupted electrical connection between the second electrical conductor and the first electrical conductor through the fins. | 2011-02-10 |
20110031583 | HIGH FREQUENCY DEVICE - A small high frequency device that is able to inhibit generation of an eddy current and a parasitic capacity and shows superior high frequency characteristics is provided. The high frequency device includes: a substrate having a depression; a dielectric layer over the substrate; and a plurality of electronic devices which are provided in the dielectric layer or on the dielectric layer, and at least one of which is opposed to the depression. | 2011-02-10 |
20110031584 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first insulating film includes five extension lines formed between connection pad portions of adjacent two predetermined wiring lines. The first insulating film also includes peripheral portions of the adjacent two connection pad portions on both sides of the five extension lines. A second insulating film made of a polyimide resin or the like is formed on the upper surface of the first insulating layer by a screen printing method or ink jet method. Since a short circuit may be easily caused by electromigration in a region where the five extension lines are parallel to another, the short circuit due to the electromigration can be prevented by covering only that region with the second insulating film. Accordingly, the region where the second insulating film is formed can be as small as possible, and the semiconductor wafer does not easily warp. | 2011-02-10 |
20110031585 | Method for fabricating a MIM capacitor using gate metal for electrode and related structure - According to one exemplary embodiment, a method for fabricating a MIM capacitor in a semiconductor die includes forming a dielectric one segment over a substrate and a metal one segment over the dielectric one segment, where the metal one segment forms a lower electrode of the MIM capacitor. The method further includes forming a dielectric two segment over the dielectric one segment and a metal two segment over the dielectric two segment, where a portion of the metal two segment forms an upper electrode of the MIM capacitor. The metal one segment comprises a first gate metal. The metal two segment can comprise a second gate metal. | 2011-02-10 |
20110031586 | High Breakdown Voltage Embedded MIM Capacitor Structure - Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device may include gate material embedded in an insulator, a plurality of metal contacts, and a plurality of capacitors. The plurality of capacitors may include a lower electrode, a dielectric formed so as to cover a surface of the lower electrode, and an upper electrode formed on the dielectric. Further, the plurality of contacts may connect each of the lower electrodes of the plurality of capacitors to the gate material. The plurality of capacitors may be connected in series via the gate material. | 2011-02-10 |
20110031587 | SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a lower electrode on a semiconductor substrate, applying a photoresist on the lower electrode, forming an opening in the photoresist spaced from the periphery of the lower electrode, forming a high-dielectric constant film of a high-k material having a dielectric constant of 10 or more, performing liftoff so that the high-dielectric-constant film remains on the lower electrode, and forming an upper electrode on the high-dielectric-constant film remaining after the liftoff. | 2011-02-10 |
20110031588 | VARACTOR STRUCTURE AND METHOD - An improved varactor diode ( | 2011-02-10 |
20110031589 | GROUP III NITRIDE SUBSTRATE, SEMICONDUCTOR DEVICE COMPRISING THE SAME, AND METHOD FOR PRODUCING SURFACE-TREATED GROUP III NITRIDE SUBSTRATE - A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×10 | 2011-02-10 |
20110031590 | Liquid film assisted laser die marking and structures formed thereby - Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a liquid on a region of a die, and then forming an identification mark through the liquid on the die. | 2011-02-10 |
20110031591 | SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a semiconductor chip possessing a shape with corners and has a circuit section. The semiconductor chip has one or more chamfered portions which are formed in a first corner group that includes one or more of the corners. Data bonding pads are disposed on the semiconductor chip and are electrically connected to the circuit section. A chip selection pad is disposed adjacent to a second corner group that includes at least one of the corners which is not formed with a chamfered portion. The chip selection pad is electrically connected to the circuit section. A plurality of the semiconductor packages may be stacked so that the chip selection pad of one of the semiconductor packages is left exposed when another semiconductor package is stacked thereover due to the chamfered portion of the other semiconductor package. | 2011-02-10 |
20110031592 | SILICON EPITAXIAL WAFER AND METHOD FOR PRODUCTION THEREOF - Disclosed is a wafer having a good haze level in spite of the fact that the inclination angle of {110} plane in the wafer is small. Also disclosed is a method for producing a silicon epitaxial wafer, which comprises the steps of: growing an epitaxial layer on a silicon single crystal substrate having a main surface of {110} plane of which an off-angle is less than 1 degree; and polishing the surface of the epitaxial layer until the surface of the epitaxial layer has a haze level of 0.18 ppm or less (as measured by SP2 at a DWO mode). | 2011-02-10 |
20110031593 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND SEMICONDUCTOR DEVICE - There are provided a method of manufacturing a semiconductor device, a substrate processing apparatus, and a semiconductor device. The method allows rapid formation of a conductive film, which has a low concentration of impurities permeated from a source owing to its dense structure, and a low resistivity. The method is performed by simultaneously supplying two or more kinds of sources into a processing chamber to form a film on a substrate placed in the processing chamber. The method comprises: performing a first source supply process by supplying at least one kind of source into the processing chamber at a first supply flow rate; and performing a second source supply process by supplying the at least one kind of source into the processing chamber at a second supply flow rate different from the first supply flow rate. | 2011-02-10 |
20110031594 | CONDUCTOR PACKAGE STRUCTURE AND METHOD OF THE SAME - The present invention provides a conductor package structure that comprises a conductive base. An adhesive layer is formed on the conductive base. An electronic element is formed on the adhesive layer. Conductors form a signal connection between the surface of a filling material and the bottom of the filling material, wherein the filling material is filled in the space between the electronic element and the conductors. | 2011-02-10 |
20110031595 | MICROWAVE MODULE - In a microwave module with at least one semiconductor chip, which provides on its upper side a connecting-line structure formed in particular as a coplanar line, which is connected to at least one adjacent incoming and/or outgoing line structure formed on the upper side of the substrate, the chip is glued with its underside and all lateral surfaces, on which no high-frequency connecting lines lead to the chip, within a recess of a metal part with good thermal conduction. | 2011-02-10 |
20110031596 | NICKEL-TITANUM SOLDERING LAYERS IN SEMICONDUCTOR DEVICES - Semiconductor devices containing nickel-titanium (NiTi or TiNi) compounds or alloys and methods for making such devices are described. The devices contain a silicon substrate with an integrated circuit, a contact layer contacting the substrate, a TiNi-containing soldering layer on the contact layer, an oxidation prevention layer on the soldering layer, a solder bump on the soldering layer, and a lead frame or PCB attached to the solder bump. The combination of the Ti and Ni materials in the soldering layer exhibits many features not found in the Ti and Ni materials alone, such as reduced wafer warpage, increased ductility for improved elasticity, decreased consumption of the Ni in the soldering layer, and decreased manufacturing costs. Other embodiments are described. | 2011-02-10 |
20110031597 | SEMICONDUCTOR DEVICE AND METHOD INCLUDING FIRST AND SECOND CARRIERS - A semiconductor device and method. One embodiment provides an integral array of first carriers and an integral array of second carries connected to the integral array of first carriers. First semiconductor chips are arranged on the integral array of first carriers. The integral array of second carriers is arranged over the first semiconductor chips. | 2011-02-10 |
20110031598 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and a method of fabricating the same are disclosed. An interposer used for the semiconductor device includes integrated circuits therein to realize the functions of a decoupling capacitor, an ESD preventing circuit, an impedance matching circuit, and termination. Therefore, it is possible to improve the reliability of the operation of the semiconductor device. | 2011-02-10 |
20110031599 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package includes a first semiconductor package having a first semiconductor chip having a first surface and a second surface facing away from the first surface, first bonding pads disposed on the first surface, and through-electrodes electrically connected with the first bonding pads The through-electrodes pass through the first and second surfaces of the first chip and extend from the second surface. A second semiconductor package has a through-holes defined therein into which the through-electrodes are inserted and second bonding pads electrically connected with the through-electrodes. | 2011-02-10 |
20110031600 | SEMICONDUCTOR PACKAGE - A semiconductor package comprises a substrate having bond fingers on an upper surface thereof and ball lands on a lower surface thereof; at least two chip modules stacked on the upper surface of the substrate, each of the at least two chip modules including a plurality of semiconductor chips having first connection members and stacked in a manner such that the first connection members of the semiconductor chips are connected to one another, the chip modules being stacked in a zigzag pattern such that connection parts of the chip modules project sideward; and second connection members electrically connecting the connection parts of the respective chip modules to the bond fingers of the substrate. | 2011-02-10 |
20110031601 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF FORMING SERIAL PATH THEREOF - A stacked semiconductor device and a method of forming a serial path of the stacked semiconductor device are provided. The stacked semiconductor device includes a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal. Each of the chips includes a serial bump disposed at the same position on one surface of each of the chips, receiving the input signal and transferring the input signal to the first internal circuit, and a serial through-silicon via (TSV) disposed at a position symmetrical to the serial bump with respect to a center of the chip to penetrate the chip, and receiving and transferring the output signal. Here, the chips are alternately rotated and stacked, so that the serial TSV and the serial bumps of adjacent chips contact each other. According to the stacked semiconductor device and method, a plurality of chips having the same pattern are rotated about the center of the chips and stacked, so that a parallel path and a serial path can be formed. | 2011-02-10 |
20110031602 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The method comprises providing multiple chips attached to a first carrier, stretching the first carrier so that the distance between adjacent ones of the multiple chips is increased, and applying a laminate to the multiple chips and the stretched first carrier to form a first workpiece embedding the multiple chips, the first workpiece having a first main face facing the first carrier and a second main face opposite to the first main face. | 2011-02-10 |
20110031603 | SEMICONDUCTOR DEVICES HAVING STRESS RELIEF LAYERS AND METHODS FOR FABRICATING THE SAME - Methods are provided for fabricating a semiconductor device. In accordance with an exemplary embodiment, a method comprises the steps of providing a semiconductor die having a conductive terminal, forming an insulating layer overlying the semiconductor die, and forming a cavity in the insulating layer which exposes the conductive terminal. The method also comprises forming a first stress-relief layer in the cavity, forming an interconnecting structure having a first end electrically coupled to the first stress-relief layer, and having a second end, and electrically and physically coupling the second end of the interconnecting structure to a packaging substrate. | 2011-02-10 |
20110031604 | SEMICONDUCTOR PACKAGE REQUIRING REDUCED MANUFACTURING PROCESSES - A semiconductor package includes a semiconductor chip having a first surface, a second surface located opposite the first surface, and side surfaces connecting the first and second surfaces. The semiconductor chip includes bonding pads disposed on the first surface and having a molding member formed to cover the first surface of the semiconductor chip. The molding member is formed so as to expose the side surfaces of the semiconductor chip. The semiconductor chip also includes bonding members having first ends electrically connected to the respective bonding pads and second ends that are connected to and opposite the first ends. The second ends are exposed from side surfaces of the molding member after passing through the molding member so as to allow various electrical connections. | 2011-02-10 |
20110031605 | PACKAGE STRUCTURE AND PACKAGE PROCESS - A package structure and a package process are provided. In the package process, firstly, a first electronic component having a plurality of first conductive bumps at a bottom thereof is provided. Then, a first insulation paste is coated on the first conductive bumps. The first electronic component is disposed on a circuit substrate having a plurality of substrate pads, and the first conductive bumps are respectively situated on the substrate pads. Next, a heating process is performed to both of the first conductive bumps and the first insulation paste, wherein the first conductive bumps is reflowed to bond the first electronic component and the substrate pads, and the first insulation paste is cured. | 2011-02-10 |
20110031606 | PACKAGING SUBSTRATE HAVING EMBEDDED SEMICONDUCTOR CHIP - A packaging substrate includes: a core board having opposite first and second surfaces and a cavity penetrating therethrough; a semiconductor chip disposed in the cavity and having an active surface with electrode pads and an opposite inactive surface; a first reinforcing dielectric layer containing a reinforcing material disposed on the first surface and the active surface and filling the gap between the chip and the cavity; a second reinforcing dielectric layer containing a reinforcing material disposed on the second surface and the inactive surface and filling the gap between the chip and the cavity; and first and second wiring layers disposed on the first and second reinforcing dielectric layers respectively and the first wiring layer electrically connecting to the electrode pads. The first and second reinforcing dielectric layers enhance the support force of the entire structure to thereby prevent delamination of the wiring layers from the dielectric layers and increase product yield and reliability. | 2011-02-10 |
20110031607 | CONDUCTOR PACKAGE STRUCTURE AND METHOD OF THE SAME - The present invention provides a conductor package structure comprising a conductive base. An adhesive layer is formed on the conductive base. An electronic element is formed on the adhesive layer. Conductors are forming signal connection between the surface of a filling material and the bottom of the filling material, wherein the filling material is filled in the space between the electronic element and the conductors. | 2011-02-10 |
20110031608 | POWER DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - Disclosed is a power device package, which has high heat dissipation performance and includes an anodized metal substrate including a metal plate having a cavity formed on one surface thereof and an anodized layer formed on both the surface of the metal plate and the inner wall of the cavity and a circuit layer formed on the metal plate, a power device mounted in the cavity of the metal plate so as to be connected to the circuit layer, and a resin sealing material charged in the cavity of the metal plate. A method of fabricating the power device package is also provided. | 2011-02-10 |
20110031609 | SEMICONDUCTOR PACKAGE HAVING THROUGH ELECTRODES THAT REDUCE LEAKAGE CURRENT AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package having through electrodes that exhibit a reduced leakage current and a method of making the same are presented. The stacked semiconductor package includes a semiconductor chip, through-holes, and a current leakage prevention layer. The semiconductor chip has opposing first and second surfaces. The through-holes pass entirely through the semiconductor chip and are exposed at the first and second surfaces. A polarized part is formed on at least one of the first and second surfaces of the semiconductor chip. The through-electrodes are disposed within the through-holes. The current leakage prevention layer covers the polarized part and exposes ends of the through-electrodes. | 2011-02-10 |
20110031610 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, PRINTED CIRCUIT BOARD AND ELECTRONIC DEVICE - Provided is a semiconductor device including a flexible circuit board which includes a first external electrode provided on a first face and second and third external electrodes provided on a second face; a plurality of memory devices and passive components; a supporter which is provided with a groove on one face; and a computing processor device. The memory devices and the passive components are connected to the first external electrode, the one face of the supporter is bonded on the first face of the flexible circuit board so that the groove houses the memory devices and the passive components. The flexible circuit board is bent along a perimeter of the supporter to be wrapped around a side face and another face of the supporter. On the flexible circuit board, the second external electrode is provided on the second face which is opposite to the first external electrode, and the third external electrode is provided on the second face which is bent to the another face of the supporter. The computing processor device is connected to the second external electrode, and a bump is formed on the third external electrode. | 2011-02-10 |
20110031611 | EMBEDDED LAMINATED DEVICE - An electronic device includes at least one semiconductor chip, each semiconductor chip defining a first main face and a second main face opposite to the first main face. A first metal layer is coupled to the first main face of the at least one semiconductor chip and a second metal layer is coupled to the second main face of the at least one semiconductor chip. A third metal layer overlies the first metal layer and a fourth metal layer overlies the second metal layer. A first through-connection extends from the third metal layer to the fourth metal layer, the first through-connection being electrically connected with the first metal layer and electrically disconnected from the second metal layer. A second through-connection extends from the third metal layer to the fourth metal layer, the second through-connection being electrically connected with the second metal layer and electrically disconnected from the first metal layer. | 2011-02-10 |
20110031612 | POWER SEMICONDUCTOR CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - A power semiconductor circuit device and a method for manufacturing the same, both of which are provided with: a base board on which at least a power semiconductor element is mounted; a resin which molds the base board and the power semiconductor element in a state where partial surfaces of the base board, including a base board surface opposite to a surface on which the power semiconductor element is mounted, are exposed; and a heat dissipating fin joined to the base board by a pressing force. A groove is formed in the base board at a portion to be joined to the heat dissipating fin, and the heat dissipating fin is joined by caulking to the groove. | 2011-02-10 |
20110031613 | SEMICONDUCTOR PACKAGE HAVING A HEAT DISSIPATION MEMBER - A semiconductor package having a heat dissipation member capable of efficiently conveying excess heat away from semiconductor chips is presented. The semiconductor package includes a semiconductor chip, through-electrodes, and a heat dissipation member. The semiconductor chip has a first surface, a second surface facing away from the first surface, and bonding pads which are disposed on the first surface. The through-electrodes are electrically connected with the bonding pads and passing through the first and second surfaces of the semiconductor chip, and protrude outward from the second surface. The heat dissipation member faces the second surface of the semiconductor chip and is coupled to the through-electrodes. | 2011-02-10 |
20110031614 | METHODS FOR FABRICATING SEMICONDUCTOR COMPONENTS AND PACKAGED SEMICONDUCTOR COMPONENTS - Packaged semiconductor components and methods for manufacturing packaged semiconductor components. In one embodiment a semiconductor component comprises a die having a semiconductor substrate and an integrated circuit. The substrate has a first side, a second side, a sidewall between the first and second sides, a first indentation at the sidewall around a periphery of the first side, and a second indentation at the sidewall around a periphery of the second side. The component can further include a first exterior cover at the first side and a second exterior cover at the second side. The first exterior cover has a first extension in the first indentation, and the second exterior cover has a second extension in the second indentation. The first and second extensions are spaced apart from each other by an exposed portion of the sidewall. | 2011-02-10 |
20110031615 | Semiconductor device - A semiconductor device having a structure that can reduce stress due to difference in coefficients of thermal expansion and prevent or suppress generation of cracks, and a semiconductor device manufacturing method, are provided. The semiconductor device includes a single crystal silicon substrate having a main face on which semiconductor elements are formed and a side face intersecting with the main face, and a sealing resin provided covering at least a portion of the side face. The side face covered by the sealing resin is equipped with a first face with a plane direction forming an angle of −5° to +5° to the plane direction of the main face. | 2011-02-10 |
20110031616 | STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES - Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming a plurality of trenches in a dielectric layer extending to an underlying metal layer. The method further includes depositing metal in the plurality of trenches to form discrete metal line islands in contact with the underlying metal layer. The method also includes forming a solder bump in electrical connection to the plurality of metal line islands. | 2011-02-10 |
20110031617 | SEMICONDUCTOR PACKAGE SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package. | 2011-02-10 |