06th week of 2012 patent applcation highlights part 19 |
Patent application number | Title | Published |
20120032656 | VOLTAGE REGULATOR FOR IMPEDANCE MATCHING AND PRE-EMPHASIS, METHOD OF REGULATING VOLTAGE FOR IMPEDANCE MATCHING AND PRE-EMPHASIS, VOLTAGE MODE DRIVER INCLUDING THE VOLTAGE REGULATOR, AND VOLTAGE-MODE DRIVER USING THE METHOD - Disclosed herein are a voltage regulator for impedance matching and pre-emphasis, a method of regulating voltage for impedance matching and pre-emphasis, and a voltage mode driver using the voltage regulator and the method. The voltage regulator includes a first loop circuit configured to regulate a supply voltage for a pre-driver of a main tap, a second loop circuit configured to regulate a supply voltage for a pre-driver of a pre-emphasis tap, and a driver voltage determination unit configured to include a reference resistor and to determine supply voltage for the voltage mode driver. The first loop circuit includes a variable resistor, a first main tap replica, and a first OP amp, and the second loop circuit includes a resistor having a resistance value identical to that of the reference resistor of the voltage regulator, a second main tap replica, a pre-emphasis tap replica, and a second OP amp. | 2012-02-09 |
20120032657 | REDUCING SHOOT-THROUGH IN A SWITCHING VOLTAGE REGULATOR - Methods, apparatuses, and devices for a voltage regulator are provided. In certain examples, a method for preventing shoot-through in a voltage regulator includes determining whether an output stage for a voltage regulator is operating in a continuous-conduction mode (CCM) or a discontinuous conduction mode (DCM); and setting the voltage regulator in one of adaptive dead time mode and programmable dead time mode based on whether the output stage is operating in CCM or DCM. | 2012-02-09 |
20120032658 | Buck-Boost Converter Using Timers for Mode Transition Control - A DC-to-DC, buck-boost voltage converter includes a duty cycle controller configured to generate control signals for a buck driver configured to drive first and second buck switching transistors at a buck duty cycle and to generate control signals for a boost driver configured to drive first and second boost switching transistors at a boost duty cycle. The duty cycle controller includes at least a duty cycle timer and an offset timer where the duty cycle controller applies the duty cycle timer and the offset timer to control transitions between the buck, the buck-boost and the boost operation modes of the voltage converter. | 2012-02-09 |
20120032659 | POWER SUPPLY DEVICE - A power supply device for transforming a DC input voltage by switching charging/discharging of an inductor, and obtaining a DC output voltage by smoothing the transformed voltage by a capacitor, includes: a transistor for synchronous rectification coupled between the inductor and the capacitor; a current determination circuit for determining whether a current flowing through the transistor is less than a lower-limit current; and a control circuit for operating the transistor in a constant current operation while the current flowing through the transistor is greater than the lower-limit current and operating the transistor in a rectification operation when the current is less than the lower-limit current, based on a determination result of the current determination circuit. | 2012-02-09 |
20120032660 | SWITCHING POWER SOURCE APPARATUS - A switching power source apparatus includes a high-side MOSFET | 2012-02-09 |
20120032661 | SWITCHING POWER SOURCE APPARATUS - A switching power source apparatus includes a high-side MOSFET | 2012-02-09 |
20120032662 | REDUCTION OF INRUSH CURRENT DUE TO VOLTAGE SAGS WITH INPUT POWER VOLTAGE RECONNECTION AT ZERO CROSSING - Various systems and methods are provided for minimizing an inrush current to a load after a voltage sag in a power voltage. In one embodiment, a method is provided comprising the steps of applying a power voltage to a load, and detecting a sag in the power voltage during steady-state operation of the load. The method includes the steps of adding an impedance to the load upon detection of the sag in the power voltage, and removing the impedance from the load when the power voltage has reached a predefined point in the power voltage cycle after the power voltage has returned to a nominal voltage. | 2012-02-09 |
20120032663 | REDUCTION OF INRUSH CURRENT DUE TO VOLTAGE SAGS WITH TIMING FOR INPUT POWER VOLTAGE RECONNECTION - Various systems and methods are provided for minimizing an inrush current to a load after a voltage sag in a power voltage. In one embodiment, a method is provided comprising the steps of applying a power voltage to a load, and detecting a sag in the power voltage during steady-state operation of the load. The method includes the steps of adding an impedance to the load upon detection of the sag in the power voltage, and removing the impedance from the load when the power voltage has reached a predefined point in the power voltage cycle after the power voltage has returned to a nominal voltage. | 2012-02-09 |
20120032664 | SINGLE INDUCTOR POWER CONVERTER SYSTEM AND METHODS - Methods, systems, and devices are described for a non-isolated dc-dc power converter that uses a single magnetic element and provides both a positive and a negative voltage output. The magnetic element, such as an inductor, is coupled with two or more switching modules that electrically switch the inductor to and from a voltage source, an inductor terminal, and/or a load. By electrically connecting and electrically isolating different components at various times, separate positive and negative voltage outputs are provided using the single inductor element. Switching may be controlled by a controller module, and a magnitude of the dc output voltage may be selected based on two or more resistors coupled with the controller module. | 2012-02-09 |
20120032665 | DISTRIBUTED MAXIMUM POWER POINT TRACKING SYSTEM, STRUCTURE AND PROCESS - Distributed maximum power point tracking systems, structures, and processes are provided for power generation structures, such as for but not limited to a solar panel arrays. In an exemplary solar panel string structure, distributed maximum power point tracking (DMPPT) modules are provided, such as integrated into or retrofitted for each solar panel. The DMPPT modules provide panel level control for startup, operation, monitoring, and shutdown, and further provide flexible design and operation for strings of multiple panels. The strings are typically linked in parallel to a combiner box, and is then toward and enhanced inverter module, which is typically connected to a power grid. Enhanced inverters are controllable either locally or remotely, wherein system status is readily determined, and operation of one or more sections of the system are readily controlled. The system provides increased operation time, and increased power production and efficiency, over a wide range of operating conditions. | 2012-02-09 |
20120032666 | METHOD AND SYSTEM OF MEASURING CURRENT IN AN ELECTRIC METER - A method and system for measuring the current flowing through an electric meter. The electric meter includes a reactive sensor positioned in series with a bus bar contained in the meter. The reactive sensor includes an inductor and the voltage across the inductance is measured. A control unit contained in the electric meter calculates the current based on the detected voltage and the value of the inductor. The value of the inductor is determined by passing a reference current through the inductor at a known frequency, such as 50 Hz or 60 Hz, and the voltage drop across the inductor is measured. Once the value of the inductor is determined, the value is stored in the control unit. | 2012-02-09 |
20120032667 | CURRENT SENSOR STRUCTURE - A current sensor structure includes a substantially ring-shaped magnetic core comprising layers of magnetic plates to be accommodated in an insulating case and secured to the case via a molding compound. Projections protruding in the magnetic plate's thickness direction are provided either on a front-side wall portion of the case in the thickness direction or on a surface of the magnetic core in the thickness direction. By virtue of, the surface of the magnetic core is supported by the front-side wall portion via the projections, leaving a gap between this surface and the wall portion to the same height as that of the projections. The gap is filled with the molding compound. Dilative and contractive deformation of the case in the direction orthogonal to the thickness direction is absorbed by the molding compound in the gap to prevent the stress from acting upon the magnetic core. | 2012-02-09 |
20120032668 | Transportation Vehicle System and Charging Method for the Transportation Vehicle System - A magnetic sensor array including a plurality of magnetic sensors detects a phase regarding a magnetic pole of a magnetic pole array including magnetic poles of N and S arranged alternately. A pitch identification unit detects a pitch number of the magnetic pole currently being detected by the magnetic sensor array, in the magnetic pole array. | 2012-02-09 |
20120032669 | MAGNETIC DEVICE FOR DETERMINATION OF ANGULAR POSITION IN A MULTIPHASE ROTARY ELECTRICAL MACHINE - Disclosed is the selecting of the optimum characteristics of a magnetic device producing a sinusoidal signal for determination of angular position in a rotary machine. The device includes a multi-polar magnetic ring which is mobile in rotation around an axis, and creates a variable magnetic field according to an angle of rotation. In close proximity to the magnetic ring, a magnetic sensor is placed in this magnetic field, and generates the sinusoidal signal. The air gap between the sensor and ring is constituted by spacing the sensor by a distance E from the magnetic ring on a radial plane. Optimum performance is achieved when a first ratio e/E of a thickness e of the multi-polar magnetic ring in a direction which is radial relative to the air gap E is between 0.4 and 2.3. A second ratio h/e of a height h of the ring, in a direction which is axial relative to the thickness e, is between 1.5 and 8. | 2012-02-09 |
20120032670 | Rotational angle sensor and method manufacturing same, and throttle control device with rotational angle sensor - A rotational angle sensor and a method for manufacturing the same, and a throttle control device with a rotational angle sensor, which may lower the cost, are provided. The rotational angle sensor includes each sensor IC for detecting a rotational angle of a rotor based on a magnetic field generated between a pair of magnets respectively disposed across the rotational axis of the rotor; each main terminal connected with each connection terminal of each sensor IC; and a holder member for holding each sensor IC and connection portions of each main terminal on each sensor side. A sensor assembly is constructed to form the sensor ICs the main terminals and the holder member into an assembly. A potting material is potted into the holder member. | 2012-02-09 |
20120032671 | METHOD TO DETERMINE PRESENCE OF ROTATOR AND METHOD TO ADJUST OPTIMAL GAIN - A rotation driving system and a method to determine the presence of a rotator on a turntable are provided. The rotation driving system includes an encoder to detect rotation information of a motor, and a controller to determine whether or not a rotator is present on a turntable and also, to adjust a gain of the motor according to moment of inertia of the rotator. | 2012-02-09 |
20120032672 | CARBURIZATION SENSING METHOD - A carburization sensing method according to the present invention includes: a first procedure of attaching a magnetic material to a reference material which has equivalent electromagnetic properties to those of a test material and is not carburized, a second procedure of measuring magnetic strength of each magnetic material and to acquire an electromagnetic test output value for each magnetic material, a third procedure of calculating a correlation between the measured magnetic strength value and the electromagnetic test output value, a fourth procedure of measuring magnetic strengths on a plurality of carburized materials, a fifth procedure of calculating a correlation between a carburized depth and the measured magnetic strength value, a sixth procedure of determining a threshold value Th | 2012-02-09 |
20120032673 | MAGNETIC SENSOR - First magnetoresistive effect elements and second magnetoresistive effect elements and are formed on the same substrate. A pinned magnetic layer of each of the first magnetoresistive effect elements has a three-layer laminated ferrimagnetic structure including magnetic layers. A pinned magnetic layer of each of the second magnetoresistive effect elements has a two-layer laminated ferrimagnetic structure including magnetic layers. The magnetization direction of the third magnetic layer of each of the magnetoresistive effect elements is antiparallel to the magnetization direction of the second magnetic layer of each of the second magnetoresistive effect elements. | 2012-02-09 |
20120032674 | Current Sensor - This disclosure is directed to current sensing techniques for use within a magnetic current sensor. According to one aspect of the disclosure, a current sensing device includes a magnetic core, and a magnetic field sensor positioned substantially within a cavity formed by an air gap interface of the magnetic core and configured to sense a magnetic field induced by an electrical current that is conducted through a conductor passing through a central opening of the magnetic core. | 2012-02-09 |
20120032675 | Apparatus and Method for Ferromagnetic Object Detector - An apparatus is provided for compensating for the effect of a stray ferromagnetic object moving past but not through a sensing region of a ferromagnetic object detector. The ferromagnetic object detector is of a type to produce a plurality of sensor signals, each sensor signal being influenced by the presence of a genuine ferromagnetic object moving through the sensing region but also liable to be influenced by the presence of the stray object. The apparatus comprises: an input for receiving the plurality of sensor signals and first means for analysing the received signals to determine whether there is a substantially same time-varying component present in each of the signals. The apparatus also comprises second means for determining whether the plurality of signals without the contribution of that time-varying component are each or collectively below a predetermined level of significance. The apparatus also comprises third means for indicating, if the respective determinations from the first and second means are both positive, that the received signals are likely to relate to a stray object and not to a genuine ferromagnetic object moving through the sensing region. | 2012-02-09 |
20120032676 | Spatial intensity correction for RF shading non-uniformities in MRI - An MRI MAP prescan data from a predetermined imaged patient volume is decomposed to produce a transmit RF field inhomogeneity map and a receive RF field inhomogeneity map for the imaged patient volume based on a three-dimensional geometrical model of the inhomogeneity maps. At least one of the transmit RF field inhomogeneity map and the receive RF field inhomogeneity map is used to generate intensity-corrected target MRI diagnostic scan image data representing the imaged patient volume. | 2012-02-09 |
20120032677 | SPATIAL INTENSITY CORRECTION FOR RF SHADING NON-UNIFORMITIES IN MRI - An MRI MAP prescan data from a predetermined imaged patient volume is decomposed to produce a transmit RF field inhomogeneity map and a receive RF field inhomogeneity map for the imaged patient volume based on a three-dimensional geometrical model of the inhomogeneity maps. At least one of the transmit RF field inhomogeneity map and the receive RF field inhomogeneity map is used to generate intensity-corrected target MRI diagnostic scan image data representing the imaged patient volume. | 2012-02-09 |
20120032678 | METHOD AND COILS FOR HUMAN WHOLE-BODY IMAGING AT 7 T - A progressive series of five new coils is described. The first coil solves problems of transmit-field inefficiency and inhomogeneity for heart and body imaging, with a close-fitting, 16-channel TEM conformal array design with efficient shield-capacitance decoupling. The second coil progresses directly from the first with automatic tuning and matching, an innovation of huge importance for multi-channel transmit coils. The third coil combines the second, auto-tuned multi-channel transmitter with a 32-channel receiver for best transmit-efficiency, control, receive-sensitivity and parallel-imaging performance. The final two coils extend the innovative technology of the first three coils to multi-nuclear ( | 2012-02-09 |
20120032679 | GRADIENT COIL ARRANGEMENT - A gradient coil arrangement for use in a magnetic imaging system, the imaging system being for generating a magnetic imaging field in an imaging region provided in a bore. The coil arrangement includes a first portion having a substantially cylindrical shape for positioning in the bore, a second portion extending outwardly from an end of the first portion, the second portion being for positioning outside the bore and at least one coil for generating a gradient magnetic field in the imaging region, the at least one coil having a first part provided on the first portion and a second part provided on the second portion. | 2012-02-09 |
20120032680 | LOW MAGNETIC FIELD RESONANCE SYSTEM - The invention provides a low-field nuclear magnetic resonance system for measuring a magnetic resonance signal of an object. The low-field nuclear magnetic resonance system includes a pre-magnetization module, a uniform magnetic field coil module, a pulse and receiving coil module, a filter amplifier module, a signal acquisition module and a processing module. The pre-magnetization module is used to establish a pre-magnetization field in the object to increase magnetization of the object. The uniform magnetic field coil module is used to change a resonance frequency and background magnetic field intensity of the object during nuclear magnetic resonance measurement by regulating a magnetic field of the coil. The processing module further includes a programming object for controlling timing processing and signal analysis of the measurement process. | 2012-02-09 |
20120032681 | DETERMINATION OF THE INTERNAL RESISTANCE OF A BATTERY CELL OF A TRACTION BATTERY WHILE USING RESISTIVE CELL BALANCING - The invention relates to a method and a device for determining the internal resistance of a battery cell of a battery, in particular a traction battery, in which the method can be used either during charging processes or discharging processes and in phases in which the battery including the battery cell does not supply or receive any electrical power, in which resistive cell balancing for balancing the charging states of the battery cells is carried out in the battery, whereby energy is removed from the battery cell via a resistor. According to the invention, a first control module is provided for determining a first voltage applied to the battery cell and a first current flowing from or to the battery cell at a first time during removal or supply of the charge and for determining a second voltage applied to the battery cell and a second current flowing from or to the battery cell at a second time during removal or supply of the charge. Further provided is a calculating unit for calculating the internal resistance of the battery cell on the basis of the quotients of the difference of the second voltage and the first voltage and the difference of the second current and the first current. | 2012-02-09 |
20120032682 | BATTERY OPTIMIZATION AND PROTECTION IN A LOW POWER ENERGY ENVIRONMENT - A method and apparatus for providing battery optimization and protection in a low power energy environment is presented. A current configuration of a battery module including a plurality of a particular type of battery is determined. A voltage level of the battery module is detected. A determination is made whether the current configuration of the battery module is a preferred configuration for the particular type of batteries of the battery module. When the determination is that the current configuration of the battery module is not the preferred configuration for the particular type of batteries of the battery module, then the battery module is reconfigured to a preferred configuration for the particular type of batteries of the battery module. | 2012-02-09 |
20120032683 | METHOD FOR DIAGNOSING CURRENT SENSORS IN AN INDUCTION MACHINE DURING OPERATION THEREOF - A method diagnoses current sensors of an n-phase induction machine which has n−1 current sensors. The n phases of the induction machine are short-circuited for a brief period of time during normal operation of the induction machine, and the time progressions of the n−1 currents are measured by the n−1 current sensors during the short-circuit operation. The actual values of the time progressions of the n−1 measured short-circuit currents are compared to corresponding prescribed target values for the n−1 short-circuit currents. A potential fault state of one or more current sensors is determined from the comparison. | 2012-02-09 |
20120032684 | ACTIVE PIN CONNECTION MONITORING SYSTEM AND METHOD - A system for monitoring a connection to an active pin of an integrated circuit (IC) die, includes an input/output (I/O) cell of an IC die, where the I/O cell is bonded to a bonding pad on a ball grid array (BGA) substrate. The system includes a test point on a printed circuit board (PCB) coupled to the bonding pad which forms an electrical/conductive pathway between the test point and the I/O cell. The system includes a clock waveform injected through a resistor into the test point. | 2012-02-09 |
20120032685 | IEEE 1394 INTERFACE TEST APPARATUS - An Institute of Electrical and Electronics Engineers (IEEE) test apparatus includes an IEEE 1394 chip, an IEEE 1394 plug, an IEEE 1394 outlet, a test header, and a switch module. The IEEE 1394 chip, plug and outlet each include a ground pin, two pairs of differential signal pins, and a power pin. The test header includes ground pin sockets, two pairs of differential signal pin sockets, and a power signal pin socket. The three power pins and the power signal pin socket are electrically connected together. The switch module is operable to electrically connect the two pairs of differential signal pins of the IEEE 1394 chip to the two pairs of differential signal pins of the IEEE 1394 plug or electrically connect the two pairs of differential signal pins of the IEEE 1394 chip to the two pairs of differential signal pins of the IEEE 1394 outlet. | 2012-02-09 |
20120032686 | VOLTAGE SOURCE FOR CALIBRATING A FAST TRANSIENT VOLTAGE MEASUREMENT SYSTEM AND CALIBRATION METHOD - The present disclosure discloses a voltage source for calibrating a fast transient voltage measurement system, comprising a DC high voltage power supply, a discharging gap, a high voltage conductor and an earthing conductor, wherein the high voltage conductor and the earthing conductor are high voltage insulated from each other and form a traveling wave line with constant wave impedance; the DC high voltage power supply is connected between the ends of the high voltage conductor and the earthing conductor; the discharging gap is connected between ends of the high voltage conductor and the earthing conductor; the discharging gap is broken down when the charging voltage on the high voltage conductor is risen to a certain amplitude. The present disclosure also provides a method for calibrating a fast transient voltage measurement system: the high voltage conductor is insulated from the earthing conductor, and is open circuit at one end and at the other end connected with the earthing conductor via the discharging gap, the high voltage breaks down the discharging gap, applying a high voltage between the high voltage conductor and the earthing conductor, a very fast transient high voltage is produced on the high voltage conductor and its waveform can be determined by theoretical calculation, the very fast transient high voltage with known waveform is used as the calibration voltage for calibrating the measurement system. This reaches the purpose of simplifying the structure of voltage source for calibrating the fast transient voltage measurement system as well as the calibration method. | 2012-02-09 |
20120032687 | DETECTION APPARATUS FOR DETECTING ELECTRIC FIELD DISTRIBUTION OR CARRIER DISTRIBUTION BASED ON THE INTENSITY OF HIGH-ORDER HARMONICS - A detection apparatus having means for evaluating generation and disappearance of a carrier is provided. A detection apparatus detects, on the basis of high-order harmonics, an electric field distribution or a carrier distribution between electrodes arranged on an object to be observed. The detection apparatus includes an emission unit for emitting a fundamental wave to the object, a detection unit for detecting the high-order harmonics generated according to the electric field distribution or the carrier distribution in the object when a voltage is applied to the object, an excitation emission unit for emitting an excitation light for generating a carrier in the object, and a control signal output unit for outputting a second signal to cause the excitation emission unit to emit the fundamental wave to the object on the basis of a first signal of the excitation emission unit, and outputting a third signal to cause the detection unit to detect the high-order harmonics, wherein the control signal output unit is configured to change a time interval from when the first signal is output to when the second and third signals are output. | 2012-02-09 |
20120032688 | CROSSTALK COMPENSATION IN ANALYSIS OF ENERGY STORAGE DEVICES - Estimating impedance of energy storage devices includes generating input signals at various frequencies with a frequency step factor therebetween. An excitation time record (ETR) is generated to include a summation of the input signals and a deviation matrix of coefficients is generated relative to the excitation time record to determine crosstalk between the input signals. An energy storage device is stimulated with the ETR and simultaneously a response time record (RTR) is captured that is indicative of a response of the energy storage device to the ETR. The deviation matrix is applied to the RTR to determine an in-phase component and a quadrature component of an impedance of the energy storage device at each of the different frequencies with the crosstalk between the input signals substantially removed. This approach enables rapid impedance spectra measurements that can be completed within one period of the lowest frequency or less. | 2012-02-09 |
20120032689 | Blade tip clearance measurement sensor for gas turbine engines - An electromagnetic field sensor assembly for blade tip clearance measurement in a gas turbine engine is disclosed that includes a ceramic sensor body, a multi-layered wire coil wound about a distal end portion of the sensor body for producing an electromagnetic field, a ceramic well enclosing the sensor body and the coil, and a metallic housing surrounding the well and having an open distal end. | 2012-02-09 |
20120032690 | PROXIMITY SWITCH - Disclosed is a proximity switch provided with an actuator unit and a sensor unit. The sensor unit is provided with an antenna coil, a transmitting circuit which transmits electromagnetic waves at a constant frequency to the antenna coil, a receiving circuit which detects external signals received by means of the antenna coil, and control circuits. The actuator unit is provided with an antenna coil, a power supply circuit which rectifies an electromotive force generated in the antenna coil, and a signal processing circuit which receives power supply from the power supply circuit, performs frequency-dividing to the signals received by means of the antenna coil, and transmits the signals from the antenna coil after the frequency-dividing. The control circuit of the sensor unit has memory for registering the frequency of the signals transmitted from the actuator unit. The control circuit determines whether the actuator unit is in proximity to the sensor unit or not by checking the received signals detected by means of the receiving circuit with the operations of the transmitting circuit and the frequency registered in the memory. | 2012-02-09 |
20120032691 | DEVICE FOR MEASURING DISTANCE BETWEEN HEADREST AND HEAD, METHOD FOR MEASURING DISTANCE BETWEEN HEADREST AND HEAD, HEADREST POSITION ADJUSTING DEVICE, AND HEADREST POSITION ADJUSTING METHOD - A headrest position adjusting device | 2012-02-09 |
20120032692 | MEMS GAS SENSOR - Systems and methods for sensing a chemical or gas species of interest are provided. In one aspect, a method of sensing a chemical includes determining a capacitance change between at least two layers in a MEMS device, the capacitance between the at least two layers indicative of a presence of one or more chemicals; and identifying the presence of the one or more chemicals based on a determined electrical response of the at least two layers and the determined capacitance change. | 2012-02-09 |
20120032693 | Crack detection in a semiconductor die and package - A method is provided in which an impedance is measured between a first of a plurality of seal ring contact pads and a ground contact pad coupled to a semiconductor substrate of a semiconductor device. The first impedance value is obtained from the measured impedance, and the first impedance value is compared with a reference impedance value to determine whether a structural defect is present in the semiconductor device based on whether the first impedance value is greater than the reference impedance value. | 2012-02-09 |
20120032694 | IN-PROCESS ELECTRICAL CONNECTOR - Characteristics of partially assembled photovoltaic modules can be determined using electrical connection apparatuses and methods. | 2012-02-09 |
20120032695 | METHOD OF AND CIRCUIT FOR BROWN-OUT DETECTION - A circuit and method for detecting a brown-out condition and providing a feed-forward transfer function in a power supply circuit. A comparison circuit is coupled to a delay element through a latch. A second delay element is connected between the first delay element and an input of the latch. The output of the first delay element is connected to a clamping circuit via a logic circuit. A first voltage is compared with a reference voltage to generate a comparison voltage, which is transmitted through the latch and the first delay element. The comparison voltage is monitored at an output of the first delay element. A brown-out condition occurs if the comparison voltage being monitored at the output of the first delay element results from the first voltage being less than the reference voltage. | 2012-02-09 |
20120032696 | DEVICE AND METHOD FOR TESTING SEMICONDUCTOR DEVICE - A testing method for testing a semiconductor device includes heating the semiconductor device until the temperature of the semiconductor device reaches a predetermined temperature; conducting other functional tests other than testing of the overheat protection function in a second step after the temperature of the semiconductor device has reached the predetermined temperature; allowing the semiconductor device to generate heat by itself such that the overheat protection function of the semiconductor device is activated, detecting a first diode forward voltage of a desired diode contained in the semiconductor device when the overheat protection function of the semiconductor device is activated and computing a first computational temperature of the semiconductor device based on the detected first diode forward voltage of the desired diode contained in the semiconductor device; and determining whether the computed first computational temperature of the semiconductor device resides in the overheat protection function activating temperature range. | 2012-02-09 |
20120032697 | PROBE FOR TESTING SEMICONDUCTOR DEVICES - A novel hybrid probe design is presented that comprises a torsion element and a bending element. These elements allow the probe to store the displacement energy as torsion or as bending. The novel hybrid probe comprises a probe base, a torsion element, a bending element, and a probe tip. The probe elastically deforms to absorb the displacement energy as the probe tip contacts the DUT contact pad. The bending element absorbs some of the displacement energy through bending. Because the torsion element and the bending element join at an angle between −90 degrees and 90 degrees, a portion of the displacement energy is transferred to the torsion element causing it to twist (torque). The torsion element can also bend to accommodate the storage of energy through torsion and bending. Also, adjusting the position of a pivot can be manipulated to alter the energy absorption characteristics of the probe. One or more additional angular elements may be added to change the energy absorption characteristics of the probe. And, the moment of inertia for the torsion and/or bending elements can by manipulated to achieve the desired probe characteristics. Other features include a various union angle interface edge shapes, pivot cutouts and buffers. | 2012-02-09 |
20120032698 | Test Device and Test Method for Multimedia Data Card and Mobile-Phone Multimedia Data Card - The present invention discloses a test device and test method for a multimedia data card and the multimedia data card of a mobile phone, wherein, the test device includes a printed circuit board (PCB) and the PCB is equipped with a detachable connection slot module which is used for connecting with each module to be tested; the test device for the multimedia data card includes a micro-connector and one end of the micro-connector connects with the connection slot module; the other end of the micro-connector connects with a PCB tester; the related data are transmitted to the PCB tester through the connection slot module and the micro-connector. By the present invention, the PCB can be tested once the PCB tester connects with the micro-USB-connector; the plug is convenient; operations such as windowing and positioning are not needed; test efficiency is improved; and the cost of developing test fixture for connecting these test points and the cost of test and manufacture are reduced. | 2012-02-09 |
20120032699 | METHOD OF MEASURING ELECTRICAL CHARACTERISTICS OF SEMICONDUCTOR WAFER - There is provided a method of measuring a leakage current or a dielectric breakdown voltage of a semiconductor wafer that has a base wafer and a buffer layer formed on the base wafer. The method includes providing, on the buffer layer, a plurality of electrodes including a hole injection electrode made of a material that injects a hole into the buffer layer when an electric field is applied thereto, measuring an electric current flowing through a pair of electrodes or a voltage between the electrodes when a voltage or an electric current is applied to the pair of electrodes, the electrodes including at least one hole injection electrode, and measuring a leakage current or a dielectric breakdown voltage caused by hole migration in the semiconductor wafer based on the current flowing through the pair of electrodes or the voltage generated between the pair of the electrodes. | 2012-02-09 |
20120032700 | MULTILAYER WIRING BOARD AND METHOD FOR EVALUATING MULTILAYER WIRING BOARD - A method for evaluating a multilayer wiring board is provided. The multilayer wiring board includes an inner-layer on which a test pattern is disposed. The method includes arranging a plurality of first patterns and a second pattern of the test pattern such that the first patterns have a comb-like shape opposed to one another, and the second pattern has an unbranched shape extending between the opposed first patterns. A voltage is applied between the first patterns and the second pattern. An impedance of the second pattern is measured. | 2012-02-09 |
20120032701 | QUAD STATE LOGIC DESIGN METHODS, CIRCUITS, AND SYSTEMS - Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs. | 2012-02-09 |
20120032702 | HARDENED PROGRAMMABLE DEVICES - Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data. | 2012-02-09 |
20120032703 | PULSE-SHRINKING DELAY LINE BASED ON FEED FORWARD - A shrinking-pulse digital delay line ( | 2012-02-09 |
20120032704 | INTEGRATION OF OPEN SPACE/DUMMY METAL AT CAD FOR PHYSICAL DEBUG OF NEW SILICON - An access pad is used to provide access to a functional block of an integrated circuit (IC) device. The access pad is formed using dummy metal in an open space in a metallization level that is between a top metallization level and a base level on which the functional block is formed in the IC device. The access pad at the metallization level provides a contact to access an underlying circuit of the functional block so that the functional integrity of the functional block of the IC device can be verified during probing. | 2012-02-09 |
20120032705 | Device for Detecting Pulsed Signals Comprising a Function for Detecting Tangling of Pulses - A device for detecting non-phase-modulated pulsed signals or sequences of pulses of a determined frequency includes means for detecting tangling of pulses, at least one amplifier receiving a radiofrequency signal, and restoring at least one first signal representative of the envelope of the input signal, and a second normalized signal. A phase jump estimation module includes means for estimating the phase of the radiofrequency signal, means for evaluating a phase jump, the presence of pulse tangling being detected if the phase jump is of a greater value than a determined threshold value. | 2012-02-09 |
20120032706 | MULTI-CHIP PACKAGE - A multi-chip package includes a plurality of chips coupled in parallel to an I/O pad and an output driver circuit included in each of the chips and configured to transmit output data to the I/O pad. The driving force of the output driver circuit is controlled on the basis of stack information indicative of the number of chips being activated. | 2012-02-09 |
20120032707 | Load driving device - A load driving device includes a power supply terminal, a ground terminal, an output terminal coupled to a load, an output transistor coupled between the power supply and output terminals, a driver circuit supplying a first control signal to turn on the output transistor and a second control signal to turn off the output transistor, a discharge circuit coupled between the control terminal of the output transistor and the output terminal, a compensation circuit that turns on when a potential of the ground terminal is at least a predetermined value to maintain a non-conductive state of the output transistor when a polarity of a power supply coupled between the power supply and ground terminals is normal, and a reverse connection protection circuit coupled between the control terminal and the ground terminal, which brings the output transistor into a conductive state when a polarity of the power supply is reversed. | 2012-02-09 |
20120032708 | GATE DRIVER POWER AND CONTROL SIGNAL TRANSMISSION CIRCUITS AND METHODS - Methods, systems, and devices are described for both power and control signal transmission through a single coupled inductor. A current driver generates a cyclical current signal on a primary winding of a coupled inductor, to induce a voltage signal at the secondary winding corresponding to the cyclical current signal. A rectifier module is coupled with the secondary winding and configured to rectify the signal induced at the secondary winding. A control timing signal module is coupled with the primary winding and configured to induce voltage pulses on the secondary winding, the induced voltage pulses having an insubstantial impact on the output of the rectifier module. A switching module coupled with the secondary winding is configured to receive the voltage pulses and control a switching signal for a power switch coupled with the output of the rectifier and provide power to a load coupled with the output of the rectifier. | 2012-02-09 |
20120032709 | SEMICONDUCTOR DEVICE DRIVING UNIT AND METHOD - A turn-off feedback unit ( | 2012-02-09 |
20120032710 | SEMICONDUCTOR DEVICE DRIVING UNIT AND METHOD - A semiconductor device ( | 2012-02-09 |
20120032711 | SYSTEM AND METHOD FOR PRE-CHARGING A CURRENT MIRROR - A system for pre-charging a current mirror includes a controller configured to provide a first current and an additional current to a current mirror to rapidly charge a capacitance associated with the current mirror based on a reference voltage or control signals. A power amplifier module includes at least one current minor and a controller. A capacitor is coupled to the current minor. The controller provides a bias current in an amount proportional to an input to a voltage-to-current converter. The controller receives a control signal that directs the controller to apply one of a pre-charge voltage and a nominal voltage to the voltage-to-current converter. | 2012-02-09 |
20120032712 | HIGH TEMPERATURE OPERATING PACKAGE AND CIRCUIT DESIGN - The invention provides a semiconductor device that is thermally isolated from the printed circuit board such that the device operates at a higher temperature and radiates heat away from the printed circuit board. In another embodiment, the semiconductor is stacked onto a second device and optionally thermally isolated from the second device. | 2012-02-09 |
20120032713 | Semiconductor Device and Power Supply Unit Utilizing the Same - A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals. | 2012-02-09 |
20120032714 | OUTPUT DRIVER DEVICE FOR INTEGRATED CIRCUIT - A driver device drives a load circuit by a common output signal from a first driver transistor and a second driver transistor. The driver device includes a first pre-driver unit that outputs a first driver control signal to the first driver transistor in response to the input signal; and a second pre-driver unit that outputs a second driver control signal to the second driver transistor in response to the input signal. The first pre-driver unit controls the first driver control signal in such a manner that the first driver control signal is rounded in the vicinity of a threshold of the first driver transistor and is sharply changed in a region exceeding the threshold. | 2012-02-09 |
20120032715 | HIGH-SPEED FREQUENCY DIVIDER AND A PHASE LOCKED LOOP THAT USES THE HIGH-SPEED FREQUENCY DIVIDER - A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise. | 2012-02-09 |
20120032716 | Initializing Components of an Integrated Circuit - Methods, systems, and computer program products for initializing one or more components of a system, the system comprising an integrated circuit that comprises at least one processor, are disclosed. A method includes initializing at least one component of the system, determining a temperature of the integrated circuit using a temperature sensing device embedded on the integrated circuit, comparing the determined temperature to a predetermined suitable temperature operating range of at least one additional component to yield a comparison result, and initializing the at least one additional component based on the comparison result. The at least one additional component may be initialized on the condition that the determined temperature of the integrated circuit is within the predetermined suitable temperature operating range of the at least one additional component. | 2012-02-09 |
20120032717 | POWER-ON RESET CIRCUIT - When the value of a power supply voltage (VDD) becomes a first threshold value or higher, a first start-up circuit ( | 2012-02-09 |
20120032718 | Digital Phase Lock System with Dithering Pulse-Width-Modulation Controller - A Digital Phase-Locked Loop (DPLL) has a digitally-controlled oscillator (DCO) that generates an output clock frequency determined by a digital input with most-significant-bits (MSB's) and a least-significant-bit (LSB). The LSB is generated by a Pulse-Width-Modulation (PWM) controller clocked by a control clock that is the output clock divided by C. A reference clock is compared to a feedback clock that is the output clock divided by M. The PWM controller generates M/C LSB's for each reference clock period and loads them in parallel to a parallel-to-serial shift register that serially delivers the LSBs. The pulse width is determined by a fine digital loop filter that filters phase comparison results using a fine time resolution. A coarse digital loop filter generates the MSB's from phase comparison results using a coarse time resolution. LSB waveforms are dithered by randomly selecting high-going or low-going pulses and randomly adjusting pulse widths. | 2012-02-09 |
20120032719 | ELECTRONIC CIRCUIT AND METHOD FOR OPERATING A MODULE IN A FUNCTIONAL MODE AND IN AN IDLE MODE - A method and an electronic circuit, the electronic circuit includes: a module that comprises multiple flip-flops and a control signal providing circuit; a power management circuit arranged to provide to the module a supply voltage of a functional level when the module is in a functional mode, and to provide to the module a supply voltage of an idle level when the module is in an idle mode; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the functional mode, a control signal that facilitates a state change of each of the multiple flip-flops; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a control signal that prevents a state change of each of the multiple flip-flops; wherein the each of the control signal providing circuit and a plurality of flip-flops of the multiple flip-flops comprises at least one hybrid circuit that comprises a low-threshold transistor that is coupled in parallel to at least one high-threshold transistor; wherein each hybrid circuit is arranged to maintain information or a control signal when provided with the supply voltage of the idle level; and wherein high-threshold transistors of each hybrid circuit are arranged to maintain information or a control signal when provided with a supply voltage of a level that is higher than the idle level. | 2012-02-09 |
20120032720 | METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES - A device that includes a dual edge triggered flip-flop that has state retention capabilities, the dual edge triggered flip-flop includes: a retention latch that includes a first inverter, a second inverter and a first transfer gate; wherein the first and second inverters receive power during a power gating period; a second latch that includes a third inverter, a fourth inverter and a second transfer gate; wherein the third and fourth inverters are powered down during a power gating period; a third transfer gate that is coupled between input nodes of the retention latch and the second latch; wherein the third transfer gate is opened during the power gating period; wherein the first transfer gate is controlled by a control signal and the second transfer gate is controlled by an inverted control signal; wherein the retention latch stores, at the end of the power gating period a retention value; wherein the retention value is selected, in response to a value of the control signal when the power gating period starts, out of a first initial value stored at the retention latch at the beginning of the power gating period and a second initial value stored at the second latch at the beginning of the power gating period. | 2012-02-09 |
20120032721 | CLOCK TREE FOR PULSED LATCHES - The invention concerns a computer implemented method of circuit conception of a clock tree ( | 2012-02-09 |
20120032722 | Offset Calibration for Amplifiers - An apparatus, a method, and a system are provided to calibrate an offset in an amplifier. The apparatus can include an amplifier, a voltage control unit, a comparator, and a processing unit. The amplifier can have four terminals: a positive differential input (V | 2012-02-09 |
20120032723 | SYSTEM AND METHOD FOR SIGNAL LIMITING - A method for processing a signal with a corresponding noise profile includes analyzing spectral content of the noise profile, filtering at least one noise harmonic within the signal based on the analyzed spectral content, and limiting the filtered signal. The noise profile may include a phase noise profile. The signal may include a sinusoidal signal and/or a noise signal. At least one filter coefficient that is used to filter the at least one noise harmonic may be determined. The filtering may include low pass filtering. The limiting may include hard-limiting of the filtered signal. A phase difference between the limited signal and a reference signal may be detected. | 2012-02-09 |
20120032724 | CIRCUIT AND METHOD FOR GENERATING PUMPING VOLTAGE IN SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node. | 2012-02-09 |
20120032725 | POWER MODULE - A power module comprises: first and second terminals; first and second switching elements having a first electrode and a second electrode which is connected to the second terminal; first and second wirings respectively connecting the first electrodes of the first and second switching elements to the first terminal; and a third wiring directly connecting the first electrode of the first switching element to the first electrode of the second switching element, wherein parasitic inductances of the first and second wiring are different or switching characteristics of the first and second switching elements are different. | 2012-02-09 |
20120032726 | POWER SUPPLY SELECTION/DETECTION CIRCUIT - A power supply selection/detection circuit to select one main power supply from a plurality of external power supplies includes a resistance element with one end connected to an external power supply and another end connected to the main power supply, a first voltage detector to receive a voltage of the external power supply and detect a voltage of the external power supply, a second voltage detector to detect a voltage between the ends of the resistance element, and a switch connected between the external power supply and a ground to short-circuit or open-circuit between the external power supply and the ground according to an output of the second voltage detector. The resistance element and the first voltage detector are disposed for each of the plurality of external power supplies, and the second voltage detector and the switch are disposed for at least one of the plurality of external power supplies. | 2012-02-09 |
20120032727 | CIRCUIT BREAKER - A circuit breaker is provided that includes primary and secondary paths that extend between first and second terminals. The primary path extends between the first and second terminals and through a first switch. The secondary path extends between the first and second terminals and through the second switch and a semiconductor switching element. During normal operation, a control system maintains the first and second switches in closed position and the semiconductor switching element in blocking state. When a fault condition occurs in the load current, the control system detects the fault condition and sets the semiconductor switching element to conducting state. The control system then sets the first switch to open position such that the load current flows between the first and second terminals through the secondary path. The control system then sets the second switch to open position and the semiconductor switching element to blocking state. | 2012-02-09 |
20120032728 | AUTO-OPTIMIZATION CIRCUITS AND METHODS FOR CYCLICAL ELECTRONIC SYSTEMS - Methods, systems, and devices are described for an adjustment module that interacts with a parameter detection module to provide a threshold value for initiating switching of a switching module in a cyclical electronic system. Aspects of the present disclosure provide a switching module used in conjunction with an inductor that is coupled with the switching module. The threshold voltage for switching the switching module may be adjusted to provide switching at substantially zero volts while maintaining sufficient energy in the inductor to drive the voltage at a switching element in the switching module to zero volts. Such auto-adjustment circuits may allow for enhanced efficiency in cyclical electronic systems. The output of an up/down counter may be used to set another parameter that effects the performance of the cyclical electronic system in order to enhance the performance of the cyclical electronic system. | 2012-02-09 |
20120032729 | METHOD AND APPARATUS FOR PROTECTING TRANSISTORS - The invention relates to a method and to an apparatus for protecting transistors (S | 2012-02-09 |
20120032730 | SEMICONDUCTOR INTEGRATED DEVICE - To reduce power consumption of a semiconductor integrated circuit and to reduce delay of the operation in the semiconductor integrated circuit, a plurality of sequential circuits included in a storage circuit each include a transistor whose channel formation region is formed with an oxide semiconductor, and a capacitor whose one electrode is electrically connected to a node that is brought into a floating state when the transistor is turned off. By using an oxide semiconductor for the channel formation region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized. Thus, by turning off the transistor in a period during which power supply voltage is not supplied to the storage circuit, the potential in that period of the node to which one electrode of the capacitor is electrically connected can be kept constant or almost constant. Consequently, the above objects can be achieved. | 2012-02-09 |
20120032731 | CHARGE PUMP DOUBLER - An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor. | 2012-02-09 |
20120032732 | HYBRID INTEGRATED SEMICONDUCTOR TRI-GATE AND SPLIT DUAL-GATE FINFET DEVICES AND METHOD FOR MANUFACTURING - A method for making an integrated circuit includes at least a tri-gate FinFET and a dual-gate FinFET. The method includes providing a semiconductor on insulator (SOI) substrate. The method also includes implanting impurities into the substrate for adjusting a threshold voltage. The method provides a nitride film overlying a surface region of the substrate and selectively etches the silicon nitride film to form a nitride cap region. The method etches the silicon layer to form a first and a second silicon fin regions. The nitride cap region is maintained on a portion of a surface region of the first silicon fin region. The method includes forming a gate dielectric, depositing a polysilicon film, and planarizing the polysilicon film by chemical mechanical polishing (CMP) using the nitride cap region as a polish stop. The method etches the polysilicon film to form gate electrodes. The method forms elevated source and drain regions. | 2012-02-09 |
20120032733 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SUPPLY VOLTAGE SUPERVISOR - A semiconductor integrated circuit device includes a power-supply terminal to which a power-supply voltage is input; and multiple MOS transistors including an Nch deplete mode MOS transistor functioning as a current source and at least one Pch enhancement mode MOS transistor formed on a silicon-on-insulator substrate including a silicon substrate, a buried-oxide film, and a silicon activate layer, each of the multiple MOS transistors dimensioned so that a bottom of a source diffusion layer and a bottom of a drain diffusion layer reach the buried-oxide film, the at least one Pch enhancement mode MOS transistor being connected to the supply terminal through the Nch depletion mode MOS transistor. The Nch depletion mode MOS transistor has electrical characteristics such that a source voltage thereof is higher than a silicon substrate voltage thereof and a saturation current of the Nch depletion mode MOS transistor is decreased. | 2012-02-09 |
20120032734 | INTERNAL VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR DEVICE - An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock. | 2012-02-09 |
20120032735 | REDUCING COUPLING COEFFICIENT VARIATION BY USING CAPACITORS - A coupler is presented that has high-directivity and low coupling coefficient variation. The coupler includes a first trace associated with a first port and a second port. The first port is configured substantially as an input port and the second port is configured substantially as an output port. The coupler further includes a second trace associated with a third port and a fourth port. The third port is configured substantially as a coupled port and the fourth port is configured substantially as an isolated port. In addition, the coupler includes a first capacitor configured to introduce a discontinuity to induce a mismatch in the coupler. | 2012-02-09 |
20120032736 | MODULATOR, DEMODULATOR AND MODULATOR-DEMODULATOR - A modulator, a demodulator and a modulator-demodulator are provided. A modulator includes a first intermediate signal processing path adapted to route a first intermediate signal; a second intermediate signal processing path adapted to route a second intermediate signal; a first amplifier coupled into the first intermediate signal processing path; a second amplifier coupled into the second intermediate signal processing path; and a chopper circuit coupled into the first intermediate signal processing path; wherein the chopper circuit is adapted to process the first intermediate signal in dependence on first baseband data; wherein the first amplifier is adapted to amplify the first intermediate signal processed by the chopper circuit in dependence on second baseband data; and wherein the second amplifier is adapted to amplify the second intermediate signal in dependence on the second baseband data. | 2012-02-09 |
20120032737 | ON-CHIP MILLIMETER WAVE LANGE COUPLER - A Lange coupler having a first plurality of lines on a first level and a second plurality of lines on a second level. At least one line on the first level is cross-coupled to a respective line on the second level via electromagnetic waves traveling through the first and second plurality of lines. The first and second plurality of lines may be made of metal, and the first level may be higher than the second level. A substrate may be provided into which the first and second plurality of lines are etched so as to define an on-chip Lange coupler. | 2012-02-09 |
20120032738 | POWER AMPLIFIER - An efficient power amplifier with a design which, even in cases when the phase characteristics of high frequency devices used in a main amp and peaking amp differ, reduces the combination loss of the two amps at a wide range of output levels. A class AB power amplifier ( | 2012-02-09 |
20120032739 | DIGITAL PREDISTORTION CIRCUIT WITH EXTENDED OPERATING RANGE AND A METHOD THEREOF - A digital predistortion circuit and method with extended operating range includes a predistortion function, a D/A converter, a multiplier for performing frequency translation and a power amplifier. The digital predistortion circuit includes a multiplier for receiving a signal to be transmitted and a gain correction factor, multiplying the gain correction factor with the signal to be transmitted, and outputting a result of the multiplication to the predistortion function, as well as a device for calculating the gain correction factor by using a predetermined reference gain and an estimated gain of the power amplifier, and outputting the calculated gain correction factor to the multiplier, whereby a gain of the power amplifier is quickly corrected. The digital predistortion circuit and the method thereof produce acceptable results for a more expanded range of TX power levels. | 2012-02-09 |
20120032740 | AMPLIFIER FOR RECEIVING INTERMITTENT OPTICAL SIGNAL - An amplifier for receiving an optical signal is disclosed. The amplifier provides a response time controller including an integrator with two time constants, a linear amplifier, a hysteresis comparator, an another integrator, and a switch to change the time constant. The switch includes two voltage followers, one of which turns off the switch to set the time constant in a longer state; while, the other of which turns on the switch and reflects the input of the integrator to set the time constant in a shorter state. | 2012-02-09 |
20120032741 | Integrated Bluetooth and Wireless LAN Transceivers Having Merged Low Noise and Power Amplifier - A group of transistors operate as a combined power amplifier, to amplify signals to be transmitted, and as a low noise amplifier, to amplify signals which are received. In a first mode, the group of transistors is configured to amplify the signals to be transmitted by turning all of the transistors in both a first subset and a second subset on. In a second mode, the group of transistors is configured to amplify the signals which have been received by turning on the first subset of transistors and turning off the second subset of transistors. | 2012-02-09 |
20120032742 | CMOS MILLIMETER-WAVE VARIABLE-GAIN LOW-NOISE AMPLIFIER - A low-noise amplifier (LNA) includes a first cascode gain stage coupled to an input node for increasing an amplitude of an RF input signal. A first variable gain network is coupled to the first cascode gain stage and includes a first inductor for boosting a gain of the first cascode gain stage, a first capacitor coupled to the first inductor for blocking a direct current (DC) voltage, and a first switch coupled to the first inductor and to the first capacitor. The first switch is configured to selectively couple the first inductor to the first cascode gain stage in response to a first control signal. | 2012-02-09 |
20120032743 | LOW-NOISE AMPLIFIER WITH GAIN ENHANCEMENT - A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node. The first inductive gate network is coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage. The first inductive gate network has a non-zero inductive input impedance and includes at least one passive circuit element. | 2012-02-09 |
20120032744 | POWER AMPLIFIER - A power amplifier comprises: an amplifier transistor; a bias circuit supplying bias current to the amplifier transistor; and a collector voltage terminal connected to a collector of the amplifier transistor. The bias circuit includes: a reference voltage terminal into which a reference voltage is input; a power terminal connected to a power source; a transistor having a control terminal connected to the reference voltage terminal, a first terminal connected to the power terminal, and a second terminal that is grounded. The transistor supplies a bias current corresponding to the reference voltage to the amplifier transistor; a variable capacitor connected between the first terminal and a grounding point; and a logic circuit controlling capacitance of the variable capacitor. | 2012-02-09 |
20120032745 | Frequency-Coupled LCVCO - In one embodiment, a method includes generating, by a LCVCO, a first signal having a first phase based on a resonant frequency of a first LC tank; generating, by a second LCVCO, a second periodic signal having a second phase based on a resonant frequency of a second LC tank; determining a phase offset between the first LC tank and the second LC tank based on the first and second signals; generating a first output signal and a second output signal based on the determined phase offset; and adjusting the phase offset such that the phase offset is substantially equal to a predetermined phase offset. In one embodiment, the adjusting comprises modulating a first impedance of the first LC tank based on the first output signal, and/or modulating a second impedance of the second LC tank based on the second output signal. | 2012-02-09 |
20120032746 | OSCILLATOR CIRCUIT - An oscillator circuit ( | 2012-02-09 |
20120032747 | MEMS OSCILLATOR - A piezoresistive MEMS oscillator comprises a resonator body, first and second drive electrodes located adjacent the resonator body for providing an actuation signal; and at least a first sense electrode connected to a respective anchor point. The voltages at the electrodes are controlled and/or processed such that the feedthrough AC current from one drive electrode to the sense electrode is at least partially offset by the feedthrough AC current from the other drive electrode to the sense electrode. | 2012-02-09 |
20120032748 | Systems and Methods of Ripple Reduction in a DC/DC Converter - Systems and devices for ripple reduction in a DC/DC converter are presented. The disclosed systems and methods enable ripple reduction in discontinuous conduction mode (DCM) operation. In DCM, the inductor current peak to peak ripple may be reduced based on the load current. To achieve the reduction of the inductor peak to peak current ripple, a digital counter is used to count the time between consecutive PWM pulses. The digital output of the counter is used to control the pulse width modulation. As the digital output of the counter increases, the PWM on-time decreases. Since the PWM pulse is demanded by the load in DCM mode, the peak to peak inductor ripple is modulated by the counter, or, in turn, modulated by the load current. | 2012-02-09 |
20120032749 | DIFFERENTIAL SIGNAL LINE STRUCTURE - A differential signal line structure is disposed on a substrate including a signal layer, a filter layer and a grounding layer. The signal layer, the filter layer and the grounding layer are arranged from up to down and in parallel manner. The differential signal line structure accordingly includes a differential signal line group, a first wire and a first grounding circuit; the differential signal line group is disposed in the signal layer; and the first wire is disposed in the filter layer and is arranged in a corresponding position right underneath the differential signal line group. The first grounding circuit is disposed in the grounding layer and is electrically connected to an end point of the first wire through a first via. | 2012-02-09 |
20120032750 | ANGLED JUNCTION BETWEEN A MICROSTRIP LINE AND A RECTANGULAR WAVEGUIDE - The present invention relates, in the field of high frequency technology, to a transition element for transferring an electromagnetic wave in a strip transmission line into a waveguide. A waveguide with a first opening is thereby applied on a substrate, on which in addition strip transmission line and strip transmission line stub are situated, and contacted and/or coupled to a strip transmission line or to a strip transmission line and a strip transmission line stub. In the first opening, an electrical field then forms a wave in the strip transmission line. | 2012-02-09 |
20120032751 | VARIABLE IMPEDANCE MATCHING CIRCUIT - A variable impedance matching circuit includes a series or parallel connection of a fixed inductive element and a first variable capacitive element and a second variable capacitive element connected in series with the serial or parallel connection. The susceptance of the circuit can be changed by changing the capacitances of the variable capacitive elements. | 2012-02-09 |
20120032752 | VERTICAL QUASI-CPWG TRANSMISSION LINES - In one example embodiment, a coplanar waveguide signal transition element transitions high-speed signals between vertically stacked coplanar waveguide transmission lines. The signal transition element comprises one or more dielectric layers and a plurality of electrically conductive vias extending through at least a portion of the one or more dielectric layers. The vias include one or more signal vias and one or more ground vias that are configured to transition signals between the vertically stacked coplanar waveguide transmission lines. The signal transition element also comprises a ground plane disposed within the one or more dielectric layers and electrically coupled to the one or more ground vias. The ground plane has one or more openings through which the one or more signal vias respectively pass. | 2012-02-09 |
20120032753 | ANTENNA SHARER - An antenna sharer with both low loss and sharp attenuation characteristic in a wide band is achieved. Antennal sharer | 2012-02-09 |
20120032754 | DELAY LINE STRUCTURE - A delay line structure includes a flat spiral delay line and two grounding guard traces. The flat spiral delay line is disposed in the layout layer in a manner of extending from an input end, bending clockwise inward until reaching a U-turn part, continuously extending and bending counterclockwise outward to an out put end so as to form two coupling areas, which are spiral and have an opening respectively. The two grounding guard traces are disposed in the layout layer in a manner of extending from the openings respectively toward the coupling areas, having an interval between the grounding guard traces and the flat spiral delay line, wherein the grounding guard traces close to the openings of the coupling areas are electrically connected to the grounding circuit through a via respectively. | 2012-02-09 |
20120032755 | DELAY LINE STRUCTURE - A delay line structure includes a serpentine delay line, a first grounding guard trace and a second grounding guard trace. The serpentine delay line is disposed in a layout layer of a substrate in a manner of extending from an input end to an out put end in serpentine so as to form at least a first coupling area having a first opening toward a first direction and at least a second coupling area having a second opening toward a direction opposite to the first direction. The first grounding guard trace is disposed in the layout layer in a manner of extending from the first opening toward the first coupling area and an end of the first grounding guard trace close to the first opening is electrically connected to the grounding circuit through a first via. The second grounding guard trace is disposed in the layout layer in a manner of extending from the second opening toward the second coupling area and an end of the second grounding guard trace close to the second opening is electrically connected to the grounding circuit through a second via. | 2012-02-09 |