| 06th week of 2013 patent applcation highlights part 33 |
| Patent application number | Title | Published |
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| 20130034891 | CONVERSION METHOD - A process is described for the preparation of water-soluble cellulose hydrolysis product. The process comprise admixing cellulose with an ionic liquid capable of solvating or dissolving at least some of the cellulose, said ionic liquid being a compound comprises solely of cations and anions and which exists in a liquid state at a temperature at or below 150° C., and in which the anions are selected from halide and cyanate; and treating the resulting solvate or solution with an acid in the presence of water, said acid having a pKa in water of less than 2 at 25° C. | 2013-02-07 |
| 20130034892 | METHOD FOR THE PRODUCTION OF A FERMENTED NATURAL PRODUCT - What is described is a process for producing a fermented natural product, wherein several ferment extracts are produced from raw materials of the natural product and admixed with a propagate from microorganisms. Also described is a plant for performing the process. | 2013-02-07 |
| 20130034893 | Methods for Coupling of Molecules to Metal/Metal Oxide Surfaces - Functionalized magnetic particles are emerging as a reliable and convenient technique in the purification of biomacromolecules (proteins and nucleic acids). We disclose a novel coupling procedure that can be used to create stable ferromagnetic nickel particles coated with Protein A for the affinity purification of antibody. The protein purification procedure is gentle, scalable, automatable, efficient and economical. By modifying the functional groups of amino acids in the protein coating, nickel particles can be used not only for affinity purification but for other sample preparation and chromatographic applications as well including nucleic acid isolations. The method can be easily modified for small and medium scale antibody purification in lab and pre-clinical research. | 2013-02-07 |
| 20130034894 | NOVEL ALLENE OXIDE SYNTHASE DERIVED FROM LEMNA PAUCICOSTATA - A highly active allene oxide synthase that can be used in the production of a plant growth regulating agent (KODA) is provided. | 2013-02-07 |
| 20130034895 | KETOREDUCTASE POLYPEPTIDES FOR THE PRODUCTION OF AZETIDINONE - The present disclosure provides engineered ketoreductase enzymes having improved properties as compared to a naturally occurring wild-type ketoreductase enzyme. Also provided are polynucleotides encoding the engineered ketoreductase enzymes, host cells capable of expressing the engineered ketoreductase enzymes, and methods of using the engineered ketoreductase enzymes to synthesize a variety of chiral compounds. | 2013-02-07 |
| 20130034896 | Purification of Blood Coagulation Factors - The present invention relates to the purification of vitamin K-dependent blood coagulation factors, such as Factor IX (FIX). In particular, the invention provides a method for purifying Factor IX having a desired content of gamma-carboxyglutamic acid from a sample comprising a mixture of species of said Factor IX having different contents of gamma-carboxyglutamic acid, said method comprising the steps of: (a) loading said Factor IX sample onto an immunoaffinity chromatography material coupled to a binding moiety for gamma-carboxyglutamic acid; (b) eluting said Factor IX; and (c) selecting a fraction obtained from said elution wherein the polypeptides in the fraction have the desired content of gamma-carboxyglutamic acids; characterised in that the total concentration of Factor IX within said sample exceeds the binding ability of the immunoaffinity chromatography material. | 2013-02-07 |
| 20130034897 | BACTERIAL HOST CELL FOR THE DIRECT EXPRESSION OF PEPTIDES - Expression systems are disclosed for the direct expression of peptide products into the culture media where genetically engineered host cells are grown. High yield was achieved with a special selection of hosts, and/or fermentation processes which include careful control of cell growth rate, and use of an inducer during growth phase. Special universal cloning vectors are provided for the preparation of expression vectors which include control regions having multiple promoters linked operably with coding regions encoding a signal peptide upstream from a coding region encoding the peptide of interest. Multiple transcription cassettes are also used to increase yield. The production of amidated peptides using the expression systems is also disclosed. | 2013-02-07 |
| 20130034898 | CONTINUOUS CULTURING DEVICE - A continuous device for culturing mammalian cells in a three-dimensional structure for the transplantation or implantation in vivo is described. The culturing device comprises (a) a scaffold formed by a matrix of interconnected growth surfaces spaced at regular intervals and (b) a fluid distribution means at the inlet and the exit of the growth areas. The device is particularly useful for culturing bone cells for dental implants or bone reconstruction. | 2013-02-07 |
| 20130034899 | CELL CULTURING DEVICE USING ELECTRICAL RESPONSIVENESS FUNCTIONAL MATERIAL, CELL CULTURING SYSTEM INCLUDING THE SAME, AND CELL CULTURING METHOD - A cell culturing device includes: an electrode on a surface of which a hydrophilicity/hydrophobicity converting material adapted to be electrically changed between hydrophilicity and hydrophobicity is provided. In this case, the electrode is disposed within a region in which a cell to be cultured is adapted to be accommodated. With the cell culturing device, the application of the suitable voltage to the electrode changes the hydrophilicity/the hydrophobicity of the hydrophilicity/hydrophobicity converting material. Thus, the feed material adsorbed to the hydrophilicity/hydrophobicity converting material is desorbed, thereby making it possible to feed the feed material to the cell. | 2013-02-07 |
| 20130034900 | REPROGRAMMATION OF EUKARYOTIC CELLS WITH ENGINEERED MICROVESICLES - The present invention relates to a non-genetic, detergent-free, bacteria-free method for reprogramming a eukaryotic cell, in particular for obtaining induced pluripotent stem cells (iPS), by using engineered microvesicles carrying at least one reprogramming transcription factor, wherein said engineered microvesicles are virus-free. | 2013-02-07 |
| 20130034901 | Use of a Proteolytic Enzyme for the Modification of the Cell Surface of a Stem Cell - The present invention relates to a stem cell and/or a population thereof having a specific profile of cell surface proteins and/or proteoglycans. The present invention also relates to use of a proteolytic enzyme in the modification of the cell surface of a stem cell. The present invention further relates to a method of modifying the cell surface of a stem cell by treatment with a proteolytic enzyme. | 2013-02-07 |
| 20130034902 | Fusion Polypeptides Capable of Activating Receptors - A fusion polypeptide comprising (A) | 2013-02-07 |
| 20130034903 | METHOD FOR CULTURING NEURAL CELLS USING CULTURE MEDIUM - A method for culturing neural cells using a culture medium is provided. Each neural cell includes a neural cell body and at least one neurite branched from the neural cell body. The culture medium includes a substrate and a carbon nanotube structure located on the substrate. A surface of the carbon nanotube structure is polarized to form a polar surface. The neural cells are cultured on the polar surface to grow neurites along the carbon nanotube wires. The carbon nanotube structure includes a number of carbon nanotube wires spaced apart from each other. A distance between adjacent carbon nanotube wires is greater than or equal to a diameter of the neural cell body. | 2013-02-07 |
| 20130034904 | CULTURE MEDIUM - A culture medium is used for culturing neural cells. Each neural cell includes a neural cell body and at least one neurite branched from the neural cell body. The culture medium includes a substrate and a carbon nanotube structure located on the substrate. The carbon nanotube structure includes a number of carbon nanotube wires spaced apart from each other. A distance between adjacent carbon nanotube wires is greater than or equal to diameters of the neural cell bodies. The carbon nanotube wires are capable of guiding extending directions of the neurites. | 2013-02-07 |
| 20130034905 | METHOD FOR MAKING CULTURE MEDIUM - A method for making a culture medium for culturing neural cells is provided. Each neural cell includes a neural cell body and at least one neurite branched from the neural cell body. The method includes the following steps. An original carbon nanotube structure is provided. The original carbon nanotube structure includes at least one drawn carbon nanotube film including a number of carbon nanotubes joined end to end by van der Waals force. The carbon nanotubes are substantially oriented along a same direction. A carbon nanotube structure including a number of carbon nanotube wires spaced from each other is formed from the original carbon nanotube structure. A distance between adjacent carbon nanotube wires is larger than or equal to a diameter of the neural cell body, the carbon nanotube wires are capable of guiding extending directions of the neurites. The carbon nanotube structure is fixed on a substrate. | 2013-02-07 |
| 20130034906 | METHODS FOR IN VITRO OOCYTE MATURATION - The invention relates to methods for assisted reproduction technology in mammals. Specifically the invention relates to methods for in vitro mammalian oocyte culture and oocyte maturation, in vitro fertilization, and in vitro embryo development. | 2013-02-07 |
| 20130034907 | BIOLOGICAL CIRCUIT CHEMOTACTIC CONVERTERS - Described herein are novel biological circuit chemotactic converter that utilize modular components, such as genetic toggle switches and single invertase memory modules (SIMMs), for detecting and converting external inputs, such as chemoattractants, into outputs that allow for autonomous chemotaxis in cellular systems. Flexibility in these biological circuit chemotactic converter is provided by combining individual modular components, i.e., SIMMs and genetic toggle switches, together. These biological converter switches can be combined in a variety of network topologies to create network systems that regulate chemotactic responses based on the combination and nature of input signals received. | 2013-02-07 |
| 20130034908 | ANALYTICAL DEVICES FOR DETECTION OF LOW-QUALITY PHARMACEUTICALS - An analytical device, in particular, a paper analytical device (PAD), for detection of at least two chemical components indicative of a low quality pharmaceutical product is provided. The analytical device can include a porous, hydrophilic medium, at least two assay regions associated with the porous, hydrophilic medium, at least one assay reagent or precursor thereof in the assay regions, and at least one electronically readable information zone. | 2013-02-07 |
| 20130034909 | DIAGNOSIS METHOD AND DIAGNOSIS APPARATUS FOR OIL-FILLED ELECTRICAL APPARATUS - Provided is a diagnosis method for an oil-filled electrical apparatus, which is for evaluating the degree of danger of copper sulfide being generated within the oil-filled electrical apparatus, comprising: a first step for detecting a specific compound contained within insulating oil inside the oil-filled electrical apparatus; a second step for evaluating the possibility of copper sulfide being generated inside the oil-filled electrical apparatus, on the basis of the result detected by the first step; and a third step for diagnosing the degree of danger of a malfunction occurring in the oil-filled electrical apparatus, on the basis of the evaluation result obtained in the second step. The specific compound contains dibenzyl disulfide and/or a reaction product of a radical resulting from dibenzyl disulfide, and di-tert-butyl-p-cresol and/or a reaction product of a radical resulting from di-tert-butyl-p-cresol, or, di-tert-butyl-phenol and/or a reaction product of a radical resulting from di-tert-butyl-phenol. | 2013-02-07 |
| 20130034910 | DIAGNOSING, PROGNOSING AND MONITORING MULTIPLE SCLEROSIS - The present invention provides a system and method for diagnosing, monitoring or prognosing Multiple Sclerosis at different stages as well as affording the prediction of disease activity and response to a treatment regimen, using at least one sensor comprising carbon nanotubes or metal nanoparticles, each coated with various organic coatings in conjunction with a pattern recognition algorithm. | 2013-02-07 |
| 20130034911 | OZONE CONVERSION SENSORS FOR AN AUTOMOBILE - A system for a vehicle includes a first ozone sensor that generates a first sensor signal indicating a first amount of ozone in air flowing into a radiator. A second ozone sensor generates a second sensor signal indicating a second amount of ozone in air flowing out of the radiator. A control module receives the first sensor signal and the second sensor signal and determines an ozone conversion rate based on the first sensor signal and the second sensor signal. | 2013-02-07 |
| 20130034912 | CENTRIFUGAL FORCE-BASED MICROFLUIDIC DEVICE AVAILABLE FOR RELIABILITY VERIFICATION, AND ANALYZING METHOD USING THE SAME - A centrifugal force-based microfluidic device for a multiplexed analysis and an analyzing method using the same are provided. The microfluidic device includes a platform and a microfluidic structure including a plurality of chambers formed within the platform, and valves positioned between the chambers. The microfluidic structure includes a sample separation chamber connected to a sample injection hole, and a plurality of reaction chambers accommodating two or more types of markers specifically reacting with different types of target materials, separately by type. At least one of the target materials is a standard material, and at least one of the markers is a standard marker specifically reacting with the standard material. | 2013-02-07 |
| 20130034913 | Method for Investigating a Specimen Containing Fluorescing Dyes with the Aid of a Microscope - In order to investigate a specimen ( | 2013-02-07 |
| 20130034914 | FLUORESCENCE-BASED APPROACH TO MONITOR RELEASE FACTOR-CATALYZED TERMINATION OF PROTEIN SYNTHESIS - Provided are probes comprising a class 1 release factor conjugated to a fluorescent label and methods of making the probes. Also provided are methods for detecting conformational changes in ribosomes and associated molecules, such as class 1 release factors. In addition, methods of identifying a compound for reducing nonsense-mediated decay of mRNA and/or for inhibiting termination of protein synthesis at a premature stop codon, are described. Methods of assaying RF3 activity are also included. | 2013-02-07 |
| 20130034915 | Device and method for measuring analytes - The present invention is directed to a system, device and method for measuring the concentration of an analyte in a fluid or matrix. A thermodynamically stabilized analyte binding ligand for use in the system, device and method is disclosed. The thermodynamically stabilized analyte binding ligand is resistant to degradation at physiological temperatures and its use within the device provides a minimally invasive sensor for monitoring the concentration of an analyte in a fluid or matrix as are present in the body of an animal. | 2013-02-07 |
| 20130034916 | FUNCTIONALIZED FLUORESCENT NANOCRYSTAL COMPOSITIONS AND METHODS FOR THEIR PREPARATION - The present invention provides for functionalized fluorescent nanocrystal compositions and methods for making these compositions. The compositions are fluorescent nanocrystals coated with at least one material. The coating material has chemical compounds or ligands with functional groups or moieties with conjugated electrons and moieties for imparting solubility to coated fluorescent nanocrystals in aqueous solutions. The coating material provides for functionalized fluorescent nanocrystal compositions which are water soluble, chemically stable, and emit light with a high quantum yield and/or luminescence efficiency when excited with light. The coating material may also have chemical compounds or ligands with moieties for bonding to target molecules and cells as well as moieties for cross-linking the coating. In the presence of reagents suitable for reacting to form capping layers, the compounds in the coating may form a capping layer on the fluorescent nanocrystal with the coating compounds operably bonded to the capping layer. | 2013-02-07 |
| 20130034917 | METHOD FOR FABRICATING MAGNETIC TUNNEL JUNCTION DEVICE - A method for fabricating a semiconductor device includes forming a plurality of layers which are stacked as a bottom layer, an MTJ layer, and a top layer, patterning the top layer and the MTJ layer using an etch mask pattern to form a top layer pattern and an MTJ pattern, forming a carbon spacer on the sidewalls of the MTJ pattern and the top layer pattern to protect the MTJ pattern and the top layer pattern, and patterning the bottom layer using the carbon spacer and the etch mask pattern as an etch mask to form a bottom layer pattern. | 2013-02-07 |
| 20130034918 | MONITORING APPARATUS AND METHOD FOR IN-SITU MEASUREMENT OF WAFER THICKNESSES FOR MONITORING THE THINNING OF SEMICONDUCTOR WAFERS AND THINNING APPARATUS COMPRISING A WET ETCHING APPARATUS AND A MONITORING APPARATUS - According to the invention, a monitoring device ( | 2013-02-07 |
| 20130034919 | METHOD FOR FABRICATING INTEGRATED ALTERNATING-CURRENT LIGHT-EMITTING-DIODE MODULE - A method for fabricating an integrated AC LED module comprises steps: forming a junction layer on a substrate, and defining a first growth area and a second growth area on the junction layer; respectively growing a Schottky diode and a LED on the first growth area and the second growth area; forming a passivation layer and a metallic layer on the Schottky diode, the LED and the substrate. Thereby, the Schottky diode is electrically connected with the LED via the metallic layer. Thus is promoted the reliability of electric connection of diodes, reduced the layout area of the module, and decreased the fabrication cost. | 2013-02-07 |
| 20130034920 | MANUFACTURING METHOD OF LED PACKAGE STRUCTURE - A method for manufacturing a plurality of holders each being for an LED package structure includes steps: providing a base, pluralities of through holes being defined in the base to divide the base into a plurality of basic units; etching the base to form a dam at an upper surface of each of the basic units of the base; forming a first electrical portion and a second electrical portion on each basic unit of the base, the first electrical portion and the second electrical portion being separated and insulated from each other by the dam; providing a plurality of reflective cups each on a corresponding basic unit of the base, each of the reflective cups surrounding the corresponding dam; and cutting the base into the plurality of basic units along the through holes to form the plurality of holders. | 2013-02-07 |
| 20130034921 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a semiconductor light-emitting device includes forming a multilayer body including a first semiconductor layer having a first major surface and a second major surface which is an opposite side from the first major surface, a second semiconductor layer including a light-emitting layer laminated on the second major surface of the first semiconductor layer, and electrodes formed on the second major surface of the first semiconductor layer and on a surface of the second semiconductor layer on an opposite side from the first semiconductor layer. The method includes forming a groove through the first semiconductor layer. The method includes forming a phosphor layer on the first major surface and on a side surface of the first semiconductor layer in the groove. | 2013-02-07 |
| 20130034922 | VERTICAL CAVITY SURFACE EMITTING LASER, VERTICAL CAVITY SURFACE EMITTING LASER DEVICE, OPTICAL TRANSMISSION DEVICE, AND INFORMATION PROCESSING APPARATUS - A vertical cavity surface emitting laser that includes: a substrate; a first semiconductor multilayer reflector; an active region; a second semiconductor multilayer reflector; a columnar structure formed from the second semiconductor multilayer reflector to the first semiconductor multilayer reflector; a current narrowing layer formed inside of the columnar structure and having a conductive region surrounded by an oxidization region; a first electrode formed at a top of the columnar structure, electrically connected to the second semiconductor multilayer reflector and defining a beam window; a first insulating film comprised of a material with a first refractive index and formed on the first electrode to cover the beam window; and a second insulating film comprised of a material with a second refractive index and formed on the first insulating film, of which a radius is smaller than a radius of the conductive region. | 2013-02-07 |
| 20130034923 | ETCHING COMPOSITION, METHOD OF FORMING A METAL PATTERN USING THE ETCHING COMPOSITION, AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE - An etching composition, a method of forming a metal pattern using the etching composition, and a method of manufacturing a display substrate are disclosed. The etching composition includes about 0.1% by weight to about 25% by weight of ammonium persulfate, about 0.1% by weight to about 25% by weight of an organic acid, about 0.01% by weight to about 5% by weight of a chelating agent, about 0.01% by weight to about 5% by weight of a fluoride compound, about 0.01% by weight to about 5% by weight of a chloride compound, about 0.01% by weight to about 2% by weight of an azole-based compound and a remainder of water. Thus, a copper layer may be stably etched to improve a reliability of manufacturing the metal pattern and the display substrate. | 2013-02-07 |
| 20130034924 | Semiconductor Diodes Fabricated by Aspect Ratio Trapping with Coalesced Films - A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The device further includes a top diode material and an active diode region between the top and bottom diode materials. | 2013-02-07 |
| 20130034925 | RFID BASED THERMAL BUBBLE TYPE ACCELEROMETER AND METHOD OF MANUFACTURING THE SAME - An RFID based thermal bubble type accelerometer includes a flexible substrate, an embedded system on chip (SOC) unit, an RFID antenna formed on the substrate and coupled to a modulation/demodulation module in the SOC unit, a cavity formed on the flexible substrate, and a plurality of sensing assemblies, including a heater and two temperature-sensing elements, disposed along the x-axis direction and suspended over the cavity. The two temperature-sensing elements, serially connected, are separately disposed at two opposite sides and at substantially equal distances from the heater. Two sets of sensing assemblies can be connected in differential Wheatstone bridge. The series-connecting points of the sensing assemblies are coupled to the SOC unit such that an x-axis acceleration can be obtained by a voltage difference between the connecting points. The x-axis acceleration can be sent by the RFID antenna to a reader after it is is modulated and encoded by the modulation/demodulation module. | 2013-02-07 |
| 20130034926 | ASSEMBLY TECHNIQUES FOR SOLAR CELL ARRAYS AND SOLAR CELLS FORMED THEREFROM - An assembly technique for assembling solar cell arrays is provided. During the fabrication of a solar cell, openings through the semiconductor layer are etched through to a top surface of the backmetal layer. The solar cells include an exposed top surface of the backmetal layer. A plurality of solar cells are assembled into a solar cell array where adjacent cells are interconnected in an electrically serial or parallel fashion solely from the top surface of the solar cells. | 2013-02-07 |
| 20130034927 | LIGHT GUIDE ARRAY FOR AN IMAGE SENSOR - An image sensor pixel that includes a photoelectric conversion unit supported by a substrate and an insulator adjacent to the substrate. The pixel includes a cascaded light guide that is located within an opening of the insulator and extends above the insulator such that a portion of the cascaded light guide has an air interface. The air interface improves the internal reflection of the cascaded light guide. The cascaded light guide may include a self-aligned color filter having air-gaps between adjacent color filters. These characteristics of the light guide eliminate the need for a microlens. Additionally, an anti-reflection stack is interposed between the substrate and the light guide to reduce backward reflection from the image sensor. Two pixels of having different color filters may have a difference in the thickness of an anti-reflection film within the anti-reflection stack. | 2013-02-07 |
| 20130034928 | PASTE FOR PREPARING MASK PATTERNS AND MANUFACTURING METHOD OF SOLAR CELL USING THE SAME - Provided are a paste for preparing etching mask patterns and a manufacturing method of a silicon solar cell using the same. The paste composition for preparing mask patterns is used to form a selective emitter of a silicon solar cell, and includes inorganic powder, an organic solvent, a binder resin, and a plasticizer. The mask patterns prepared from the paste composition have good adhesion with a substrate, thereby preventing edge curling, and have good etching resistant characteristic in an etch-back process for forming a selective emitter, enabling formation of a stable emitter. | 2013-02-07 |
| 20130034929 | Method for Forming CMOS Image Sensors - A method includes forming a blocking layer over a substrate, and etching the blocking layer to form a trench in the blocking layer. A dielectric layer is formed, wherein the dielectric layer comprises a first portion over the blocking layer, and a second portion in the trench. After the step of forming the dielectric layer, an implantation is performed to implant an impurity into the substrate to form a deep well region. After the implantation, the dielectric layer and the blocking layer are removed. | 2013-02-07 |
| 20130034930 | APPARATUS FOR MANUFACTURING DYE-SENSITIZED SOLAR CELL, AND METHOD OF MANUFACTURING DYE-SENSITIZED SOLAR CELL - In an apparatus for manufacturing a dye-sensitized solar cell, a photosensitization dye solution makes contact with an electrode material layer that functions as a working electrode of a dye-sensitized solar cell so that the photosensitizing dye is adsorbed on the layer. Such an apparatus for manufacturing a dye-sensitized solar cell has a substrate housing section to house a substrate with the electrode material layer formed on its surface, and a circulation mechanism to circulate the photosensitization dye solution in such a way that the solution passes a surface of the substrate housed in the substrate housing section. In such an apparatus, a cross-sectional area of a flow path for the photosensitization dye solution in a portion facing the substrate in the substrate housing section is set smaller than a cross-sectional area of a flow path for the photosensitization dye solution in other portions. | 2013-02-07 |
| 20130034931 | Gallium arsenide solar cell with germanium/palladium contact - A method of forming a solar cell including: providing a semiconductor body including at least one photoactive junction; forming a semiconductor contact layer composed of GaAs deposited over the semiconductor body; and depositing a metal contact layer including a germanium layer and a palladium layer over the semiconductor contact layer so that the specific contact resistance is less than 5×10 | 2013-02-07 |
| 20130034932 | Thin-Film Devices Formed From Solid Group IIIA Particles - Methods and devices are provided for forming thin-films from solid group IIIA-based particles. In one embodiment of the present invention, a method is described comprising of providing a first material comprising an alloy of a) a group IIIA-based material and b) at least one other material. The material may be included in an amount sufficient so that no liquid phase of the alloy is present within the first material in a temperature range between room temperature and a deposition or pre-deposition temperature higher than room temperature, wherein the group IIIA-based material is otherwise liquid in that temperature range. The other material may be a group IA material. A precursor material may be formulated comprising a) particles of the first material and b) particles containing at least one element from the group consisting of: group IB, IIIA, VIA element, alloys containing any of the foregoing elements, or combinations thereof. The temperature range described above may be between about 20° C. and about 200° C. It should be understood that the alloy may have a higher melting temperature than a melting temperature of the IIIA-based material in elemental form. | 2013-02-07 |
| 20130034933 | Dichalcogenide selenium ink and methods of making and using same - A method for preparing a Group 1a-1b-3a-6a material using a selenium ink comprising a chemical compound having a formula RZ—Se | 2013-02-07 |
| 20130034934 | WAFER LEVEL PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a wafer level package is provided that enables suppressing the wearing of a cutter and extending the lifetime of the cutter, including forming insulating first resin over the top face of a substrate, which includes a groove for wiring to be formed; forming a film of first metal that is to serve as a portion of the wiring on the top face of the first resin using physical vapor deposition; forming a film of second metal that is to form a portion of the wiring on the top face of the first metal, with a lower hardness than the first metal; setting a cutter at a height corresponding to a place where the film of the first metal is not formed on a side face of the groove or the film thickness is low; and cutting at least the first resin by scanning the cutter. | 2013-02-07 |
| 20130034935 | DICING DIE-BONDING FILM - Provide is a dicing die-bonding film that prevents the occurrence of reflow cracking and that is capable of manufacturing a semiconductor device having excellent reliability with good productivity. The dicing die-bonding film of the present invention comprises at least: a dicing film in which a pressure-sensitive adhesive layer is provided on a support base material; and a die-bonding film that is provided on the pressure-sensitive adhesive layer, wherein the dicing die-bonding film has a water absorption rate of 1.5% by weight or less calculated from the following formula (1). | 2013-02-07 |
| 20130034936 | STRUCTURE AND METHOD FOR POWER FIELD EFFECT TRANSISTOR - Methods for fabricating a packaged semiconductor device includes providing a metal plate having a single flat first surface and a parallel second surface. The flat first surface ending in four sawed plate sides. The plate having on the second surface at least one mesa of the same metal and a linear array of insular mesas. The at least one mesa is raised from the second surface. A single terminal of a semiconductor chip is attached to the second plate surface. | 2013-02-07 |
| 20130034937 | Exposed Die Package for Direct Surface Mounting - A method of forming an electronic assembly includes attaching a backside metal layer the bottomside of a semiconductor die. An area of the backside metal layer matches an area of the bottomside of the die. A die pad and leads are encapsulated within the molding material. The leads include an exposed portion that includes a bonding portion. A gap exposes the backside metal layer along a bottom surface of the package. Bond wires couple the pads on the topside of the die to the leads and the bonding portions. Packaged semiconductor device is soldered to a printed circuit board (PCB). The backside metal layer and the bonding portions of the leads are soldered substrate pads on said PCB. | 2013-02-07 |
| 20130034938 | REPLACEMENT GATE ETSOI WITH SHARP JUNCTION - A method includes providing a silicon-on-insulator wafer (e.g., an ETSOI wafer); forming a sacrificial gate structure that overlies a sacrificial insulator layer; forming raised source/drains adjacent to the sacrificial gate structure; depositing a layer that covers the raised source/drains and that surrounds the sacrificial gate structure; and removing the sacrificial gate structure leaving an opening that extends to the sacrificial insulator layer. The method further includes widening the opening so as to expose some of the raised source/drains, removing the sacrificial insulator layer and forming a spacer layer on sidewalls of the opening, the spacer layer covering only an upper portion of the exposed raised source/drains, and depositing a layer of gate dielectric material within the opening. A gate conductor is deposited within the opening. | 2013-02-07 |
| 20130034939 | METHOD OF MANUFACTURING POWER DEVICE - A method of manufacturing a power device includes forming a first drift region on a substrate. A trench is formed by patterning the first drift region. A second drift region is formed by growing n-gallium nitride (GaN) in the trench, and alternately disposing the first drift region and the second drift region. A source electrode contact layer is formed on the second drift region. A source electrode and a gate electrode are formed on the source electrode contact layer. A drain electrode is formed on one side of the substrate which is an opposite side of the first drift region. | 2013-02-07 |
| 20130034940 | Low Threshold Voltage And Inversion Oxide thickness Scaling For A High-K Metal Gate P-Type MOSFET - A method of forming a semiconductor structure. The semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in T | 2013-02-07 |
| 20130034941 | FORMING SIC MOSFETS WITH HIGH CHANNEL MOBILITY BY TREATING THE OXIDE INTERFACE WITH CESIUM IONS - Methods of forming a semiconductor structure include providing an insulation layer on a semiconductor layer and diffusing cesium ions into the insulation layer from a cesium ion source outside the insulation layer. A MOSFET including an insulation layer treated with cesium ions may exhibit increased inversion layer mobility. | 2013-02-07 |
| 20130034942 | HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY EARLY CAP LAYER ADAPTATION - When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material. | 2013-02-07 |
| 20130034943 | Tri-Gate Field-Effect Transistors Formed by Aspect Ration Trapping - Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach | 2013-02-07 |
| 20130034944 | METHOD FOR MAKING A DISILICIDE - Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height. | 2013-02-07 |
| 20130034945 | Nonvolatile Memory Device and Method of Fabricating the Same - Provided is a method of fabricating a nonvolatile memory device. The method of fabricating a nonvolatile memory device, the method comprising: sequentially stacking a first interlayer insulating film, a first sacrificial film, a second interlayer insulating film, and a second sacrificial film on a semiconductor substrate; forming a first penetrating portion, which exposes a region of a top surface of the semiconductor substrate, by etching the first and second interlayer insulating films and the first and second sacrificial films; forming an epitaxial layer on the exposed region of the top surface of the semiconductor substrate in the first penetrating portion by epitaxial growth; forming a first electrode, which contacts a resistance change film and the epitaxial layer, in the first penetrating portion; exposing regions of side surfaces of the epitaxial layer by removing the first epitaxial film; forming an insulating film inside the exposed regions of the side surfaces of the epitaxial layer; and forming a second electrode on the exposed regions of the side surfaces of the epitaxial layer. | 2013-02-07 |
| 20130034946 | Integrating the Formation of I/O and Core MOS Devices with MOS Capacitors and Resistors - An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode. | 2013-02-07 |
| 20130034947 | ATOMIC LAYER DEPOSITION OF METAL OXIDES FOR MEMORY APPLICATIONS - Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent. | 2013-02-07 |
| 20130034948 | Method of Manufacturing a Semiconductor Device - A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer. | 2013-02-07 |
| 20130034949 | METHOD OF FORMING TRENCH ISOLATION - A method of forming trench isolation with different depths of a semiconductor device is disclosed. A semiconductor substrate having a first mask layer formed thereon is first provided. A first etching process is performed with the first mask layer as an etching mask to form a shallow trench structure, followed by forming a first dielectric layer on the semiconductor substrate to fill the shallow trench structure. The first dielectric layer is then patterned to form a second mask layer which is used in a second etching process to form a deep trench structure. After that, a dielectric material is applied to fill the deep trench structure. | 2013-02-07 |
| 20130034950 | METHOD FOR FABRICATING P-TYPE POLYCRYSTALLINE SILICON-GERMANIUM STRUCTURE - A method for fabricating a P-type polycrystalline silicon-germanium structure comprises steps: forming an aluminum layer and an amorphous germanium layer on a P-type monocrystalline silicon substrate in sequence; annealing the P-type monocrystalline silicon substrate, the aluminum layer and the amorphous germanium layer at a temperature of 400-650° C.; and undertaking an aluminum-induced crystallization process in which germanium atoms of the amorphous germanium layer and silicon atoms of the P-type monocrystalline silicon substrate simultaneously pass through the aluminum layer and then the amorphous germanium layer being induced and converted into a P-type polycrystalline silicon-germanium layer between the P-type monocrystalline silicon substrate and the aluminum layer. The present invention is a simple, reliable and low-cost method to fabricate a P-type polycrystalline silicon-germanium layer on a P-type monocrystalline silicon substrate. In addition, the obtained P-type polycrystalline silicon-germanium layer can convert sunlight of longer wavelengths into electric energy. | 2013-02-07 |
| 20130034951 | METHOD OF MANUFACTURING FREE-STANDING GALLIUM NITRIDE SUBSTRATE - A method of manufacturing a free-standing gallium nitride (GaN) substrate, by which a free-standing GaN substrate can be manufactured without warping or cracks. The method includes the steps of collecting polycrystalline GaN powder that is deposited in a reactor or on a susceptor in a process of growing single crystalline GaN, loading the collected polycrystalline GaN powder into a forming mold, preparing a polycrystalline GaN substrate by sintering the loaded polycrystalline GaN powder, and forming a single crystalline GaN layer by growing single crystalline GaN over the polycrystalline GaN substrate. It is possible to reduce warping and cracks that are caused, due to the difference in the coefficient of thermal expansion, during the growth or cooling of single crystalline GaN in the process of manufacturing the free-standing GaN substrate. | 2013-02-07 |
| 20130034952 | TRANSISTOR STRUCTURE HAVING A TRENCH DRAIN - A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength. | 2013-02-07 |
| 20130034953 | CMOS SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising: a gate electrode of the n-type MOSFET having a first insulation layer composed of a high-k material, and a first metal layer provided on the first insulation layer and composed of a metal material; and a gate electrode of the p-type MOSFET having a second insulation layer composed of a high-k material, and a second metal layer provided on the second insulation layer and composed of a metal material, wherein the first insulation layer and the second insulation layer are composed of the different high-k materials, and the first metal layer and the second metal layer are composed of the same metal material. | 2013-02-07 |
| 20130034954 | INTEGRATED CIRCUIT SYSTEM INCLUDING NITRIDE LAYER TECHNOLOGY - An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas. | 2013-02-07 |
| 20130034955 | SEMICONDUCTOR DEVICE - A technique for expanding an effective area in which a semiconductor structure required for a semiconductor device to function is desired. With the semiconductor device | 2013-02-07 |
| 20130034956 | CLEANING RESIDUAL MOLDING COMPOUND ON SOLDER BUMPS - A method of forming wafer-level chip scale packaging solder bumps on a wafer substrate involves cleaning the surface of the solder bumps using a laser to remove any residual molding compound from the surface of the solder bumps after the solder bumps are reflowed and a liquid molding compound is applied and cured. | 2013-02-07 |
| 20130034957 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device may include, but is not limited to, the following processes. A multi-layered structure is prepared over a semiconductor substrate. The multi-layered structure may include, but is not limited to, first and second patterns of a first insulating film, a second insulating film covering the first pattern of the first insulating film, and a first conductive film covering the second pattern of the first insulating film. The second insulating film and the first conductive film are polished under conditions that the first and second insulating films are greater in polishing rate than the first conductive film, to expose the first and second patterns of the first insulating film. | 2013-02-07 |
| 20130034958 | Method of Fabricating an Integrated Device - A method of fabricating an integrated device including a MicroElectroMechanical system (MEMS) and an associated microcircuit is provided. In one embodiment, the method comprises: forming a high temperature contact through a dielectric layer to an underlying element of a microcircuit formed adjacent to a MicroElectroMechanical System (MEMS) structure on a substrate; and depositing a layer of conducting material over the dielectric layer, and patterning the layer of conducting material to form a local interconnect (LI) for the microcircuit overlying and electrically coupled to the contact and a bottom electrode for the adjacent MEMS structure. Other embodiments are also provided. | 2013-02-07 |
| 20130034959 | ELECTROLESS PLATING APPARATUS AND METHOD - An electroless plating apparatus and method designed specifically for plating at least one semiconductor wafer are disclosed. The apparatus comprises a container, a wafer holder, an electrolyte supplying unit, and an ultrasonic-vibration unit. The container is provided with at least an inlet and used for containing electrolyte. The wafer holder is provided within the container. The electrolyte supplying unit is used to supply the electrolyte into the container via the inlet. The ultrasonic-vibration unit consisting of at least one frequency ultrasonic transducer is disposed in the container for producing a uniform flow of electrolyte in the container. Thereby, the wafers can be uniformly plated, especially for wafers with fine via-holes or trench structures. | 2013-02-07 |
| 20130034960 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - The present invention discloses a method of fabricating a semiconductor device. In the present invention, after the formation of a photo-resist mask on a substrate, the photo-resist is subjected to a plasma pre-treatment, and then etch is conducted. With the plasma pre-treatment, a line width roughness of a linear pattern of the photo-resist can be improved, and thus much better linear patterns can be formed on the substrate during the subsequent etching steps. | 2013-02-07 |
| 20130034961 | Plasma Etching Method - A plasma etching method capable of forming a tapering etching structure having a smooth surface is provided. A fluorine-containing gas and a nitrogen gas are used and plasma is generated from these gases simultaneously, and a silicon substrate K is etched by the plasma while an etch-resistant layer is formed on the silicon substrate K by the plasma and then a fluorine-containing gas and an oxygen-containing gas are used and plasma is generated from these gases simultaneously, and the silicon substrate K is etched by the plasma while an etch-resistant layer is formed on the silicon substrate K by the plasma generated from the oxygen-containing gas, thereby forming a tapering etching structure H having a wide top opening width and a narrow bottom width. | 2013-02-07 |
| 20130034962 | Method for Reducing a Minimum Line Width in a Spacer-Defined Double Patterning Process - The invention discloses a method for reducing a minimum line width in a spacer-defined double patterning process of the present invention. In the method, the silicon nitride spacers can be converted into trenches in the interlayer dielectric layer by using a silicon dioxide film as a mask and by means of a chemically mechanical polishing process and an etching process, so that the minimum line width of the trenches can be determined by the width of the silicon nitride spacers, and thus a smaller line width can be achieved and the process can be simple and easy to control. | 2013-02-07 |
| 20130034963 | METHODS OF FORMING FINE PATTERNS FOR SEMICONDUCTOR DEVICE - Methods of forming fine patterns for a semiconductor device include forming a hard mask layer on an etch target layer; forming a carbon containing layer on the hard mask layer; forming carbon containing layer patterns by etching the carbon containing layer; forming spacers covering opposing side walls of each of the carbon containing layer patterns; removing the carbon containing layer patterns; forming hard mask patterns by etching the hard mask layer using the spacers as a first etching mask; and etching the etch target layer by using the hard mask patterns a second etching mask. | 2013-02-07 |
| 20130034964 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The present invention discloses a method of manufacturing a semiconductor device. In order to form a trench with a smaller width, patterns of various monomers are formed by utilizing self-assembly characteristics of a block copolymer comprising various monomers. A metal or metal nitride is deposited on a surface of the block copolymer, the metal or metallic nitride selectively depositing due to a preferential chemical affinity between various monomers and the metal or metal nitride. After reaching a certain thickness, the metal or metal nitride layer begins to grow laterally. Deposition can be stopped by controlling deposition time so that the metal or metal nitride layer grows laterally but does not completely cover the surface of the block copolymer. Etching is then conducted using the metal or metal nitride layer as a mask to obtain a trench with a very small width. | 2013-02-07 |
| 20130034965 | METHODS OF FORMING FINE PATTERNS USING DRY ETCH-BACK PROCESSES - In a method of fabricating patterns in an integrated circuit device, first mask patterns, sacrificial patterns, and second mask patterns are formed on a target layer such that the sacrificial patterns are provided between sidewalls of adjacent ones of the first and second mask patterns. The sacrificial patterns between the sidewalls of the adjacent ones of the first and second mask patterns are selectively removed using a dry etch-back process, and the target layer is patterned using the first and second mask patterns as a mask. | 2013-02-07 |
| 20130034966 | CHEMICAL DISPERSION METHOD AND DEVICE - A method of semiconductor fabrication including providing a semiconductor wafer and dispensing a first chemical spray onto the wafer using a first nozzle and dispensing a second chemical spray using a second nozzle onto the wafer. These dispensing may be performed simultaneously. The method may further include moving the first and second nozzle. The first and second nozzle may provide the first and second chemical spray having at least one different property. For example, different chemical compositions, concentrations, temperatures, angles of dispensing, or flow rate. A chemical dispersion apparatus providing two nozzles which are operable to be separately controlled is also provided. | 2013-02-07 |
| 20130034967 | GASKET WITH POSITIONING FEATURE FOR CLAMPED MONOLITHIC SHOWERHEAD ELECTRODE - An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which is mechanically attached to a backing plate by a series of spaced apart cam locks. A thermally and electrically conductive gasket with projections thereon is compressed between the showerhead electrode and the backing plate at a location three to four inches from the center of the showerhead electrode. A guard ring surrounds the backing plate and is movable to positions at which openings in the guard ring align with openings in the backing plate so that the cam locks can be rotated with a tool to release locking pins extending from the upper face of the electrode. | 2013-02-07 |
| 20130034968 | DRY-ETCH FOR SILICON-AND-CARBON-CONTAINING FILMS - A method of etching exposed silicon-and-carbon-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-and-carbon-containing material. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon-and-carbon-containing material from the exposed silicon-and-carbon-containing material regions while very slowly removing other exposed materials. The silicon-and-carbon-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate. The methods may be used to selectively remove silicon-and-carbon-containing material at more than twenty times the rate of silicon oxide. | 2013-02-07 |
| 20130034969 | Thin Film Deposition Method - The present invention provides a thin film deposition method, comprising: seasoning a first deposition chamber; seasoning a second deposition chamber; pre-processing the first deposition chamber, depositing a thin film in the first deposition chamber, cleaning the first deposition chamber, post-processing and withdrawing the wafers; pre-processing the second deposition chamber, depositing a thin film in the second deposition chamber, cleaning the second deposition chamber, post-processing and withdrawing the wafers; characterized in that there is a time interval between the step of seasoning the second deposition chamber and the step of seasoning the first deposition chamber. The method of stabilizing the thin film thickness of the present invention can well solve the problem that the thin film on the first pair of wafers of each batch of products becomes thinner or thicker during the deposition. In addition, the present invention greatly reduces the influences from human activities without increasing the seasoning wafers, thus realizing automation; moreover, the affected wafers no longer need to be scraped, thus increasing the yield of products. | 2013-02-07 |
| 20130034970 | PLASMA PROCESSING METHOD - A method for forming a fluorocarbon layer using a plasma reaction process includes the step of applying a microwave power and an RF bias. The microwave power and the RF bias are applied under a pressure ranging from 20 mTorr to 60 mTorr. | 2013-02-07 |
| 20130034971 | INTERCONNECTING MECHANISM FOR 3D INTEGRATED CIRCUIT - An interconnecting mechanism is provide, which includes paired first sub-interconnecting mechanisms and paired second sub-interconnecting mechanisms. The first pair of sub-interconnecting mechanisms includes first and second axially symmetrical spiral conductive elements. The second pair of sub-interconnecting mechanisms includes third and fourth axially symmetrical spiral conductive elements. Configuring the pairs of sub-interconnecting mechanisms in a differential transmission structure having a spiral shape is used to avert sounds and noise signals between different chips or substrates caused by a miniaturizing fabrication process or an increased wiring density. | 2013-02-07 |
| 20130034972 | STRADDLE MOUNT CONNECTOR FOR A PLUGGABLE TRANSCEIVER MODULE - A straddle mount connector includes a connector body having a base and a plug. The plug extends a length from the base to an end surface of the plug. The plug has opposite first and second sides and is configured to be received within a receptacle of a receptacle connector. Electrical contacts are held by the connector body and include mating segments arranged in a row that extends along the first side of the plug. The mating segments extend lengths along the first side of the plug from the base to contact tips. The contact tip of a first of the electrical contacts is positioned closer to the end surface of the plug than the contact tip of a second of the electrical contacts such that the mating segment of the first electrical contact mates with a corresponding mating contact before the mating segment of the second electrical contact. | 2013-02-07 |
| 20130034973 | ELECTRONIC DEVICE AND CONNECTION PORT THEREOF - A portable electronic device including a main body and a connection port is provided. The main body has a containing cavity. The connection port includes a supporting component and a connector. The supporting component is slidably disposed at the main body along a sliding direction and slides between an accommodating position and an operation position relative to the main body. The connector is disposed on the supporting component and has a plugging direction. When the supporting component is located at the accommodating position, the connector is contained in the containing cavity and the plugging direction is perpendicular to the sliding direction. When the supporting component is located at the operation position, the connector is located out of the containing cavity, and the supporting component has a tilting angle relative to the main body. | 2013-02-07 |
| 20130034974 | ELECTRIC JUNCTION BOX - An electric junction box for preventing rattle between cassette blocks assembled to each other before being fixed to main body case, includes a first cassette block a second cassette block configured to be assembled to each other by locking structure, an electric distribution member for distributing power to the second cassette block from the first cassette block. The electric distribution member includes an input power source line, and a pair of connectors connected with both ends of the input power source line and engaged with the lower surface of the first cassette block and the lower surface of the second cassette block, respectively. A direction of drawing the input power source line out of each of the pair of connectors is arranged perpendicular to a direction engaging the pair of connectors with the first cassette block and the second cassette block. | 2013-02-07 |
| 20130034975 | CONNECTOR AND STRUCTURE FOR CONNECTING CIRCUIT BOARD AND EXTERNAL CONNECTOR - A structure for connecting a circuit board and an external connector includes a lead and a stress dampening unit. The lead electrically connects the circuit board and the external connector. The external connector is fitted to and removed from the lead. The stress dampening unit dampens stress applied to the circuit board by the lead when the external connector is fitted to and removed from the lead. | 2013-02-07 |
| 20130034976 | CONNECTION STRUCTURE FOR CONNECTING A TERMINAL FITTING AND A CIRCUIT BOARD - A board connecting portion ( | 2013-02-07 |
| 20130034977 | RECEPTACLE CONNECTOR FOR A PLUGGABLE TRANSCEIVER MODULE - A receptacle connector includes a dielectric connector body having a receptacle configured to receive a mating connector therein. Signal and ground contacts are held by the connector body. The signal and ground contacts include mating segments that are arranged within the receptacle of the connector body in a row that extends a length along a row axis. The mating segments of the signal and ground contacts include mating interfaces that extend within the receptacle for mating with corresponding mating contacts of the mating connector. A ground shield extends within the receptacle. The ground shield overlaps the mating segments of the signal and ground contacts within the receptacle along the length of the row of the mating segments. | 2013-02-07 |
| 20130034978 | Crosstalk Reduction - An apparatus includes a backplane having a ground plane. Conductor through holes extend through the backplane in rows and columns for conductors to project through the backplane in orthogonal arrays. Each row and column of the conductor through holes includes ground holes, each of which is sized to receive only a single ground conductor, with the single ground conductor in connection with the ground plane. Each row and column of the conductor through holes also includes signal holes, each of which is sized to receive only a single signal conductor, with the single signal conductor free of a connection with the ground plane. The backplane further has a plurality of nonconductor through holes at locations between and offset from the rows and columns of conductor through holes, with each of the plurality of nonconductor through holes having plating electrically connected to the ground plane. | 2013-02-07 |
| 20130034979 | PORTABLE ELECTRONIC DEVICE AND CONNECTING PORT THEREOF - A portable electronic device including a main body and a connecting port is provided. The main body has an containing cavity. The connecting port includes a base and at least one movable component. The base is disposed at the main body. The movable component is movably connected to the base and moves between an accommodated position and an operation position relatively to the base. When the movable component is located at the accommodated position, the height of the connecting port is less than or equal to the height of the containing cavity such that the connecting port is adapted to be accommodated in the containing cavity. When the movable component is located at the operation position, the height of the connecting port is greater than the height of the containing cavity, and a connector is adapted to be fixed between the base and the movable component. | 2013-02-07 |
| 20130034980 | FIXING DEVICE FOR POWER MODULE - A fixing device for fixing a power module includes a supporting rack, a latching member, and a resilient member connected between the supporting rack and the latching member. The supporting rack includes a base forming a hook engaging in a latching hole defined in the power module. A receiving hole is defined in the base. A protrusion extends down from the base. A slope facing the receiving hole is formed on the protrusion. A resilient tongue extends from the sliding plate. An abutting block extends down from a distal end of the tongue. When disassembling the power module, the latching member is slid relative to the base. The hook is disengaged from the latching hole. The slope abuts against the abutting block. The abutting block moves upward. The tongue is deformed to push up the power module to separate the power module from the supporting rack. | 2013-02-07 |
| 20130034981 | ELECTRONIC DEVICE WITH MEMORY CARD CONNECTOR - An electronic device includes a housing, a card reader, and a cover. The housing includes a slot and two protrusions defined on the inner wall of the housing. The cover includes a body and two connection ends. The body is for covering the slot. The connection ends extend from the body. Each of the two connection ends includes a sliding slot which receives one of the two protrusions respectively to guide the two connection ends to slide. When the cover covers the card which contains a memory card therein, the cover is operable to be pressed to eject the memory card. When the memory card is ejected, it push the body of the cover to cause the two connection ends to slide along the two protrusions to make the body of the cover uncover the slot and rotate to expose the memory card. | 2013-02-07 |
| 20130034982 | PLUG-TYPE CONNECTION FOR TRANSMITTING ELECTRICAL ENERGY - A plug-type connection comprises a housing ( | 2013-02-07 |
| 20130034983 | COAXIAL CABLE CONNECTOR HAVING ELECTRICAL CONTINUITY MEMBER - A coaxial cable connector comprising a connector body; a post engageable with the connector body, wherein the post includes a flange; a nut, axially rotatable with respect to the post and the connector body, the nut having a first end and an opposing second end, wherein the nut includes an internal lip, and wherein a second end portion of the nut corresponds to the portion of the nut extending from the second end of the nut to the side of the lip of the nut facing the first end of the nut at a point nearest the second end of the nut, and a first end portion of the nut corresponds to the portion of the nut extending from the first end of the nut to the same point nearest the second end of the nut of the same side of the lip facing the first end of the nut; and a continuity member disposed within the second end portion of the nut and contacting the post and the nut, so that the continuity member extends electrical grounding continuity through the post and the nut is provided. | 2013-02-07 |
| 20130034984 | LATCH FOR A CARD EDGE CONNECTOR SYSTEM - A latch for securing a circuit card assembly to a circuit board mounted card edge connector includes first and second arms disposed on opposite ends of the card edge connector. The first and second arms define a reception space that receives the circuit card assembly. The first arm has a deflectable spring latch that is movable between a released position and a latched position. The circuit card assembly is secured by the spring latch in the latched position. The second arm has a latch hook that is configured to hook around and engage a portion of the circuit card assembly during mating of the circuit card assembly and the card edge connector. The latch hook defines a pivot point for pivoting the circuit card assembly into the card edge connector during mating of the circuit card assembly and the card edge connector. | 2013-02-07 |
| 20130034985 | CONNECTOR MECHANISM FOR CONNECTING A PLUG - A connector mechanism includes a housing whereon an opening is formed, a socket, and a rotary casing for rotatably covering the opening. The rotary covering includes a main body, a pivoting portion, a stopping portion, and an engaging portion for engaging with an engaging structure of a plug as the plug is inserted into the opening and fastened on the socket so as to fix the plug. The connector mechanism further includes a resilient component for driving the rotary covering to rotate relative to the housing so that the engaging portion engages with the engaging structure of the plug as the plug is fastened on the socket, and a stopping component for stopping the stopping portion of the rotary covering as the resilient component drives the rotary covering to rotate relative to the housing. | 2013-02-07 |
| 20130034986 | ELECTRONIC DEVICE AND METHOD FOR ATTACHING AND DETACHING A CONNECTOR THEREOF - An electronic device is provided. The electronic device includes a connection unit and a connector. The connection unit includes at least one port. The connector includes a connector body and at least one connection element. The connection element is disposed on the connector body and is detachably connected to the port, wherein the connection element is rotated between a first orientation and a second orientation, the connection element is fixed to the port when the connection element is in the second orientation, and the connection element is separated from the port when the connection element is in the first orientation. | 2013-02-07 |
| 20130034987 | Connection Terminal Block - An apparatus for connecting a measuring transducer with a control/evaluation unit, wherein at least one clamping apparatus is placed on a molded part. The clamping apparatus serves for producing a connection between at least one connecting line of the measuring transducer and at least one connecting line of the control/evaluation unit, wherein a soldering tab is provided, which serves for producing a soldered connection between the connecting line of the measuring transducer and the clamping apparatus, and wherein the soldering tab is embodied at least partially in such a manner so as, and serves, to damp possibly occurring vibrations. | 2013-02-07 |
| 20130034988 | ELECTRICAL CONNECTOR FOR FLEXIBLE LED STRIP SEAL - An electrical connector for a flexible LED strip seal comprises a metal body ( | 2013-02-07 |
| 20130034989 | Arrangement of Lamp Socket and Lamp Base - A lamp socket for supporting a light source provided with an LED, the lamp socket including a cooling element; a socket housing which includes socket contacts for electrically connecting the light source; and a lamp base which supports an LED connected to a heat conducting element and is insertable in the socket housing and includes base contacts which are connectable with the socket contacts through a contact force for providing power to the LED, wherein the cooling element on the socket side is connected with the heat conducting element on the base side—optionally through a device that promotes heat transfer, such as heat conducting foil or heat conducting paste—with a contact pressure that promotes heat transfer, wherein the contact pressure provided through a pressing force produced through a suitable device in order for the cooling element to absorb heat generated by the LED during operations, wherein the electric contact between the socket contacts and the base contacts is provided through a contact configuration and/or a contact support that does not provide forces opposite to the pressing force. | 2013-02-07 |
| 20130034990 | Shielded USB Connector Module with Molded Hood and LED Light Pipe - There is provided a system and method for a shielded connector module with a molded hood and an LED light pipe. There is provided a shielded connector module comprising a system-in-package (SiP) device having a surface mounted light emitting diode (LED), a metallic shield surrounding the SiP device, a molded hood surrounding the metallic shield, and an LED light pipe in a proximity with the surface mounted LED, the LED light pipe being directed through the metallic shield and the molded hood. By designing the LED light pipe with a concave surface for surrounding the surface mounted LED and by using various techniques to reduce a gap between the LED and the light pipe, light capture and transmission may be optimized for easily viewable high intensity light. A fresnel lens may be optionally attached to the light pipe for wider viewing angles. | 2013-02-07 |
