06th week of 2013 patent applcation highlights part 23 |
Patent application number | Title | Published |
20130033894 | LUMINOUS VEHICLE GLAZING AND MANUFACTURE THEREOF - A luminous vehicle glazing containing: a first sheet having a first and a second main face; a peripheral light source, the emitting face facing an injection side, which is a side of the second face; a surface diffusion extractor, which extracts the guided light via the first and/or the second main face, or a volume diffusion extractor in the first sheet; a fluid-tight cap, which covers the peripheral light source and is impermeable to liquid water or water vapor, wherein the cap is a facial cap, faces the second face, joined by a fastening element, and associated with an interfacial sealing element. | 2013-02-07 |
20130033895 | Thin Edge-Lit LED Backlight Panel and Light Guide - A backlight sufficiently bright to be useful as a backlight for a high definition LCD television panel, or other types of visual display screens is disclosed. An LED wide enough to provide adequate light energy is used. The light energy is directed into a thin substrate panel via a tapered aperture port, and released toward a viewing surface in a uniform manner due to light guide disrupters calculated to optimize the output pattern. | 2013-02-07 |
20130033896 | ELECTRONIC DEVICE WITH LIGHT BAR - An electronic device includes a frame, a front panel secured to the frame, two light sources secured to the front panel, and a light bar. The frame includes a first sidewall, a second sidewall, and a top wall connected to the first sidewall and the second sidewall. A first supporting portion is located between the first sidewall and the top wall. A second supporting portion is located between the second sidewall and the top wall. The top wall, the first supporting portion, and the second supporting portion cooperatively define an installation hole. A light bar includes a body including a bridge and a light guiding portion located on the bridge. The bridge is located on the supporting portion and the second supporting portion. The light guiding portion is engaged in the installation hole. Two light sources are aligned with two opposite sides of the light guiding portion. | 2013-02-07 |
20130033897 | PLANER LIGHT SOURCE DEVICE AND DISPLAY DEVICE USING THE SAME - A planar light source device includes: a point light source that emits light; a circuit board that has a mounting portion, on which the point light source mounted, and a fixing portion, on which a connector supplying electric power to the point light source is mounted; and a frame that holds the circuit board with the point light source, wherein the circuit board has a protruding portion that protrudes from an end portion of the fixing portion, and wherein the fixing portion of the circuit board is fixed at an inner portion of the frame, and wherein the protruding portion of the circuit board is fixed at an outer portion of the frame, which is opposite to the inner portion of the fixing portion. | 2013-02-07 |
20130033898 | SPREAD ILLUMINATING APPARATUS - A spread illuminating apparatus includes a light source, a flexible printed circuit board, and a light guiding plate. The light guiding plate has a light incident face, and a light output portion planarly outputting light. The light guiding plate has an inclined portion between the light incident face and the light output portion, the inclined portion having an inclined face gradually reducing in thickness from the light incident face toward the light output portion; the flexible printed circuit board is placed on the light guiding plate from the side of the inclined face, and has a mounting portion mounting the light source, and a bent portion bent to the mounting portion and fixed to the inclined face of the inclined portion, and the bent portion includes a thickness reduced portion having a thickness less than the mounting portion. | 2013-02-07 |
20130033899 | REFLECTING BASE MATERIAL, BACKLIGHT UNIT, AND METHOD FOR MANUFACTURING REFLECTING BASE MATERIAL - A reflecting base material that can reliably prevent the occurrence of uneven brightness, a backlight unit that uses the same, and a method for manufacturing the same are provided. Surface profile information of the reflecting base material | 2013-02-07 |
20130033900 | LIGHTING ASSEMBLY WITH CONFIGURABLE ILLUMINATION PROFILE - A lighting assembly includes an edge-lit light guide and a light redirecting member. Light extracting elements at the light guide extract light from the light guide as intermediate light. Light redirecting elements at the light redirecting film are configured to redirect the intermediate light received from the light guide to illuminate a target surface in accordance with a defined illumination profile. | 2013-02-07 |
20130033901 | BACKLIGHT DEVICE AND LIQUID CRYSTAL DISPLAY APPARATUS - A planar light source device includes a first light source for emitting a first light ray having a punctate spatial luminance distribution; a second light source for emitting a second light ray; a first spatial luminance distribution conversion portion for changing the first light ray to a linear spatial luminance distribution; a second spatial luminance distribution conversion portion for changing a spatial luminance distribution of the first and second light rays to a planar spatial luminance distribution; wherein the first light ray is a laser light; the second light ray has a divergence angle larger than the divergence angle of the first light ray when the first light ray is emitted from the first light source; and a slow-axis direction of the first light ray entering the second spatial luminance distribution conversion portion is parallel to an outgoing direction of the planar light. | 2013-02-07 |
20130033902 | SMOOTH MODE TRANSITION PLATEAU FOR A POWER SUPPLY CONTROLLER - A power converter controller is disclosed. An example controller includes a drive signal generator coupled to generate a drive signal to control a switching of a power switch to control a transfer of energy from an input of a power supply to an output of the power supply. A feedback circuit is coupled to receive a feedback signal representative of the output of the power supply. The feedback circuit coupled to generate a control signal in response to the feedback signal. An oscillator circuit is coupled to generate an oscillating signal in response to the control signal. The drive signal generator is coupled to generate the drive signal in response to the oscillating signal. A frequency of the oscillating signal increases from a first frequency to a second frequency with respect to the control signal for a first range of control signal values. The frequency of the oscillating signal remains substantially equal to the second frequency for a second range of control signal values. The frequency of the oscillating signal decreases from the second frequency to a third frequency with respect to the control signal for a third range of control signal values. The first range of control signal values is less than the second range of control signal values and the second range of control signal values is less than the third range of control signal values. | 2013-02-07 |
20130033903 | CURRENT MODE REGULATOR - Disclosed are advances in the arts with novel and useful current mode regulators. Circuits, systems, and methods for current mode regulation include a primary side for receiving an input signal and a secondary for outputting an output signal. A regulator spans the primary and secondary sides in a configuration by which the input signal may be rectified and thereafter provided to the output node as an output signal. A current monitor is provided at the output node for comparing the output signal to a reference. A communication link is included for providing feedback to the primary side of the regulator for use in regulating the signal. | 2013-02-07 |
20130033904 | PHASE-SHIFTED FULL BRIDGE CONVERTER WITH REDUCED CIRCULATING CURRENT - A phase-shifted full bridge converter is provided. The converter includes a transformer having a primary winding and a secondary winding having a center tap, an input stage comprising a full bridge switching circuit coupled to the primary winding, and an output stage coupled to the secondary winding. The output stage includes a circulating current control circuit to provide a portion of output current to reduce output current provided from the secondary winding during a freewheeling time period and reduce the circulating current in the primary winding. | 2013-02-07 |
20130033905 | SYSTEMS AND METHODS FOR FLYBACK POWER CONVERTERS WITH SWITCHING FREQUENCY AND PEAK CURRENT ADJUSTMENTS BASED ON CHANGES IN FEEDBACK SIGNALS - System and method for regulating a power converter. The system includes a first comparator configured to receive a first input signal and a second input signal and generate a first comparison signal based on at least information associated with the first input signal and the second input signal, a pulse-width-modulation generator configured to receive at least the first comparison signal and generate a modulation signal based on at least information associated with the first comparison signal, a driver component configured to receive the modulation signal and output a drive signal to a switch to adjust a primary current flowing through a primary winding of the power converter, and a voltage-change-rate detection component configured to sample the feedback signal to generate a first sampled signal for a first modulation period and to sample the feedback signal to generate a second sampled signal for a second modulation period. | 2013-02-07 |
20130033906 | Apparatus And Method For Providing An Alternating Current - A system for providing, from a direct current (DC) voltage source, an alternating current (AC) to an electrical grid outputting a grid voltage, the system including: a transformer for coupling to the DC voltage source through a first switch controlled by a first control signal, and configured to provide a converted voltage based on a DC voltage; a rectifier coupled to the transformer, and configured to generate an envelope voltage of the converted voltage; a plurality of switches coupled to the rectifier to receive the generated envelope voltage of the converted voltage, the plurality of switches being controlled by a plurality of control signals, respectively, and configured to generate the AC from the generated envelope voltage of the converted voltage; and control apparatus coupled to the first switch and the plurality of switches, and configured to provide, based on the grid voltage, the first control signal and the plurality of control signals. | 2013-02-07 |
20130033907 | ADAPTIVE HARMONIC REDUCTION APPARATUS AND METHODS - Power conversion systems with active front end converters for example motor drives and power generation systems for distributed energy sources are presented with adaptive harmonic minimization for grid-tie converters for minimized or reduced total harmonic distortion in the line current spectrum including the source harmonic current, the load harmonics and the PWM harmonics. | 2013-02-07 |
20130033908 | INVERTER FOR AN ELECTRIC MACHINE AND METHOD FOR OPERATING AN INVERTER FOR AN ELECTRIC MACHINE - An inverter for an electric machine as well as a method for operating an inverter for an electric machine. In this context, the inverter has at least one output stage unit for producing a connection between the electric machine and a power supply network, a control unit for controlling the at least one output stage unit, a supply unit independent of the power supply network for the power supply of the output stage unit(s), at least one emergency operation control assigned to the output stage unit(s) for controlling the output stage unit(s) in the fault case, as well as at least one emergency operation supply assigned to the output stage unit(s) for generating a power supply for the output stage unit(s) from the power supply network in the fault case. | 2013-02-07 |
20130033909 | CIRCIUT AND METHOD FOR PROTECTING A CONTROLLABLE POWER SWITCH - A circuit for protecting a controllable power switch is provided. The controllable power switch has a first power switch terminal connected to a first terminal, a second power switch terminal connected to a second terminal, and a power switch control terminal. Further, the circuit includes a diode with a first diode terminal and a second diode terminal, and a controllable control switch having a first control switch terminal connected to the first diode terminal, a second control switch terminal, and a control switch control terminal. A signal applied to the power switch control terminal is based on a signal at the second control switch terminal. Further a method for protecting a controllable power switch is described. | 2013-02-07 |
20130033910 | Power Converter Circuit - A power converter includes a DC/AC converter with input terminals and output terminals. A DC/DC converter includes input terminals for receiving a DC input voltage and output terminals for providing a DC output voltage. The output terminals are coupled to the input terminals of the DC/AC converter. The DC/DC converter also includes a control circuit that is configured to control an output current of the DC/DC converter dependent on a reference signal. The reference signal has a frequency that is dependent on a frequency of the AC output voltage. | 2013-02-07 |
20130033911 | POWER CONVERTING APPARATUS - A power converting apparatus, includes: switching elements (S | 2013-02-07 |
20130033912 | FIVE-LEVEL DC-AC CONVERTER - A five-level DC-AC converter includes a capacitor set and a full-bridge circuit. The capacitor set contains two DC capacitors, a power electronic switch and two diodes. When the power electronic switch is turned on/off, the two DC capacitors are connected in series/parallel to provide a two-level DC voltage to the full-bridge circuit. The full-bridge circuit further converts the two-level DC voltage to output a voltage with three voltage levels in the positive half cycle and three voltage levels in the negative half cycle. This achieves the goal of using five power electronic switches to convert DC power into AC power with five voltage levels. | 2013-02-07 |
20130033913 | POWER CAPACITOR - A power capacitor, in particular a DC link capacitor, having a capacitor housing which has a first housing wall, in particular made of metal, which is galvanically connectable to a housing of an electronics unit, in particular a power electronics unit, and planar energizing units for energizing the power capacitor. A first subregion of a first energizing unit extends in an inner space of the housing adjacent to and at a distance from the first housing wall or from a different housing wall of the capacitor housing that is conductively connected to the first housing wall. A layer made of a dielectric material other than air is situated between the first subregion of the first energizing unit and this housing wall. | 2013-02-07 |
20130033914 | Power Conversion Device - A power conversion device ( | 2013-02-07 |
20130033915 | CONTENT ADDRESSABLE MEMORIES WITH WIRELINE COMPENSATION - What is disclosed is a novel memory array and process for creating a memory array to reduce wireline variability. The method includes accessing a routing design of a memory array with a plurality of memory cells. Each memory cell in the array includes one or more access devices, and a group of wires electrically connected between one or more of the memory cells and peripheral circuitry (PC). The group of the group of wires is divided into at least one subgroup (N). Next, a capacitance (C | 2013-02-07 |
20130033916 | SEMICONDUCTOR DEVICE HAVING PLURAL CIRCUIT BLOCKS THAT OPERATE THE SAME TIMING - Disclosed herein is a device that includes first and second ports arranged in a first direction and first and second circuits arranged between the first and second ports. The first and second ports are coupled to the first and second circuits, respectively. The first and second circuits include first and second sub circuits that control an operation timing thereof based on a timing signal, respectively. The control signal is transmitted through a control line extending in a second direction. Distances between the control line and the first and second sub circuits in the first direction are the same as each other. A coordinate of the control line in the first direction is different from an intermediate coordinate between coordinates of the first and second ports in the first direction. | 2013-02-07 |
20130033917 | READER FOR MAGNETIC SHIFT REGISTER - A reader for magnetic shift register is provided. The reader includes a magnetic reference layer, a tunneling layer, a magnetic canceling layer and an isolated layer. The magnetic reference layer and the magnetic canceling layer are respectively configured at different sides of a magnetic track for providing anti-parallel magnetic fields. The magnetic reference layer overlaps the magnetic canceling layer in a perpendicular direction of the magnetic track. The magnetic reference layer electrically connects to a readout circuit. The magnetic canceling layer is floating. The tunneling layer is configured between the magnetic reference layer and the magnetic track for providing a magnetic tunnel junction (MTJ). The isolated layer is configured between the magnetic canceling layer and the magnetic track for avoiding a current in the magnetic track from tunneling to the magnetic canceling layer. | 2013-02-07 |
20130033918 | METHOD AND STRUCTURE FOR ULTRA-HIGH DENSITY, HIGH DATA RATE FERROELECTRIC STORAGE DISK TECHNOLOGY USING STABILIZATION BY A SURFACE CONDUCTING LAYER - A electrometric access head includes a supporting substrate and a plurality of read elements mounted on the supporting substrate. Each read element includes an electrometric sensor for detection of a sign of polarization of domains within a ferroelectric data layer of a ferroelectric storage medium. The ferroelectric data layer serves as a layer for storing information as bits defined by the signs of polarization of domains within the ferroelectric data layer, each polarized domain including a volume dipole polarization within the ferroelectric data layer and including an area of bound charge on and adjacent to a surface of the ferroelectric data layer. | 2013-02-07 |
20130033919 | NONVOLATILE MEMORY SYSTEM AND PROGRAM METHOD THEREOF - A nonvolatile memory system and a program method thereof are provided. The nonvolatile memory system includes a nonvolatile memory cell array, an input/output (I/O) control circuit configured to control a program or read operation for the nonvolatile memory cell array; and a controller configured to store an equation representing a resistance-current (R-I) curve for resistance states of memory cells included in the nonvolatile memory cell array, apply an initial program current calculated based on the equation, calculate the equation based in on a resistance of a memory cell subjected to the initial program current, predict a reprogram current based on the equation obtained from the calculation, and control the I/O control circuit. | 2013-02-07 |
20130033920 | IONIC DEVICES CONTAINING A MEMBRANE BETWEEN LAYERS - A device contains a first layer ( | 2013-02-07 |
20130033921 | SEMICONDUCTOR DEVICE - A semiconductor device using resistive random access memory (ReRAM) elements and having improved tamper resistance is provided. The semiconductor device is provided with a unit cell which stores one bit of cell data and a control circuit. The unit cell includes n ReRAM elements (n being an integer of 2 or larger). At least one of the ReRAM elements is an effective element where the cell data is recorded. In reading the cell data, the control circuit at least selects the effective element and reads data recorded thereon as the cell data. | 2013-02-07 |
20130033922 | RESISTIVE-SWITCHING DEVICE CAPABLE OF IMPLEMENTING MULTIARY ADDITION OPERATION AND METHOD FOR MULTIARY ADDITION OPERATION - The present disclosure provides a resistive-switching device capable of implementing multiary addition operation and a method for implementing multiary addition operation using the resistive-switching device. The resistive-switching device has a plurality of resistance values each corresponding to a respective data value stored by the resistive-switching device and ranging from a high resistance value to a low resistance value. The data value stored by the resistive-switching device is increased by ‘1’ successively with a series of set pulses having a same pulse width and a same voltage amplitude being applied thereto. The data value stored by the resistive-switching device is set to ‘0’ with a reset pulse being applied thereto, and meanwhile a data value stored by a higher-bit resistive-switching device is increased by ‘1’ with a set pulse being applied thereto. In this way, multiary addition operation is implemented. The operation of the resistive-switching device can implement data storage and the multiary addition operation simultaneously, and thus substantially simplifies the circuit structure. As a result, the data storage can be integrated with calculation. | 2013-02-07 |
20130033923 | CIRCUIT FOR CONCURRENT READ OPERATION AND METHOD THEREFOR - A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation. | 2013-02-07 |
20130033924 | CODE COVERAGE CIRCUITRY - A circuit includes a memory ( | 2013-02-07 |
20130033925 | Semiconductor Device - An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring, a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode are included. The first transistor is provided over a substrate including a semiconductor material and a second transistor includes an oxide semiconductor layer. | 2013-02-07 |
20130033926 | SEMICONDUCTOR MEMORY DEVICE HAVING BALANCING CAPACITORS - A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers. | 2013-02-07 |
20130033927 | MAGENTIC RESISTANCE MEMORY APPARATUS HAVING MULTI LEVELS AND METHOD OF DRIVING THE SAME - A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first free layer disposed on the tunnel layer having a variable magnetization direction, and a second magnetic device disposed on the first magnetic device including a plurality of free layers insulated with a spacer layer interposed. | 2013-02-07 |
20130033928 | SEMICONDUCTOR STORAGE DEVICE AND DATA PROCESSING METHOD - Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory cell arrays COA and DTA containing a plurality of memory cells MC each having a magnetoresistive element are provided, a series of data is written to the memory cell arrays COA and DTA, and at the time of erasing, an erasing operation is carried out by writing predetermined data only to the memory cell array COA. | 2013-02-07 |
20130033929 | WRITE SCHEME IN A PHASE CHANGE MEMORY - In a phase change memory, an input data corresponding to a plurality of memory cells is received and a previous data is read from the plurality of memory cells. The input data is compared with the previous data. In the case where the input data is different from the previous data for one or more of the plurality of memory cells and a write count is less than a maximum value, one or more of the plurality of memory cells is programmed with the input data and the write count is updated or incremented. Such operations of data comparison and update of the write count are repeated. If the write count reaches the maximum value, it will be determined that the writing is failed. | 2013-02-07 |
20130033930 | SUPPLY VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The output terminal of the first charge pump circuit is connected to a secondary-side charging terminal of the second charge pump circuit. The secondary-side is an output-side of the corresponding charge pump circuit, and the charging terminal is an auxiliary charging terminal that supplies an auxiliary charge to a secondary-side output terminal of the corresponding charge pump circuit. The output terminal of the second charge pump circuit outputs a voltage value that is the result of adding a prescribed voltage value to the value of the first internal supply voltage applied to the charging terminal. | 2013-02-07 |
20130033931 | STORAGE ELEMENT AND STORAGE DEVICE - Provided is a storage element including a storage layer that holds information according to a magnetization state of a magnetic body, a magnetization fixing layer that has magnetization serving as a reference of the information stored in the storage layer, and an insulation layer that is formed of a non-magnetic body disposed between the storage layer and the magnetization fixing layer. The information is stored by reversing the magnetization of the storage layer using spin torque magnetization reversal occurring with a current flowing in a lamination direction of a layer configuration of the storage layer, the insulation layer, and the magnetization fixing layer, and a size of the storage layer is less than a size in which a direction of the magnetization is simultaneously changed. | 2013-02-07 |
20130033932 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a charge storage film and a memory cell transistor. The transistor is provided for each of storage regions configured to store charge in the film. The control unit sets the transistors to an erase threshold by setting erase information in the regions; subsequently sets the transistors to thresholds corresponding to information having n values by programming the information having the n values to at least one of the regions in which the erase information is set; and controls information of at least one storage region before being programmed adjacent to the regions programmed with the information to have a value providing a threshold of the transistor nearer than the erase threshold to the thresholds corresponding to the information having the n values in the state of the transistors provided in the regions being set to the thresholds corresponding to the information having the n values. | 2013-02-07 |
20130033933 | ADJUSTING OPERATIONAL PARAMETERS FOR MEMORY CELLS - Techniques and devices relating to adjusting one or more operational parameters for memory cells are provided. One such device may include a detection unit configured to perform one or more reading operations on a set of memory cells to determine an upper bound of the threshold voltages of the set of memory cells. The device may further include a parameter adjustment unit configured to adjust one or more operational parameters for the set of memory cells based, at least in part, on the determined upper bound of the threshold voltages. Other techniques and devices are also provided. | 2013-02-07 |
20130033934 | Memory Cell Arrangement, Method for Controlling a Memory Cell, Memory Array and Electronic Device - In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well. | 2013-02-07 |
20130033935 | MEMORY DIE SELF-DISABLE IF PROGRAMMABLE ELEMENT IS NOT TRUSTED - Techniques are disclosed herein for automatically self-disabling a memory die in the event that a programmable element on the memory die for indicating whether the memory die is defective cannot be trusted. Memory die are provided with chip enable circuitry to allow particular memory die to be disabled. If the programmable element can be trusted, the state of the programmable element is provided to the chip enable circuitry to enable/disable the memory die based on the state. However, if the programmable element cannot be trusted, then the chip enable circuitry may automatically disable the memory die. This provides a greater yield for multi-chip memory packages because packages having memory die with a programmable element that cannot be trusted can still be used. | 2013-02-07 |
20130033936 | METHODS TO OPERATE A MEMORY CELL - Memory devices and methods for operating a memory cell are disclosed, such as a method that uses two program verify levels (e.g., low program verify level and program verify level) to determine how a data line voltage should be increased. A threshold voltage of a memory cell that has been biased with a programming voltage is determined and its relationship with the two program verify levels is determined. If the threshold voltage is less than the low program verify level, the data line can be biased at a ground voltage (e.g., 0V) for a subsequent programming pulse. If the threshold voltage is greater than the program verify level, the data line can be biased at an inhibit voltage for a subsequent programming pulse. If the threshold voltage is between the two program verify levels, the data line voltage can be increased for each subsequent programming pulse in which the threshold voltage is between the two program verify levels. | 2013-02-07 |
20130033937 | METHODS FOR PROGRAM VERIFYING A MEMORY CELL AND MEMORY DEVICES CONFIGURED TO PERFORM THE SAME - A method for program verify is disclosed, such as one in which a threshold voltage of a memory cell that has been biased with a programming voltage can be determined and its relationship with multiple program verify voltage ranges can be determined. The program verify voltage range in which the threshold voltage is located determines the subsequent bit line voltage. The subsequent bit line voltage may be less than a previous bit line voltage used to program the memory cell. | 2013-02-07 |
20130033938 | NONVOLATLE MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A nonvolatile memory device is programmed by performing a plurality of program loops each comprising applying a program voltage to a selected wordline to change a threshold voltage of a selected memory cell, and applying a verification voltage to the selected wordline to verify a program state of the selected memory cell. In each program loop, the nonvolatile memory device determines a program condition and increments the program voltage by an amount determined according to the program condition. | 2013-02-07 |
20130033939 | FUNCTIONAL DATA PROGRAMMING AND READING IN A MEMORY - Methods for functional programming memory cells and apparatuses are disclosed. One such method for functional programming includes encoding a group of data with a function to generate representative data and programming the representative data to the memory. In one embodiment, the representative data is a pattern of threshold voltages to be programmed to a group of memory cells. | 2013-02-07 |
20130033940 | APPARATUS AND METHODS OF BIT LINE SETUP - Methods and apparatus are disclosed, including an apparatus that has a memory cell array with a memory cell selectively coupled to a bit line. A control circuit is configured to provide a control signal. A voltage generator is configured to provide a sense signal and a precharge signal in response to the control signal. The apparatus further includes a page buffer configured to provide a bit line voltage to the bit line based on the sense signal and the precharge signal, to thereby control a programming of the memory cell. | 2013-02-07 |
20130033941 | Non-Volatile Semiconductor Memory Having Multiple External Power Supplies - A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory. | 2013-02-07 |
20130033942 | SYSTEM-IN PACKAGE INCLUDING SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DETERMINING INPUT/OUTPUT PINS OF SYSTEM-IN PACKAGE - A semiconductor memory device includes an internal clock generation unit configured to generate an internal clock including periodic pulses during a period of a test mode; a DQ information signal generation block configured to generate DQ information signals which are sequentially enabled, in response to the internal clock; and a data output block configured to output the DQ information signals to DQ pads during a period of the test mode. | 2013-02-07 |
20130033943 | DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A data input/output circuit includes: an amplification unit configured to generate a data signal by amplifying data of a first input/output line coupled to a bank during a read operation, and generate a driving signal by amplifying data of a second input/output line coupled to a data input/output pad during a write operation; a read driving unit configured to drive the second input/output line in response to the data signal during the read operation; and a write driving unit configured to drive the first input/output line in response to the driving signal during the write operation. | 2013-02-07 |
20130033944 | INTERNAL VOLTAGE GENERATION CIRCUIT - An internal voltage generation circuit includes: a selection unit configured to select one of first and second reference voltages as a selection reference voltage in response to a self refresh signal and a power-down mode signal and output the selection reference voltage; a driving signal generation unit configured to compare the selection reference voltage with a negative word line voltage applied to an unselected word line and generate a driving signal; and a driving unit configured to change the negative word line voltage in response to the driving signal. | 2013-02-07 |
20130033945 | SYSTEM AND METHOD FOR INTERFACING BURST MODE DEVICES AND PAGE MODE DEVICES - A burst read control circuit acts as an interface to allow a burst-read capable device to execute burst reads from a page-mode capable memory device. The burst read control circuit coordinates burst read requests from the burst-read capable device and subsequent responses from the page-mode capable memory device by accessing subsequent and contiguous memory locations of the page-mode capable memory device. | 2013-02-07 |
20130033946 | FREQUENCY-AGILE STROBE WINDOW GENERATION - The disclosed embodiments relate to components of a memory system that support frequency-agile strobe enable window generation during read accesses. In specific embodiments, this memory system contains a memory controller which includes a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path, wherein the timing signal includes a delay from the read path. In some embodiments, the timing circuit further comprises two calibration loops. The first calibration loop tracks the timing-enable signal with respect to a cycle-dependent delay in the delay, wherein the cycle-dependent delay depends on a frequency of the strobe signal. The second calibration loop tracks the timing-enable signal with respect to a cycle-independent delay in the delay, wherein the cycle-independent delay does not depend on the frequency of the strobe signal. In some embodiments, the first calibration loop and the second calibration loop are cascaded. | 2013-02-07 |
20130033947 | CLOCK GENERATOR - Disclosed herein is a clock generator that comprises a master or first oscillator having an output terminal which provides a master clock signal and at least one slave or second oscillator having an output terminal which provides a slave clock signal, the master and slave oscillators comprising respective time delay stages and latches, the slave oscillator also comprising logic gates connected to the outputs of the latches and configured to logically combine said outputs to generate a slave clock signal having a different phase with respect to a master clock signal. | 2013-02-07 |
20130033948 | DEVICE AND METHOD FOR DETECTING RESISTIVE DEFECT - The invention provides a device and method for detecting a resistive defect in a static random access memory (SRAM) device. A first aspect of the invention provides a static random access memory (SRAM) device comprising: a bitline; a wordline; a bitline precharge circuit electrically connected to the bitline and adapted to provide to the bitline a first precharge voltage for precharging the bitline during normal operation of the SRAM device and a second precharge voltage less than the first precharge voltage for testing the SRAM device for a resistive defect between the bitline and the wordline. | 2013-02-07 |
20130033949 | DATA CONTROL CIRCUIT - The data control circuit includes an input/output line and a driver. The input/output line precharging circuit precharges a global input/output line to a predetermined voltage when either a reading operation or a writing operation is inoperative. The driver includes a number of MOS transistors and drives the global input/output line in response to receiving data from a local input/output line and a complementary local input/output line during the reading operation. | 2013-02-07 |
20130033950 | APPARATUS AND METHOD FOR REFRESHING DRAM - A refresh method for DRAM is provided, in which a memory cell array is arranged to have multiple storing pages. Each storing page has a counter value. The method includes detecting out a portion of the storing pages being no longer used, indicated as a “no-use portion”, and another portion of the storing pages being still in use, indicated as “in-use portion”. Then, only the in-use portion of the storing pages is performed with a refreshing operation. | 2013-02-07 |
20130033951 | STRUCTURE AND METHOD FOR STORING MULTIPLE REPAIR PASS DATA INTO A FUSEBAY - Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended. | 2013-02-07 |
20130033952 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a reference voltage generation unit configured to generate first and second reference voltages, wherein a level of the first reference voltage increases with decreasing internal temperature, and a level of the second reference voltage decreases with decreasing internal temperature; and a level control unit configured to control an internal voltage in response to the first and second reference voltages so as to decrease the absolute value of the internal voltage. | 2013-02-07 |
20130033953 | COMPUTER MOTHERBOARD AND VOLTAGE ADJUSTMENT CIRCUIT THEREOF - A voltage adjustment circuit includes a south bridge, a complex programmable logic device (CPLD), a power supply unit, a voltage conversion unit, and a resistance unit. The south bridge detects a type of a number of dynamic random access memories (DRAMs), and outputs a corresponding signal according to a detected result of the type of the DRAMs. The CPLD is connected to the south bridge to receive the signal, and outputs a corresponding control signal according to the signal. The voltage conversion unit is connected to the power supply unit and the DRAMs, and converts voltage output from the power supply unit into a stable voltage. The resistance unit is connected to the CPLD and the voltage conversion unit, and provides different resistance according to the control signal received from the CPLD, to adjust the voltage output from the voltage conversion unit to an operation voltage of the DRAMs. | 2013-02-07 |
20130033954 | Memory Buffers and Modules Supporting Dynamic Point-to-Point Connections - A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports. | 2013-02-07 |
20130033955 | Processes and apparatus for making concrete and concrete products - A process for making concrete includes treating water with ions and/or ozone to form treated water, and mixing the treated water with aggregate and cement. A system for making concrete includes means for treating charging water with ions, ozone and/or charged particles to form treated water, and means for mixing the treated water with aggregate and cement. | 2013-02-07 |
20130033956 | SCREW FEED ELEMENTS FOR EXTRUDING VISCOELASTIC MASSES - The invention relates to novel screw feed elements for multi-shaft screw feed machines having screw feed profiles rotating in the same direction in pairs and precisely abrading in pairs, to the use of the screw elements in multi-shaft screw feeding machines and to a method for extrusion of viscoelastic masses. | 2013-02-07 |
20130033957 | Stirrer having Programmable Stirring Mode Control - A stirrer having programmable stirring mode control comprises a stirrer main body, an input interface, a controller and a frequency changer. The stirrer main body drives a stirring axle to rotate through a driving mechanism. The controller controls the frequency changer through a vector control circuit so as to control changeable frequency three-phase alternating current voltages or current of a three-phase induction motor. The controller executes stirring steps of multiple set of material items at an automatic mode. Predetermined parameters of the stirring step can be stored after updating, thereby forming the stirrer. | 2013-02-07 |
20130033958 | Machine for the treatment of food mixtures with centralized activation - A machine for the treatment of food mixtures with centralized activation includes a collection container or cylinder for a food mixture, in which a rotating shaft is positioned, wherein, on a sleeve at least partially integral with the rotating shaft, there is a shaped support for both a treatment tool and for scraping and mixing blades of the walls and bottom of the container or cylinder, the shaped support carrying transmissions for the rotation of both the treatment tool and the scraping and mixing blades and the shaped support. | 2013-02-07 |
20130033959 | BLENDER WITH VARYING INTERNALLY AND EXTERNALLY SHAPED CONTAINER - A blender includes a container having a plurality of substantially triangular shaped ribs projecting into a processing zone of the container. The plurality of spaced ribs each include a width and a depth that taper from a top end section adjacent a teardrop shaped opening of the container to a more narrow bottom end section adjacent a bottom wall of the container. A side wall of the container continuously tapers from the teardrop shaped opening to a substantially square shaped bottom end portion including first, second, third and fourth side wall sections connected to one another at respective rounded corners. A blade assembly is coupled to the container and includes a plurality of blades angled at different planes with respect to a horizontal plane. Each of the blades includes a beveled leading edge, resulting in a downward suction force that draws ingredients down into the blade for processing. | 2013-02-07 |
20130033960 | METHOD AND SYSTEM OF A CONTROLLABLE TAIL BUOY - Controllable tail buoy. At least some of the illustrative embodiments are methods including: towing a sensor streamer and tail buoy through water, the sensor streamer defining a proximal end and a distal end with the tail buoy coupled to the distal end, and the towing with the sensor streamer and the tail buoy submerged; and during the towing controlling depth of the distal end of the sensor streamer at least in part by the tail buoy; and steering the distal end of the sensor streamer at least in part by the tail buoy. | 2013-02-07 |
20130033961 | Correcting Time Lapse Seismic Data for Overburden and Recording Effects - Time lapse or 4D seismic data are corrected for geologic overburden and seismic recording system effects. The data from a survey at one time of interest is processed within a selected frequency band and the reservoir level is normalized by the overburden. The results are used to extract reservoir amplitudes from the data of that same survey. Frequencies where overburden signal-to-noise ratios vary dramatically between time lapse surveys may then be avoided in processing of data from the area of interest. | 2013-02-07 |
20130033962 | SEISMIC DATA RECORDING - A seismic survey is conducted by positioning an array of remote acquisition units (RAUs). Each of the RAUs records seismic data derived from one or more geophones in digital form in local memory. The data is collected by a harvester unit traversed across the survey territory as by an aircraft using point-multipoint communications, and subsequently transferred from the harvester unit to a central control unit. | 2013-02-07 |
20130033963 | POSITIONING APPARATUS FOR EXCAVATING AND SIMILAR EQUIPMENT - In the use of a backhoe digger an indication of the precise depth of the bucket is required. This may be done by measuring the angles and extensions of the elements of the backhoe and calculating the result. This is commonly done by means of angle resolvers and linear encoders. Retro-fitting and calibration of such equipment is very difficult, and according to the invention the same data may be obtained by means of an inclinometer and length measuring devices based on pulsed ultrasound. | 2013-02-07 |
20130033964 | METHOD AND DEVICE FOR ACTIVELY DETECTING OBJECTS IN VIEW OF PREVIOUS DETECTION RESULTS - A method for detecting an object within a surrounding area of a vehicle, includes: repeatedly transmitting wave pulses into the surrounding area; repeatedly receiving wave pulses, which correspond to the transmitted wave pulses reflected by the objects; detecting the object with the aid of a signal representation of the received wave pulses, and ascertaining at least one signal characteristic of a first received wave pulse. The detecting of the object includes: comparing the curve in the form of the signal characteristic of the first received wave pulse to the curve of a further received wave pulse, which was received after the first received wave pulse, location information of the object being corrected in light of the comparison. | 2013-02-07 |
20130033965 | Apparatus and Method to Locate and Track a Person in a Room with Audio Information - An apparatus is described that can monitor the sounds and voices of infants and children in a house by judicially placing nodes in key locations of the home. The network has intelligence and uses voice recognition to enable, disable, reroute, or alter the network. The network uses voice recognition to follow a child from node to node, monitors the children according to activity and uses memory to delay the voices so the adult can hear the individual conversations. An adult that has been assigned privilege can disable all nodes from any node in the network. Another apparatus can locate an individual by voice recognition or sounds they emit including walking, breathing and even a heartbeat. The sound is detected at several microphones that have a specific positional relationship to a room or an enclosement. Triangulations of the time differences of the audio signal detected by the microphones are used to determine the location or position of the audio source in the room. This information can be used to provide an improved audio delivery system to the individual. | 2013-02-07 |
20130033966 | METHOD AND APPARATUS FOR INTRA-BODY ULTRASOUND COMMUNICATION - An intra-body ultrasonic signal can be converted into a first electrical signal, a local oscillator signal can be generated in an implantable system. The first electrical signal and the local oscillator signal can be mixed in an implantable system, such as to generate a demodulated signal, processed, such as using a filter. The filtered, demodulated signal can be further processed, such as implantably determining a peak amplitude of the first portion of the demodulated signal received from the filter over a time interval, implantably generating a dynamic tracking threshold that starts at an amplitude proportional the first portion of the demodulated signal and exponentially decays over a time interval, and determining a noise floor in the absence of a received intra-body ultrasonic signal and implantably comparing the peak amplitude and the tracking threshold and generate the digital output based on the difference. | 2013-02-07 |
20130033967 | TRANSDUCER MODULE - The present invention is directed to a transducer module including a first transducer and a second transducer. The second transducer is disposed between the first transducer and a first plate. | 2013-02-07 |
20130033968 | Sparker Array Source - A sparker array includes a plurality of sparker sources of sound and light emissions, the plurality of sparker sources arranged in a geometric pattern with respect to a region, the array configured to deliver a maximal acoustic output to the region. Sparker sources may include reflectors. A single electrical source to drive a sparker array may be employed. A sparker system may include two or more sparker arrays. A time delay may be employed to trigger electrical circuits of the sparker arrays. Sparker arrays may be used to deliver shock waves with increased operational life, consistency and efficacy for specific applications. | 2013-02-07 |
20130033969 | TRANSDUCER AND SYSTEM OF ARRANGEMENT FOR A PANEL ARRAY - A sensor system includes a pressure sensor portion, and an accelerometer. Outputs from the sensor system are handled by a signal processing system that includes a first beamforming module for inputs from a pressure sensor, a second beamforming module for inputs from an accelerometer, and an adaptive beam interpolation module. A method for signal processing signals from both a pressure sensor and an accelerometer. An array of sensors transfers data wirelessly. | 2013-02-07 |
20130033970 | ANALOG ELECTRONIC TIMEPIECE - An analog electronic timepiece includes a plurality of hands; a dial plate having scales for time display; a driving unit that drives the hands so that the hands are driven independently of each other; and a control unit that transmits a drive signal to the driving unit and moves the hands to allow the hands to point to positions set for the respective hands. The control unit (i) allows each hand to point to one of positions of one o'clock to nine o'clock and twelve o'clock among the scales to indicate that a digit in a predetermined place represented by each hand is one of “1” to “9” and “0”; and (ii) expresses a numerical value by a combination of digits corresponding to the respective positions pointed by the respective hands. | 2013-02-07 |
20130033971 | System and Method for Managing and Distributing Audio Recordings - Disclosed are system, methods and computer program products for recording, playing back, responding to and sharing audio recordings. In one example embodiment, the system includes an audio management server that stores and distributes through various third-party websites audio clips, such as voice, music, sounds, and other recordings made by system users. The audio clips can be recorded by system users directly through a central website hosted by the server. Alternatively, the audio clips can be recorded on various third-party websites using audio widgets provided by the audio management server. In addition, the recorded audio clips can be shared on various other third-party websites, such as blogs, social networking sites, celebrity sites and the like, using the audio widget provided by the server. | 2013-02-07 |
20130033972 | THERMALLY-ASSISTED MAGNETIC RECORDING HEAD, HEAD GIMBAL ASSEMBLY AND MAGNETIC RECORDING DEVICE - A thermally-assisted magnetic recording head that includes a pole that generates a writing magnetic field, a waveguide through which light propagates, a plasmon generator that surface-evanescent-couples with the light propagating through the waveguide, wherein the plasmon generator includes a portion where a cross-sectional area gradually decreases as going toward a depth side from an air bearing surface when being observed from a cross section parallel to the air bearing surface. The volume of the plasmon generator can be decreased and an exposed area of a front surface on the air bearing surface can be increased. When a thermal expansion from the temperature increase occurs in the plasmon generator, a rate that the plasmon generator projects from the air bearing surface is suppressed to extremely low levels. Accordingly, a chronological degradation of output can be suppressed and thermally-assisted recording having a high and long-term reliability is achieved. | 2013-02-07 |
20130033973 | OPTICAL RECORDING MEDIUM, RECORDING/REPRODUCING APPARATUS, RECORDING/REPRODUCING METHOD - Provided is an optical recording medium, including a recording target track that is a track on which small record carriers are arranged and on which information recording is performed by modulating the small record carriers through light irradiation; and a wobbling track on which the small record carriers are arranged in a wobbling manner, wherein a single wobbling track is formed to run parallel to a set of a plurality of recording target tracks. | 2013-02-07 |
20130033974 | SERVO CONTROL DEVICE, OPTICAL DISK DEVICE, AND DATA TRANSFER METHOD - A servo control device includes: a phase compensator configured to generate a plurality of types of control values for controlling a driver based on a signal output from an optical pickup, and output the control values; and a transfer data generator configured to serially transfer the control values to the driver. The phase compensator sends, to the transfer data generator, a notification that the phase compensator has output a control value which needs to be sent with a reduced delay among the control values. In response to the notification, the transfer data generator determines whether or not the transfer data generator is transferring one of the control values, and if the transfer data generator is not transferring one of the control values, the transfer data generator starts transferring a control value associated with the notification among the control values. | 2013-02-07 |
20130033975 | REVERSIBLE RECORDING MEDIUM BASED ON OPTICAL STORAGE OF INFORMATION, METHOD OF REVERSIBLE RECORDING ON SUCH A MEDIUM - A reversible recording medium based on optical storage of at least one item of information within a support material, includes at least one layer of support material having: base molecules able to take, in a local zone, a first collective state of molecules able to generate a first signal of second harmonic characteristic of this first collective state of molecules when excited by electromagnetic reading radiation; the base molecules having the first collective state of molecules able to transform, at least in part, into transformed molecules so as to pass to a second collective state of molecules when excited by electromagnetic writing radiation, the molecules having the second collective state of molecules able to generate a second signal of second harmonic characteristic of this second collective state of molecules when excited by the electromagnetic reading radiation. The molecules exhibit a molecular structure based on a coumarin skeleton of Formula (I). | 2013-02-07 |
20130033976 | STRUCTURE AND METHOD FOR GENERATING AN OPTICAL IMAGE FROM AN ULTRASONIC HOLOGRAPHIC PATTERN - An acoustic hologram imaging system constructed from a machined housing having folded optics. Various surfaces of the housing are machined to provide a precise alignment to the optical members to be connected thereto, such as a mirror, a lens assembly, a light emitting laser diode, a camera, and the like. A three-part lens is described having different materials with different indexes of refraction in order to provide a desired focus of the light. In addition, an optical spatial filter is disclosed in which, according to various embodiments, all, some, or none of the light passing therethrough is attenuated for recording of the optical image of the hologram. | 2013-02-07 |
20130033977 | CODEBOOK GENERATION SYSTEM AND ASSOCIATED METHODS - A codebook generation system and associated methods are generally described herein. | 2013-02-07 |
20130033978 | Source Alive Route Injection - Multiple redundant sources for a datastream can be established in a network, where the redundant sources are configured with the same source address. One of the redundant sources provides the datastream to a receiver of a multicast group. If the redundant source fails, another redundant source can be used in its place, ensuring the receiver continues to receive the datastream. A routing element coupled to a redundant source monitors the redundant source for failure and informs the rest of the network of the status of the coupled redundant source. The routing element can inform other routing elements of the status by advertising or withdrawing a route that reaches the coupled redundant source, which the other routing elements can use to update their routing tables. | 2013-02-07 |
20130033979 | MOBILE TERMINAL APPARATUS, RADIO BASE STATION APPARATUS AND RADIO COMMUNICATION METHOD - Provided are a mobile terminal apparatus, a radio base station apparatus and a radiocommunication method, capable of saving PHICH resources enough and realizing effective retransmission control of uplink SU-MIMO. The radio communication method of the present invention is characterized in that a radio base station apparatus receives signals of plural codewords, when there is an error in each of the codewords, generates a one-bit negative response physical HARQ indicator channel signal and transmits the physical HARQ indicator channel signal, and a mobile terminal apparatus receives the physical HARQ indicator channel signal and transmits retransmission signals of all the codewords to the radio base station apparatus based on the negative response physical HARQ indicator channel signal. | 2013-02-07 |
20130033980 | COMMUNICATIONS SYSTEM PROVIDING ENHANCED CHANNEL SWITCHING FEATURES BASED UPON MODULATION FIDELITY AND RELATED METHODS - A wireless communications system includes a base station, and a communications device configured to communicate with the base station via different wireless communications channels using a modulation standard wherein a received modulation differs from a transmitted modulation (e.g., due to environmental conditions) as measured by a modulation fidelity value. The base station and the communications device are configured to cooperate to determine respective modulation fidelity values associated with a current channel and an alternate channel based upon an estimated modulation fidelity calculated from the received modulation, and to selectively switch between the current channel and the alternate channel based upon the determined modulation fidelity values. | 2013-02-07 |
20130033981 | METHOD AND SYSTEM FOR DISTRIBUTING NETWORK TRAFFIC AMONG MULTIPLE DIRECT HARDWARE ACCESS DATAPATHS - A system for distributing network traffic among direct hardware access datapaths, comprising: a processor; one or more activated PNICs; a host operating system; and a virtual machine (VM). Each activated PNIC sends and receives data packets over a network. Each activated PNIC is configured with a virtual function. The VM includes a VNIC and a virtual link aggregator configured to maintain a list identifying each activated PNIC. Virtual function mappings for the VM associate the VM with virtual functions for the activated PNICs. The virtual link aggregator selects the first activated PNIC for servicing a network connection and determines a virtual function for the first activated PNIC. The VNIC for the first activated PNIC uses the virtual function to directly transfer network traffic for the network connection between the VM and the first activated PNIC. | 2013-02-07 |
20130033982 | Bulk Data Transport in a Network - A network is configured to utilize available bandwidth to conduct bulk data transfers without substantially affecting the successful transmission of time-sensitive traffic in the network. In order to avoid this interference, the packets carrying data for bulk data transfers are associated with a low priority class such that the routers of the network will preferentially drop these packets over packets associated with the normal traffic of the network. As such, when the normal traffic peaks or there are link or equipment failures, the normal traffic is preferentially transmitted over the bulk-transfer traffic and thus the bulk-transfer traffic dynamically adapts to changes in the available bandwidth of the network. Further, to reduce the impact of dropped packets for the bulk-transfer traffic, the packets are encoded at or near the source component using a loss-resistant transport protocol so that the dropped packets can be reproduced at a downstream link. | 2013-02-07 |
20130033983 | Access Category Enforcement in Wireless Local Area Networks - The present invention provides a control function in an access point, switch, or like node on a wireless local area network. The control function operates to ensure frames transmitted by a user terminal are transmitted using an appropriate transmission priority scheme. The control function will assist and provide an appropriate priority level to the user terminal. Frames transmitted from the user terminal are passed through the control function, which will analyze priority level information provided in the frames to determine if the frames were transmitted using the appropriate transmission priority scheme. An enforcement action may be taken in response to identifying frames that were not transmitted using the appropriate transmission priority scheme. | 2013-02-07 |
20130033984 | SYSTEM AND METHOD FOR REMOTELY CONTROLLING NETWORK OPERATORS - A system and method for controlling communications networks. Network performance information is gathered from a first communications network using performance information packet data packets. A network operator of the first communications network is controlled from a secondary communications network using the performance information packet data packets. Changes to the network operator are implemented based on instructions included in the performance information packet data packets. | 2013-02-07 |
20130033985 | TRANSMISSION DEVICE, TRANSMISSION METHOD AND COMPUTER PROGRAM - Flow control can be performed for every piece of end-to-end traffic. A transmission device includes a reception buffer which temporarily accumulates received transmission unit data, a signal generation section configured to generate a control signal for instructing to stop transmission of transmission unit data by designating another transmission device serving as an end point of a transmission side for traffic of the transmission unit data to be received by its own device as a transmission destination when an amount of accumulation in the reception buffer has exceeded a predetermined upper-limit threshold value, and a transmission section configured to transmit the control signal. | 2013-02-07 |
20130033986 | Quality of Service Control in Multiple Hop Wireless Communication Environments - One or more relay stations may be employed along a wireless communication access path between an ingress station and an egress station. A logical communication tunnel is established between the ingress and egress stations through any number of intermediate relay stations to handle session flows of PDUs. As PDUs arrive, the ingress station may determine and add scheduling information to the PDUs before they are delivered to the downstream intermediate relay stations or egress stations. The scheduling information is used by the downstream stations to schedule the PDUs for further delivery. The scheduling information may also be used by the egress station to schedule the PDUs for delivery. The scheduling information added to the PDU by the ingress station bears on a QoS class associated with the PDU, a deadline for the egress station to deliver the PDU, or a combination thereof. | 2013-02-07 |
20130033987 | METHOD FOR ENABLING THE EFFICIENT OPERATION OF ARBITRARILY INTERCONNECTED MESH NETWORKS - Wireless mesh networks (or “meshes”) are enabled for arbitrary interconnection to each other and may provide varying levels of coverage and redundancy as desired. Interoperability between meshes having differing configurations, internal operations, or both, may be freely intermixed and inter-operated in unrestricted combination. Enhanced explicit inter-bridge control protocols operate using pre-existing control packets. Pre-existing broadcast packet floods are used to learn the best paths across interconnected meshes (termed a “multi-mesh”). Enhanced routing protocols operating within each mesh may optionally examine information limited to the respective mesh when forwarding traffic, thus enabling robust multi-mesh scaling with respect to memory and processing time required by the routing protocols. Communication scalability is improved by enabling frequency diversity across the multi-mesh by configuring meshes within interference range of each other for operation at a plurality of frequencies. Each mesh may operate at a respective non-interfering frequency. | 2013-02-07 |
20130033988 | ESTIMATING MULTIMEDIA DATA PACKET BUFFERING TIME STREAMED OVER A SELECTED WIRELESS NETWORK - A computer-implemented method for estimating buffering time of multimedia data packets for efficient playout of multimedia applications by a mobile device is provided. A wireless network with highest quality of service is selected from a plurality of wireless networks based on recorded information related to multimedia calls placed by the mobile device over the plurality of wireless networks. A multimedia call is placed over the selected wireless network for the mobile device and one or more conditions related to the selected wireless network and the mobile device is monitored. Information related to the one or more conditions of the selected wireless network and the mobile device are gathered. Based on the gathered information, buffering time of multimedia data packets is estimated. Before playout, multimedia data packets that are received by the mobile device are buffered for a predetermined time period corresponding to the estimated buffering time. | 2013-02-07 |
20130033989 | ENHANCED DOWNLINK RATE ADAPTATION FOR LTE HETEROGENEOUS NETWORK BASE STATIONS - Downlink rate adaptation in wireless communication systems are disclosed in which a UE reports RIs for both interference-free and interference-limited subframes. In general, the RI for the interference-free subframes will be higher than the RI reported for the interference-limited subframes. However, an eNB selects an RI and a transmission rate for interference-limited subframes based on what the UE can sustain instead of based only on the RI reported by the UE. | 2013-02-07 |
20130033990 | SYSTEMS, METHODS AND APPARATUS FOR WIRELESS CONDITION BASED MULTIPLE RADIO ACCESS BEARER COMMUNICATIONS - Systems, devices, and methods for wireless condition based multi radio access based wireless communication are provided. In one aspect, a device configured to communicate via a wireless communication link is provided. The device includes a controller configured to send a request for network resources for packet data transmission. The controller may be configured to suppress the request for network resources based in part on a condition of the wireless communication link and a type of wireless communication that is being transmitted by the device. | 2013-02-07 |
20130033991 | METHOD AND SYSTEM FOR RADIO LINK FAILURE INFORMATION PROCESSING - Disclosed in the present invention are a method and system for processing radio link failure information. In the above method, a network device managing a cell notifies the peer of the RLF information processing ability of the network device for the peer to carry out RLF information processing according to the RLF information processing ability, wherein the RLF information processing ability comprises: whether or not each cell managed by the network device supports RLF reporting information processing. By way of the technical solution provided by the present invention, not only meaningless waste of resources of the terminal is avoided, but also the network side is avoided to carry out meaningless processing and forwarding after receiving the RLF information, thus reducing the overhead of air interface signaling resources, and reducing the memory and power consumption waste for the terminal and network element to carry out RLF information processing. | 2013-02-07 |
20130033992 | RADIO BASE STATION APPARATUS AND SCHEDULING METHOD - The present invention provides a radio base station apparatus and a scheduling method that can improve user throughput performance in an adaptive AF-type relay transmission method. The scheduling method according to the present invention includes the steps of receiving a signal including a reference signal, measuring an instantaneous channel gain by path loss and fading, among a mobile terminal apparatus, a radio relay station apparatus and a radio base station apparatus, with respect to an uplink, using the reference signal; and performing downlink resource allocation based on the instantaneous channel gain by path loss and fading. | 2013-02-07 |
20130033993 | Distributed Overlay Network Data Traffic Management by a Virtual Server - An approach is provided in which a data traffic module executing on a network interface card receives a data packet initiated by a first virtual machine with a destination at a second virtual machine. The data traffic module identifies one or more physical path translations corresponding to a logical connectivity that is independent of physical topology constraints of a physical network. In turn, the data traffic module encapsulates the data packet with the one or more physical path translations and sends the encapsulated data packet to the second virtual machine over the physical network. | 2013-02-07 |