06th week of 2009 patent applcation highlights part 63 |
Patent application number | Title | Published |
20090037675 | Archival and Retrieval of Data Using Linked Pages and Value Compression - A method for archiving data comprises storing static information in a header compartment, the static information including one or more pointers. The method further comprises writing updated time stamps to a page compartment for one or more measurand updates, and writing, to a page compartment, a pointer to a data compartment entry. The method further comprises writing measurand data to a data compartment entry. | 2009-02-05 |
20090037676 | DYNAMIC TIMER CONFIGURATION FOR MONITORING A LONG BUSY STATE IN A REMOTE MIRROR AND COPY ENVIRONMENT - A system is disclosed that includes a host system to issue a write command, a primary storage controller to write data to a primary volume, and a secondary storage controller to mirror the data to a secondary volume. In the event the secondary storage controller is unable to mirror the data due to a busy state, a busy signal may be sent to the primary storage controller. The primary storage controller may initiate a timer in the event it receives the busy signal, and, in the event the busy state does not end before expiration of the timer, notify the host system that the primary and secondary volumes are in a suspended state. To alter the duration of the timer, the host system may be configured to dynamically alter the duration of the timer by sending a command to the primary storage controller. | 2009-02-05 |
20090037677 | DYNAMIC TIMER CONFIGURATION FOR TASK MONITORING IN A REMOTE MIRROR AND COPY ENVIRONMENT - A system is disclosed that includes a host system to issue a write command, a primary storage device to write data to a primary volume, and a secondary storage device to mirror the data to a secondary volume. A task timer may be initiated upon sending the data from the primary storage device to the secondary storage device. The secondary storage device may also send an acknowledge signal to the primary storage device in the event it successfully mirrors the data to the secondary volume. In the event the acknowledge signal is not received before the timer expires, the primary storage device may notify the host system that the primary and secondary volumes are in a suspended state. To alter the duration of the timer, the host system may be further configured to dynamically alter the duration of the timer by sending a command to the primary storage device. | 2009-02-05 |
20090037678 | PROTECTED PORTION OF PARTITION MEMORY FOR COMPUTER CODE - A system comprises a plurality of computing nodes and a plurality of separate memory devices. A separate memory device is associated with each computing node. The separate memory devices are configured as partition memory in which memory accesses are interleaved across multiple of such memory devices. A protected portion of the partition memory is reserved for use by complex management (CM) code that coordinates partitions implemented on the system. The protected portion of partition memory is restricted from access by operating systems running in the partitions. | 2009-02-05 |
20090037679 | DATA MIGRATION WITHOUT INTERRUPTING HOST ACCESS - A system includes a source storage device, a target storage device, a host coupled to the source storage device and the target storage device, and a first migration device coupled to the source storage device and the target storage device. The first migration device includes a first virtual storage device. The first migration device is configured to migrate data from the source storage device to the target storage device, and the first virtual storage device is configured to receive write access requests for the data from the host during the data migration and send the access request to the source storage device and target storage device. | 2009-02-05 |
20090037680 | ONLINE VIRTUAL MACHINE DISK MIGRATION - A method for migrating a virtual machine disk (VM disk) from first physical storage to second physical storage while the virtual machine (VM) is running, the method comprising: (a) taking a snapshot of the VM disk as represented by a first parent VM disk stored on the first physical storage, whereby a first child VM disk is created on one of the first or second physical storage; (b) copying the first parent VM disk to the second physical storage as a second parent VM disk; (c) re-parenting the first VM child disk to the second parent VM disk; and (d) consolidating the first child VM disk and the second parent VM disk. | 2009-02-05 |
20090037681 | Computer-readable storage medium in which storage-management program is recorded, storage-management apparatus, and storage-management method - A storage-management apparatus and method that manages storage areas. The storage-management apparatus includes a collecting unit that collects valid-area-determination information items, each of which shows whether a corresponding one of the storage areas is a valid or invalid area, and timestamp information items, each of which shows that a corresponding one of the storage areas has been accessed. In accordance with the valid-area-determination information items and the timestamp information items, data from a storage area which is selected from among valid areas and whose timestamp information item is oldest is copied to a storage area which is selected from among invalid areas and whose timestamp information item is oldest, and timestamp information items and valid-area-determination information items concerning the storage area from which the data is copied and concerning the storage area to which the data is copied is updated. | 2009-02-05 |
20090037682 | HYPERVISOR-ENFORCED ISOLATION OF ENTITIES WITHIN A SINGLE LOGICAL PARTITION'S VIRTUAL ADDRESS SPACE - Access control to shared virtual address space within a single logical partition is provided. The access control includes: associating, by a hypervisor of the data processing system, a memory protection key with a portion of a single logical partition's virtual address space being shared by multiple entities, the key preventing access by one of the multiple entities to that portion of the virtual address space, and allowing access by another of the entities to that portion of the virtual address space; and locking by the hypervisor the memory protection key from modification by the one entity, wherein the locking prevents the one entity from modifying the key and thereby gaining access to the portion of the single logical partition's virtual address space with the associated memory protection key. In one embodiment, the one entity is the single logical partition itself, and the another entity is a partition adjunct. | 2009-02-05 |
20090037683 | Semiconductor Memory Arrangement - A semiconductor memory arrangement includes a substrate, a first control device disposed on the substrate and adapted to receive command and address signals, a second control device, and a plurality of memory units. The second control device is adapted to receive the command and address signals from the first control device and to transmit the command and address signals to the memory units of the plurality of memory units. | 2009-02-05 |
20090037684 | MEMORY MANAGEMENT METHOD AND COMPUTER USING THE METHOD - Memory management by garbage collection involves a memory area that is allocated in a computer. Data is created in the memory area in accordance with a program executed by a processor of the computer, and it is checked whether or not data necessary to execute the program exists in the memory area to be released, in response to an explicit instruction to release the memory area. As a result of the check, if data necessary to execute the program does not exist in the memory area, the memory area is released. As a result of the check, if data necessary to execute the program exists in the memory area, the data is moved to a memory area different from the memory area to be released. | 2009-02-05 |
20090037685 | FAIR MEMORY RESOURCE CONTROL FOR MAPPED MEMORY - A method system and computer program product for managing memory allocation among plural virtual application environments supported by a common operating system. The technique may include establishing a mapping between a virtual application environment (or processes therein) and a mapping proxy that is reachable via a reverse mapping pathway adapted to facilitate identification of virtual addresses associated with a memory page frame. The virtual application environment (or processes therein) may be identified as an allocation recipient of the memory page frame by traversing the reversing mapping pathway to the mapping proxy. The memory page frame may be reclaimed for allocation to another virtual application environment by invalidating data therein or transferring the data to a storage resource based upon memory usage by the identified virtual application environment. | 2009-02-05 |
20090037686 | Application inspection tool for determining a security partition - An embodiment of the invention provides an apparatus and method for determining a security partition in a computer for an application. The apparatus and method can determine required system resources, security requirements, and partition rules for an application, can determine allocated system resources, security characteristics, and partitions rules for each security partition in the computer, and can identify at least one proposed security partition for the application. | 2009-02-05 |
20090037687 | PARTITION-BASED METHOD AND APPARATUS FOR DIAGNOSING MEMORY LEAK IN JAVA SYSTEMS - A partition-based method for diagnosing memory leaks in Java systems, comprising dividing heap memory of a Java virtual machine into a plurality of partitions based on a partition plan, wherein each partition has at least one partition owner; monitoring the status of the respective partitions to determine whether there is a partition in which the memory space is exhausted; and if there is a partition in which the memory space is exhausted, determining that the memory leak may occur in the partition and analyzing the partition to obtain leaked objects and objects related to the leaked objects. The present invention also provides a partition-based apparatus for diagnosing memory leak in Java systems. | 2009-02-05 |
20090037688 | Communicating between Partitions in a Statically Partitioned Multiprocessing System - In one embodiment, a method comprises assigning a unique node number to each of a first plurality of nodes in a first partition of a system and a second plurality of nodes in a second partition of the system. A first memory address space spans first memory included in the first partition and a second memory address space spans second memory included in the second partition. The first memory address space and the second memory address space are generally logically distinct. The method further comprises programming a first address map in the first partition to map the first memory address space to node numbers, wherein the programming comprises mapping a first memory address range within the first memory address space to a first node number assigned to a first node of the second plurality of nodes in the second partition, whereby the first memory address range is mapped to the second partition. | 2009-02-05 |
20090037689 | Optimal Use of Buffer Space by a Storage Controller Which Writes Retrieved Data Directly to a Memory - A storage controller which uses the same buffer to store data elements retrieved from different secondary storage units. In an embodiment, the controller retrieves location descriptors ahead of when data is available for storing in a target memory. Each location descriptor indicates the memory locations at which data received from a secondary storage is to be stored. Only a subset of the location descriptors may be retrieved and stored ahead when processing each request. Due to such retrieval and storing of limited number of location descriptors, the size of a buffer used by the storage controller may be reduced. Due to retrieval of the location descriptors ahead, unneeded buffering of the data elements within the storage controller is avoided, reducing the latency in writing the data into the main memory, thus improving performance. | 2009-02-05 |
20090037690 | Dynamic Pointer Disambiguation - Dynamic pointer analysis techniques are able to produce faster pointer dependency test code and analyze more complex code in high-level languages such as in the programming languages C and C++ (not excluding other languages), as compared to known techniques. | 2009-02-05 |
20090037691 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS - The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. | 2009-02-05 |
20090037692 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS - The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. | 2009-02-05 |
20090037693 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS - The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. | 2009-02-05 |
20090037694 | Load Misaligned Vector with Permute and Mask Insert - Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be maximized while processing bandwidth required to store vector data misaligned is minimized. Furthermore, embodiments of the invention provide logic within the load data path which allows vector data which is stored misaligned to be aligned as it is loaded into a vector register. By aligning misaligned vector data as it is loaded into a vector register, memory bandwidth may be maximized while processing bandwidth required to align misaligned vector data may be minimized. | 2009-02-05 |
20090037695 | DATA FETCH CIRCUIT AND METHOD THEREOF - A data fetch circuit and a method thereof are provided. A multi-phase clock signal is generated according to an input clock, and an input data is over-sampled according to the multi-phase clock signal in order to detect transition points of the input data. One of reference phases of the multi-phase clock signal is selected according to the detected transition point for fetching the input data and obtaining enough setup/hold time margin. Accordingly, appropriate data fetch points is found without complicated negative feed-back mechanism. Besides, a periodical monitoring mechanism may be further adopted for improving the accuracy of data fetch. | 2009-02-05 |
20090037696 | PROCESSOR - A processor ( | 2009-02-05 |
20090037697 | SYSTEM AND METHOD OF LOAD-STORE FORWARDING - A system and method for data forwarding from a store instruction to a load instruction during out-of-order execution, when the load instruction address matches against multiple older uncommitted store addresses or if the forwarding fails during the first pass due to any other reason. In a first pass, the youngest store instruction in program order of all store instructions older than a load instruction is found and an indication to the store buffer entry holding information of the youngest store instruction is recorded. In a second pass, the recorded indication is used to index the store buffer and the store bypass data is forwarded to the load instruction. Simultaneously, it is verified if no new store, younger than the previously identified store and older than the load has not been issued due to out-of-order execution. | 2009-02-05 |
20090037698 | ADAPTIVE ALLOCATION OF RESERVATION STATION ENTRIES TO AN INSTRUCTION SET WITH VARIABLE OPERANDS IN A MICROPROCESSOR - A method and device for adaptively allocating reservation station entries to an instruction set with variable operands in a microprocessor. The device includes logic for determining free reservation station queue positions in a reservation station. The device allocates an issue queue to an instruction and writes the instruction into the issue queue as an issue queue entry. The device reads an operand corresponding to the instruction from a general purpose register and writes the operand into a reservation station using one of the free reservations station positions as a write address. The device writes each reservation station queue position corresponding to said instruction into said issue queue entry. When the instruction is ready for issue to an execution unit, the device reads out the instruction from the issue queue entry the reservation station queue positions to the execution unit. | 2009-02-05 |
20090037699 | APPARATUS AND METHOD FOR PROCESSING SEMICONDUCTOR - A semiconductor processing apparatus includes a tester for inspecting a semiconductor device, a display unit | 2009-02-05 |
20090037700 | Method and system for reactively assigning computational threads of control between processors - A method and system for reactively assigning computational threads of control between processors provide a coordination model implemented by a software framework. The coordination model comprises five (5) entities which implement the three elements of a coordination model: 1) Behavior, 2) Data, 3) Container, 4) Source and 5) Processor. The invention decomposes an application into a cooperative collection of distributed and networked Behaviors, which are subsequently executed by Containers. A designer using this invention implements a Behavior for each logical stage of execution, which represents the core service-processing logic for that stage. | 2009-02-05 |
20090037701 | Method of Updating Electronic Operationg Instructions of a Vehicle and an Operating Instructions Updating System - A method and system for updating electronic operating instructions of a vehicle is provided. Local operating instruction data objects are stored in a local storage device arranged in the vehicle so that they can be used by the driver. Corresponding current operating instruction data objects are stored in an external storage device. One data object category, respectively, is assigned to the operating instruction data objects. For updating, a current operating instruction data object is transmitted from the external storage device to the local storage device in order to modify the corresponding local operating instruction data object in the local storage device The frequency of the updating of a local operating instruction data object depends on the data object category assigned to the data object. | 2009-02-05 |
20090037702 | Processor and data load method using the same - A processor includes an instruction decoder, an instruction execution part and a register file. The instruction decoder is adapted to decode an instruction. The instruction execution part is adapted to execute processing corresponding to the instruction decoded by the instruction decoder. The register file is capable of storing load data from a data memory and supplying input data to the instruction execution part. The register file includes a plurality of registers, each of which is capable of holding a plurality of bits of data. Furthermore, the register file is configured to update the data held by the plurality of registers by shifting the data held by the plurality of registers among the plurality of registers. | 2009-02-05 |
20090037703 | CONDITIONAL DATA WATCHPOINT MANAGEMENT - A method, system and computer program product for managing a conditional data watchpoint in a set of instructions being traced is shown in accordance with illustrative embodiments. In one particular embodiment, the method comprises initializing a conditional data watchpoint and determining the watchpoint has been encountered. Upon that determination, examining a current instruction context associated with the encountered watchpoint prior to completion of the current instruction execution, further determining a first action responsive to a positive context examination; otherwise, determining a second action. | 2009-02-05 |
20090037704 | TRACE CONTROL FROM HARDWARE AND SOFTWARE - A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core. | 2009-02-05 |
20090037705 | Method and Device for Processing Data Words and/or Instructions - A method for processing data words and/or instructions, a distinction being made, in the processing, between at least two operating modes, and a first operating mode corresponding to a compare mode and a second operating mode corresponding to a performance mode, in the compare mode, a comparator unit being activated and this comparator unit being deactivated in the performance mode, wherein the comparator unit is activated for the compare mode as a function of two equal data words and/or instructions getting to be processed and the at least equal data words and/or instructions in each case being distributed by a control unit to the at least two execution units. | 2009-02-05 |
20090037706 | Processor Lock - A data processing system has an embedded processor and a system memory. The embedded processor has access to a specific one of multiple sets of instructions pre-stored in the system memory, only if a control code valid for the specific set is supplied from a source external to the system. | 2009-02-05 |
20090037707 | Determining When a Set of Compute Nodes Participating in a Barrier Operation on a Parallel Computer are Ready to Exit the Barrier Operation - Methods, apparatus, and products are disclosed for determining when a set of compute nodes participating in a barrier operation on a parallel computer are ready to exit the barrier operation that includes, for each compute node in the set: initializing a barrier counter with no counter underflow interrupt; configuring, upon entering the barrier operation, the barrier counter with a value in dependence upon a number of compute nodes in the set; broadcasting, by a DMA engine on the compute node to each of the other compute nodes upon entering the barrier operation, a barrier control packet; receiving, by the DMA engine from each of the other compute nodes, a barrier control packet; modifying, by the DMA engine, the value for the barrier counter in dependence upon each of the received barrier control packets; exiting the barrier operation if the value for the barrier counter matches the exit value. | 2009-02-05 |
20090037708 | TARGET BRANCH PREDICTION USING CORRELATION OF LOCAL TARGET HISTORIES - A system for predicting multiple targets for a single branch includes: a branch target buffer that includes a previous next address for an instruction and that receives an indirect instruction address to provide a first branch target prediction; a first branch table for capturing local past target information of an indirect branch in an encoded form; a second branch table which is a correlation table for storing potential branch targets based on a local branch history and which provides a second branch target prediction when the first branch target prediction is not successful; an exclusion predictor for inhibiting updates of inefficient entries; and a multiplexer to select the predicted target as output. | 2009-02-05 |
20090037709 | BRANCH PREDICTION DEVICE, HYBRID BRANCH PREDICTION DEVICE, PROCESSOR, BRANCH PREDICTION METHOD, AND BRANCH PREDICTION CONTROL PROGRAM - A branch prediction device capable of preventing degradation of branch prediction accuracy and a delay in processing speed is provided. The branch prediction device includes a branch prediction information accumulation processing section which stores branch prediction groups in which a plurality of pieces of branch prediction information are grouped, and performs accumulation-processing of the branch prediction information. The branch prediction device further includes a pipeline access control section which performs processing, upon request, by pipeline processing, including first selection control processing for selection-controlling at least one branch prediction group from the branch prediction groups, and second selection control processing for selection-controlling one or a plurality of pieces of branch prediction information from the branch prediction group, and controls an access to the branch prediction information accumulation processing section. | 2009-02-05 |
20090037710 | RECOVERY FROM NESTED KERNEL MODE EXCEPTIONS - A system and method for instrumentation of software, the software comprising a set of instructions (program or code) which are executable on a processor of a system, for example a computer system. A location in the instruction to insert a probe is first identified. The instruction is replaced with the probe by copying the instruction to a predefined location. The instruction is executed in the kernel space. A first exception is generated upon encountering the probe and calling a first exception handler, and the first exception handler is configured to call an instrumentation routine. A second exception is generated when the instrumentation routine encounters an error and calling a second exception handler, recovering from the exceptions and returning to a sane state to continue normal execution of the instruction. | 2009-02-05 |
20090037711 | Option-Based Reverse Configuration System - A configurator is provided with the ability to enable a customer to configure a system based upon selection of components to reside within the system. Based upon selected components, the customer is presented with systems in which the selected components can reside. | 2009-02-05 |
20090037712 | Systems and Methods for Process and User Driven Dynamic Voltage and Frequency Scaling - Certain embodiments of the present invention provide a method for power management including determining at least one of an operating frequency and an operating voltage for a processor and configuring the processor based on the determined at least one of the operating frequency and the operating voltage. The operating frequency is determined based at least in part on direct user input. The operating voltage is determined based at least in part on an individual profile for processor. | 2009-02-05 |
20090037713 | OPERATION, ADMINISTRATION AND MAINTENANCE (OAM) FOR CHAINS OF SERVICES - In one embodiment, a method can include: selecting an operation, administration, and maintenance (OAM) type for a destination, where the destination is enabled for a service insertion architecture (SIA); encapsulating an OAM packet with the OAM type indicated in a service header therein; and sending the OAM packet to the destination. | 2009-02-05 |
20090037714 | COMPONENT CONFIGURATION UTILIZING VAGUE SPECIFICATIONS - A computer implemented method, data processing system, and a computer program product configures components in a data processing system. A request for a vaguely specified component for implementation into a data processing system is received. Responsive to receiving the request, at least one corresponding component is identified. The corresponding component is then displayed to a user for implementation of the corresponding component. | 2009-02-05 |
20090037715 | Fingerprint reader resetting system and method - A fingerprint reader resetting method comprising enabling an electronic device to accept a reset command for a fingerprint reader in response to a physical presence state being set to unlocked during initialization of an electronic device to reset a state of the fingerprint reader. | 2009-02-05 |
20090037716 | Image forming apparatus and processing method of revising basic settings - When a setting input through a control portion falls within the first setup range, the settings in the first setup storage are rewritten with the setting in the second setup storage. Since the setting was revised, the revision history including the setup content and the data of the setting is stored in a revision history storage. Next, a determination process for the revised setting is carried out. Specifically, it is determined whether a usually expected input setting from the control portion falls within the second setup range. When it does not fall within the second setup range, the controller determines that the input setting is not a proper value, and reads out the setting before revision, stored in the third setup storage to rewrite the settings in the first setup storage with it. | 2009-02-05 |
20090037717 | FIRMWARE RETRIEVAL ACROSS A NETWORK - A system comprises a processor and non-volatile storage coupled to the processor. The non-volatile storage comprises firmware that is executable by the processor. The processor determines whether the firmware is available to be executed. If the firmware is not available to be executed, the processor determines a location across a network and retrieves a second firmware image from that location. | 2009-02-05 |
20090037718 | BOOTING SOFTWARE PARTITION WITH NETWORK FILE SYSTEM - In a software partition (SWPAR) environment, a method, system and computer program product enables a SWPAR to be remotely booted, independent of the booting of the OS on the global system environment, using network file system (NFS) services and protocols. A request to mount a NFS, hosted by an external server into a SWPAR environment is transmitted. The NFS services are automatically transitioning to a first operating state that enables support for user-level NFS services without requiring the NFS services be active. The SWPAR is automatically booted and access to the SWPAR provided during operation of the NFS services in the first operating state. Once the SWPAR has completed booting, the NFS services is transitioned back to a normal operating state in which SWPAR operates as a standalone device providing its own user-level NFS services. | 2009-02-05 |
20090037719 | Enabling a heterogeneous blade environment - In one embodiment, the present invention includes a method for receiving a request for power-up of a first blade of a chassis, enabling the first blade to power-up in a reduced boot mode and receiving a communication including characteristic information and policy information associated with the first blade, and analyzing the characteristic information and the policy information to determine a policy and a boot configuration for the first blade. Other embodiments are described and claimed. | 2009-02-05 |
20090037720 | Hard Disk Security Method in a Computer System - This invention presented a hard disk security method in a computer system, which provides a hard disk security mechanism combining with the power-on password function for the storage data in a hard disk by restoring the partition table into the BIOS ROM in advance, and deleting the partition table of the hard disk to secure the hard disk. | 2009-02-05 |
20090037721 | PROGRAM DEVELOPMENT METHOD, PROGRAM DEVELOPMENT SUPPORTING SYSTEM, AND PROGRAM INSTALLATION METHOD - An development environment of a high security level is provided for a key-installed system. Development of a program for a system having an LSI device which includes a secure memory is performed by providing another LSI device having the same structure and setting the provided LSI device to a development mode which is different from a product operation mode. Alternatively, the provided LSI device is set to an administrator mode to perform development and encryption of a key-generation program. The LSI device is set to a key-generation mode to execute the encrypted key-generation program, thereby generating various keys. | 2009-02-05 |
20090037722 | Integration Model for Instant-On Environment - An instant-on environment consists of components residing in a computer boot ROM and/or also on a mass storage device. Main components to the instant-on environment include a loader, EPG1, and EPG2. The loader is a module that is integrated into the computer boot ROM, based on an embedded OS, that functions to load other instant-on environment components. There are various methods of integrating the loader into boot firmware to optimize for different requirements. EPG1 is a first user screen that appears on the computer display within seconds after power-on, and from which the user can choose to launch one of the instant-on environment's applications or launch the primary OS. EPG2 is launched if the user chooses to launch an instant-on environment application. EPG2 is a Linux-based desktop environment that the user enters once he selects an application from EPG1. | 2009-02-05 |
20090037723 | Method for the Autonomic Configuration of a Data Storage Device - A method is disclosed for configuring a data storage device. A storage module stores configuration data on a remote storage system that may include operating systems, applications, updates, and an index. A boot module boots a computer system from a program other than the regular boot program to provide access to a network in communication with the remote storage system. A device configuration module autonomically downloads and installs the operating systems, applications, and updates in response to data stored in an index on the remote storage system. | 2009-02-05 |
20090037724 | Server method and system for rendering content on a wireless device - A server implemented method for processing data for a wireless device. The server in response to a user request executes an application program for generating content for rendering on the wireless device where the content is wireless device generic. A first screen description based on the content and a device profile of the wireless device is generated. The device profile may describe a rendering capability of the wireless device. The first screen may be in a syntax generic format independent of the wireless device type and describe relative screen location and display object size information independent of screen dimensions. The first screen is translated into a second screen description that includes discrete low level rendering commands within the rendering capability of the wireless device that is syntax generic. Low level rendering commands include physical screen positions of display elements. The translated second screen is then transmitted to the wireless device. | 2009-02-05 |
20090037725 | CLIENT-SERVER OPAQUE TOKEN PASSING APPARATUS AND METHOD - In the computer client-server context, typically used in the Internet for communicating between a central server and user computers (clients), a method is provided for token passing which enhances security for client-server communications. The token passing is opaque, that is tokens as generated by the client and server are different and can be generated only by one or the other but can be verified by the other. This approach allows the server to remain stateless, since all state information is maintained at the client side. This operates to authenticate the client to the server and vice versa to defeat hacking attacks, that is, penetrations intended to obtain confidential information. The token as passed includes encrypted values including encrypted random numbers generated separately by the client and server, and authentication values based on the random numbers and other verification data generated using cryptographic techniques. | 2009-02-05 |
20090037726 | SECURE VERIFICATION USING A SET-TOP-BOX CHIP - One or more methods and systems of authenticating or verifying a set-top-box chip in a set-top-box are presented. In one embodiment, a set-top-box incorporates a set-top-box chip used to decode or decrypt media content provided by a cable television operator or carrier. The set-top-box chip incorporates a decryption circuitry, a compare circuitry, a hash function circuitry, a key generation circuitry, a back channel return circuitry, a linear feedback shift register, a timer reset circuitry, a modify enable status circuitry, a one time programmable memory, and a non-volatile memory. The cable TV carrier validates a set-top-box chip used in a set-top-box by way of a verification sequence that requires a successful verification by the set-top-box chip. | 2009-02-05 |
20090037727 | METHOD AND APPARATUS FOR SECURELY EXCHANGING CRYPTOGRAPHIC IDENTITIES THROUGH A MUTUALLY TRUSTED INTERMEDIARY - A method of securely exchanging cryptographic identities through a mutually trusted intermediary is disclosed. Data, which specifies a petitioner's cryptographic identity and a petitioner's resource identifier, is received. Input, which specifies an authority's resource identifier, is received. The petitioner's cryptographic identity and the petitioner's resource identifier are sent to a destination that is associated with the authority's resource identifier. Data, which specifies the authority's cryptographic identity, is received. The authority's cryptographic identity is sent to a destination that is associated with the petitioner's resource identifier. | 2009-02-05 |
20090037728 | Authentication System, CE Device, Mobile Terminal, Key Certificate Issuing Station, And Key Certificate Acquisition Method - Provided is an authentication system for improving user-friendliness. An IC card ( | 2009-02-05 |
20090037729 | AUTHENTICATION FACTORS WITH PUBLIC-KEY INFRASTRUCTURE - A user access control system comprising a workstation coupled to a computer network and operable to receive a request for an authenticated access to the computer network, and to prompt for and receive one or more credentials associated with the request, a gating authentication server coupled to the computer network and operable to receive the one or more credentials and to provide as a gating factor an authenticated credential, and a public key infrastructure server coupled to the computer network and operable to generate private/public key pairs associated with the authenticated credential, wherein the private/public key pairs are either generated after a request for access to the computer system has been received at the workstation and the gating authentication server has authenticated the one or more credentials provided through the workstation, or the private/public key pairs are retrieved from a previously generated virtual smart card based on the authentication credential. | 2009-02-05 |
20090037730 | Device For Protection of the Data and Executable Codes of a Computer System - A security and protection device ( | 2009-02-05 |
20090037731 | Architecture and Design for Central Authentication and Authorization in an On-Demand Utility Environment Using a Secured Global Hashtable - A Centralized Authentication & Authorization (CAA) system that prevents unauthorized access to client data using a secure global hashtable residing in the application server in a web services environment. CAA comprises a Service Request Filter (SRF) and Security Program (SP). The SRF intercepts service requests, extracts the service client's identifier from a digital certificate attached to the request, and stores the identifier in memory accessible to service providers. The client identifier is secured by the SP using a key unique to the client identifier. When the web services manager requests the client identifier, the web services manager must present the key to the SP in order to access the client identifier. Thus, the present invention prevents a malicious user from attempting to obtain sensitive data within the application server once the malicious user has gained access past the firewall. | 2009-02-05 |
20090037732 | TETHERED DEVICE SYSTEMS AND METHODS - Systems and methods are described for applying digital rights management techniques to tethered devices. In one embodiment, a host device is operable to translate a relatively sophisticated license into a simpler format for use on a relatively low-capability device. In another embodiment, a method of using extended SCSI commands to communicate over a USB connection is provided. | 2009-02-05 |
20090037733 | Method for Recording and Distributing Digital Data and Related Device - The invention relates to a method for burning digital data onto a blank disk by a client device, the digital data being transmitted to the client device by a remote content server. The method comprises the following steps carried out by the client device: setting up a secure authenticated channel with the content server; receiving the digital data transmitted by the content server; verifying the existence of the secure authenticated channel and authorizing the burning of the digital data received only during the existence of the secure authenticated channel; and burning onto the blank disk the digital data received. The invention also relates to a client device and a method for distributing digital data. | 2009-02-05 |
20090037734 | DEVICE AUTHENTICATION SYSTEM, MOBILE TERMINAL DEVICE, INFORMATION DEVICE, DEVICE AUTHENTICATING SERVER, AND DEVICE AUTHENTICATING METHOD - According to a device authentication system ( | 2009-02-05 |
20090037735 | METHOD AND SYSTEM FOR DELIVERING SECURE MESSAGES TO A COMPUTER DESKTOP - A system and method for delivering a secure message to the desktop of a computer for a user. The system comprises polling a server to determine if any messages are waiting for the user. The polling includes providing and authenticating security credentials associated with the user. If a message is waiting on the server, a notification is generated on the computer of the user. A portion of the message may be delivered to the desktop as part of the notification. The message is encrypted with a public-private key pair associated with the user and delivered to the desktop of the computer. The communication link between the computer and the server may comprise a secure channel. | 2009-02-05 |
20090037736 | System and Method for Establishing a Secure Group of Entities in a Computer Network - This invention relates to a system and method for establishing a secure group of entities in a computer network, such as those originating from different trust domains, for the purpose of protecting the activity being executed. The invention allows for the on-demand automated creation of a virtual security perimeter around an arbitrary group of services originating from different trust domains. The security perimeter allows the activity being executed within the group to be protected, and for inter-group messages and communication to be kept confidential. A shared security context is also provided by which the group can be regulated, and new entities can be invited to join the group. The preferred embodiment of the invention has application to service orientated architectures and preferably makes use of existing technologies, such as W3C web services and security protocols, and OASIS service co-ordination protocols. | 2009-02-05 |
20090037737 | ASYNCHRONOUS ENHANCED SHARED SECRET PROVISIONING PROTOCOL - An Asynchronous Enhanced Shared Secret Provisioning Protocol (ESSPP) provides a novel method and system for adding devices to a network in a secure manner. A registration process is launched by at least one of two network devices together. These two devices then automatically register with each other. When two devices running Asynchronous ESSPP detect each other, they exchange identities and establish a key that can later be used by the devices to mutually authenticate each other and generate session encryption keys. An out-of-band examination of registration signatures generated at the two devices can be performed to help ensure that there was not a man-in-the-middle attacker involved in the key exchange. | 2009-02-05 |
20090037738 | Digital certificates - A method for producing a certificate, the certificate including data, the method including choosing a seed s, the seed s including a result of applying a function H to the data, generating a key pair (E,D), such that E=F(s,t), F being a publicly known function, and including s and t in the certificate. Related methods, and certificates produced by the various methods, are also described. | 2009-02-05 |
20090037739 | METHOD FOR IDENTIFYING A COUNTERFEIT SECURITY DOCUMENT - A method of determining a counterfeit security document which includes a number of coded data portions indicative of an identity of the security document; and at least part of a digital signature of at least part of the identity. The method includes using a sensing device to sense at least one coded data portion and generate indicating data. The indicating data is used by a processor to obtain a determined identity and at least one determined signature part, which are then used to determine if the security document is a counterfeit document. | 2009-02-05 |
20090037740 | Optimization methods for the insertion, protection, and detection of digital watermarks in digital data - Disclosed herein are methods and systems for encoding digital watermarks into content signals. Also disclosed are systems and methods for detecting and/or verifying digital watermarks in content signals. According to one embodiment, a system for encoding of digital watermark information includes: a window identifier for identifying a sample window in the signal; an interval calculator for determining a quantization interval of the sample window; and a sampler for normalizing the sample window to provide normalized samples. According to another embodiment, a system for pre-analyzing a digital signal for encoding at least one digital watermark using a digital filter is disclosed. According to another embodiment, a method for pre-analyzing a digital signal for encoding digital watermarks comprises: (1) providing a digital signal; (2) providing a digital filter to be applied to the digital signal; and (3) identifying an area of the digital signal that will be affected by the digital filter based on at least one measurable difference between the digital signal and a counterpart of the digital signal selected from the group consisting of the digital signal as transmitted, the digital signal as stored in a medium, and the digital signal as played backed. According to another embodiment, a method for encoding a watermark in a content signal includes the steps of (1) splitting a watermark bit stream; and (2) encoding at least half of the watermark bit stream in the content signal using inverted instances of the watermark bit stream. Other methods and systems for encoding/decoding digital watermarks are also disclosed. | 2009-02-05 |
20090037741 | Logging Off A User From A Website - Methods, systems, and computer program products are described for logging off a user from a website, including detecting through a browser a predefined exit channel for a website; detecting a user's leaving the website outside the predefined exit channel; and guiding browser operation toward the predefined exit channel. | 2009-02-05 |
20090037742 | BIOMETRIC AUTHENTICATION DEVICE, SYSTEM AND METHOD OF BIOMETRIC AUTHENTICATION - A biometric sensor device, a portable electronic device including an actuatable biometric input device, and method of biometric authentication that includes an input device that generates a signal or completes a circuit when actuated, and a biometric reader that reads a biometric of a user when the user actuates the input device to generate the signal or complete the circuit. An authentication section authenticates the biometric read on the biometric reader to generate one of a data access allowance function based on authentication of the biometric input to the actuatable biometric input device and a data access prevention function based on non-authentication of the biometric input to the actuatable biometric input device. The data access allowance function permits data to be accessed at the data access interface, and the data access prevention function prevents reading and/or access to data anywhere on the data storage and access device. | 2009-02-05 |
20090037743 | BIOMETRIC AUTHENTICATION DEVICE, SYSTEM AND METHOD OF BIOMETRIC AUTHENTICATION - A biometric sensor device, a portable electronic device including an actuatable biometric input device, and method of biometric authentication that includes an input device that generates a signal or completes a circuit when actuated, and a biometric reader that reads a biometric of a user when the user actuates the input device to generate the signal or complete the circuit. An authentication section authenticates the biometric read on the biometric reader to generate one of a data access allowance function based on authentication of the biometric input to the actuatable biometric input device and a data access prevention function based on non-authentication of the biometric input to the actuatable biometric input device. The data access allowance function permits data to be accessed at the data access interface, and the data access prevention function prevents reading and/or access to data anywhere on the data storage and access device. | 2009-02-05 |
20090037744 | Biometric pin block - A system for biometric user identification. Biometric information is captured from a user and compared to a biometric template that is read from an identification token associated with the user. A data structure is constructed comprising data having a predetermined arrangement, wherein the predetermined arrangement is selected to indicate the result of the comparison | 2009-02-05 |
20090037745 | METHODS FOR SECURE BACKUP OF PERSONAL IDENTITY CREDENTIALS INTO ELECTRONIC DEVICES - A method and system for securely enrolling personal identity credentials into personal identification devices. The system of the invention comprises the manufacturer of the device and an enrollment authority. The manufacturer is responsible for recording serial numbers or another unique identifier for each device that it produces, along with a self-generated public key for each device. The enrollment authority is recognized by the manufacturer or another suitable institution as capable of validating an individual before enrolling him into the device. The enrollment authority maintains and operates the appropriate equipment for enrollment, and provides its approval of the enrollment. The methods described herein discuss post-manufacturing, enrollment, backup, and recovery processes for the device. | 2009-02-05 |
20090037746 | METHODS FOR SECURE RESTORATION OF PERSONAL IDENTITY CREDENTIALS INTO ELECTRONIC DEVICES - A method and system for securely enrolling personal identity credentials into personal identification devices. The system of the invention comprises the manufacturer of the device and an enrollment authority. The manufacturer is responsible for recording serial numbers or another unique identifier for each device that it produces, along with a self-generated public key for each device. The enrollment authority is recognized by the manufacturer or another suitable institution as capable of validating an individual before enrolling him into the device. The enrollment authority maintains and operates the appropriate equipment for enrollment, and provides its approval of the enrollment. The methods described herein discuss post-manufacturing, enrollment, backup, and recovery processes for the device. | 2009-02-05 |
20090037747 | Security Chip - Two kinds of security chips having a security interface are provided. One kind of security chip comprises a processor module, an encrypt/decrypt module, a memory module, a power detecting module and a security I/O module, and all of the modules are connected with each other by an internal bus in the security chip; the other kind of security chip comprises a processor module, an encrypt/decrypt module, a memory module, a power detecting module and an I/O interface module, all of the modules being connected with each other by the internal bus in the security chip, wherein, the security chip also comprises a security input module, a security output module and a south bridge interface module, and all of the modules are connected with each other by the internal bus in the security chip. With the security chip provided by the present invention, it is possible to encrypt/decrypt the I/O information of an information processing device, ensure the safety of the I/O information, and thus prevent the information from being listened to or otherwise revealed. | 2009-02-05 |
20090037748 | METHOD AND APPARATUS FOR FORBIDDING USE OF DIGITAL CONTENT AGAINST COPY CONTROL INFORMATION - Provided is a method of preventing digital content from being used despite the presence of copy control information. In the method, a security apparatus capable of restricting use of contents generates a nonce with respect to a storage device and stores the nonce in the storage device and a memory separated from the storage device when content is stored in the storage device; updates the nonces stored in the memory and storage device when movement of the content occurs; and permits use of the content only when the nonce of the storage device, which is stored in the memory, is equal to the nonce stored in the storage device if the content is requested for use, thereby preventing a disk cloning attack. | 2009-02-05 |
20090037749 | System and method of tamper-resistant control - A method of tamper-resistant control comprising reading a flag of an electronic device with firmware, the flag indicating a provision enable/disable state of the electronic device and provisioning a management processor of the electronic device to facilitate communications between the management processor and a server in response to reading the flag indicating a provision enable/disable state | 2009-02-05 |
20090037750 | MAKING A STORAGE DEVICE UNUSABLE UNTIL A REQUEST IS PROVIDED TO RECOVER AN OPERATING SYSTEM OR SYSTEM FIRMWARE - A system comprises a storage device comprising code that is executable to cause recovery of at least one of an operating system and system firmware. Logic coupled to the storage device is also provided to cause the storage device to be unusable until a request is provided to recover at least one of the operating system and system firmware. | 2009-02-05 |
20090037751 | POWER REGULATOR CIRCUIT OF A MOTHERBOARD - An exemplary power regulator circuit of motherboard includes a power connector comprising a power supply on pin, a power good pin and a first power pin for being coupled to an ATX power supply, the power good pin providing a first power good signal; an electric switch having a first terminal connected to the power supply on pin of the power connector, a second terminal connected to the power good pin of the power connector, and a grounded third terminal; a diode with the cathode connected to the power good pin of the power connector, and the anode connected to the first power pin of the power connector via a first resistor and grounded via a first capacitor; and an output terminal connected to the anode of the diode to provide a second power good signal. | 2009-02-05 |
20090037752 | Power Supply Apparatus with System Controller - In a power supply apparatus for supplying a target power supply voltage to a microprocessor, a system controller sets the target power supply voltage to be supplied to the microprocessor based on a voltage configuration signal outputted from the microprocessor and outputs a voltage setting signal corresponding to the target power supply voltage. The regulator circuit generates the target power supply voltage set by the system controller based on the voltage setting signal outputted from the system controller and supplies the voltage to the microprocessor | 2009-02-05 |
20090037753 | Methods and apparatus to selectively power functional units - A processing engine fetches one or more lines of software instructions into an instruction cache. Based on the contents of the cache, potentially needed functional units are identified as functional units that are operable to execute at least one software instruction stored within the instruction cache. Unneeded functional units are identified as functional units that are not operable to execute a software instruction stored within the instruction cache. A power increase is initiated for selected ones of the potentially needed functional units that are determined to be in a low power state. A power decrease is initiated for selected ones of the unneeded functional units that are determined to be in an operable power state. | 2009-02-05 |
20090037754 | BATTERY MODULE, COMPUTER SYSTEM HAVING THE SAME, AND CONTROL METHOD OF THE COMPUTER SYSTEM - A computer system includes a device which operates depending on a clock frequency; a battery unit which comprises a plurality of battery cells and supplies power to the device; a temperature sensor which senses temperature of the battery cells; and a controller which decreases the clock frequency if the sensed temperature is beyond a first preset critical point. | 2009-02-05 |
20090037755 | Microcontroller and control method therefor - Provided is a microcontroller including: a first low-voltage detection circuit to detect that a power supply voltage is equal to or lower than a first voltage value; a second low-voltage detection circuit to detect that the power supply voltage is equal to or lower than a second voltage value, the second voltage value being lower than the first voltage value; a CPU to stop operating when the first low-voltage detection circuit detects that the power supply voltage is equal to or lower than the first voltage value; and a real-time clock to continue operating unless the second low-voltage detection circuit detects that the power supply voltage is equal to or lower than the second voltage value, in which the first low-voltage detection circuit, the second low-voltage detection circuit, the CPU, and the real-time clock are formed on a single chip. | 2009-02-05 |
20090037756 | System and Method for Suspending Operation of a Mobile Unit - Described is a method for suspending operation of a mobile unit. Data, settings, an operating system state, and/or at least one application state of a mobile unit is saved to a non-volatile memory. At least one component of the mobile device is deactivated. The mobile unit is placed in a suspend mode. | 2009-02-05 |
20090037757 | Method and Related apparatus for reducing CHIPSET power consumption - A method for reducing computer system power consumption. The computer system includes a memory module having a plurality of address pins, and a chipset having a plurality of driving units for driving the address pins. The method includes obtaining number of required address pins by detecting a capacity of the memory module, and disabling the driving units so as to make a number of the active driving units substantially equal to the number of the required address pins. | 2009-02-05 |
20090037758 | USE OF T4 TIMESTAMPS TO CALCULATE CLOCK OFFSET AND SKEW - Disclosed are a method and system for calculating clock offset and skew between two clocks in a computer system. The method comprises the steps of sending data packets from a first processing unit in the computer system to a second processing unit in the computer system, and sending the data packets from the second processing unit to the first processing unit. First, second, third and fourth time stamps are provided to indicate, respectively, when the packets leave the first processing unit, arrive at the second processing unit, leave the second processing unit, and arrive at the first processing unit. The method comprises the further steps of defining a set of backward delay points using the fourth time stamps, and calculating a clock offset between clocks on the first and second processing units and clock skews of said clocks using said set of backward delay points. | 2009-02-05 |
20090037759 | Clock shifting and prioritization system and method - A clock shifting and prioritization method comprising adjusting a frequency for a plurality of clocks corresponding to a plurality of respective components of an electronic device based on a desired user configuration setting for operating the electronic device. | 2009-02-05 |
20090037760 | CIRCUIT ARRANGEMENT HAVING A PLURALITY OF COMMUNICATION INTERFACES - A circuit arrangement including at least two communication interfaces, a clock input, a frequency divider, and a frequency comparator configured to compare a frequency applied to the clock input with a reference frequency, and to output a comparison signal, wherein based on the comparison signal, the circuit arrangement is configured to divide the frequency applied to the clock input and to activate a communication interface of the at least two communication interfaces. | 2009-02-05 |
20090037761 | Clock Source Control for Modular Computer System - A computer system provides for connecting consecutively positioned modules to operate collectively as server. Each module calculates a modulo difference between its position and that of a module serving as a clock source; each module selects a clock input as a function of the result of that calculation. | 2009-02-05 |
20090037762 | Electronic document presentment services in the event of a disaster - The disaster recovery techniques, for presentment of a company's bills, statements or the like, provide electronic document presentment in the event of a disaster that impacts the company's print mail delivery operation or other existing mailing system(s). Files containing electronic documents are received, from a system associated with the print mail delivery operation, and the documents are stored in a database. Preferably, the systems use the company's existing data files. The files may be converted to a format compatible with one or more electronic delivery methodologies, if necessary. The disaster recovery systems present notice and/or data from the documents to the company's customers electronically, for example as e-mail (notice or message containing some or all of the document data), as a document attachment to an e-mail, via a web site, and possibly via telephone voice announcement. | 2009-02-05 |
20090037763 | Systems and Methods for Providing IIP Address Stickiness in an SSL VPN Session Failover Environment - The SSL VPN session failover solution of the appliance and/or client agent described herein provides an environment for handling IP address assignment and end point re-authorization upon failover. The appliances may be deployed to provide a session failover environment in which a second appliance is a backup to a first appliance when a failover condition is detected, such as failure in operation of the first appliance. The backup appliance takes over responsibility for SSL VPN sessions provided by the first appliance. In the failover environment, the first appliance propagates SSL VPN session information including user IP address assignment and end point authorization information to the backup appliance. The backup appliance maintains this information. Upon detection of failover of the first appliance, the backup appliance activates the transferred SSL VPN session and maintains the user assigned IP addresses. The backup appliance may also re-authorize the client for the transferred SSL VPN session. | 2009-02-05 |
20090037764 | MEMORY-MODULE CONTROLLER, MEMORY CONTROLLER AND CORRESPONDING MEMORY ARRANGEMENT, AND ALSO METHOD FOR ERROR CORRECTION - A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module. | 2009-02-05 |
20090037765 | SYSTEMS AND METHODS FOR MAINTAINING LOCK STEP OPERATION - A system is provided for rapidly synchronizing two or more processing elements in a fault-tolerant computing system. Embodiments of this system allow for the rapid synchronization of two processing elements through partial copies of the contents of memory associate with each processing element. | 2009-02-05 |
20090037766 | Storage System With Cascaded Copy targeting and Enhanced Integrity - A storage controller includes an interface to host computer apparatus and an interface to a plurality of controlled storage apparatus. The storage controller comprises a host write component operable to send a request to write a data object to a source data image at one of said plurality of controlled storage apparatus; a copy component operable in response to a metadata state to control copying of said data object to a target data image in a delimited sequence of data images in a cascade at said plurality of controlled storage apparatus and a fill-in component operable in response to detection of an offline condition of a disk containing said target data image to control substitution of a fill-in disk in place of said disk containing said target data image. | 2009-02-05 |
20090037767 | NONVOLATILE MEMORY SYSTEM - A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error. | 2009-02-05 |
20090037768 | Generation of backing electric current on the basis of a combination of components - This descriptive document is about a new backup device that takes advantage of the components of a PC's conventional power supply and it combines them with additional typical electronic components from an uninterruptible power supply (UPS). The result of such combination is a lower cost backup function that is applied directly to the PC and, therefore, eliminates the requirement of external devices—such as a UPS—to perform this backup function.
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20090037769 | DYNAMIC MODIFICATION OF SCHEMAS IN STREAMING DATABASES - A method for dynamically modifying a database schema in a streaming database management system receives a new database schema, compares the new schema to an existing schema, identifies the differences between the new schema and the existing schema, and applies the identified differences to the database in a single transaction, thereby producing a database organized according to the new database schema. | 2009-02-05 |
20090037770 | WATCHDOG MECHANISM WITH FAULT ESCALATION - A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a watchdog trigger is not correctly serviced; entering from the normal mode into a first escalation level of nx escalation levels upon detection of the watchdog fault, wherein nx is an integer equal to or greater than 1; detecting correct watchdog events, which are watchdog events in which a watchdog trigger is correctly serviced; and concurrently detecting watchdog faults, leaving the first escalation level if a first escalation condition is met. An electronic device embodiment includes a CPU and program instructions for carrying out the method. | 2009-02-05 |
20090037771 | MPLS diagnostics tool - A method, system and diagnostic tool for diagnosing a problem in CSPF and non-CSPF MPLS networks, including problems with LDP tunnels. This includes one or more of the following: hopping from network element to network element; determining whether an LSP between elements is operational; determining whether the hop was strict or loose; evaluating whether there is an existing path between the elements; finding and remembering an IGP link between the elements; recognizing whether the LSP is an FRR LSP; diagnosing a cause of the LSP between the elements being down; and altering a display of a topology map of the network to indicate the cause of the problem. | 2009-02-05 |
20090037772 | FUZZY CLASSIFICATION APPROACH TO FAULT PATTERN MATCHING - A method and apparatus are provided for diagnosing faults in a monitored system. Estimates of parameter data are generated from the system with reference parameter data characteristic of known behavior of the system. The generated estimates of the parameter data are compared with measured parameter data. A residual is determined for each of the parameters based on a relationship between the estimates of the parameter data and the measured parameter data. A fuzzy classification rule is implemented to determine a likelihood that a predetermined fault exists by using residuals for parameters used to indicate the existence of the predetermined fault. | 2009-02-05 |
20090037773 | Link Failure Detection in a Parallel Computer - Methods, apparatus, and products are disclosed for link failure detection in a parallel computer including compute nodes connected in a rectangular mesh network, each pair of adjacent compute nodes in the rectangular mesh network connected together using a pair of links, that includes: assigning each compute node to either a first group or a second group such that adjacent compute nodes in the rectangular mesh network are assigned to different groups; sending, by each of the compute nodes assigned to the first group, a first test message to each adjacent compute node assigned to the second group; determining, by each of the compute nodes assigned to the second group, whether the first test message was received from each adjacent compute node assigned to the first group; and notifying a user, by each of the compute nodes assigned to the second group, whether the first test message was received. | 2009-02-05 |
20090037774 | CLIENT SERVER SYSTEM FOR ANALYSIS AND PERFORMANCE TUNING OF REMOTE GRAPHICS DEVICES - Embodiments of the invention provide a data communications protocol and client server architecture used for the performance analysis and debugging of a graphics application running on a remote device. The remote device may be a hand-held video game console, a mobile phone, or convergence device, but may also be a personal computer system. A graphical application debugger may include a host component and a target component. The host component executes on a host system and presents a debugging interface to a developer. The target component may record data related to the performance of a graphics pipeline on the target device and transmit this data back to the host system over a communication link. The target component may be included as part of an instrumented version of a graphics device driver. | 2009-02-05 |