06th week of 2009 patent applcation highlights part 20 |
Patent application number | Title | Published |
20090033365 | TRANSMITTING APPARATUS - To provide a transmitting apparatus capable of suppressing the fluctuation of a common mode potential and performing high-speed, long-distance signal transmission. The transmitting apparatus has a main buffer circuit and a pre-emphasis buffer circuit | 2009-02-05 |
20090033366 | DATA TRANSMISSION SYSTEM AND CABLE - A data transmission system capable of transmitting data at high speed without being bound by a counterpart's power supply voltage can be realized. The data transmission system comprises multiple electronic equipment having individual power supplies, a cable for connecting between the multiple electronic equipment so as to transmit signals therebetween, digital data transmitting circuits extending between the multiple electronic equipment and the cable and each having an open drain type output section at the transmitting end, and an input section provided with a pull-up type resistor at the receiving end, wherein the resistor and the output section are moved from the electronic equipment to the connector of the cable so that parasitic capacitance for restricting time constant of waveforms of signals when rising is changed from a capacitance to a small capacitance. | 2009-02-05 |
20090033367 | Transmission Device - A transmission device including: a driver unit which generates an output signal having an amplitude by a resistance division of a power-supply voltage; and an output-amplitude correction unit which generates current according to variation in the power-supply voltage, and corrects the amplitude by using the current. | 2009-02-05 |
20090033368 | LOGIC BLOCK, A MULTI-TRACK STANDARD CELL LIBRARY, A METHOD OF DESIGNING A LOGIC BLOCK AND AN ASIC EMPLOYING THE LOGIC BLOCK - A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of standard cells having different track heights. In one embodiment, the invention provides a logic block including: (1) a first row of standard cells having a first track height and (2) a second row of standard cells adjacent to the first row and having a second track height that differs from the first track height. | 2009-02-05 |
20090033369 | ARBITRARY QUANTUM OPERATIONS WITH A COMMON COUPLED RESONATOR - A quantum logic gate is formed from multiple qubits coupled to a common resonator, wherein quantum states in the qubits are transferred to the resonator by transitioning a classical control parameter between control points at a selected one of slow and fast transition speeds, relative to the characteristic energy of the coupling, whereby a slow transition speed exchanges energy states of a qubit and the resonator, and a fast transition speed preserves the energy states of a qubit and the resonator. | 2009-02-05 |
20090033370 | COMPARATOR WITH LOW SUPPLIES CURRENT SPIKE AND INPUT OFFSET CANCELLATION - A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V− input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration. | 2009-02-05 |
20090033371 | AMPLIFIER CIRCUIT FOR DOUBLE SAMPLED ARCHITECTURES - A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section. | 2009-02-05 |
20090033372 | SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS - First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half. | 2009-02-05 |
20090033373 | Circuit and Method for Trimming Integrated Circuits - A programmable after-package, on-chip reference voltage trim circuit for an integrated circuit having a plurality of programmable trim cells generating a programmed sequence. A converter is provided to convert the bit sequence into a trim current. The trim current is added to an initial value of a reference voltage to be trimmed, as generated by the integrated circuit. Once the correct value of the trim current is determined, isolation circuitry is programmed to isolate the trim circuitry from the remainder of the IC, thereby freeing the logic and package pins associated with the IC for use by users of the IC. The preferred trim circuitry includes fuses which are blown in accordance with a bit value supplied to the trim cell to permanently fix a trim current value, once a best fit value is determined. | 2009-02-05 |
20090033374 | Clock generator - A frequency divider, comprising an input for receiving an input clock signal having a first frequency; a divider, for generating an output signal having an instantaneous frequency equal to the first frequency divided by an instantaneous division ratio; and a sequence generator, for generating a sequence of instantaneous division ratios by adding a sequence of instantaneous dither values to an integer value. The instantaneous division ratios in the sequence have a mean value that is equal to an integer desired ratio, but none of the instantaneous division ratios in the sequence is equal to the integer desired ratio. | 2009-02-05 |
20090033375 | METHOD AND APPARATUS FOR IDENTIFYING AND REDUCING SPURIOUS FREQUENCY COMPONENTS - A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal. The method may also include converting the amplified analog signal to an amplified digital signal. Of course, additional implementations are also within the scope of the present disclosure. | 2009-02-05 |
20090033376 | Locked loop circuit - A circuit for receiving an input signal having a first frequency and generating an output signal having a second frequency. The circuit comprises a forward branch for receiving the input signal and generating the output signal and a return branch for generating a feedback signal from the output signal. The forward branch comprises a frequency detector for receiving the input signal and the feedback signal and outputting a value based on a ratio of a frequency of the feedback signal to the first frequency; a word length reduction block for receiving a fractional component of a first division factor and generating a modulated output; an adder for forming a sum of an integer component of the first division factor and the modulated output of the word length reduction block; a subtracting element for subtracting the output value of the frequency detector from the sum; and an oscillator controlled by an output from the subtracting element. | 2009-02-05 |
20090033377 | Drive Circuit and Inverter for Voltage Driving Type Semiconductor Device - A drive circuit for driving a semiconductor element is equipped with: a first switch connected to a positive side of a DC power supply; a second switch connected to the other terminal of the first switch and to a negative side of the DC power supply; a third switch connected to the positive side of the DC power supply; a fourth switch connected to the other terminal of the third switch; a fifth switch connected to the other terminal of the fourth switch and to the negative side of the DC power supply; and a capacitor connected to the other terminal of the first switch and to the other terminal of the fourth switch. A gate of the semiconductor element is connected to the other terminal of said third switch; and a source of the semiconductor element is connected to the negative side of the DC power supply. | 2009-02-05 |
20090033378 | PROGRAMMABLE FREQUENCY MULTIPLIER - A programmable frequency multiplier device which includes a frequency doubler section configured to receive an input signal having a frequency f, and to output doubled signals, each of the doubled signals having a frequency 2 | 2009-02-05 |
20090033379 | Generation of a Digital Controlled Precise Analog Sine Function - This disclosure relates to semiconductor device having a trapezoid shaped resistive strip with a plurality of legs coupled along one strip edge to produce an analog sine wave. | 2009-02-05 |
20090033380 | REDUNDANT CLOCK SWITCH CIRCUIT - A redundant clock switch circuit that includes two delay circuits and control logic is presented. The first delay circuit is configured to delay a first clock signal to produce a first delayed clock signal, while the second delay circuit is configured to delay a second clock signal to produce a second delayed clock signal. The control logic is configured to control the delay circuits to maintain phase alignment between the first and second delayed clock signals. The control logic is also configured to select one of the first and second delayed clock signals as an output clock signal. | 2009-02-05 |
20090033381 | PHASE LOCKED LOOP, VOLTAGE CONTROLLED OSCILLATOR, AND PHASE-FREQUENCY DETECTOR - A phase locked loop, voltage controlled oscillator, and phase-frequency detector are provided. The phase locked loop comprises a phase-frequency detector (PFD), a loop filter (LF), a voltage controlled oscillator (VCO), and a 3-stage frequency divider. The PFD receives a reference signal and a feedback signal to determine phase and frequency errors. The LF), coupled to the phase-frequency detector, filters the phase and frequency errors to generate a control voltage. The VCO, coupled to the loop filter, generates a VCO output signal according to the control voltage. The 3-stage frequency divider, coupled to the voltage controlled oscillator, divides the frequency of the VCO output signal 3 times to generate the feedback signal. | 2009-02-05 |
20090033382 | Frequency synthesizer - A circuit for receiving an input signal and generating an output signal, the input signal having a first frequency, the output signal having a second frequency. The circuit comprises a forward branch for generating the output signal and a return branch for feeding back the output signal. The return branch comprises a frequency divider for receiving the output signal, for dividing the frequency of the output signal by a factor, and for outputting a modified output signal. The forward branch comprises a detector for comparing the input signal and the modified output signal and outputting a comparison signal indicative of the comparison; a word-length reduction circuit for reducing the number of bits of the comparison signal, thereby generating a reduced-length comparison signal; a digital-to-analog converter for converting the reduced-length comparison signal to analog, thereby generating an analog signal; and an oscillator, controlled by said analog signal. By reducing the word length of the input to the digital-to-analog converter, the digital-to-analog converter may be greatly simplified. | 2009-02-05 |
20090033383 | HIGH OUTPUT RESISTANCE, WIDE SWING CHARGE PUMP - Disclosed are current sink and source circuits, a charge pump that incorporates them, and a phase locked loop that incorporates the charge pump. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation. | 2009-02-05 |
20090033384 | METHOD AND SYSTEM FOR MANAGING DIGITAL TO TIME CONVERSION - A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal. | 2009-02-05 |
20090033385 | Glitch Reduced Delay Lock Loop Circuits and Methods for Using Such - Various embodiments of the present invention provide delay lock loop circuits. Such delay lock loop circuits include two or more delay stages that each include a plurality of selectable delay elements. A reference signal drives an input of the first delay stage, and the first delay stage provides a first output. The first output drives an input of the second delay stage, and the second delay stage provides a second output. The circuits further include a first selector register that is associated with the first delay stage. A value maintained in the first selector register determines a number of the selectable delay elements utilized in the first delay stage. Modification of the value maintained in the first selector register is synchronized to the first output. The circuits further include a second selector register associated with the second delay stage. A value maintained in the second selector register determines a number of the selectable delay elements utilized in the second delay stage. Modification of the value maintained in the second selector register is synchronized to the second output. | 2009-02-05 |
20090033386 | Delay Lock Loop Circuits Including Glitch Reduction and Methods for Using Such - Various systems and methods for delaying one signal in relation to another are disclosed. As one example, a delay lock loop circuit is discussed that includes at least a first delay stage and a second delay stage, each including a plurality of selectable delay elements. The delay stages are configured such that a gated reference signal drives an input of the first delay stage, and a first output from the first delay stage drives an input of the second delay stage. The circuits further include a unified selector register that is associated with both the first delay stage and the second delay stage. A value maintained in the unified selector register determines a number of the selectable delay elements utilized in the first delay stage and a number of the selectable delay elements utilized in the second delay stage. In operation, modification of the value maintained in the unified selector register is synchronized to the reference signal. A reference signal gate is included that receives the reference signal and provides the gated reference signal. The gated reference signal is substantially the reference signal modified such that the gated reference signal is not asserted when modification of the unified selector register is enabled. | 2009-02-05 |
20090033387 | Master Slave Delay Locked Loops and Uses Thereof - Various systems and methods for delaying a signal relative to another signal are disclosed. As one example, a delay lock loop circuit is disclosed that includes at least two delay stages. Each of the aforementioned delay stages include a plurality of selectable delay elements. Such selectable delay elements may be, but are not limited to, a plurality of single input buffers, and a plurality of multiple input logic gates. Further, a first of the delay stages is selectably driven by one of a first signal and a reference signal, and the stage provides a first stage output. A second of the delay stages is selectably driven by one of a second signal and the first stage output, and the stage provides a second stage output. The circuit further includes a mode signal that has at least two states. One of the two states causes the first signal to drive the first delay stage and the second signal to drive the second delay stage, and the other state causes the reference signal to drive the first delay stage and the first stage output to drive the second delay stage. In some cases, the first state is referred to as a slave state and the second state is referred to as a master state. In addition, the circuit includes a feedback loop. | 2009-02-05 |
20090033388 | Systems and Methods for Reduced Area Delay Locked Loop - Various systems and methods for signal synchronization are disclosed. For example, some embodiments of the present invention provide methods for reduced area delay signal timing. Such methods include providing a delay lock loop circuit with a plurality of selectable delay elements. The methods further include operating the delay lock loop circuit in a first mode where a program number is established in relation to a reference frequency. The program number corresponds to a number of the plurality of selectable delay elements used to establish a first delay time at the reference frequency. The program number is multiplied by a multiplicand, and the product of the multiplication is used while operating the delay lock loop circuit in a second mode to select the number of delay elements utilized in delaying an input signal. In the second mode, an input signal is delayed by a second delay time that is approximately the first delay time multiplied by the multiplicand. | 2009-02-05 |
20090033389 | MICRO-PHASE ADJUSTING AND MICRO-PHASE ADJUSTING MIXER CIRCUITS DESIGNED WITH STANDARD FIELD EFFECT TRANSISTOR STRUCTURES - Disclosed herein are embodiments of a programmable phase adjusting circuit, a programmable phase adjusting mixer circuit and design structures for these circuits. These circuits comprise a variable delay device connected between input and output nodes. The device includes multiple FETs with input diffusion regions that are connected to a voltage rail via switches so that they can be selectively biased, gates that are connected in series to the input node so that a periodic input signal can be propagated sequentially through each of the gates and output diffusion regions that are connected in parallel to the output node. A current source is connected between the output node and another voltage rail for biasing the output node when the variable delay device is off. The variable delay device enables a circuit in which small increments of selectable phase adjustments can be made to the periodic input signal as a function of propagation delay. | 2009-02-05 |
20090033390 | SIGNAL PROCESSING APPARATUS AND CONTROL METHOD THEREOF - A signal processing apparatus and a control method thereof are provided. The signal processing apparatus includes: a signal processor which respectively processes an input video signal and an input audio signal; a communication unit which is communicably linked with an external audio output unit that outputs the audio signal; and a controller which controls the signal processor to delay and process one of the video signal and the audio signal by a delay value corresponding to the external audio output unit if the external audio output unit is predetermined. | 2009-02-05 |
20090033391 | CIRCUITS TO DELAY A SIGNAL FROM A MEMORY DEVICE - A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to realize said first delay altered by the fraction number of delay elements. | 2009-02-05 |
20090033392 | Delay locked loop with improved jitter and clock delay compenstating method thereof - A delay locked loop can remove a jitter component that inevitably occurs due to feedback latency in the conventional DLL. That is, the present invention has benefit of removing the jitter component by controlling the delay lines based on the predicted data. The delay locked loop includes a pattern detecting unit for generating and storing a noise pattern by detecting inputted noise data, a pre-delay control unit for determining a delay amount depending on the output of the pattern detecting unit, and a pre-delay line for delaying an internal clock depending on the delay amount that is determined by the pre-delay control means. | 2009-02-05 |
20090033393 | METHOD AND APPARATUS FOR REGULATING A DIODE CONDUCTION DUTY CYCLE - A power converter control method and apparatus is disclosed. A control circuit for use in a power converter according to aspects of the present invention includes a clock signal generator coupled to generate a clock signal to control switching of a power switch to be coupled to the control circuit. Feedback circuitry is coupled to receive a feedback signal, which is representative of an output of a power converter during a feedback portion of an off time of the power switch. The feedback circuitry is coupled to respond to the feedback signal to control the clock signal generator to regulate a duty cycle of the feedback portion of the off time of the power switch as a proportion of a total power switch switching cycle period. | 2009-02-05 |
20090033394 | Data retention in operational and sleep modes - A circuit is disclosed for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input operable to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output and a forward data path therebetween, wherein a signal value is operable to be received at said data input, is clocked through said at least one latch and passes to said data output along said forward data path; at least one of said at least one latch comprises a retention latch operable to retain a signal value during said sleep mode, said retention latch not being located on said forward data path; and a tristateable device, said tristateable device being arranged between said forward data path and said retention latch and being operable to selectively isolate said retention latch from said forward data path in response to receipt of a first sleep signal; wherein in response to receipt of a second sleep signal, said second sleep signal being received after said first sleep signal, said circuit is operable to enter said sleep mode such that a voltage difference across said portion of said circuit is reduced such that said portion of said circuit is powered down, and a voltage difference across said retention latch and said tristateable device is maintained. | 2009-02-05 |
20090033395 | MULTIPLE SOURCE-SINGLE DRAIN FIELD EFFECT SEMICONDUCTOR DEVICE AND CIRCUIT - Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal. | 2009-02-05 |
20090033396 | SETUP/HOLD TIME CONTROL CIRCUIT - A setup/hold time control circuit includes a reference signal output unit that sets any one of multiple ports as a reference port and buffers a signal input through the reference port to output as a reference signal. The setup/hold time control circuit also includes a plurality of comparative signal output units that set the remaining ports as comparative ports. The comparative signal output unit synchronizes signals that are input from the comparative ports with the reference signal and outputs the signals as internal signals. The setup/hold time control circuit improves high speed operation of a semiconductor memory device by improving upon the setup/hold time difference between multiple ports. | 2009-02-05 |
20090033397 | Delay time adjusting method of semiconductor integrated circuit - The delay time variation of transistors caused by the manufacturing variation is desired to be adjusted. A relation table storing a relation between sizes and voltage values (supply voltages and bias voltages) is provided. Macros each of which includes a transistor and a setting voltage generation circuit for applying a setting voltage to the transistor are formed on a chip. A process data indicating a size of the transistor is generated. The voltage value corresponding to the size of the transistor indicated by the process data in the relation table is selected as an optimum voltage value (supply voltage Vdd, bias voltage Bias) for each of the macros. The setting voltage of each of the macros is set to the optimum voltage value. The delay time can be adjusted without requiring a detection circuit for detecting the delay time. | 2009-02-05 |
20090033398 | Clock Distribution Network Wiring Structure - A wiring structure for clock signals has two or more parallel clock signal wires disposed in adjacent power wire bays that span the distance between the sinks to which the clock signal wires are to be coupled. The parallel clock signal wires are shorted one to another by stubs placed at locations in order to time the clock wiring structure. The delay tuning of the structure is obtained by the discrete movement of wiring stubs between the wiring bays of the pre-defined power grid. | 2009-02-05 |
20090033399 | Method and Device for Adjusting a Pulse Detection Threshold, and Pulse Detection and Corresponding Receiver - The invention relates to a method for adjusting a pulse detection threshold consisting in detecting a pulse when the edge of said pulse envelop crosses the threshold, in allocating (A) a staring value (TH | 2009-02-05 |
20090033400 | VOLTAGE TOLERANT FLOATING N-WELL CIRCUIT - Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state. | 2009-02-05 |
20090033401 | Level Shifting Circuit With Symmetrical Topology - A shifter circuit includes a pair of feed forward sections and a pair of feedback sections. The sections are arranged and coupled to form a balanced symmetrical topology. The feed forward sections each include inverter pairs of PMOS and NMOS devices. The feedback sections each include a pair of cross-coupled devices. A pair of output nodes are operatively positioned between the pair of feedback sections. A method for using the circuit to generate output signals at respective output ports is also disclosed. | 2009-02-05 |
20090033402 | LEVEL CONVERSION CIRCUIT - A level conversion circuit according to the present invention comprises: a first transistor having a gate thereof grounded, for inputting the input voltage to a source thereof and outputting an output voltage from a drain thereof; a second transistor having a drain thereof to which a power supply voltage is applied, for inputting the output voltage outputted from the drain of the first transistor to a gate thereof and outputting, from a source thereof, the output voltage determined by the power supply voltage; a level shift circuit for inputting the output voltage outputted from the source of the second transistor to an input end thereof and outputting, from an output end thereof, a voltage whose level is shifted by a predetermined amount; and a resistance inserted between the output end of the level shift circuit and a ground. Thus, it becomes possible to reduce a current Ii flowing to the gate of the first transistor to a level close to zero. | 2009-02-05 |
20090033403 | LEVEL CONVERTING CIRCUIT - A level shifter in which short circuit current and the increase in delay are reduced when a first power source is controlled. | 2009-02-05 |
20090033404 | Broadband cascode mixer - A mixer has a cascode configuration. With the configuration, the mixer is operated under a low voltage. And, the present invention has a good circuit gain, a good broadband operation and a low power consumption. The mixer can be realized with a CMOS transistor. Hence, the present invention is fit to be applied in a receiver module. | 2009-02-05 |
20090033405 | DRIVER CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME - A driver circuit of the present invention includes: a pair of switch elements (P | 2009-02-05 |
20090033406 | INTERNAL VOLTAGE GENERATOR OF SEMICONDUCTOR INTEGRATED CIRCUIT - The internal voltage generator of a semiconductor integrated circuit includes at least one variable reference voltage generating unit that generates a base reference voltage increased or decreased according to the variation in temperature, at least one level shifting unit that transforms the base reference voltage outputted by the at least one variable reference voltage generating unit into at least one prescribed reference voltage for generating internal voltage and outputs the transformed reference voltage, and at least one internal voltage generating unit that generates an internal voltage by using the at least one reference voltage for generating internal voltage outputted by the at least one level shifting unit. | 2009-02-05 |
20090033407 | STRUCTURE FOR A HIGH OUTPUT RESISTANCE, WIDE SWING CHARGE PUMP - Disclosed are design structures for current sink and source circuits, a charge pump, and a phase locked loop. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation. | 2009-02-05 |
20090033408 | Voltage Pump Circuit with an Oxide Stress Control Mechanism for use in High-Voltage Applications in an Integrated Circuit - A voltage pump circuit that has an oxide stress control mechanism is disclosed. In particular, the oxide stress control mechanism of the voltage pump circuit ensures a safe transistor gate-to-source voltage in high-voltage applications in an integrated circuit. In particular, the down level of the gate voltage of the output transistor may be conditionally limited. For example, an offset in the down level of the gate voltage is created by conditionally developing an offset voltage in the lower rail voltage of the gate driver. The offset voltage is created by directing a predetermined current through a resistance. The current is conditional such that the current is about zero when the power supply voltage is less than or equal to a predetermined level, and the current is greater than zero when the power supply voltage is greater than a predetermined level. | 2009-02-05 |
20090033409 | Bias correction device - A bias correction device to be used on a power supply which has a high voltage output end and a low voltage output end bridges the high voltage output end and the low voltage output end. When the output voltage at the low voltage output end is too low the bias correction device makes the high voltage output end to output a voltage to compensate the low voltage output end so that the voltage at the low voltage output end is raised to be maintained a preset output voltage level. | 2009-02-05 |
20090033410 | POWER ELECTRONICS DEVICES WITH INTEGRATED CONTROL CIRCUITRY - A power switch apparatus includes a substrate; a semiconductor die mounted on the substrate and including power electronics circuitry for a high power, alternating current motor application; gate drive circuitry mounted on the substrate and electrically coupled to the power electronics circuitry on the semiconductor die; and control circuitry mounted on the substrate and electrically coupled to the gate drive circuitry. | 2009-02-05 |
20090033411 | Oscillation Maintentance Circuit For Half Duplex Transponder - An oscillation maintenance circuit for a half-duplex transponder that has an LC resonant circuit, a storage capacitor and a rectifier connected to charge the storage capacitor with a rectified oscillation signal, having an end-of-burst detector providing an end-of-burst signal when the amplitude of the oscillation signal has dropped below a predetermined threshold. A clock regenerator provides a clock signal derived from the oscillation signal. Switching means controlled by the clock signal in the presence of the end-of-burst signal connect the storage capacitor with LC resonant circuit through at least one current limiting resistor during part of the period of the clock signal, in such a manner that energy is fed into the LC resonant circuit. | 2009-02-05 |
20090033412 | Remote Audio Amplifier Monitoring System - An apparatus is provided for remotely monitoring a plurality of amplifiers on a display device. The amplifiers are provided to process audio signals and directly or indirectly connected to a network. In the apparatus, a collecting section collects a group code from each of the amplifiers through the network. The group code is allocated to each amplifier according to a grouping system for grouping the plurality of the amplifiers. A display control section displays a tree diagram of the amplifiers according to the collected group codes on the display device as a graphical representation of the grouping system. | 2009-02-05 |
20090033413 | GAIN CONTROLLED AMPLIFIER AND CASCODED GAIN CONTROLLED AMPLIFIER BASED ON THE SAME - A gain controlled amplifier and a cascoded gain controlled amplifier based on the same are disclosed. The gain controlled amplifier includes an operational amplifier for amplifying an input signal, an input resistor connected to an input terminal of the operational amplifier, a feedback resistor connected to an output terminal of the operational amplifier, and a resistor circuit for providing voltages having different levels to the input terminal and the output terminal of the operational amplifier, respectively, according to a digital signal composed of specified bits. The gain controlled amplifier employs an R-2R ladder circuit controlled by a digital signal so as to obtain a gain that is in linear proportion to a decibel scale. Since the R-2R ladder circuit operates with a small resistance value, the chip size of the gain controlled amplifier can be reduced. | 2009-02-05 |
20090033414 | METHOD AND SYSTEM FOR POLAR MODULATING OFDM SIGNALS WITH DISCONTINUOUS PHASE - Aspects of a method and system for polar modulating OFDM signals with discontinuous phase may include amplifying an OFDM signal via a plurality of amplifiers such that a combined gain of the plurality of amplifiers comprises a coarse amplitude gain and an amplitude offset gain. A gain of one or more of the plurality of amplifiers may be adjusted to set the coarse amplitude gain, and a gain of one or more remaining ones of the plurality of amplifiers may be adjusted to set the amplitude offset gain. The setting of the coarse amplitude gain and/or the amplitude offset gain may be adjusted dynamically and/or adaptively. | 2009-02-05 |
20090033415 | METHOD AND SYSTEM FOR AMPLITUDE CALIBRATION FOR POLAR MODULATION WITH DISCONTINUOUS PHASE - Aspects of a method and system for amplitude calibration for polar modulation with discontinuous phase may include amplifying a signal via a plurality of amplifiers such that a combined gain of the plurality of amplifiers comprises a coarse amplitude gain, an amplitude offset gain and a calibration gain. A gain of one or more of the plurality of amplifiers may be adjusted to set the coarse amplitude gain, and a gain of one or more remaining ones of the plurality of amplifiers may be adjusted to set the amplitude offset gain and the calibration gain. The setting of the coarse amplitude gain, the calibration gain and/or said amplitude offset gain may be adjusted dynamically and/or adaptively. | 2009-02-05 |
20090033416 | METHOD AND SYSTEM FOR POLAR MODULATING QAM SIGNALS WITH DISCONTINUOUS PHASE - Aspects of a method and system for polar modulating QAM signals with discontinuous phase may include amplifying a signal via a plurality of amplifiers such that a combined gain of the plurality of amplifiers comprises a coarse amplitude gain and an amplitude offset gain. A gain of one or more of the plurality of amplifiers may be adjusted to set the coarse amplitude gain, and a gain of one or more remaining ones of the plurality of amplifiers may be adjusted to set the amplitude offset gain. The setting of the coarse amplitude gain and/or said amplitude offset gain may be adjusted dynamically and/or adaptively. The signal may be generated by phase-modulation of a radio-frequency carrier. The combined gain of the plurality of amplifiers may be controlled based on a desired amplitude modulation. The plurality of amplifiers may be integrated within an integrated circuit (IC) or chip. | 2009-02-05 |
20090033417 | METHOD AND SYSTEM FOR POLAR MODULATION WITH DISCONTINUOUS PHASE FOR RF TRANSMITTERS WITH POWER CONTROL - Aspects of a method and system for polar modulation with discontinuous phase for RF Transmitters with power control may include amplifying a signal via a plurality of amplifiers such that a combined gain of the plurality of amplifiers comprises a coarse amplitude gain, a power level gain and an amplitude offset gain. A gain of one or more of the plurality of amplifiers may be adjusted to set the coarse amplitude gain and the power level gain. A gain of one or more remaining ones of the plurality of amplifiers may be adjusted to set the amplitude offset gain. The setting of the coarse amplitude gain, the power level gain and/or the amplitude offset gain may be adjusted dynamically and/or adaptively. | 2009-02-05 |
20090033418 | Training sequence and digital linearization process for power amplifier - A training sequence and digital linearization process for a power amplifier are provided. In particular, a system for maintaining linear operation of an amplifier is includes an estimation component configured to determine compensation coefficients. The system further includes a digital pre-distorter configured to compensate for non-linear operation of the amplifier based on the compensation coefficients. The compensation coefficients are determined based on a training sequence signal having a time synchronization portion and a linearization sequence portion. | 2009-02-05 |
20090033419 | CLASS D AMPLIFIER WITH INCREASED EFFICIENCY - The present invention is a method of operating a speaker by converting an audio signal to a pulse-width modulated signal that has a plurality of positive pulses and a plurality of negative pulses as a function of the audio signal, then driving an H-bridge circuit interconnected to a speaker, wherein the H-bridge circuit comprises an A-side and a B-side, wherein the A-side comprises a first switching transistor and a second switching transistor, and wherein the B-side comprises a first switching transistor and a second switching transistor. For each positive pulse, the A-side of the H-bridge circuit is driven by pushing the first switching transistor of the A-side while grounding the second switching transistor of the A-side. For each negative pulse, the B-side of the H-bridge circuit is driven by pushing the first switching transistor of the B-side while grounding the second switching transistor of the B-side. | 2009-02-05 |
20090033420 | OPERATIONAL AMPLIFIER CIRCUIT, CONSTANT VOLTAGE CIRCUIT USING THE SAME, AND APPARATUS USING THE CONSTANT VOLTAGE CIRCUIT - A disclosed operational amplifier circuit with a multi-stage amplifier configuration provides fast-response and high withstand-voltage characteristics without using high withstand-voltage transistors as output transistors in its amplifying stages. The output voltage range of a differential amplifier circuit in a first stage is limited by voltage clamping based on a reverse withstand voltage of a bipolar diode. The output voltage range of an amplifier circuit in a second stage is limited by voltage clamping based on a reverse withstand voltage of another bipolar diode. A constant voltage circuit and an apparatus including such an operational amplifier circuit are also disclosed. | 2009-02-05 |
20090033421 | DIFFERENTIAL INPUT DRIVER USING CURRENT FEEDBACK AND CROSS-COUPLED COMMON BASE DEVICES - A differential input driver circuit ( | 2009-02-05 |
20090033422 | Multi-level slew and swing control buffer - A buffer amplifier and an associated method have been provided for slew rate and swing level control in the buffering of a signal. The method accepts an input signal having a voltage swing, a swing control signal, and a slew rate control signal. The voltage swing for each output in a set of serially-connected buffer stages is selected in response to the swing control signal. The selected voltage swing for a subset of buffer stages is modified in response to the slew rate control signal. Selecting the voltage swing for each output entails selecting a source current for each buffer stage. A bias current is generated and mirrored through a current source connected to each buffer stage. Modifying the selected voltage swing for each of the subset of buffer stages includes modifying the bias current to the subset of buffer stages. | 2009-02-05 |
20090033423 | OUTPUT BUFFER AND POWER AMPLIFIER COMPRISING THEREOF - The present invention relates an output buffer and a power amplifier having the same. The output buffer includes a push-pull circuit unit, an output unit, and a driver. The push-pull circuit unit includes transistors connected to each others in a push-pull formation between a high level power voltage and a low level power voltage. The output unit is connected to the high level power voltage and the low level power voltage, and the driver drives the output unit according to a signal from the push-pull circuit unit. | 2009-02-05 |
20090033424 | RADIO RECEIVER - There is provided a method that comprises identifying a parasitic signal transfer in a filter using a signal-directed graph; and adding compensation paths to the filter to reduce or eliminate the effect of the parasitic signal transfer A corresponding filter is provided which comprises a plurality of amplifier stages that generate one or more filter poles; at least one component coupled to at least one of the amplifier stages, the component causing a parasitic effect in the filter; and means for applying a compensation current to the at least one amplifier stage to reduce or eliminate the parasitic effect. A radio receiver is further provided that comprises a filter for receiving and filtering in-phase and quadrature signals; an amplifier for receiving and amplifying one of said filtered in-phase and quadrature signals; means for receiving the amplified and filtered in-phase or quadrature signal from said amplifier, and for regenerating the other one of said in-phase and quadrature signals from said amplified and filtered signal. | 2009-02-05 |
20090033425 | Method and System for a Highly Efficient Power Amplifier Utilizing Dynamic Biasing and Predistortion - Aspects of a method and system for a highly efficient power amplifier (PA) utilizing dynamic biasing and predistortion are presented. Aspects of the system may include a processor that enables computation of a value of a variable bias component of a bias current based on a bias slope value and an amplitude of an envelope input signal. The processor may enable computation of a value of the bias current based on the selected constant bias current component value and the variable bias current component value. A PA may enable generation of an output signal in response to a generated baseband signal by utilizing the bias current to amplify an amplifier input signal. The bias current may be generated based on the envelope input signal. A feedback signal may be generated based on the output signal, which may be used to predistort a subsequent baseband signal. | 2009-02-05 |
20090033426 | PRE-EMPHASIS CIRCUIT - An amplifier stage or circuit for providing pre-emphasis. The circuit includes a first input node configured to receive a first data signal and a second input node configured to receive a second data. The circuit also includes an adjustable delay stage configured to at least partially produce a delay in the first and/or second data signals to thereby generate a first delayed signal and/or second delayed signal. The circuit additionally includes a pulse generation stage configured to generate a first pulse signal from the first delayed signal and the first data signal and/or produce a second pulse signal from the second delayed signal and the second data signal. The circuit further includes a first output node configured to output the first pulse signal and a second output node configured to output the second pulse signal. | 2009-02-05 |
20090033427 | OSCILLATOR, PLL OSCILLATOR, RADIO APPARATUS - An oscillator includes a plurality of oscillating units connected in parallel with each other, and a control unit which controls the number of parallel connections of the plurality of oscillating units based on an instruction signal indicating accuracy to be tolerated with respect to oscillation outputs of the oscillating units. | 2009-02-05 |
20090033428 | VOLTAGE CONTROLLED OSCILLATOR - An integrated circuit is provided. The integrated circuit comprises a voltage controlled oscillator and a first compensation capacitor. The voltage controlled oscillator generates an oscillation signal. The first compensation capacitor, coupled in parallel to the voltage controlled oscillator, receives a control voltage to generate a negative temperature coefficient capacitance to compensate for frequency drift of the oscillation signal. The control voltage is temperature dependent. | 2009-02-05 |
20090033429 | Phase locked loop for stably operating in a matter that is insensitive to variation in process, voltage and temperature and method of operating the same - A phase locked loop for stably operating in a matter that is insensitive to variation in PVT and a method of operating the same. The PLL according to the present invention includes a PFD, a charge pump circuit, a loop filter, a VCO, and a peak voltage detector. The PFD compares a phase or frequency of a reference signal with a phase or frequency of an output signal and outputs an up signal or a down signal based on the comparison result. The charge pump circuit generates a pumping current in response to the up signal or the down signal and increases or decreases the pumping current in response to a detection signal. The loop filter outputs control voltage according to the pumping current. The VCO outputs the output signal having a frequency determined based on the control voltage. The peak voltage detector detects the peak value of the control voltage and outputs the detection signal based on the detection result. The PLL detects the peak value of control voltage and controls the operation of a charge pump circuit based on the detection result thereby decreasing the peaking and ringing phenomena of the control voltage and then stably operating in a manner that is insensitive to variation in PVT. | 2009-02-05 |
20090033430 | Injection-locked frequency divider - An injection-locked frequency divider includes a ring oscillator, a signal injection circuit, a first adjustable load circuit and a second adjustable load circuit. The ring oscillator generates an oscillation signal according to a differential signal outputted by the signal injection circuit. According to an adjustable voltage, the first and second adjustable load circuits can respectively change equivalent impedances of the first adjustable load circuit and the second adjustable load circuit so that a free-running frequency of the oscillation signal of the ring oscillator is adjusted and an injection-locked frequency range of the injection-locked frequency divider is expanded. | 2009-02-05 |
20090033431 | Oscillation Circuit - The present invention provides a highly accurate oscillation circuit. For example, the oscillation circuit includes plural ring oscillator units RO | 2009-02-05 |
20090033432 | OSCILLATION DRIVER DEVICE, PHYSICAL QUANTITY MEASURING DEVICE, AND ELECTRONIC INSTRUMENT - An oscillation driver device includes a gain control amplifier, an automatic gain control circuit, and a mode setting circuit. When the mode setting circuit has switched a mode from a normal operation mode to a low power consumption mode, the automatic gain control circuit is disabled, and the gain in an oscillation loop that drives the vibrator changes from a state in which the gain in the oscillation loop is controlled to be unity by the automatic gain control circuit to a state in which the gain in the oscillation loop is set to be larger than unity. When the mode setting circuit has switched the mode from the low power consumption mode to the normal operation mode, the automatic gain control circuit resumes operation, and the gain in the oscillation loop changes from the state in which the gain in the oscillation loop is set to be larger than unity to the state in which the gain in the oscillation loop is controlled to be unity by the automatic gain control circuit. | 2009-02-05 |
20090033433 | Circuits, Systems, and Methods for a Voltage Controlled Oscillator with Coarse, Fine, and Center Tuning - Circuits, systems, and methods for generating a variable oscillator output. The circuits generally comprise a capacitor configured to receive first and second currents of a first polarity (e.g., charging currents) and a third current of a second polarity opposite to the first polarity (e.g., a discharge current). The circuit further comprises a first circuit configured to receive a bias input, a second circuit configured to receive a coarse control input, and a third circuit configured to receive a fine control input. The first circuit is further configured to provide the first current in response to the bias input. The second circuit is further configured to provide the second current in response to the coarse control input, such that the second current generally has a magnitude of from zero to a multiple of the magnitude of the first current. The third circuit is further configured to provide the third current when the capacitor has a voltage that passes a threshold voltage determined by the fine control input. The present invention advantageously provides for producing a variable oscillator output over a broad range with the coarse control input, while also having low gain with the fine control input. The present invention is also advantageously suitable for standard integrated circuit manufacturing processes because the bias input can be adjusted to compensate for process variations. | 2009-02-05 |
20090033434 | OSCILLATION CIRCUIT - A first switch (SW | 2009-02-05 |
20090033435 | SWITCHING CIRCUIT - Disclosed is a switch circuit capable of reducing distortion caused by harmonics and preventing an increase in insertion loss even if the number of ports increases. The switching circuit includes one common output port, M first switches having one set of ends connected in common to a first node (M≧2 where M is a constant), N second switches having one set of ends connected in common to the common output port (N≧1 where N is a constant), a third switch having one end connected to the common output port and the other end connected to the first node, M first input ports respectively connected to the other set of ends of the first switches, and N second input ports respectively connected to the other set of ends of the second switches. One selected among the first input ports and the second input ports is connected to the common output port, and if one of the first input ports is selected, the third switch is closed. | 2009-02-05 |
20090033436 | Directional Coupler in Coaxial Line Technology - A directional coupler comprising a first connection for the inlet or outlet of a shaft, a first decoupling connection which is used to decouple a coupled shaft, a second connection for the inlet or outlet of the inlet or outlet shaft from the first connection and a second decoupling connection which is used to decouple the coupled shaft. The first connection and the first decoupling connection are connected to the internal conductor and to the external conductor of a coaxial conductor on the first connection surface thereof, by means of a first network. The second connection and the second decoupling connection are connected to the internal conductor and to the external conductor of the coaxial conductor on the second connection surface thereof, by means of a second network. The coaxial conductor is curved in such a manner that it is arranged in a parallel manner in relation to the first and second connection surfaces thereof, with a planar circuit board containing the first connection, the second connection, the first decoupling connection and/or second decoupling connection. | 2009-02-05 |
20090033437 | FILTER MODULE AND COMMUNICATION APPARATUS - In a filter module, a common input/output portion of a switch circuit is set as a first port. A first filter arranged to pass a signal in a first frequency band is connected between a first input/output portion of the switch circuit and a second port. A second filter arranged to pass a signal in a second frequency band is connected between a second input/output portion and the second port. A phase adjusting circuit is provided such that an impedance in the second frequency band as seen from the first port while the switch circuit selects the first input/output portion is in a substantially short-circuited state. This arrangement prevents leakage of unwanted signals from a signal path used in a communication system not in operation among two communication systems for different frequency bands while the other communication system is engaged in communication. | 2009-02-05 |
20090033438 | Adjustable Phase Shifter For Antenna - An adjustable phase shifter for an antenna includes a metal circuit portion, a coupling portion, and a grounding portion. The metal circuit portion is used for receiving a fed-in signal, while the coupling portion is disposed on one side of the metal circuit portion and is disposed at an angle with respect to the metal circuit portion, for controlling a phase angle of the fed-in signal by adjusting the angle formed therebetween. The grounding portion is disposed on the other side of the metal circuit portion in parallel. The structure of the adjustable phase shifter for adjusting the phase angle output by the phase shifter is simple, so as to improving the fabrication efficiency. Moreover, the fabrication efficiency of the adjustable phase shifter is able to be further improved by adopting an attachable impedance matcher, or changing the structure of the coupling portion. | 2009-02-05 |
20090033439 | MULTILAYER FILTER - A multilayer filter wherein the capacitances of capacitors are reduced to reduce the size of the filter without substantially affecting the filter frequency characteristics. A predetermined filter circuit includes plural electrodes in a dielectric ceramic device body. Each of the capacitors is respectively disposed at input and output ends of the filter circuit and has one end connected to one of input/output terminals. Winding-type inductors, interposed between the input/output terminals and the one ends of the capacitors, are in the device body. | 2009-02-05 |
20090033440 | ACTIVE RESONANT CIRCUIT WITH RESONANT-FREQUENCY TUNABILITY - The present invention is directed to provide a low-power-consumption wide-range RF signal processing unit having a small chip occupation area. A semiconductor integrated circuit has, on a semiconductor chip, a resonant circuit including a first capacitor having a capacitance which can be controlled by a first control signal of a first control terminal, and a gyrator for equivalently emulating an inductor by including a second capacitor having a capacitance which can be controlled by a second control signal of a second control terminal. The capacitance and the inductor form a parallel resonant circuit. At the time of changing parallel resonant frequency, the capacitances of the first and second capacitors are coordinately changed. The parallel resonant circuit is suitable for an active load which is connected to an output node of an amplifier. | 2009-02-05 |
20090033441 | DIELECTRIC PORCELAIN COMPOSITION AND HIGH FREQUENCY DEVICE USING THE SAME - A dielectric porcelain composition of the present invention includes a first component and second component. If the first component is represented by the general formula of xBaO—yNd | 2009-02-05 |
20090033442 | NON-COPLANAR HIGH-SPEED INTERCONNECTS - In one example embodiment, a high-speed package includes first and second layers and a multi-channel non-coplanar interconnect. The first layer includes first and second sets of coplanar transmission lines. The second layer includes third and fourth sets of coplanar transmission lines. The multi-channel non-coplanar interconnect includes first and second channels. The first channel connects the first set of transmission lines to the third set of transmission lines. The second channel connects the second set of transmission lines to the fourth set of transmission lines. | 2009-02-05 |
20090033443 | Transmission line - A circuit board is provided, and a method for manufacturing the same, suitable for use in high frequency circuits, and comprising a planar pattern of transmission line conductors for linking components formed on or within the circuit board, the transmission line conductors being formed within a corresponding pattern of trenches arranged so that the conductors lie beneath a finished surface of the circuit board which is polished flat to permit one or more cover boards to be bonded thereto. | 2009-02-05 |
20090033444 | CONFIGURABLE HIGH FREQUENCY COAXIAL SWITCH - Various embodiments are provided herein for a configurable high frequency coaxial switch. The switch includes a switch housing module that has at least two ports and is adapted for operation in a wide frequency band. The switch also includes at least one frequency-matching port component module that is configured to connect a transmission line to one of the ports of the switch housing module. The at least one frequency-matching port component module is also configured to provide a match to a desired frequency range. In use, the switch housing module together with the at least one frequency-matching port component module allow for operation of the configurable high frequency coaxial switch at the desired frequency range. | 2009-02-05 |
20090033445 | MEMS actuators with stress releasing design - The micro-electromechanical (MEMS) actuator comprises a hot arm member and a cold arm member. The cold arm member comprises at least two longitudinally spaced-apart flexors. The actuators may also be constructed with at least one among the hot arm member and the cold arm member comprising at least one spring section. The stress in this improved MEMS actuator is more uniformly distributed, thereby reducing the mechanical creep and improving its reliability as well as its operation life. | 2009-02-05 |
20090033446 | Electromagnetic relay assembly - An electromagnetic relay enables current to pass through switch termini and comprises a coil assembly, a rotor or bridge assembly, and opposing, balanced switch assemblies. The coil assembly comprises a coil and a C-shaped core. The coil is wound round a coil axis extending through the core. The core comprises core termini parallel to the coil axis. The bridge assembly comprises a bridge and a pair of actuators. The bridge comprises medial, lateral, and transverse field pathways. The actuators extend laterally from the lateral field pathway. The core termini are coplanar with the axis of rotation and received intermediate the medial and lateral field pathways. The actuators are cooperable with the switch assemblies. The coil creates a magnetic field directable through the bridge assembly via the core termini for imparting bridge rotation about the axis of rotation. The bridge rotation displaces the actuators for opening and closing the switch assemblies. | 2009-02-05 |
20090033447 | Electromagnetic relay assembly - An electromagnetic relay enables current to pass through switch termini and comprises a coil assembly, a rotor or bridge assembly, and a switch assembly. The coil assembly comprises a coil and a C-shaped core. The coil is wound round a coil axis extending through the core. The core comprises core termini parallel to the coil axis. The bridge assembly comprises a bridge and an actuator. The bridge comprises medial, lateral, and transverse field pathways. The actuator extends laterally from the lateral field pathway. The core termini are coplanar with the axis of rotation and received intermediate the medial and lateral field pathways. The actuator is cooperable with the switch assembly. The coil creates a magnetic field directable through the bridge assembly via the core termini for imparting bridge rotation about the axis of rotation. The bridge rotation displaces the actuator for opening and closing the switch assembly. | 2009-02-05 |
20090033448 | Device Having a Shape Memory Element - Conventional devices have a valve needle and a shape memory element which, by the application of a controllable magnetic field, executes a control stroke travel that operates the actuator, and having a coil that excites the magnetic field which is situated in a magnet housing which, at its end face, is bordered with respect to an actuating axis by a front wall in each case, the front walls having a through opening radially within the coil. It is a disadvantage that the magnetic field excited around the coil is conducted unfavorably, so that at most a slight magnetic field develops in the shape memory element. The shape memory element has a magnetic field flowing through it, in the direction of its longitudinal extension, if at all. Since the shape memory element has a high magnetic resistance and is developed to be very long in the axial direction, only a very weak magnetic field can be induced in the shape memory element. In response to the magnetic field that is weak at most, the shape memory element can generate only a very slight lift of the valve needle. In the device according to the present invention, a strong magnetic field is conducted through the shape memory elements, and in this way, a large control stroke travel is achieved. The shape memory element(s) is/are positioned generally only in the through opening(s). | 2009-02-05 |
20090033449 | ELECTRONIC DEVICE - An electronic device includes a housing, a connecting member and a roller. The housing has a track and an aperture. The connecting member moves along the track. The roller rotatably connects with an end of the connecting member. The connecting member moves the roller to be exposed through the aperture or concealed in the housing. | 2009-02-05 |
20090033450 | LOW EDDY CURRENT CRYOGEN CIRCUIT FOR SUPERCONDUCTING MAGNETS - A low eddy current cryogen circuit for superconducting magnets including at least a first cooling coil made of an electrically conducting material and having at least one electrical isolator incorporated in the first cooling coil. The electrical isolator is located to inhibit induced eddy current loops due to inductive coupling of the first cooling coil with eddy current inducing field sources. | 2009-02-05 |
20090033451 | IGNITION COIL - An ignition coil includes a coil body, a plug connection portion protruding from the coil body, and a connector for electrically connecting the ignition coil to an outside. In the coil body, a primary coil is arranged on an inner peripheral side of a secondary coil, and a center core is arranged on an inner peripheral side of the primary coil. The secondary coil includes a secondary electric wire having thereon an insulating film, wound around an outer periphery of a resinous secondary spool. Furthermore, the connector is formed integrally with an end of the secondary spool in an axial direction. | 2009-02-05 |
20090033452 | IGNITION COIL - An ignition coil includes a coil body transversely arranged outside of a plug hole, and a plug connection portion protruding in a direction perpendicular to an axial direction of the coil body. A secondary coil of the coil body has a maximum outer diameter portion, and an inclined outer diameter portion arranged on two sides of the maximum outer diameter portion in the axial direction. The secondary coil includes a secondary electric wire that is wound obliquely around an outer periphery of a secondary spool such that reduced winding parts and enlarged winding parts are alternately superimposed on each other. The reduced winding part is wound with a winding diameter decreasing obliquely from one side to the other side in the axial direction, and the enlarged winding part is wound with a winding diameter increasing obliquely from the other side to the one side in the axial direction. | 2009-02-05 |
20090033453 | Power-circuit breaking device - For providing a power-circuit breaking device, which can easily mount a fuse and has a small number of component and a simple structure, the power-circuit breaking device includes a first connector housing having a pair of circuit terminals connected with a power circuit, and a second connector housing closing the power circuit by fitting with the first connector housing. The second connector housing includes a fuse having a pair of terminals to be connected with the pair of circuit terminals, a housing having a lock arm engaged with a cutout provided at the terminal and a cover an entry opening of a receiving section of the housing. The cover includes a limiter limiting the lock arm to move to disengaging the terminal. | 2009-02-05 |
20090033454 | MEMS actuators with even stress distribution - The micro-electromechanical (MEMS) switch comprises a first double-sided cantilever MEMS actuator attached to a substrate and movable in two opposite directions, and a second cantilever MEMS actuator attached to the substrate. In use, the first MEMS actuator is moved in either directions to distribute the stress more uniformly, thereby reducing the mechanical creep and improving its reliability as well as its operation life. | 2009-02-05 |
20090033455 | Antenna-Based Trigger - Described is a device including a processor, a wireless arrangement including an antenna, and a memory arrangement storing first data and second data. The first data includes predetermined antenna characteristics and the second data includes predetermined triggering characteristics for triggering a function of the device. When third data fails to match the first data, the processor compares the third data to the second data, the third data being indicative of characteristics changes of the antenna. The processor triggers a corresponding function of the device as a function of the third data and the second data. | 2009-02-05 |
20090033456 | Compact electronic security locker system - An embodiment of the present invention provides a compact electronic security locker system that includes an array of lockers, each of which is electronic locked and electronically accessed. One aspect of an embodiment of the present invention allows authorized personnel access to the identification of the person storing an article in a particular locker. In another aspect of an embodiment of the present invention, the storage lockers are arranged in a matrix of rows and columns and are constructed to have a size to accommodate items having a size of common cell phones. | 2009-02-05 |
20090033457 | Method for managing mobile operating devices - The invention relates to a method for managing mobile operating devices ( | 2009-02-05 |
20090033458 | Integrated apparatus for the control of the accesses - The invention relates to an integrated apparatus for the control of accesses, which can be used, in particular, coupled with an automated opening system for doors, main doors, gates and the like, wherein it comprises a single support element on which are disposed a section for the control of accesses and a section for the drive of the automated system. | 2009-02-05 |
20090033459 | VEHICLE DOOR LOCK CONTROL APPARATUS - A disclosed vehicle door lock control apparatus mounted in a vehicle for locking and unlocking the closed doors includes an automatic door locking unit locking the doors when no operation of opening a vehicle door is detected within a prescribed period of time-out time after the doors are unlocked by the user; and a time-out time determining unit determining the prescribed period of time-out time based on own vehicle position information. The time-out time determining unit, when the user requests to unlock the doors within a prescribed time after the doors are locked by the automatic door locking unit, learns that the prescribed period of time-out time with respect to an own vehicle position is to be extended. | 2009-02-05 |
20090033460 | System and Method for Operating a Transmitter With a Proximity Sensor - A system and method are provided that use at least one proximity sensor to illuminate a transmitter such that the transmitter can be seen by the user and/or to activate the transmitter so that the user can interface with the transmitter and send code to a receiver via the transmitter to effect an action, such as the opening or closing of a barrier or garage door. The transmitter can also be deactivated so that the proximity sensor is not continually triggering actions by the transmitter thereby potentially causing unwanted actions by the transmitter. | 2009-02-05 |
20090033461 | Biometric Access Control Protection - An access control system ( | 2009-02-05 |
20090033462 | Rf ID Tag Device - The present invention aims to overcome the drawback with conventional RFID tag devices having a short communication range, and expand the communication range to several times or more that in the conventional scheme. The conventional scheme is based on equilibrium feeding/equilibrium modulation (a two-terminal circuit for antenna operation), whereas the present invention is based on disequilibrium feeding/equilibrium modulation (a three-terminal circuit for antenna operation). The conventional scheme is based on simple rectification of received RF signals, whereas the present invention employs a circuit based on a combination of a stub resonance-based, impedance transformation boosting scheme and a ladder boosting scheme. The conventional scheme is based on ASK or BPSK modulation, whereas the present invention is based on passive modulation, but can employ a QPSK modulation circuit. | 2009-02-05 |
20090033463 | SWITCHABLE ACTIVE-PASSIVE RFID TAG - Various embodiments of the invention combine a passive RFID tag with a manually switchable battery for additional transmit range when needed. In some embodiments, connecting the battery may also modify the contents of the data transmitted from the RFID tag. This feature may be particularly useful in applications in which a device generally only needs to identify itself as being in a small area, but may occasionally need to send out an alert with greater range. | 2009-02-05 |
20090033464 | TRANSPONDER WITH ACCESS PROTECTION AND METHOD FOR ACCESS TO THE TRANSPONDER - A transponder is provided having at least one memory area, whereby the memory area is assigned an access password, the access password is assigned at least one attribute bit, and the length and/or structure of the access password can be set by the attribute bit. The invention relates further to a method for access to at least one access password-protected memory subarea of the transponder and to an RFID system comprising a transponder. | 2009-02-05 |