05th week of 2012 patent applcation highlights part 69 |
Patent application number | Title | Published |
20120030445 | ADVANCED PROCESSOR TRANSLATION LOOKASIDE BUFFER MANAGEMENT IN A MULTITHREADED SYSTEM - An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner. | 2012-02-02 |
20120030446 | METHOD AND SYSTEM FOR PROVIDING DISTRIBUTED PROGRAMMING ENVIRONMENT USING DISTRIBUTED SPACES, AND COMPUTER READABLE RECORDING MEDIUM - Disclosed herein are a method, a system, and a computer-readable recording medium for providing distributed programming environment by using a distributed space. | 2012-02-02 |
20120030447 | PROCESS, CIRCUITS, DEVICES, AND SYSTEMS FOR ENCRYPTION AND DECRYPTION AND OTHER PURPOSES, AND PROCESSES OF MAKING - A wireless communications device ( | 2012-02-02 |
20120030448 | SINGLE INSTRUCTION MULTIPLE DATE (SIMD) PROCESSOR HAVING A PLURALITY OF PROCESSING ELEMENTS INTERCONNECTED BY A RING BUS - A single instruction multiple data (SIMD) processor having a plurality of processing elements and including: a splitting unit for splitting an address of the read-only parameter data in the data memory into a first part and a second part at a bit position corresponding to the number of the processor elements; and a comparing unit for comparing the number of shifting, on a ring bus, of the read-only parameter data, which is taken from the internal memory at the address in accordance with the first part, with a difference between an own processor element position and a portion of the global address of the read-only parameter data to be accessed, the portion designating a position in the ring of the processor element in which the read-only parameter data to be accessed is stored and corresponding to the second part, to cause the other processor elements to take the read-only parameter data. | 2012-02-02 |
20120030449 | DATA TAG CONTROL FOR QUANTUM-DOT CELLULAR AUTOMATA - The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data tag using the local tag decoder, communicating the instructions to a processing element, communicating the data along a second wire-like element to the processing element, and processing the data with the processing element according to the instructions. A length of the first wire-like elements and a length of the second wire-like element are approximately the same such that communication of the instructions and the data to the processing element are synchronized. | 2012-02-02 |
20120030450 | METHOD AND SYSTEM FOR PARALLEL COMPUTATION OF LINEAR SEQUENTIAL CIRCUITS - A method and system for parallel computation of a linear sequential circuit (LSC) based on a state transition matrix is disclosed herein. A multistep state transition matrix and a multistep output generation matrix can be pre-computed and stored in association with the linear sequential circuit. The multiple state transitions and the multiple output bits can be computed by multiplying the current input-state vector with a multistep next state transition matrix and a multistep output generation matrix, respectively. Multiple state transitions and multiple output bits can be generated in parallel in a single clock cycle based on the pre-computed state transition matrix and the output generation matrix utilizing a dot product in order to improve computational speed. Such a simple augmentation provides a flexible and inexpensive solution for high speedup linear sequential circuit computation with respect to a processor. | 2012-02-02 |
20120030451 | PARALLEL AND LONG ADAPTIVE INSTRUCTION SET ARCHITECTURE - An Parallel and Long Adaptive Instruction Set Architecture (PALADIN) is provided to optimize packet processing. The Instruction Set Architecture (ISA) includes instructions such as aggregate comparison, comparison OR, comparison AND and bitwise instructions. The ISA also includes dedicated packet processing instructions such as hash, predicate, select, checksum and time to live adjust, move header left, post, move header left/right and load/store header/status. | 2012-02-02 |
20120030452 | MODIFYING COMMANDS - The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes a command queue configured to hold commands, and circuitry configured to modify at least a number of commands in the queue and execute the modified commands. | 2012-02-02 |
20120030453 | INFORMATION PROCESSING APPARATUS, CACHE APPARATUS, AND DATA PROCESSING METHOD - A more efficient technique is provided in an information processing apparatus which executes processing using pipelines. An information processing apparatus according to this invention includes a first pipeline, second pipeline, processing unit, and reorder unit. The first pipeline has a plurality of first nodes, and shifts first data held in a first node to a first node. The second pipeline has a plurality of second nodes respectively corresponding to the first nodes of the first pipeline, and shifts second data held in a second node to a second node. The processing unit executes data processing using the first data and the second data. The reorder unit holds one of the output second data based on attribute information of the second data output from the second pipeline, and outputs the held second data to the second pipeline. | 2012-02-02 |
20120030454 | SYSTEM AND METHOD FOR DYNAMICALLY CONFIGURING PROCESSING SPEEDS IN A WIRELESS MOBILE TELECOMMUNICATIONS DEVICE - There is disclosed a system and method executable in a wireless mobile communication device for dynamically configuring processing speed for a main processor in the device during device initialization. In an embodiment, the method comprises: initiating a boot-rom procedure; determining whether a battery is present in the device, and in response to the presence of the battery, determining whether the battery charge level is above a predetermined threshold; determining whether a USB connection to the device is present, and in response to the presence of a USB connection, enumerating the USB connection; and wherein, in response to the presence of the battery and the battery charge level being above a predetermined threshold, or in response to the USB connection being enumerated at a higher current, the processing speed of the main processor is increased. | 2012-02-02 |
20120030455 | Information handling system remote input/output connection system - An information handling system (IHS) remote input/output (I/O) connection system includes an enclosure having a power button, a communication bus connection point, and an audio connection point. A cable dongle extends from the enclosure. The cable dongle has a first end and a second end. The cable dongle also includes a connection from the power button on the enclosure on the first end to a communication connection point plug on the second end, which mates with a connection point plug on a remote I/O device card that enables a parallel (ACPI) S5-capable power button from the IHS to exist on the enclosure. The cable dongle further includes a communication cable coupled to the communication bus connection point on the first end and having a communication connection point plug on the second end. In addition, the cable dongle includes an audio cable coupled to the audio connection point on the first end and having an audio connection point plug on the second end. | 2012-02-02 |
20120030456 | Booting Devices Using Virtual Storage Arrays Over Wide-Area Networks - Virtual storage arrays consolidate data storage at a data center for physical and virtual computer systems at one or more branch network locations. Standalone and virtualized computer systems at a branch network location load, execute, and store their operating systems, applications, and data using virtual storage arrays and do not require any built-in or external non-volatile data storage devices such as hard disk drives or solid-state drives at the branch network location. The virtual disks of the virtual storage array are mapped to physical data storage at the data center and accessed via a WAN using storage block-based protocols. A storage block cache at the branch network location includes storage blocks prefetched based on knowledge about the computer systems at the branch network location and the behavior of their operating systems and applications. | 2012-02-02 |
20120030457 | OFFLOADING THE PROCESSING OF A NETWORK PROTOCOL STACK - A computer system is partitioned during a pre-boot phase of the computer system between a first partition and a second partition, wherein the first partition to include a first processing unit and the second partition to include a second processing unit. An Input/Output (I/O) operating system is booted on the first partition. A general purpose operating system is booted on the second partition. Network transactions are issued by the general purpose operating system to be performed by the I/O operating system. The network transactions are performed by the I/O operating system. | 2012-02-02 |
20120030458 | METHOD AND APPARATUS FOR BOOTING HOST - Provided are a method and a device for booting a host embodying a downloadable conditional access system (DCAS), wherein one of a plurality of pre-determined booting modes is decided as a booting mode of the host based on first information indicating whether a host can communicate with a broadcasting service provider and second information indicating whether a software-based security client providing information required for decrypting broadcasting data is installed to a hardware-based security module connected to the host, and the host is booted in the decided booting mode. | 2012-02-02 |
20120030459 | Secure Network Extension Device and Method - A network extension device comprising a CPU, memory, protected I/O connectable to local controls and peripherals, external communications port, a trusted device connected to the CPU such that it can provide attestation of the network extension device's trusted operation to a connected known external network, and a protected interface connected to at least one network extension module that includes a local network communications port. Optionally, a traffic encryption module may be provided, and the trusted device's attestation may include a check of its operation. Also, a method comprising connecting the network extension device to an external network, performing an operating mode check, causing the network extension device to operate in a mode and perform a security check that correspond to the result, causing the trusted device to attest trusted operation to the external network and thereafter causing the CPU to function fully and permitting access to the external network. | 2012-02-02 |
20120030460 | Authority-Neutral Certification for Multiple-Authority PKI Environments - A method for facilitating electronic certification, and systems for use therewith, are presented in the context of public key encryption infrastructures. Some aspects of the invention provide methods for facilitating electronic certification using authority-neutral service requests sent by an application, which are then formatted by a server comprising a middleware that can convert the authority-neutral request into certification authority specific objects. The server and middleware then return a response from a selected certification authority back to the service requesting application. Thus, the server and/or middleware act as intermediaries that facilitate user transactions in an environment having multiple certification authorities without undue burden on the applications or the expense and reliability problems associated therewith. | 2012-02-02 |
20120030461 | MOBILE CERTIFICATE DISTRIBUTION IN A PKI - A method of providing certificate issuance and revocation checks involving mobile devices in a mobile ad-hoc network (MANET). The wireless devices communicate with each other via Bluetooth wireless technology in the MANET, with an access point (AP) to provide connectivity to the Internet. A Certificate authority (CA) distributes certificates and certification revocation lists (CRLs) to the devices via the access point (AP). Each group of devices has the name of the group associated with the certificate and signed by the CA. A device that is out of the radio range of the access point may still connect to the CA to validate a certificate or download the appropriate CRL by having all the devices participate in the MANET. | 2012-02-02 |
20120030462 | SYSTEM AND DEVICE FOR ENCRYPTING AND DECRYPTING ELECTRONIC FILES AND METHOD THEREOF - A method for encrypting electronic files includes: receiving a request signal consisting of an IP address of a receiver and information about a desired electronic file; obtaining a function and the desired electronic file from a storage unit, and starting to time; obtaining a timing length when the electronic file has been obtained completely; substituting the timing length into the function to obtain an encryption key via an encryption module; and encrypting the electronic file using the encryption key. | 2012-02-02 |
20120030463 | DATA SECURE SYSTEM AND METHOD OF STORING AND READING DATA - A data secure system includes a computer host and a storage device having a certification signature. The computer host includes an encryption/decryption program, a data transceiver unit, an encryption module, and a decryption module. The data transceiver unit is communicatively connected to the storage device and an external device for receiving a raw data from the external device. The encryption module reads certification signature from the storage device via the encryption/decryption program, encrypts the raw data into an encryption data according to the certification signature, and stores the encryption data in the storage device. The decryption module reads the certification signature and the encryption data from the storage device via the encryption/decryption program and decrypts the encryption data according to the certification signature. Moreover, a method of storing and reading data is also provided. | 2012-02-02 |
20120030464 | SECRET SHARING SYSTEM, SHARING APPARATUS, SHARE MANAGEMENT APPARATUS, ACQUISITION APPARATUS, PROCESSING METHODS THEREOF, SECRET SHARING METHOD, PROGRAM, AND RECORDING MEDIUM - A secure secret sharing system is implemented. Shares SH(α, h(α)) are generated by secret sharing of secret information separately for each subset SUB(α); each of share management apparatuses PA(α, h(α)) generates a shared secret value DSH(α, h(α)) by performing a common operation to a corresponding share SH(α, h(α)) and common information containing a common value σ(α) shared in each subset SUB(α); and an acquisition apparatus generates a reconstructed secret value SUBSK(α) by reconstruction processing for each subset SUB(α), using a plurality of shared secret values DSH(α, h(α)) corresponding to the same subset SUB(α), and generates generation information SK by using the reconstructed secret values SUBSK(α). | 2012-02-02 |
20120030465 | Indirect Pairing of Communication Devices - A method for establishing a communication link between two devices, the communication link employing a protocol that provides for link establishment information sufficient for establishing a link between two devices to be negotiated between those devices; the method comprising: establishing communication links between each of the two devices and one or more further devices; transmitting from the one or more further devices to each of the two devices information that defines link establishment parameters for a link between the two devices; and establishing the link between the two devices using the defined link establishment parameters. | 2012-02-02 |
20120030466 | RELAY DEVICE, WIRELESS COMMUNICATIONS DEVICE, NETWORK SYSTEM, PROGRAM STORAGE MEDIUM, AND METHOD - A relay device first uses latest authentication data to determine whether request-authentication data transmitted from a wireless communications device is valid. If the latest authentication data is used to determine that the request-authentication data is valid, the relay device carries out relayed communications with the wireless communications device. If the latest authentication data is used to determine that the request-authentication data is invalid, the relay device next uses a former authentication data to determine whether the request-authentication data is valid. If the former authentication data is used to determine that the request-authentication data is valid, the relay device provides the wireless communications device with the latest authentication data to update authentication data in the wireless communications device. | 2012-02-02 |
20120030467 | METHODS AND SYSTEMS FOR FACILITATING COMMUNICATIONS BETWEEN VEHICLES AND SERVICE PROVIDERS - Methods and systems for facilitating communications between a vehicle and a service provider are provided. A first address of a vehicle communication device and a second address of a service provider communication device are obtained at a remote location that is remote to both the vehicle and the service provider. A set of keys, including a first key and a second key, is generated at the remote server. The first key is for use by the vehicle in establishing communications with the service provider, and the second key is for use by the service provider in establishing communications with the vehicle. The first key is provided to the vehicle, and the second key is provided to the service provider. | 2012-02-02 |
20120030468 | SYSTEM AND METHOD FOR OPTIMAL VERIFICATION OF OPERATIONS ON DYNAMIC SETS - A system and method for cryptographically checking the correctness of outsourced set operations performed by an untrusted server over a dynamic collection of sets that are owned (and updated) by a trusted source is disclosed. The system and method provides new authentication mechanisms that allow any entity to publicly verify a proof attesting the correctness of primitive set operations such as intersection, union, subset and set difference. Based on a novel extension of the security properties of bilinear-map accumulators as well as on a primitive called accumulation tree, the system and method achieves optimal verification and proof complexity, as well as optimal update complexity, while incurring no extra asymptotic space overhead. The method provides an efficient proof construction, adding a logarithmic overhead to the computation of the answer of a set-operation query. Applications of interest include efficient verification of keyword search and database queries. | 2012-02-02 |
20120030469 | Streamlined CSR Generation, Certificate Enrollment, and Certificate Delivery - The process of acquiring SSL certificates for enterprise SSL customers is improved by reducing the number of steps used to acquire the SSL certificate and streamlining the process. An on-line CSR generator on the certificate enrollment form is used to submit the customer information (i.e. Common Name, Organizational Unit, Organization, City/Locality, State/Province, and Country Code) and generate the CSR. By making the CSR generation part of the enrollment process, the administrator can use the same enrollment form to submit the customer information along with the contact information pertinent to the enterprise. | 2012-02-02 |
20120030470 | WIRELESS PROGRAMMING OF VEHICLE MODULES - A system and method for programming a vehicle module via a secure local area wireless connection. The method carried by the system involves establishing a wireless connection between a vehicle telematics unit and a dealership wireless node. Then, the dealership sends via the wireless node a digital certificate to the vehicle telematics unit. The vehicle uses the digital certificate to verify that the dealership is authorized to provide the vehicle with an upgrade to one or more of the vehicle's components. In response of the verification, an upgrade is performed to one or more vehicle components via the wireless communication. | 2012-02-02 |
20120030471 | DOWNLOAD MANAGEMENT SYSTEM - A download management system includes a server, a computer host and a storage device. The server stores an encrypted data, which is encrypted according to a certification signature. The computer host is communicatively connected to the server for executing a management program. The storage device is connected electrically to the computer host and includes the certification signature, wherein the download management execution program is capable of reading the certification signature from the storage device, downloading the encrypted data from the server, decrypings the encrypted data according to the certification signature to obtain a decrypted data, and storing the decrypted data in the storage device. | 2012-02-02 |
20120030472 | AUTHENTICATION METHOD, SYSTEM, SERVER, AND CLIENT - An authentication method is disclosed herein. The method includes: by a server, using a Trigger message nonce to generate a Trigger message, and sending the generated Trigger message to a client so that the client can extract the Trigger message nonce; after determining that the Trigger message nonce is valid, using the Trigger message nonce to generate a digest, and authenticating the Trigger message generated by using the Trigger message nonce; after the authentication succeeds, sending a session request to the server indicated by the Trigger message, where the session request carries a session ID. The corresponding system, server and client are disclosed herein. The present invention makes the authentication process more secure through the client and the server based on the DS or DM protocol. | 2012-02-02 |
20120030473 | UNIQUE BLOCK HEADER PATTERNS FOR MEDIA VERIFICATION - Authenticating the source of digital media is performed by using unique, randomly generated variably encoded frequency patterns to create mastering specific, profiles for sets end user media which can be verified by a manufacturer. A method for verifying the authenticity of an optical storage device includes the steps of: reading a randomly generated signature key value for the optical storage device; determining manufacturing information for the optical storage device; and matching read randomly generated signature key values and manufacturing information with known valid key the to determine the authenticity of the device. | 2012-02-02 |
20120030474 | System and Method for Personal Biometric Data Sequestering and Remote Retrieval with Power Checking - Provided is a sequestered personal match server apparatus and protocol for remote use, across common telecommunications technology or infrastructure, for establishing a blinded, zero-knowledge transaction between distributed computing devices, in which personal data is stored or retrieved and may be further transmitted or represented to the user's selected transaction counterparts, including boundary-keepers. A user may cloak their legal identification in some transaction or may substantiate it, since the capacity of proving the user's traceability to their legal identity is consistent with an electronic report issued to any user-queried interests indicating the success or failure of an attempt at accessing the data within the device. Biometrics and device sequestration are viewed as synergistic enhancements to scalability, including methods of power-checking any attempt at breach by or through various agencies of a commercial, private or public market. Transparency of use is further emphasized by relying upon common, mature electronics, which the user may bootstrap and use, unaided. The more important embodiments assume a role for a public witness agent or officer, during commissioning or first-use of said electronic device. A preferred embodiment further develops wireless networking synergies in approaching personal safety as an economic concern. | 2012-02-02 |
20120030475 | MACHINE-MACHINE AUTHENTICATION METHOD AND HUMAN-MACHINE AUTHENTICATION METHOD FOR CLOUD COMPUTING - A Machine-Machine Authentication method and a Human-Machine Authentication method for Cloud Computing. A Smart Card IC that includes a TPM/TCM/USB key function module and a storage memory, and a bio-feature identification method are used to achieve the Machine-Machine Authentication and Human-Machine Authentication. The Machine-Machine Authentication uses the Smart Card IC to achieve an authentication between the Server and the Client, and the Human-Machine Authentication uses the bio-feature identification method to achieve an authentication between the user and the Client or the user and the Server. | 2012-02-02 |
20120030476 | SYSTEM AND METHOD FOR AUTOMATICALLY COLLECTING OPINIONS - A system and a method for automatically collecting opinions are provided. The method for automatically collecting opinions according to the present invention comprises the steps of: distributing, to user terminals, content containing actual metadata corresponding to metadata items required for executing an opinion-collecting service program; and extracting opinions of users contained in the reply content received from user terminals, and compiling statistics with the extracted opinions. The present invention enables an automatic online collection of user opinions regarding voting, public opinion polls, surveys and other feedback via PCs or portable communication equipment, and automatically compiles statistics with the collected user opinions. | 2012-02-02 |
20120030477 | SCALABLE SEGMENT-BASED DATA DE-DUPLICATION SYSTEM AND METHOD FOR INCREMENTAL BACKUPS - A system in accordance with exemplary embodiments may provide a scalable segment-based data de-duplication for incremental backups. In the system, a master device on a secondary-storage node side may receive at least incremental changes, fingerprints, mapping entities, and distribute de-duplication functionality to at least a slave device, and performs data de-duplication on said plurality of segments via a way to cluster a plurality of fingerprints in a data locality unit called container for the incremental changes, varied sampling rates of a plurality of segments by having a fixed sampling rate for stable segments and by assigning a lower sampling rate for a plurality of unstable target files of de-duplication, and a per-segment summary structure to avoid unnecessary I/Os involved in de-duplication. | 2012-02-02 |
20120030478 | Dynamic Storage Enabler For Service Delivery HUB On A Mobility Network - A system includes a hub having interfaces to an application service provider and a portal in communication with an end user, a storage enabler connected to the hub, the storage enabler having application programming interfaces configured to receive a request for a storage facility from the application service provider and to allocate the storage facility based on the request for storage, and wherein the hub provides a single interface for the application service provider to request the storage facility when servicing the end user without regard to a location of the end user. The storage enabler is further configured to track data stored by one of the end user and the application service provider and to further provide encryption functionality. | 2012-02-02 |
20120030479 | STORAGE APPARATUS, HOST APPARATUS, AND STORAGE SYSTEM - Disclosed herein is a storage apparatus including: a first storage block configured to record and hold encrypted content data and output the encrypted content data on an on-demand basis; a second storage block configured to record and hold a confidential title key; a title stream key generation block configured to generate a title stream key corresponding to a subject of encryption of the content data by use of the held confidential title key; and a communication block configured to transmit the generated title stream key with confidentiality thereof held. | 2012-02-02 |
20120030480 | BATTERY PACK AND ELECTRONIC APPARATUS - A battery pack includes at least one rechargeable battery configured to output power; a remaining battery capacity detection unit configured to detect a remaining battery capacity of the at least one rechargeable battery; and a cryptographic unit configured to output a response word in response to an external request word by encrypting the external request word based on a cryptographic algorithm with a common code key. | 2012-02-02 |
20120030481 | Measuring Data Switching Activity in a Microprocessor - A mechanism is provided for approximating data switching activity in a data processing system. A data switching activity identification mechanism in the data processing system receives an identification of a set of data storage devices and a set of bits in the set of data storage devices in the data processing system to be monitored for the data switching activity. The data switching activity identification mechanism sums a count of the identified bits that have changed state for the data storage device along with other counts of the identified bits that have changed state for other data storage devices in the set of data storage devices to form an approximation of data switching activity. A power manager in the data processing system then adjusts a set of operational parameters associated with the data processing system using the approximation of data switching activity. | 2012-02-02 |
20120030482 | DATA PROCESSING HAVING MULTIPLE LOW POWER MODES AND METHOD THEREFOR - A method is provided for operating a data processing system having a memory. The memory is coupled between a first power supply voltage terminal for receiving a first variable potential and a second power supply voltage terminal for receiving a second variable potential. An initial difference between the first variable potential and the second variable potential is not less than a first voltage. The method comprises: receiving a command to transition the data processing system from a first power supply voltage to a second power supply voltage; changing the second variable potential so that a difference between the second variable potential and the first variable potential is greater than the first voltage; and after changing the second variable potential, changing the first variable potential, wherein a difference between the first variable potential and the second variable potential is not less than the first voltage. | 2012-02-02 |
20120030483 | COMPUTER SYSTEM - A computer system includes a power supply, a number of first power interfaces, a second power interface, and a voltage regulating module. The power supply includes a number of direct current (DC) voltage output terminals, to output a number of DC voltages to a motherboard of the computer system. The first power interfaces are connected to the DC voltage output terminals of the power supply, to output the DC voltages to first peripheral devices. The voltage regulating module includes an input terminal and an output terminal. The input terminal is connected to one of the DC voltage output terminals of the power supply, to receive the DC voltage from the connected DC voltage output terminal. The output terminal is connected to the second power interface, to output a regulated second voltage to a second peripheral device through the second power interface. | 2012-02-02 |
20120030484 | DISPLAY APPARATUS WITH DUAL-SCREEN AND DISPLAY METHOD THEREOF - A method applied in a display apparatus is provided. The display apparatus includes a first screen, a second screen, power signal means. The first screen is volatile. The second screen is non-volatile. The power signal means generate a power off signal in response to a user operation. The method includes: determining whether a power off signal is received; displaying a user interface on the first screen if the power off signal is received; controlling the display on the second screen in response to a user selection on the operation interface; generating a shutdown signal; and powering off the first screen, and the second screen when receiving the shutdown signal. | 2012-02-02 |
20120030485 | ELECTRONIC DEVICE - A USB electronic device with a power source loaded therein, which is connected to another USB electronic device via a USB connector, comprises a voltage detection unit that detects a voltage at an identification pin of the USB connector, a power supply control unit that controls connection/disconnection between a power supply pin of the USB connector and the power source based upon a change in voltage at the identification pin detected by the voltage detection unit and an allow/disallow control unit that executes control to allow/disallow detection of the voltage change at the identification pin. | 2012-02-02 |
20120030486 | POWER MANAGEMENT SYSTEM FOR WIRELESS AUTONOMOUS TRANSDUCER SOLUTIONS - An autonomous transducer system is disclosed. In one aspect, the system includes an energy scavenging module, energy storage module, a load circuit having at least one functional block providing a given functionality, and a power management module arranged for providing power supplied by the energy scavenging module to the load circuit or for exchanging power with the energy storage module. The power management module may further include a tuning module configured to tune the at least one functional block of the load circuit according to a given configuration scheme. | 2012-02-02 |
20120030487 | INFORMATION PROCESSING APPARATUS AND POWER CONTROL METHOD - According to one embodiment, an information processing apparatus includes a first circuit, a second circuit, and a controller. The first circuit is configured to detect consumed power of the information processing apparatus. The second circuit is configured to supply power received from a battery or an external power supply device, to a component in the information processing apparatus. The controller is configured to control the second circuit to receive the power from both of the battery and the external power supply device when the consumed power detected by the first circuit is higher than a capacity of the external power supply device. | 2012-02-02 |
20120030488 | METHOD AND APPARATUS FOR INDICATING MULTI-POWER RAIL STATUS OF INTEGRATED CIRCUITS - Methods and apparatus provide for indicating multi-power rail status of integrated circuits by taking into account a clock signal provided by, for example, core logic, in addition to considering voltage levels of multiple power rails. In one example, the apparatus includes multi-power rail status indicating logic that provides a multi-power rail status signal. The multi-power rail status signal is synchronized for assertion with a clock signal of the integrated circuit, such as the core logic of the integrated circuit, in response to an assertion of an asynchronous multi-power rail voltage stability signal. The asynchronous multi-power rail voltage stability signal indicates a state of a plurality of voltage signals from a plurality of power rails supplied to the integrated circuit. The multi-power rail status indicating logic may include a synchronous assertion/asynchronous de-assertion multi-power rail status signal generator that receives the clock signal and the asynchronous multi-power rail voltage stability signal, and in response to of the assertion of the asynchronous multi-power rail voltage stability signal, synchronizes the asynchronous multi-power rail voltage stability signal with the clock signal to assert the multi-power rail status signal. | 2012-02-02 |
20120030489 | Power supply control within an integrated circuit - An integrated circuit | 2012-02-02 |
20120030490 | COMMUNICATION SYSTEM - A communication system includes a network formed by a plurality of control units, each operated in a high power consumption mode and a low power consumption mode. A selected one or more of the control units act solely or in cooperation with each other to implement a specific function. Each of the selected one or more of the control units related to the specific function is set in the high power consumption mode. Each of the non-selected control units unrelated to the specific function is set in the low power consumption mode. | 2012-02-02 |
20120030491 | ELECTRICAL APPARATUS AND POWER SUPPLY CONTROL METHOD - An electrical apparatus has a controller for switching between a normal power mode and power saving modes. A receiver receives instructions for a manipulation on the apparatus. A switch controller switches to a first power saving mode when no instruction for manipulation is received within a first standby time in the normal power mode, switches to a second and lower power saving mode when no instruction for manipulation is received and the time reaches a preset second standby time in the first power saving mode, switches to the normal power mode when an instruction for manipulation is received when the apparatus is in the first or second power saving mode, and switches to the second or a third power saving mode for supplying less power than the first power saving mode but more than the second when the time reaches the first standby time if a predetermined condition is satisfied. | 2012-02-02 |
20120030492 | SERVER SYSTEM - The present invention provides a server system comprising a first group of mainboard modules and a second group of mainboard modules, each of the first and second groups of mainboard modules including a plurality of mainboard modules. Each mainboard module includes a mainboard and a daughter board electrically connected to the mainboard; a first adaptor and a second adaptor; a hard disk array including a hard disk backplane and a plurality of hard disks, wherein the hard disk backplane is electrically connected to the first adaptor and the second adaptor; a first power control board and a second power control board respectively connected to at least one power supply, wherein the first power control board and the second power control board are electrically connected to the hard disk array; and a management board electrically connected to the first adaptor and the second adaptor. | 2012-02-02 |
20120030493 | Power Capping System And Method - A system, and a corresponding method, for temporarily capping power consumption includes a mechanism for determining total power consumption by a number of components, a mechanism for disconnecting and reconnecting power to one or more of the components, and a mechanism for determining when to disconnect and reconnect power to the components. | 2012-02-02 |
20120030494 | POWER SUPPLY SELECTOR AND POWER SUPPLY SELECTION METHOD - In the field of electronic technologies, a power supply selector and a power supply selection method are provided. The power supply selector includes: a first selection module, configured to select a power supply from multiple candidate power supplies; a control module, coupled to the first selection module, and configured to use the power supply selected by the first selection module as a power supply, and compare voltages of the multiple candidate power supplies to generate a control signal of each candidate power supply; and a second selection module, coupled to the control module, and configured to select a power supply for output in the multiple candidate power supplies under the control of the control signal of each candidate power supply. The technical solution is used to select a power supply from multiple candidate power supplies. | 2012-02-02 |
20120030495 | Clock Distribution in a Distributed System with Multiple Clock Domains Over a Switched Fabric - System and method for synchronizing devices. A device reads a first counter coupled to and associated with a master clock and a second counter coupled to and associated with the device, where the device is one of one or more devices coupled to the master clock and each other via a switched fabric, where each device includes a respective clock, and is coupled to and associated with a respective second counter. Each of the first counter and the second counters is accessible by each of the one or more devices. The device determines a difference between the device's associated second counter and the first counter, and determines and stores a time reference for the device relative to the master clock based on the determined difference, where the time reference is useable to timestamp events or synchronize future events. | 2012-02-02 |
20120030496 | Specification of Isochronous Data Transfer in a Graphical Programming Language - System and method for transferring data. A system diagram is displayed, where the system diagram includes multiple device icons corresponding to respective devices, each device icon having associated executable function nodes specified for deployment on the corresponding device. The function nodes are interconnected to form a distributed graphical program that is deployable and executable in a distributed manner on the devices. User input is received to the system diagram specifying isochronous data transfer among the function nodes. Invocation timing relationships among the function nodes are automatically determined based on the specified isochronous data transfer, including phase relationships between execution of the function nodes. The determined invocation timing relationships are displayed among the function nodes. The graphical program is deployable and executable in a distributed manner on the devices according to the determined invocation timing relationships, where during execution of the graphical program, data are transferred isochronously between the function nodes. | 2012-02-02 |
20120030497 | CONTROL CIRCUIT AND OPERATING METHOD THEREOF - A control circuit includes a plurality of clock synchronization units configured to shift an input signal in response to clock signals which are inputted thereto, a selection output block configured to select an output signal from output signals of the plurality of clock synchronization units, and output the selected output signal, and a clock supply block configured to sequentially supply the clock signals to the plurality of clock synchronization units. | 2012-02-02 |
20120030498 | INTERACTIVE DEVICE WITH TIME SYNCHRONIZATION CAPABILITY - An interactive device having time synchronization capability is provided. In one embodiment, the interactive device has a computer processor that stores an internal clock. The computer processor may be preprogrammed to generate announcements based on a particular time of the internal clock. A user may input and adjust the time of the internal clock. In another embodiment, a setup module is provided which includes a computer processor that stores a setup time. The setup module establishes a connection with an interactive device, and time synchronizes the interactive device such that the internal clock of the interactive device is running the same time as the setup module. The setup module is capable of synchronizing the internal clock of multiple interactive devices, despite the interactive devices being programmed on separate occasions. The interactive device may be synchronized by the setup module via a hard-wired connection or wireless means. | 2012-02-02 |
20120030499 | Distribution of an incrementing count value - Circuitry is disclosed that comprises: at least one element located within the circuitry and configured to hold an increasing count value; an encoder for receiving the increasing count value from a source of the increasing count value and configured to encode the increasing count value into encoded values, the encoded values each indicating an exponential amount to be applied to the count value held in the at least one element; interconnect circuitry for receiving the encoded value and transmitting the encoded value to the at least one element; wherein the at least one element comprises a decoder for decoding the encoded values and for increasing the count value in dependence upon the exponential amount. | 2012-02-02 |
20120030500 | Hysteresis Management in SOI Data Processing Circuits - Embodiments of systems and methods are described for reducing the effects of hysteresis in the operation of data processing circuitry. In this embodiment of the invention, adaptive control circuitry is used to reduce the effects of hysteresis. The embodiment disclosed herein provides significant reduction in the effects of hysteresis and, therefore, a significant reduction in the amount of guard band needed to compensate for hysteresis effects in SOI processes and thereby improving the performance/power characteristics of the circuit. | 2012-02-02 |
20120030501 | AUTOMATIC DETERMINATION OF SUCCESS OF USING A COMPUTERIZED DECISION SUPPORT SYSTEM - Methods and systems are provided for improving the repair efficacy of a repair action using inferred feedback. The method comprises downloading a repair procedure, which has a probability of success for correcting the fault code. Repair action data is input into to the computing device and is tracked and correlated with the downloaded procedure. The method then adjusts a probability of success of the repair procedure in clearing the fault code generated by the complex system based at least on the correlation. The system comprises a means for receiving repair data, a means for tracking repair action data taken, a means for correlating the tracked repair action and the repair data, and a means for updating a probability of success of the repair action based at least in part on the correlation of the repair data, the repair action data and the operating status of the complex system. | 2012-02-02 |
20120030502 | TENANT RESCUE FOR SOFTWARE CHANGE PROCESSES IN MULTI-TENANT ARCHITECTURES - A multi-tenant system can be switched to a downtime state to implement a transition from a current state to a target state of a core software platform. During a second phase of the transition an error associated with tenant-specific content of a first customer tenant of the plurality of customer tenants of the multi-tenant system can be identified. The second phase can be suspended for the first customer tenant while continuing the second phase for a remainder of the plurality of customer tenants for which an error has not been identified. After a scheduled duration of the downtime state, the multi-tenant system can be reactivated such that the multi-tenant system includes the remainder of the plurality of customer tenants with the transition implemented and the first customer tenant either with the transition implemented if the error has been corrected or without the transition implemented if the error has not been corrected. | 2012-02-02 |
20120030503 | System and Method for Providing High Availability for Distributed Application - A system and method is provided for ensuring high availability for a distributed application. A management object manages multiple scenarios defined for protection units associated with a distributed application. The management object may coordinate various operations performed at the protection units based on management object configuration information. | 2012-02-02 |
20120030504 | HIGH RELIABILITY COMPUTER SYSTEM AND ITS CONFIGURATION METHOD | 2012-02-02 |
20120030505 | Method and Apparatus for Calendaring Reminders - An electronic calendar includes such features as recurring reminders, dividing unpredictable work loads into equal pieces, template free parsing, a reminders scheduling algorithm to reduce spikes, dynamic delivery and recovery algorithms, methods for splitting the work load between controllers and workers and for monitoring progress, all within the context of a calendar architecture for a large enterprise. | 2012-02-02 |
20120030506 | READ DISTURB SCORECARD - Systems and methods are disclosed for handling read disturbs based on one or more characteristics of read operations performed on a non-volatile memory (“NVM”). In some embodiments, a control circuitry of a system can generate a variable damage value determined based on one or more characteristics of a read operation. Using the damage value, the control circuitry can update a score associated with the block. If the control circuitry determines that the score exceeds a pre-determined threshold, at least a portion of the block can be relocated to a different memory location in the NVM. In some embodiments, portions of the block may be relocated over a period of time. | 2012-02-02 |
20120030507 | DATA STORAGE DEVICE - A data storage device includes an interface that is configured to interface with a host, a command bus, multiple memory devices that are operably coupled to the command bus and a controller that is operably coupled to the interface and to the command bus. The controller is configured to receive a verify on write command from the host using the interface, write data to one of the memory devices, read the data from the memory device, calculate an error correction code for the data as the data is being read, verify the data was written correctly to the memory device using the error correction code and communicate results to the host using the interface. | 2012-02-02 |
20120030508 | DATABASE SYSTEM CONFIGURED FOR AUTOMATIC FAILOVER WITH USER-LIMITED DATA LOSS - Techniques used in an automatic failover configuration having a primary database system, a standby database system, and an observer. In the automatic failover configuration, the primary database system remains available even in the absence of both the standby and the observer as long as the standby and the observer become absent sequentially. The failover configuration may use asynchronous transfer modes to transfer redo to the standby and permits automatic failover only when the observer is present and the failover will not result in data loss due to the asynchronous transfer mode beyond a specified maximum. The database systems and the observer have copies of failover configuration state and the techniques include techniques for propagating the most recent version of the state among the databases and the observer and techniques for using carefully-ordered writes to ensure that state changes are propagated in a fashion which prevents divergence. | 2012-02-02 |
20120030509 | MECHANISM FOR MAINTAINING CACHE SOFT REPAIRS ACROSS POWER STATE TRANSITIONS - A processor core includes one or more cache memories and a repair unit. The repair unit may repair locations in the cache memories identified as having errors during an initialization sequence. The repair unit may further cause information corresponding to the repair locations to be stored within one or more storages. In response to initiation of a power-down state of a given processor core, the given processor core may execute microcode instructions that cause the information from the one or more storages to be saved to a memory unit. During a recovery of the given processor core from the power-down state, the processor core may execute additional microcode instructions that cause the information to be retrieved from the memory unit, and saved to the one or more storages. The repair unit may restore repairs to the locations in the cache memories using the information. | 2012-02-02 |
20120030510 | METHOD TO RECOVER DATA SECTOR DAMAGED BY ABRUPT POWER LOSS IN HARD DISK DRIVES - A hard disk drive that is coupled to a non-volatile memory. The non-volatile memory includes data that was designated to be stored in the hard disk drive in a previous time period. When a power loss event is detected the hard disk drive stores the track address of the last written track in non-volatile memory. When power is returned, the hard drive retrieves the last track address from the non-volatile memory. The data can then be rewritten onto the last track. Such an approach allows relatively large sectors of 4 Kbytes to be recaptured after a power loss event. | 2012-02-02 |
20120030511 | EFFICIENT FAILURE RECOVERY IN A DISTRIBUTED DATA STORAGE SYSTEM - A method is provided for efficiently recovering information in a distributed storage system where a list of values that should be stored on a storage device is maintained. A first convergence round is scheduled to be performed on the list of values to bring each value to an At Maximum Redundancy (AMR) state. A second convergence round is scheduled to be performed on the list by selecting a wait time interval from a predefined range of wait time intervals between starts of convergence rounds. | 2012-02-02 |
20120030512 | PROVISIONING OF DATA TO A VEHICLE INFOTAINMENT COMPUTING SYSTEM - Various embodiments include a software provisioning system and method for a vehicle infotainment computer. Software provisioning of the vehicle infotainment computer may occur during vehicle assembly. A software provisioning request may be received for custom installing software to the vehicle infotainment computer. The custom install may be based on a customization schedule which may include a location identifier (such as uniform resource identifiers or file paths) for locating the software. In response to the request, the software may be located on a provisioning server or a portable memory device based on the customization schedule. The software may be transmitted to memory of the vehicle infotainment computer and custom installed on the vehicle infotainment computer. | 2012-02-02 |
20120030513 | Mechanism to Provide Assured Recovery for Distributed Application - A system and method is provided for providing assured recovery for a distributed application. Replica servers associated with the distributed application may be coordinated to perform integrity testing together for the whole distributed application. The replica servers connect to each other in a manner similar to the connection between master servers associated with the distributed application, thereby preventing the replica servers from accessing and/or changing application data on the master servers during integrity testing. | 2012-02-02 |
20120030514 | MODULE TESTING ADJUSTMENT AND CONFIGURATION - In one embodiment, a method for testing adjustment and configuration is disclosed. The method can include accessing source code of a test framework that is configured for testing a module, creating a configuration folder having a property override for a test suite for the module testing, determining a source root folder for the test suite, starting the test framework by passing in an identifier for the test suite, and adding a custom test to the source root folder using the configuration folder to customize the test suite. The method can further include compiling the test framework with each of the plurality of test folders enabled. The method also may use a refactoring tool to make changes in a file within the test framework. | 2012-02-02 |
20120030515 | USE OF ATTRIBUTE SETS FOR TEST ENTITY IDENTIFICATION DURING SOFTWARE TESTING - An attribute collector may collect an attribute set for each test entity of a plurality of test entities associated with a software test executed in a software environment. An attribute analysis signal handler may receive an attribute analysis signal associated with a change in the software environment, and a view generator may provide an attribute-based view associated with an affected attribute set associated with the change, the attribute-based view identifying an affected test entity that is affected by the change. | 2012-02-02 |
20120030516 | METHOD AND SYSTEM FOR INFORMATION PROCESSING AND TEST CARE GENERATION - A method and system for information processing and test case generation. The system includes: a pattern storage module for storing at least one resource identifier patterns, where the resource identifier patterns are extracted from a server code of a web application by analyzing the server code; a client code analyzer module for analyzing a client code generated from the server code and finding at least one event sequences matching with the resource identifier patterns; and a test case generator module for fetching a client state established from the client code, executing the event sequences on the client state, and generating a test case, where the test case includes a second resource identifier generated as an execution result of the event sequence. | 2012-02-02 |
20120030517 | EXPOSING APPLICATION PERFORMANCE COUNTERS FOR .NET APPLICATIONS THROUGH CODE INSTRUMENTATION - Disclosed is a method for adding performance counters to a .NET application after compilation of the .NET application to Common Intermediate Language code without a requirement for code changes to the original .NET application code or application recompilation from the development side. With regard to a further aspect of a particularly preferred embodiment, the invention may provide a method for adding the performance counters by declarative instrumentation of a .NET application at runtime or compile time, without the need for an application developer to hardcode instrumentation logic into the application. An instrumentation configuration file provides declarative definition for performance counters that are to be added to a particular application, and particularly includes a complete list of performance counters that need to be added and settings for each performance counter. | 2012-02-02 |
20120030518 | LAST BRANCH RECORD INDICATORS FOR TRANSACTIONAL MEMORY - In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed. | 2012-02-02 |
20120030519 | INTEGRATED DISSIMILAR HIGH INTEGRITY PROCESSING - A self-checking network is provided, comprising a first command processor configured to execute a performance function and a second command processor configured to execute the performance function, coupled to the first command processor. The self-checking network also comprises a first monitor processor configured to execute a monitor function that is coupled to the first command processor and a second monitor processor configured to execute the monitor function that is coupled to the second command processor. The first and second command processors compare outputs, the first and second monitor processors compare outputs, and the first monitor processor determines whether an output of the first command processor exceeds a first selected limit. | 2012-02-02 |
20120030520 | Storage and output of trace data - A trace output unit for collecting, buffering and outputting trace data generated by trace circuitry monitoring processing activities of a data processing apparatus is described. The trace output unit comprises an input for receiving a stream of trace data; a plurality of data stores arranged in parallel with each other for storing the trace data; and storage control circuitry for controlling storage of items of the trace data in the data stores. The control circuitry is configured to route the trace items to selected ones of the data stores and to store control data identifying related trace items stored in different data stores. The trace output unit further comprises output control circuitry configured to identify related trace items stored in different data stores from the stored control data and to recombine the related trace items from different data stores to form an output trace data stream. | 2012-02-02 |
20120030521 | SELECTIVE BRANCH-TRIGGERED TRACE GENERATION APPARATUS AND METHOD - A method for selectively generating trace data is disclosed. Such a method includes executing a first module on a processor. The processor is operably coupled to a memory storing the first module and one or more branch modules. The method further includes detecting the execution of an instruction of the first module to execute a branch module. In response to detecting execution of the instruction, traces of branch modules subsequently executed by the processor are generated. Upon detecting a return of execution by the processor to the first module, the generation of traces is terminated and a trace report is generated. A corresponding apparatus and computer program product are also disclosed herein. | 2012-02-02 |
20120030522 | FAULT CAUSE EXTRACTION APPARATUS, FAULT CAUSE EXTRACTION METHOD, AND PROGRAM RECORDING MEDIUM - Performance information which is a possible generation cause of a fault is extracted accurately. | 2012-02-02 |
20120030523 | Alarm Threshold For BGP Flapping Detection - Methods and systems are described that improve the alarming logic for Border Gateway Protocol (BGP) flapping events. Embodiments provide an alarm threshold on BGP flapping conditions and alert on BGP related events. A reduction in silent failures and network outage minutes is achieved. | 2012-02-02 |
20120030524 | HIGH RELIABILITY METHOD OF DATA PROCESSING, AND CONTROLLER UNIT - In a method of data processing within a controller ensuring that voting operations are reliably performed error free and in a corresponding controller unit, the input data are characteristic for the particular application where voting occurs. Voting whether or not the incoming data is correct involves a voting comparison method, a voting average method, and checking for a difference being within a certain range. The time dependent signature indicates correctly transmitted input data. Voting, based on the reviewed signature characteristics is an encoded operation. The time dependent signature indicates the data is coming from a correct source, has been a modification, and correct timing slides. Voting whether or not the incoming data is correct is performed in an encoded manner. A correct data is transmitted to be further used to actuate an actuator. The erroneous data is transmitted to be further sent to a fail safe guard. | 2012-02-02 |
20120030525 | NOTIFICATION SYSTEMS AND METHODS WHERE A NOTIFIED PCD CAUSES IMPLEMENTATION OF A TASK(S) BASED UPON FAILURE TO RECEIVE A NOTIFICATION - Systems and methods are disclosed for automated notification systems. A representative system, among others, can be summarized as follows. A host computer system, or base station, is designed to monitor travel data corresponding to a mobile thing and to initiate a notification communication to a personal communications device (PCD) indicating travel status of the mobile thing (MT) to a remote computer system. The remote computer system, within or associated with the PCD, is designed to detect a failure to receive the notification communication and to cause one or more tasks to be performed based upon the notification communication failure. | 2012-02-02 |
20120030526 | COMMUNICATION DEVICE - A communication device includes a receiving unit, a first determining unit, and a sending unit. The receiving unit is configured to receive, from a terminal device, a plurality of input values corresponding to a plurality of setting items. The first determining unit, when the plurality of setting items includes a plurality of related items that are related to each other, is configured to determine whether input values, among the plurality of input values, corresponding to the plurality of related items are compatible. The sending unit is configured to send error data indicating an error screen toward the terminal device when the input values corresponding to the plurality of related items are incompatible, the error screen showing that at least one input value among the plurality of input values has an error. | 2012-02-02 |
20120030527 | SEMICONDUCTOR MEMORY DEVICE - Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. | 2012-02-02 |
20120030528 | SEMICONDUCTOR STORAGE DEVICE - As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value. | 2012-02-02 |
20120030529 | REFRESH OF NON-VOLATILE MEMORY CELLS BASED ON FATIGUE CONDITIONS - In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block. | 2012-02-02 |
20120030530 | DETERMINISTIC DATA VERIFICATION IN STORAGE CONTROLLER - Exemplary method, system, and computer program embodiments for performing deterministic data verification by a storage controller are provided. Each of a plurality of concurrent write tasks is configured to be placed in a plurality of overlapping data storage ranges by performing at least one of: implementing a data generation function for generating pseudo-random data using a data seed, and generating a range map, the range map utilized as a lookup data structure to verify a chronological order for performing the plurality of concurrent write tasks, wherein a data address space is first designated in the range map as undetermined. Each of a plurality of read tasks is analyzed by comparing data read from a sub range in the plurality of overlapping data storage ranges against the data seed associated with the sub range. | 2012-02-02 |
20120030531 | Safe Memory Storage By Internal Operation Verification - The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous. | 2012-02-02 |
20120030532 | STRUCTURES AND CONTROL PROCESSES FOR EFFICIENT GENERATION OF DIFFERENT TEST CLOCKING SEQUENCES, CONTROLS AND OTHER TEST SIGNALS IN SCAN DESIGNS WITH MULTIPLE PARTITIONS, AND DEVICES, SYSTEMS AND PROCESSES OF MAKING - A scannable integrated circuit ( | 2012-02-02 |
20120030533 | IMPLEMENTING SWITCHING FACTOR REDUCTION IN LBIST - A method and circuit are provided for implementing switching factor reduction in Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides. Switching factor reduction logic is coupled to a Pseudo-Random Pattern Generator (PRPG) providing channel input patterns to a plurality of LBIST channels used for the LBIST diagnostics. The switching factor reduction logic selectively provides controlled channel input patterns for each of the plurality of channels. | 2012-02-02 |
20120030534 | PHYSICAL UPLINK SHARED CHANNEL ENCODER FOR USER EQUIPMENT MODEM AND ENCODING METHOD OF THE SAME - Provided are a Physical Uplink Shared CHannel (PUSCH) encoder and an encoding method of the same. The PUSCH encoder includes a plurality of encoding units and a channel interleaving unit interleaving the data transferred from the plurality of encoding units. Herein, the respective encoding units perform encoding operations on different data. The PUSCH encoder is configured to perform the respective encoding operations in parallel. In accordance with the PUSCH encoder and the encoding method thereof, the encoding operations are performed on different data in parallel to reduce latency, leading to an increase in processing speed of a codec system. Furthermore, the increase in processing speed of the codec system results in the improvement of performance and throughput per unit hour in a data communication system. | 2012-02-02 |
20120030535 | Distributed Block Coding (DBC) - Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement. | 2012-02-02 |
20120030536 | Initializing Decoding Metrics - A method includes, during a first iteration of a first decoder for decoding convolutionally encoded data elements, determining a first value of a first path metric. The method also includes, during a second iteration of the first decoder, determining a second value of the first path metric by using the first value of the first path metric as an initial value of the first path metric. | 2012-02-02 |
20120030537 | SYMBOL ENCODING FOR TOLERANCE TO SINGLE BYTE ERRORS - The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol. | 2012-02-02 |
20120030538 | Forward Error Correction Decoding - A system may be used to predict when a decoding process will fail to correct an error burst within a transmission. A decoder may receive an input bit stream and process it to produce an output bit stream, which may be convolutionally encoded. K-bits of the convolutionally encoded output bit stream may be compared with a corresponding k-bits of a delayed version of the input bit stream, with the k-bits starting at a first bit and ending at first bit+k. For each bit of the k-bits in the convolutionally encoded output bit stream and in the corresponding k-bits of the delayed version of the input bit stream, a number of conflicting bits and whether the number of conflicting bits exceeds a threshold number of conflicting bits may be determined. The output bit stream may be sent to a block decoding component for decoding with the bits marked for erasure. | 2012-02-02 |
20120030539 | ERROR-FLOOR MITIGATION OF CODES USING WRITE VERIFICATION - Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous too bits, and (iii) stores the erroneous-bit indices to a record in a table. At some later time, the written codeword is read and sent to a decoder. If the decoder fails with a near codeword, a write-error recovery process searches the table and retrieves the erroneous-bit information. The codeword bits at those indices are adjusted, and the modified codeword is submitted to further processing. | 2012-02-02 |
20120030540 | RAM MEMORY DEVICE SELECTIVELY PROTECTABLE WITH ECC - An SRAM memory device including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; each row of memory cells is adapted to store a RAM word; the RAM word includes a corresponding data word, a corresponding ECC word to be used for error detection and correction purposes and a corresponding applicative word to be used during debugging operations. The SRAM memory device further includes a configurable port adapted to receive a RAM word and to program corresponding memory cells of a selected row based on the received RAM word during a writing access of the SRAM memory device. The SRAM memory device further includes a memory controller unit including circuitry for selectively configuring the configurable port in one among a plurality of modes. The plurality of modes includes a first mode, wherein the configurable port is configured in such a way to disable the programming of the data word and of the corresponding ECC word of the received RAM word and at the same time enable the programming of the applicative word of the received RAM word during the writing access. The plurality of modes includes a second mode, wherein the configurable port is configured in such a way to disable the programming of the applicative word of the received RAM word and at the same time enable the programming of the data word and of the corresponding ECC word of the received RAM word during the writing access. | 2012-02-02 |
20120030541 | TRANSMISSION DEVICE, RECEPTION DEVICE, TRANSMISSION METHOD, AND RECEPTION METHOD - In a transmission device, a determining unit determines, for use in transmission, an LDPC encoding method corresponding to occurrence conditions of external noise from a plurality of LDPC encoding methods each having the same code length and the same code rate and being defined by a different parity check matrix, and an encoding unit generates a codeword bit sequence by encoding transmission data using the LDPC encoding method determined by the determining unit. | 2012-02-02 |
20120030542 | DATA STORAGE DEVICE - A data storage device includes an interface that is configured to interface with a host, a command bus, multiple memory devices that are operably coupled to the command bus and a controller that is operably coupled to the interface and to the command bus. The controller is configured to receive a copy command from the host using the interface, read data from a source memory device in response to the copy command, write the data to a destination memory device in response to the copy command and communicate results to the host using the interface. | 2012-02-02 |
20120030543 | PROTECTION OF APPLICATION IN MEMORY - A method, a memory controller and a processor architecture for protecting an application in a memory are disclosed. The application is cached as memory lines according to a size of a cache line. For example, the method comprises: in response to a load access request from a processor, reading from the memory a flagged memory line and an ECC checksum corresponding to the memory line, wherein the flagged memory line is obtained by performing a logic operation on a predetermined bit of the memory line and a flag bit for identifying the memory line; performing an ECC check on the flagged memory line by using the ECC checksum to obtain a value of the flag bit of the memory line; restoring the flagged memory line to the memory line according to the value of the flag bit; and determining whether or not to load the memory line according to the value of the flag bit and the type of the load access request from the processor. | 2012-02-02 |
20120030544 | Accessing Memory for Data Decoding - A method comprises receiving a sequence of unique memory addresses associated with concatenated, convolutionally encoded data elements. The method also comprises identifying each of the unique memory addresses as being included in one group of a plurality of address groups. Each address group substantially includes an equivalent number of unique addresses. The method also comprises, in parallel, accessing at least one memory address associated with each group of the plurality of address groups to operate upon the respective concatenated, convolutionally encoded data elements associated with each of the unique memory addresses being accessed. | 2012-02-02 |