05th week of 2012 patent applcation highlights part 18 |
Patent application number | Title | Published |
20120025336 | CONVERTER MODULE AND METHOD OF MANUFACTURING THE SAME - To provide a converter module easily achieving miniaturization and profile reduction without decreasing the pressure detection sensitivity. The converter module includes: a converter which converts vibration of a diaphragm into an electric signal; and a semiconductor substrate which processes the electric signal obtained as a result of the conversion performed by the converter. The converter includes: a base including a cavity part having an opening in a front surface of the base; and the diaphragm which is arranged on the front surface to cover the opening of the cavity part and converts the vibration into the electric signal. The semiconductor substrate is formed as a part of the base. | 2012-02-02 |
20120025337 | MEMS TRANSDUCER DEVICE HAVING STRESS MITIGATION STRUCTURE AND METHOD OF FABRICATING THE SAME - A micro-electromechanical systems (MEMS) transducer device mounted to a package substrate includes an active transducer having a resonator stack formed over a cavity through a transducer substrate, and a stress mitigation structure between the transducer substrate and the package substrate. The stress mitigation structure reduces stress induced on the transducer substrate due to mismatched coefficients of thermal expansion (CTEs) of the transducer substrate and the package substrate, respectively. | 2012-02-02 |
20120025338 | Non-Volatile Magnetic Memory Element with Graded Layer - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound. | 2012-02-02 |
20120025339 | MAGNETIC MEMORY WITH STRAIN-ASSISTED EXCHANGE COUPLING SWITCH - A magnetic tunnel junction cell having a free layer and first pinned layer with perpendicular anisotropy, the cell including a coupling layer between the free layer and a second pinned layer, the coupling layer comprising a phase change material switchable from an antiferromagnetic state to a ferromagnetic state. In some embodiments, at least one actuator electrode proximate the coupling layer transfers a strain from the electrode to the coupling layer to switch the coupling layer from the antiferromagnetic state to the ferromagnetic state. Memory devices and methods are also described. | 2012-02-02 |
20120025340 | VERTICAL SILICON PHOTOMULTIPLER WITH SUPERIOR QUANTUM EFFICIENCY AT OPTICAL WAVELENGTHS - The vertical silicon photomultiplier according to the present invention includes a trench electrode and a PN-junction layer perpendicular to the trench electrode forms and can maximize the quantum efficiency at optical wavelengths, 200˜900 nm in such a way that: it generates electric fields horizontal thereto, by applying a reverse bias voltage to between the trench electrode and the PN junction layer, so that, although ultraviolet light does not reach the PN-junction layer but is incident on the surface, electron-hole pairs can be produced by the horizontally generated electric fields although and an avalanche breakdown can be thus generated, and it allows ultraviolet light, capable of being transmitted to a relatively deep depth, to react with the PN-junction layer. | 2012-02-02 |
20120025341 | Aligning a sensor with a faceplate - An assembly includes a first packaged device that contains a first image sensor having first fiducial marks thereon. On a portion of the first packaged device at a predetermined location relative to the first fiducial marks is adhesive, and a first connection body is fixed within the adhesive and registered at the predetermined location relative to the first fiducial marks. The first connection body is mated into the first counter hole formed in a plate at a predetermined location. | 2012-02-02 |
20120025342 | INTEGRATED CIRCUIT COMBINATION OF A TARGET INTEGRATED CIRCUIT AND A PLURALITY OF CELLS CONNECTED THERETO USING THE TOP CONDUCTIVE LAYER - A target integrated circuit (TIC) having a top conductive layer (TCL) that may be connected to a plurality of cells that are further integrated over the TIC. Each of the plurality of cells comprises two conductive layers, a lower conductive layer (LCL) below the cell and an upper conductive layer (UCL) above the cell. Both conductive layers may connect to the TCL of the TIC to form a super IC structure combined of the TIC and the plurality of cells connected thereto. Accordingly, conductivity between the TIC as well as auxiliary circuitry to the TIC maybe achieved. | 2012-02-02 |
20120025343 | THERMOELECTRIC DEVICE HAVING A VARIABLE CROSS-SECTION CONNECTING STRUCTURE - A thermoelectric device having a variable cross-section connecting structure includes a first electrode, a second electrode, and a connecting structure connecting the first electrode and the second electrode. The connecting structure has a first section and a second section. The width of the second section is greater than the width of the first section, and the width of the first section is less than a width that is approximately equivalent to a phonon mean free path through the first section. | 2012-02-02 |
20120025344 | TRACEABLE INTEGRATED CIRCUITS AND PRODUCTION METHOD THEREOF - An embodiment of a method for producing traceable integrated circuits includes forming on a wafer of semiconductor material functional regions for implementing specific functionalities of corresponding integrated circuits, forming at least one seal ring around each functional region of the corresponding integrated circuit, and forming on each integrated circuit at least one marker indicative of information of the integrated circuit. Forming on each integrated circuit at least one marker may include forming the at least one marker on at least a portion of the respective seal ring that is visible. | 2012-02-02 |
20120025345 | METHOD, APPARATUS, AND DESIGN STRUCTURE FOR SILICON-ON-INSULATOR HIGH-BANDWIDTH CIRCUITRY WITH REDUCED CHARGE LAYER - A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view. | 2012-02-02 |
20120025346 | FABRICATING PROCESS OF CIRCUIT SUBSTRATE AND CIRCUIT SUBSTRATE STRUCTURE - A fabricating process of circuit substrate sequently includes: providing a substrate with a pad and a dielectric stack layer disposed at the substrate and overlaying the pad, in which the stack layer includes two dielectric layers and a third dielectric layer located between the two dielectric layers, and the etching rate of the third dielectric layer is greater than the etching rate of the two dielectric layers; forming an opening corresponding to the pad at the stack layer; performing a wet etching process on the stack layer to remove the portion of the third dielectric layer surrounding the opening to form a gap between the portions of the two dielectric layers surrounding the opening; performing a plating process on the stack layer and the pad to respectively form two plating layers at the stack layer and the pad, in which the gap isolates the two plating layers from each other. | 2012-02-02 |
20120025347 | Method of forming a MIM capacitor - An embedded memory system includes an array of dynamic random access memory (DRAM) cells, on the same substrate as an array of logic transistors. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-insulator-metal capacitor in a dielectric layer. The eDRAM system includes fewer metal layers in the logic area than in the memory area | 2012-02-02 |
20120025348 | SEMICONDUCTOR DEVICE COMPRISING A PASSIVE COMPONENT OF CAPACITORS AND PROCESS FOR FABRICATION - A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block. | 2012-02-02 |
20120025349 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits. | 2012-02-02 |
20120025350 | VERTICAL TRANSIENT VOLTAGE SUPPRESSORS - A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region. | 2012-02-02 |
20120025351 | SEMICONDUCTOR DEVICE - A bipolar transistor of the invention has a second base region | 2012-02-02 |
20120025352 | BIPOLAR JUNCTION TRANSISTOR DEVICES - A bipolar junction transistor (BJT) device including a base region, an emitter region and a collector region comprises a substrate, a deep well region in the substrate, a first well region in the deep well region to serve as the base region, a second well region in the deep well region to serve as the collector region, the second well region and the first well region forming a first junction therebetween, and a first doped region in the first well region to serve as the emitter region, the first doped region and the first well region forming a second junction therebetween, wherein the first doped region includes a first section extending in a first direction and a second section extending in a second direction different from the first direction, the first section and the second section being coupled with each other. | 2012-02-02 |
20120025353 | Semiconductor And Solar Wafers - A silicon-on-insulator or bonded wafer includes an upper portion having a trapezoid shape in cross-section and a lower portion having an outer peripheral edge having a curved shape. | 2012-02-02 |
20120025354 | LAMINATED SEMICONDUCTOR SUBSTRATE, LAMINATED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region. | 2012-02-02 |
20120025355 | LAMINATED SEMICONDUCTOR SUBSTRATE, LAMINATED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have electromagnetic shielding layer formed in regions other than the scribe-groove parts using a ferromagnetic body. Further, in the laminated semiconductor substrate, a through hole which penetrates the plurality of semiconductor substrates laminated in a laminated direction is formed in the scribe-groove part, and the laminated semiconductor substrate has a through electrode penetrating the plurality of semiconductor substrates through the through hole. | 2012-02-02 |
20120025356 | SEMICONDUCTOR DEVICE PACKAGES HAVING ELECTROMAGNETIC INTERFERENCE SHIELDING AND RELATED METHODS - The semiconductor device package includes a conformal shield layer applied to the exterior surface of the encapsulant. and an internal fence or separation structure embedded in the encapsulant. The fence separates the package into various compartments. with each compartment containing at least one die. The fence thus suppresses EMI between adjacent packages. The package further includes a ground path connected to the internal fence and conformal shield. | 2012-02-02 |
20120025357 | LEADFRAME FOR IC PACKAGE AND METHOD OF MANUFACTURE - A leadframe for use in an integrated circuit (IC) package comprising a metal strip partially etched on a first side. In some embodiments, the leadframe may be selectively plated on the first side and/or on a second side. The leadframe may be configured for an IC chip to be mounted thereon and for a plurality of electrical contacts to be electrically coupled to the leadframe and the IC chip. | 2012-02-02 |
20120025358 | SEMICONDUCTOR ELEMENT WITH SEMICONDUCTOR DIE AND LEAD FRAMES - A semiconductor element to be mounted on a circuit carrier includes a semiconductor die and at least one lead frame. In order to reduce the size required for mounting a semiconductor die on a circuit carrier, a semiconductor element includes a semiconductor die and at least one lead frame. The at least one lead frame is directly attached to the semiconductor die at a connection region of the semiconductor die, and the connection region provides an electrical connection to and mechanical support for the semiconductor die. | 2012-02-02 |
20120025359 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A conventional semiconductor device has a problem that a frame constituting a heat sink is expensive and the heat sink is highly likely to come off a resin package. A semiconductor device of the present invention reduces the frame price because a heat sink is formed by subjecting a frame with a uniform thickness to pressing or something similar. Furthermore, the heat sink is less likely to come off a resin package because step regions of the heat sink are pressed as connection regions to be connected to the other frame in which leads are arranged, and thereby, resin constituting the resin package goes around the step regions and reaches up to back surfaces of the respective step regions. Moreover, a structure which makes the heat sink much less likely to come off is realized because recessed portions are arranged in the step regions of the heat sink. | 2012-02-02 |
20120025360 | SEMICONDUCTOR ENCAPSULATION AND METHOD THEREOF - A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves. | 2012-02-02 |
20120025361 | SEMICONDUCTOR DEVICE, LEAD FRAME ASSEMBLY, AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a lead frame, a semiconductor element mounted on the lead frame, and a frame-like member formed on the lead frame, surrounding the semiconductor element, and covering a side surface of the lead frame and exposing a lower surface of the lead frame. The frame-like member has at least one concave portion in a side surface thereof. The concave portion has a ceiling portion located at the same height as or lower than an upper surface of the lead frame, and a bottom portion located higher than the lower surface of the lead frame. | 2012-02-02 |
20120025362 | Reinforced Wafer-Level Molding to Reduce Warpage - A method for forming an electrical package to reduce warpage. The method includes providing a wafer and coupling a die thereto. A mold compound material is applied to the wafer such that the mold compound material surrounds the die. The method further includes applying a reinforcing material to the mold compound material. The mold compound material is thereby disposed between the wafer and the reinforcing material. | 2012-02-02 |
20120025363 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes first and second substrates, a sealant and a filler. The first substrate has a surface including an active region and a bonding region. The first substrate has a component in the active region and a pad in bonding region. The pad is electrically connected to the component. The sealant is disposed on the surface surrounding the active region. The sealant has a breach at a side of the active region. The second substrate is bonded to the first substrate via the sealant. The second substrate has a first opening corresponding to the pad, and a second opening corresponding to the breach. The filler fills the second opening, covers the breach such that the first substrate, the second substrate, the sealant and the filler together form a sealed space for accommodating the component. | 2012-02-02 |
20120025364 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device. | 2012-02-02 |
20120025365 | MICROELECTRONIC PACKAGES WITH NANOPARTICLE JOINING - A method of making an assembly includes the steps of applying metallic nanoparticles to exposed surfaces of conductive elements of either of or both of a first component and a second component, juxtaposing the conductive elements of the first component with the conductive elements of the second component with the metallic nanoparticles disposed therebetween, and elevating a temperature at least at interfaces of the juxtaposed conductive elements to a joining temperature at which the metallic nanoparticles cause metallurgical joints to form between the juxtaposed conductive elements. The conductive elements of either of or both of the first component and the second component can include substantially rigid posts having top surfaces projecting a height above the surface of the respective component and edge surfaces extending at substantial angles away from the top surfaces thereof. | 2012-02-02 |
20120025366 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device comprises: forming a circuit pattern and a first metal film on a first major surface of a body wafer; forming a through-hole penetrating the body wafer from a second major surface of the body wafer and reaching the first metal film; forming a second metal film on a part of the second major surface of the body wafer, on an inner wall of the through-hole, and on the first metal film exposed in the through-hole; forming a recess on a first major surface of a lid wafer; forming a third metal film on the first major surface of the lid wafer including inside the recess of the lid wafer; with the recess facing the circuit pattern, and the first metal film contacting the third metal film, joining the lid wafer to the body wafer; and dicing the joined body wafer and lid wafer along the through-hole. | 2012-02-02 |
20120025367 | SEMICONDUCTOR DEVICE - A semiconductor device which includes a substrate, a semiconductor element arranged on the substrate, a heat dissipation component arranged on the semiconductor element, and a mold component covering an upper part of the substrate, the semiconductor element and the heat dissipation component, wherein an area of a surface on the semiconductor element of the heat dissipation component is larger than an area of a surface on which the heat dissipation component of the semiconductor element is arranged. | 2012-02-02 |
20120025368 | Semiconductor Device Cover Mark - A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate. | 2012-02-02 |
20120025369 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes a substrate, a semiconductor element, a plurality of element contacts and a molding compound. The substrate includes a passivation layer and a plurality of substrate pads. Each substrate pad includes a protrusion and an embedded portion. The embedded portion is embedded in the passivation layer, and the protrusion projects from the passivation layer. The semiconductor element includes a plurality of under bump metallurgies (UBM) with recesses. The ratio of the width of each recess to the first width of the protrusion is larger than 1. The element contacts connect the UBM and the substrate pads. The molding compound covers the semiconductor element. | 2012-02-02 |
20120025370 | SEMICONDUCTOR STRUCTURE COMPRISING PILLAR AND MOISTURE BARRIER - A semiconductor structure includes multiple semiconductor devices on a substrate and a metal layer disposed over the semiconductor devices, the metal layer comprising at least a first trace and a second trace. A conductive pillar is disposed directly on and in electrical contact with the first trace of the metal layer, and a dielectric layer is selectively disposed between the metal layer and the conductive pillar, where the dielectric layer electrically isolates the second trace from the pillar. A moisture barrier surrounds the semiconductor devices around a periphery of the semiconductor structure, and extends from the substrate through the dielectric layer to the conductive pillar. | 2012-02-02 |
20120025371 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, wiring formed thereon, a first insulating film formed on the wiring, provided with a first opening, a pad electrode formed so as to be in contact with the wiring, a second insulating film formed on the pad electrode film, provided with a second opening, and a flip chip bump formed so as to be in contact with the pad electrode film. In this case, the second insulating film exists between the flip chip bump and the pad electrode film, in a region directly underneath the outer edge of the flip chip bump, as seen in a plan view, and the outer edge of the flip chip bump is formed in a region inside the outer edge of the pad electrode film. | 2012-02-02 |
20120025372 | CHIP HAVING A DRIVING INTEGRATED CIRCUIT - A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved. | 2012-02-02 |
20120025373 | Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnects on Different Height Traces - A method of making a semiconductor device includes providing a substrate, and forming a first conductive layer over the substrate. A patterned layer is formed over the first conductive layer. A second conductive layer is formed in the patterned layer. A height of the second conductive layer is greater than a height of the first conductive layer. The patterned layer is removed. A first bump and a second bump are formed over the first and second conductive layers, respectively, wherein the second bump overlaps the first bump, and wherein an uppermost surface of the second bump is vertically offset from an uppermost surface of the first bump. Bond wires are formed on the first and second bumps. The bond wires are arranged in a straight configuration. Lowermost surfaces of the first conductive layer and second conductive layer are substantially coplanar. | 2012-02-02 |
20120025374 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUNDED INTERCONNECT - An integrated circuit packaging system includes: a package carrier; an integrated circuit attached to the package carrier; a rounded interconnect on the package carrier; and an encapsulation over the package carrier covering the integrated circuit and exposing the rounded interconnect having a characteristic free of denting. | 2012-02-02 |
20120025375 | ROUTABLE ARRAY METAL INTEGRATED CIRCUIT PACKAGE FABRICATED USING PARTIAL ETCHING PROCESS - An integrated circuit assembly is fabricated on a metal substrate strip in an array format that has raised circuitry pattern formed by photolithographic and metal etching processes. The circuitry pattern is formed on one side of the metal substrate only. The raised circuitry's etch depth extends partially through the metal substrate. Die attachment can be performed using a non-conductive material applied directly onto and around the raised circuitry features directly under the die. After wirebond and molding processes, the molded metal substrate strip assembly is processed through a metal etching process to remove the metal substrate portion that is exposed beyond the mold cap. A solder mask coating can be applied to protect the metal circuitry and to define the package pad opening to form Land-Grid-Array (LGA) packages. Solder balls can also be attached to form Ball-Grid-Array (BGA) packages. | 2012-02-02 |
20120025376 | BALL GRID ARRAY PACKAGE - A BGA package includes an IC die, a substrate, a plurality of solder balls, and a square contact pad. The portions of the contact pad capable of interfering with the IC die are removed to ensure the space between two of the contact pads is sufficient to avoid noise interference. | 2012-02-02 |
20120025377 | SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING A WIRING OF A SEMICONDUCTOR DEVICE - A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode. | 2012-02-02 |
20120025378 | SOLDER INTERCONNECT ON IC CHIP - A semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump. The bump is connected to the line and is adapted to be electrically connected to the line. A plane that is horizontal to an active surface of the semiconductor chip is defined. The area that the connection region of the line and the bump is projected on the plane is larger than 30,000 square microns or has an extension distance larger than 500 microns. | 2012-02-02 |
20120025379 | FRONT-END PROCESSING OF NICKEL PLATED BOND PADS - A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. | 2012-02-02 |
20120025380 | MANGANESE OXIDE FILM FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - There is provided a manganese oxide film forming method capable of forming a manganese oxide film having high adhesivity to Cu. In the manganese oxide film forming method, a manganese oxide film is formed on an oxide by supplying a manganese-containing gas onto the oxide. A film forming temperature for forming the manganese oxide film is set to be equal to or higher than about 100° C. and lower than about 400° C. | 2012-02-02 |
20120025381 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - An interlayer insulating film containing oxygen and carbon is formed on a semiconductor substrate. A groove is formed in the interlayer insulating film. An auxiliary film containing predetermined first and second metallic elements is formed on a bottom surface and a sidewall of the formed groove. Then, an interconnect body layer containing copper is formed to fill the groove. By performing a thermal treatment, a first barrier film containing a compound of the first metallic element and an oxygen element of the interlayer insulating film, and a second barrier film containing a compound of the second metallic element and carbon element of the interlayer insulating film are formed on the interlayer insulating film on the bottom surface and the sidewall of the groove. | 2012-02-02 |
20120025382 | Devices Formed With Dual Damascene Process - Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. | 2012-02-02 |
20120025383 | INTEGRATED CIRCUIT STRUCTURE INCORPORATING A CONDUCTOR LAYER WITH BOTH TOP SURFACE AND SIDEWALL PASSIVATION AND A METHOD OF FORMING THE INTEGRATED CIRCUIT STRUCTURE - Disclosed are embodiments of a structure having a metal layer with top surface and sidewall passivation and a method of forming the structure. In one embodiment, a metal layer is electroplated onto a portion of a seed layer at the bottom of a trench. Then, the sidewalls of the metal layer are exposed and, for passivation, a second metal layer is electroplated onto the top surface and sidewalls of the metal layer. In another embodiment, a trench is formed in a dielectric layer. A seed layer is formed over the dielectric layer, lining the trench. A metal layer is electroplated onto the portion of the seed layer within the trench and a second metal layer is electroplated onto the top surface of the metal layer. Thus, in this case, passivation of the top surface and sidewalls of the metal layer is provided by the second metal layer and the dielectric layer, respectively. | 2012-02-02 |
20120025384 | ELECTRONIC DEVICE AND METHOD FOR PRODUCTION - An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer. | 2012-02-02 |
20120025385 | Low Resistance Peripheral Local Interconnect Contacts with Selective Wet Strip of Titanium - Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided. | 2012-02-02 |
20120025386 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device according to an embodiment includes a cell array block having a plurality of cell arrays stacked therein, each of the cell arrays including a plurality of memory cells and a plurality of selective wirings selecting the plurality of memory cells are stacked, a pillar-shaped first via extending in a stack direction from a first height to a second height and having side surfaces connected to a first wiring, and a pillar-shaped second via extending in the stack direction from the first height to the second height and having side surfaces connected to a second wiring upper than the first wiring, the second wiring being thicker in the stack direction than the first wiring and having a higher resistivity than the first wiring. | 2012-02-02 |
20120025387 | CHIP PACKAGE AND FABRICATING METHOD THEREOF - A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion. | 2012-02-02 |
20120025388 | THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE HAVING IMPROVED POWER AND THERMAL MANAGEMENT - A three dimensional (3D) integrated circuit (IC) structure having improved power and thermal management is described. The 3D IC structure includes at least first and second dies. Each of the first and second dies has at least one power through silicon via (TSV) and one signal TSV. The at least one power and signal TSVs of the first die are connected to the at least one power and signal TSVs of the second die, respectively. The 3D IC structure also includes one or more peripheral TSV structures disposed adjacent to one or more sides of the first and/or the second die. The peripheral TSV structures supply at least power and/or signals. | 2012-02-02 |
20120025389 | Hermetic Wafer Level Packaging - Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers. | 2012-02-02 |
20120025390 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a plurality of storage node contact plugs passing through a first interlayer dielectric layer, a plurality of storage nodes in contact with the storage node contact plugs, each including a first electrode having a pillar shape and a second electrode spaced apart from the first electrode by a certain distance and surrounding the first electrode, and a second interlayer dielectric layer filling a gap between the second electrodes of neighboring storage nodes. | 2012-02-02 |
20120025391 | Semiconductor device and multilayer semiconductor device - Disclosed herein is a semiconductor device including: an input terminal receiving, if a preceding-stage semiconductor device is layered on a predetermined one of an upper layer and a lower layer, a bit train outputted from the preceding-stage semiconductor device; a semiconductor device identifier hold block holding a semiconductor device identifier for uniquely identifying the semiconductor device; a semiconductor device identifier computation block executing computation by using the semiconductor device identifier to update the semiconductor device identifier held in the semiconductor device identifier hold block according to a result of the computation; a control block once holding data of a bit train entered from the input terminal to control updating of the semiconductor device identifier executed by the semiconductor device identifier computation block based on the held data; and an output terminal outputting the bit train held in the control block to a succeeding-stage semiconductor device layered on another layer. | 2012-02-02 |
20120025392 | Increased Stability of a Complex Material Stack in a Semiconductor Device by Providing Fluorine Enriched Interfaces - When forming complex metallization systems, a sensitive material, such as a ULK material, may be deposited on a silicon-containing dielectric material, such as an etch stop material, with superior adhesion by performing a surface treatment on the basis of fluorine radicals. Due to the fluorine treatment, silicon-fluorine bonds are generated, which are then broken up upon interacting with the chemically active component during the further deposition process. Consequently, the subsequent material layer is chemically bonded to the underlying material, thereby imparting superior stability to the interface, which in turn may result in superior robustness and reliability of the metallization system upon performing reflowing processes and operating complex packaged semiconductor devices. | 2012-02-02 |
20120025393 | Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module - A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug. | 2012-02-02 |
20120025394 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first insulating film formed on a substrate; a pad embedded in the first insulating film; and a second insulating film that is formed on the first insulating film and has an opening exposing at least part of the pad. The pad includes a plurality of pad interconnects, and an interconnect link is provided to electrically connect adjacent interconnects among the plurality of pad interconnects. The width of the pad interconnects is smaller than the height of the pad interconnects and larger than the width of the interconnect link. | 2012-02-02 |
20120025395 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a first porous layer that is formed over a substrate and includes a SiO | 2012-02-02 |
20120025396 | SEMICONDUCTOR DEVICE WITH DIE STACK ARRANGEMENT INCLUDING STAGGERED DIE AND EFFICIENT WIRE BONDING - A semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package. | 2012-02-02 |
20120025397 | Semiconductor Chip Layout - A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays. | 2012-02-02 |
20120025398 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated circuit package including: providing a base substrate, connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon, mounting a base component over the base substrate, and forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system; and releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed. | 2012-02-02 |
20120025399 | FILM FOR FLIP CHIP TYPE SEMICONDUCTOR BACK SURFACE, AND ITS USE - The present invention relates to a film for flip chip type semiconductor back surface, which is to be disposed on the back surface of a semiconductor element to be flip chip-connected onto an adherend, the film containing a resin and a thermoconductive filler, in which the content of the thermoconductive filler is at least 50% by volume of the film, and the thermoconductive filler has an average particle size relative to the thickness of the film of at most 30% and has a maximum particle size relative to the thickness of the film of at most 80%. | 2012-02-02 |
20120025400 | FILM FOR FLIP CHIP TYPE SEMICONDUCTOR BACK SURFACE, DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE, PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE, AND FLIP CHIP TYPE SEMICONDUCTOR DEVICE - The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C. | 2012-02-02 |
20120025401 | INTEGRATED CIRCUIT PACKAGE WITH VOLTAGE DISTRIBUTOR - An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor. | 2012-02-02 |
20120025402 | METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES INCLUDING A UNIFORM PATTERN OF CONDUCTIVE LINES - Methods of forming semiconductor device structures are disclosed. One method comprises forming a plurality of loops of a conductive material. Each loop of the plurality of loops comprises a uniform pattern. In one embodiment, a portion of the conductive material is removed from at least one location in each loop of the plurality of loops. Contacts are formed to the conductive material. A semiconductor device structure is also disclosed. | 2012-02-02 |
20120025403 | DESIGN APPARATUS OF SEMICONDUCTOR DEVICE, DESIGN METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A design method of a semiconductor device includes four steps. The first step is of arranging grid wiring which includes a plurality of wiring lines arranged in parallel to each other and a plurality of vias connecting the plurality of wiring lines with each other. The second step is of arranging a plurality of internal circuits connected to the grid wiring. The third step is of calculating a current density of a current flowing in the grid wiring by the plurality of internal circuits. The fourth step is of dividing each of the plurality of wiring lines into portions each having a wiring length such that electromigration corresponding to the current density is suppressed. | 2012-02-02 |
20120025404 | FILM FOR FLIP CHIP TYPE SEMICONDUCTOR BACK SURFACE - The present invention relates to a film for flip chip type semiconductor back surface to be formed on the back surface of a semiconductor element flip chip-connected to an adherend, the film for flip chip type semiconductor back surface having a tensile storage elastic modulus at 25° C. after thermal curing within a range of from 10 GPa to 30 GPa, in which the tensile storage elastic modulus at 25° C. after thermal curing of the film for flip chip type semiconductor back surface falls within a range of from 4 times to 20 times the tensile storage elastic modulus at 25° C. before thermal curing thereof. | 2012-02-02 |
20120025405 | LIQUID ENCAPSULATING RESIN COMPOSITION, SEMICONDUCTOR DEVICE USING LIQUID ENCAPSULATING RESIN COMPOSITION, AND METHOD OF MANUFACTURING THE SAME - Disclosed is a liquid encapsulating resin composition containing an epoxy resin (A), an amine type curing agent (B), and a basic compound (C), wherein, in case that the liquid encapsulating resin composition is filled between a semiconductor element and a substrate connected to each other by solder bumps, the residue of a fluxing agent used for forming the solder bump connection is removed. | 2012-02-02 |
20120025406 | DEVICE INTRODUCED IN A JOYSTICK - The present utility model relates to a joystick that allows manual control of its basic functions for safe and correct operation (to the operator and the environment) of motorized backpack sprayers—equipment used for spraying/atomizing liquids for pest and disease control in agriculture, as well as for vectors of endemic diseases in public health. The joystick basically consists of a body ( | 2012-02-02 |
20120025407 | VESSEL AND METHOD FOR TREATING CONTAMINATED WATER - A method for removing immiscible fluid from contaminated water includes at least one chamber; an injection line in fluid communication with an inlet of the one chamber; bubble generation means in fluid communication with the injection line for injecting gas bubbles into the injection line and allowing mixing in the injection line of the gas bubbles and the contaminated water to form an inlet fluid; an inlet weir within the chamber adjacent the inlet; an immiscible fluid weir within the chamber; a trough for collecting the immiscible fluid and allowing the immiscible fluid to flow out of the at least one chamber through an immiscible fluid outlet; and a cleaned water outlet generally at the bottom of the chamber. | 2012-02-02 |
20120025408 | Natural mist humidifier - A mist humidifier includes a water supply, at least one nebulization device and at least one heater mechanism. The nebulization device nebulizes at least a portion of a flow of water from the water supply and discharges a flow of mist particles. The heater mechanism selectively heats at least a portion of the flow of mist particles. | 2012-02-02 |
20120025409 | METHOD AND APPARATUS FOR VACUUM PROCESS OF ISOSTATIC PRESSING OF POWDER MATERIAL - A method for a vacuum process of isostatic pressing of powder material comprises preparing an explosive charged rubber bag by charging a rubber bag with powder, forming a vacuum environment by putting the explosive charged rubber bag in a vacuum box, sealing an inlet of the explosive charged rubber bag which is in a vacuum state, and maintaining the vacuum state by putting the explosive charged rubber bag in a fluid contained in a reservoir by a predetermined depth in a state that the inlet of the explosive charged rubber bag has been sealed. | 2012-02-02 |
20120025410 | APPARATUS AND METHOD FOR FABRICATING THREE-DIMENSIONAL NONWOVEN FABRIC STRUCTURE - An apparatus for fabricating three-dimensional nonwoven fabric structure is disclosed, which includes an adjustable frame, a three-dimensional mold, a rotary shaft connecting the three-dimensional mold and the adjustable frame, and a meltblown device. The three-dimensional mold is rotated relative to the adjustable frame. The meltblown device has plural nozzles for spinning a plurality of fibers, wherein the three-dimensional mold is rotated in front of the nozzles to select the fibers, and a three-dimensional nonwoven fabric structure is formed on the three-dimensional mold. | 2012-02-02 |
20120025411 | METHOD FOR MAKING CEMENTED CARBIDE PRODUCTS - A method for the production of tungsten carbide based cemented carbide or cermet tools or components using the powder injection moulding method includes mixing of hard constituent powder and a metallic binder powder with an organic binder system, consisting of 30-60 wt-% olefinic polymers and 40-70 wt-% nonpolar waxes, acting as a carrier for the powder. A metallic binder powder that is granulated with a nonpolar wax is used. | 2012-02-02 |
20120025412 | INTEGRAL COOLING FIXTURE ADDENDUM FOR PANELS FORMED IN METAL FORMING PROCESS - One embodiment includes a method for forming panels in which a particular shaping of the addendum contours of the formed panel to provide the functionality of the cooling fixture. | 2012-02-02 |
20120025413 | METHOD OF MANUFACTURING GRAPHENE - Provided are a method and apparatus of manufacturing high quality large area graphene in large quantities. The method includes placing a supporting belt, on which a catalyst layer is loaded, into a chamber; increasing a temperature of the catalyst layer by injecting a carbon source into the chamber; forming graphene on the catalyst layer by cooling the catalyst layer; and taking out the supporting belt, on which the catalyst layer, on which the graphene is formed, is loaded, from the chamber to an outside, wherein a ratio between a melting point of the supporting belt and a maximum temperature Tmax of the catalyst metal layer that the catalyst layer is heated in the chamber is equal to or less than 0.6. | 2012-02-02 |
20120025414 | FORMATION AND ENCAPSULATION OF MOLECULAR BILAYER AND MONOLAYER MEMBRANES - Disclosed herein are compositions, methods, and devices related to bilayer and monolayer membranes, their encapsulation in a hydrogel, and their formation. Methods of using the disclosed compositions and devices are also disclosed. | 2012-02-02 |
20120025415 | METHOD AND DEVICE FOR PRODUCING PLASTIC MOLDED SKINS HAVING DIFFERENT SUBREGIONS - The present invention relates to a method and a device for producing plastic molded skins having different subregions. For this purpose, before melting the first plastic material, a region of the molding tool surface ( | 2012-02-02 |
20120025416 | APPARATUS AND METHOD FOR MANUFACTURING BALL JOINT - Provided is an apparatus and method for manufacturing a ball joint that are capable of reducing a torque applied between a ball stud and a ball seat. | 2012-02-02 |
20120025417 | MOLDED PULL-OFF TAB - A removable molding tab facilitates loading component parts into a mold by providing a body with holding configurations suitable to releasably secure the component parts in mold ready positions. The component parts are loaded into a mold as a preassembly with the removable tab. The tab is removed after the component parts are placed into the mold. | 2012-02-02 |
20120025418 | METHOD OF MANUFACTURING DAMPER ASSEMBLY OF REFRIGERATOR - Provided is a method of manufacturing a damper assembly. In the method, a case constituting an appearance of the damper assembly and having an open surface is molded, the case is inserted in a jig, the case is filled with a thermal insulating material to blow and mold the thermal insulating material, and a closing plate is coupled to the case to cover the open surface of the case. The closing plate contacts the discharge duct when the damper assembly closes the discharge duct. Accordingly, dimension stability, a defect rate, and sealing and insulating performances of the damper assembly are improved. | 2012-02-02 |
20120025419 | IMPRINTING APPARATUS AND IMPRINT TRANSFER METHOD - The present invention provides an imprinting apparatus or an imprint transfer method in which uniformity of curing quality by UV light is maintained and a uniform application thickness of a UV curable resin is achieved, even if glass is contaminated with dust and/or smudges or has a flaw. A feature of the present invention resides in an imprinting apparatus or an imprint transfer method that, while irradiating an transferred object with energy, transfers a concavo-convex configuration on a stamper's surface onto the transferred object and, subsequently, detaches the stamper from the transferred object, the imprint transfer method including: pressurizing a first reverse surface of at least one of the stamper and the transferred object with a planar pressurizing body having a flat surface configuration; subsequently, pressurizing a second reverse surface of at least one of the stamper and the transferred object with a fluid; and controlling pressurization timing of pressurization by the planar pressurizing body and pressurization by the fluid, thus completing the transfer. | 2012-02-02 |
20120025420 | SHEET PRESS MOLDING METHOD AND METHOD OF MANUFACTURING FUEL CELL SEPARATOR - Provided is a sheet press molding method by which a molded product having a small plate thickness deviation is obtained. Such a sheet press molding method is provided with a process in which a molded product ( | 2012-02-02 |
20120025421 | METHOD FOR PRODUCING LIQUID CRYSTAL POLYESTER COMPOSITION - The present invention provides a method for producing a liquid crystal polyester composition, the method comprising feeding a liquid crystal polyester and a polyhydric alcohol fatty acid ester into an extruder having a vent portion, followed by melt-kneading in a state where the degree of decompression of the vent portion is −0.06 MPa or less in terms of a gauge pressure. The composition obtained by the method can provide a molded article having a thin wall portion and complicated shape. | 2012-02-02 |
20120025422 | Process And Apparatus For Demolding And Palletizing Cast Concrete Blocks - A method for demolding concrete blocks which are cast in a resilient mold supported in a rigid frame, the mold having a top surface and at least one cavity with an opening on the top surface, which cavity holds a cured cast concrete block. The mold has two opposing edges. The demolded blocks are stacked on a collection surface. A support is positioned over the cavity and the mold, the support and the frame are inverted and positioned in demolding apparatus. After two opposing edges of the mold are engaged by the demolding apparatus, the support is withdrawn to allow the mold to sag. The blocks may release from the mold and fall onto the collection surface. If any blocks remain in the mold, a plunger mechanism is pushed against the sagging mold to release the blocks. Guide members may facilitate positioning the blocks on the collection surface. | 2012-02-02 |
20120025423 | CAVITY INSERT FOR A MOLDING SYSTEM, THE CAVITY INSERT HAVING A DEFORMABLE PORTION - According to embodiments of the present invention, there is provided a cavity insert for a molding system, the cavity insert having a deformable portion. More specifically, A cavity insert ( | 2012-02-02 |
20120025424 | PROCESS FOR PREPARING TABLET POWDER OR POURED COSMETIC PRODUCTS - A new process for preparing tablet powder or poured cosmetic products comprises preparing different cosmetic compounds in a slurry, i.e. “semi-liquids”, preparing a pre-moulded container ( | 2012-02-02 |
20120025425 | INJECTION MOULDING OF PLASTICS ARTICLES - An injection moulding apparatus includes an openable mould ( | 2012-02-02 |
20120025426 | METHOD AND SYSTEM FOR THERMAL IMPRINT LITHOGRAPHY - A method and apparatus of thermal imprint lithography includes moving an imprinter against a surface to be imprinted, supplying energy to a layer of heating material, and forming features in the surface to be imprinted. The imprinter comprises a main body and the layer of heating material under the main body. In an embodiment the layer of heating material is electrically heated. In alternate embodiments, the layer of heating material is optically heated. | 2012-02-02 |
20120025427 | METHOD OF MAKING TRANSPARENT CONDUCTIVE FILM - A method of making a transparent conductive film includes providing a carbon nanotube array and a substrate. At least one carbon nanotube film is extracted from the carbon nanotube array, and stacked on the substrate to form a carbon nanotube film structure. The carbon nanotube film structure is irradiated by a laser beam along a predetermined path to obtain a predetermined pattern. The predetermined pattern is separated from the other portions of the carbon nanotube film, thereby forming the transparent conductive film from the predetermined pattern of the carbon nanotube film. | 2012-02-02 |
20120025428 | DEVICE FOR TRANSFORMING MATERIALS BY INDUCTION HEATING - The present invention concerns a device for molding of thermoplastic matrix composite materials or thermosetting materials. Two mold casings that are mobile relative to each other, electrically conductive material include a molding zone designed to be in contact with the material to be transformed, and an induction circuit for generating a magnetic field. The faces of one of the two mold casings are situated so as to be facing induction circuit, except for the molding zones, being coated with a shielding layer made of a non-magnetic material preventing the magnetic field from penetrating into the mold casings. The mold casings are electrically insulated from each other during the molding phase to define an air gap wherein flows the magnetic field that induces currents at the surface of the molding zones, thus localizing the heating at the interface between the molding zone and the material to be transformed. | 2012-02-02 |
20120025429 | NANOFIBER MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING NANOFIBERS - Provided is a nanofiber manufacturing apparatus including an effusing body ( | 2012-02-02 |
20120025430 | PROCESS AND PLANT FOR PRODUCING TYRES - A compound plant for processing elastomeric compounds for tyres with both a high quality and a high throughput includes at least one batch mixing device in combination with at least one multi-shaft continuous mixing device having a high number of shafts. For example, the multi-shaft continuous mixing device could be a ring extruder having a plurality of co-rotating screws disposed to form a ring. In operation, a first elastomeric compound is discharged from the at least one batch mixing device and processed with the at least one multi-shaft continuous mixing device to obtain a second elastomeric compound | 2012-02-02 |
20120025431 | HIGH-PRESSURE BOTTLE-BLOWING PROCESS AND APPARATUS - A high-pressure bottle-blowing apparatus performs a high-pressure bottle-blowing process including steps of: a. providing at least one preform to a molding device; b. closing a first mold half and a second mold half of the molding device to form a mold cavity between the first mold half and the second mold half for accommodating the preform therein; c. providing a high-pressure gas to blow and form the preform into a semi-finished container; d. pushing a movable block below the mold cavity toward the mold cavity to indent the semi-finished container and form the semi-finished container with a bottom so as to shape a finished container; e. releasing the finished container from the molding device. | 2012-02-02 |
20120025432 | CERAMICS MANUFACTURE USING RAPIDLY HYDRATABLE CELLULOSIC BINDER - A method for making a ceramic body, the method including: mixing inorganic ceramic-forming ingredients to form a batch; adding a rapidly hydratable cellulosic binder and a liquid vehicle to the batch and further mixing to form a plasticized mixture; extruding the plasticized mixture to form a green body. The green body can then be heated sufficiently to produce a predominant ceramic phase, thereby transforming the green body into the ceramic body. | 2012-02-02 |
20120025433 | METHOD AND APPARATUS FOR REMOTE CONTROLLING, MONITORING AND/OR SERVICING HEAT-TREATMENT EQUIPMENT VIA WIRELESS COMMUNICATIONS - A method and apparatus provide for remote control, monitoring and/or servicing of heat-treatment equipment via wireless communications networks. Specifically, the method and apparatus can be used in pre and post-weld heat-treatment applications for steel pipes in a variety of industries, including, but not limited to, power plants, chemical and petrochemical plants and refineries. Importantly, the embodiment generates and manages all the documentation necessary to input and verify the specified heat-treatment process. It will produce and deliver to the customer the reports and certificates required by the applicable quality control standards, requirements and regulatory authorities. | 2012-02-02 |
20120025434 | METHOD FOR THE PRODUCTION OF A REFRACTORY FILTER - A method for the production of closed edge filters suitable for filtering molten metal and filters made by such a method. The method, comprises:
| 2012-02-02 |
20120025435 | SPRING AND SPRING ASSEMBLY - A spring includes a first end, a second end, and a spring main body between the first end and the second end. The spring main body includes a compression spring portion and a torsion spring portion, and the spring main body is substantially located in a same plane. | 2012-02-02 |