05th week of 2013 patent applcation highlights part 45 |
Patent application number | Title | Published |
20130029419 | Blood-Brain Barrier Model - A method of creating a multicellular blood-brain barrier model is disclosed. In one embodiment, the method comprises culturing primary brain microvascular endothelial cells or embryonic stem cell-derived endothelial cells upon a permeable support in the presence of neural progenitor cells. | 2013-01-31 |
20130029420 | METHOD OF CULTURING VASCULAR SMOOTH MUSCLE CELLS, CULTURE DEVICE AND MEDICAL MATERIAL OBTAINED BY THE CULTURE - There is provided a method for culturing vascular smooth muscle cells while maintaining their normal function, and a culture device and regenerative medical material for the same. The method takes advantage of vascular smooth muscle cell recognition of elastin as an extracellular matrix. The invention provides a method for culturing vascular smooth muscle cells on elastin, a culture device having elastin anchored on the cell-growing surface, a culture device wherein the cell-growing surface is composed of an elastin molded article, and medical materials obtained by culturing vascular smooth muscle cells using such culture devices. | 2013-01-31 |
20130029421 | Methods for Making Cell Culture Substrates - Cell culture substrates are provided. Aspects of the cell culture substrate include a substrate with a surface having at least one hydrophilic region and at least one hydrophobic region, and a surfactant layer present on the surface of the substrate and configured to produce a cell-binding surface on the hydrophilic regions of the surface. Also provided are kits which include the cell culture substrate, as well as methods of producing the cell culture substrate. The cell culture substrate and methods described herein find use in a variety of applications, including single-cell culture applications. | 2013-01-31 |
20130029422 | Composite Substrate for 3D Cell Culture - A cell culture article comprises a substrate having a micro-structured surface and a thin hydrophobic elastomeric coating disposed on the substrate. The coating forms a micro-structured cell culture surface and is sufficiently thin to reduce absorption of hydrophobic molecules from an aqueous medium in contact with the coating, relative to articles fabricated entirely from the hydrophobic elastomer. | 2013-01-31 |
20130029423 | METHOD OF EFFICIENTLY ESTABLISHING INDUCED PLURIPOTENT STEM CELLS - Provided are a method of improving the efficiency of establishment of iPS cells, comprising the step of contacting one or more substances selected from the group consisting of members of the GLIS family (e.g., GLIS1) and nucleic acids that encode the same and one or more substances selected from the group consisting of members of the Klf family and nucleic acids that encode the same, with a somatic cell, an iPS cell comprising an exogenous nucleic acid that encodes a member of the GLIS family or a member of the Klf family, that can be obtained by the method, and a method of producing a somatic cell by inducing the differentiation of the iPS cell. | 2013-01-31 |
20130029424 | METHOD FOR THE GENERATION OF MONOCLONAL ANTIBODIES DERIVED FROM HUMAN B CELLS - The present invention relates, in general, to human B cells, and, in particular to a method of immortalizing and cloning human B cells and to monoclonal antibodies derived therefrom. The invention further relates to methods of using the monoclonal antibodies for therapeutic and diagnostic purposes. | 2013-01-31 |
20130029425 | Genetic Inhibition by Double-Stranded RNA - A process is provided of introducing an RNA into a living cell to inhibit gene expression of a target gene in that cell. The process may be practiced ex vivo or in vivo. The RNA has a region with double-stranded structure. Inhibition is sequence-specific in that the nucleotide sequences of the duplex region of the RNA and of a portion of the target gene are identical. The present invention is distinguished from prior art interference in gene expression by antisense or triple-strand methods. | 2013-01-31 |
20130029426 | Dual Inducible System for the cSPP System - The present invention provides a dual inducible system for single protein production, as well as a method of inducing high level protein expression using amino acids. | 2013-01-31 |
20130029427 | Methods and Apparatus for Determination of Halohydrocarbons - A real-time, on-line method and analytical system for determining halohydrocarbons in water which operate by (1) extracting on-line samples; (2) purging volatile halohydrocarbons from the water (e.g., with air or nitrogen); (3) carrying the purge gas containing the analytes of interest over a porous surface where the analytes are adsorbed; (4) recovering the analytes from the porous surface with heat (thermal desorption) or solvent (solvent elution) to drive the analytes into an organic chemical mixture; (5) generating an optical change (e.g., color change) in dependence upon a reaction involving the analytes and a pyridine derivative; and (6) measuring optical characteristics associated with the reaction to quantify the volatile halogenated hydrocarbon concentration. | 2013-01-31 |
20130029428 | PREPARATION METHOD OF ANTIGEN-IMMOBILIZED IMMUNO- FLUORESCENCE SLIDE AND IMMUNO-FLUOROSCENCE SLIDE PREPARED THEREBY - A method of preparing an antigen-immobilized immuno-fluorescence slide, the method comprising: immobilizing a C-reactive protein on a slide to prepare a protein chip; mixing an antibody that specifically binds to a target protein, with streptavidin to label the antibody with a fluorescent nanoparticle; immuno-reacting the antibody by competitive mixing, assaying with a fluorescence camera, wherein the immobilizing of the C-reactive protein on the slide comprises: modifying the slide with 3-aminopropyltrimethoxysilane to prepare a modified slide; hydrating the slide modified with 3-aminopropyltrimethoxysilane; activating the modified slide by using a glutaraldehyde solution; dissolving a C-reactive protein at a concentration of 0.01-0.5 mg/ml in a 30-70 mM phosphate buffer solution (pH 6.5-7.8) to prepare an antigen solution for immobilization; placing a petri dish comprising the slide on a spotting guide and spotting 1-100 μl of the antigen solution on spotting points; and performing a reaction on the slide prepared as described above for 1-6 hours to immobilize the antigen, and an immune-fluorescence slide prepared by using the method. | 2013-01-31 |
20130029429 | METHOD FOR AVOIDING INFLUENCE OF ENDOGENOUS LIPOPROTEIN AND REAGENT - To identify the aforementioned interference component present in serum or plasma, to thereby provide means for avoiding any interference effect caused by the component. | 2013-01-31 |
20130029430 | PLASMON SENSOR, AND USAGE METHOD AND MANUFACTURING METHOD THEREOF - A plasmon sensor has a first metal layer and a second metal layer. The first metal layer has a bottom surface and a top surface configured to be supplied with an electromagnetic wave. The second metal layer has a top surface confronting the bottom surface of the first metal layer. Between the first metal layer and the second metal layer, there is provided a hollow region configured to be filled with a specimen containing a medium. Analyte capturing bodies are physically adsorbed at least one of below the first metal layer and above the second metal layer. | 2013-01-31 |
20130029431 | METHOD FOR MANUFACTURING NONVOLATILE MEMORY DEVICE - According to one embodiment, a method for manufacturing a nonvolatile memory device including a plurality of memory cells is disclosed. Each of the plurality of memory cells includes a base layer including a first electrode, a magnetic tunnel junction device provided on the base layer, and a second electrode provided on the magnetic tunnel junction device. The magnetic tunnel junction device includes a first magnetic layer, a tunneling barrier layer provided on the first magnetic layer, and a second magnetic layer provided on the tunneling barrier layer. The method can include etching a portion of the second magnetic layer and a portion of the first magnetic layer by irradiating gas clusters onto a portion of a surface of the second magnetic layer or a portion of a surface of the first magnetic layer. | 2013-01-31 |
20130029432 | THIN-WAFER CURRENT SENSORS - Embodiments relate to IC current sensors fabricated using thin-wafer manufacturing technologies. Such technologies can include processing in which dicing before grinding (DBG) is utilized, which can improve reliability and minimize stress effects. While embodiments utilize face-up mounting, face-down mounting is made possible in other embodiments by via through-contacts. IC current sensor embodiments can present many advantages while minimizing drawbacks often associated with conventional IC current sensors. | 2013-01-31 |
20130029433 | PROCESS CONDITION MEASURING DEVICE - An instrument comprises a substrate, a plurality of sensors distributed at positions across the substrate's surface, at least one electronic processing component on the surface, electrical conductors extending across the surface and connected to the sensors and processing component, and a cover disposed over the sensors, processing component and conductors. The cover and substrate have similar material properties to a production substrate. The cover is configured to electromagnetically shield the sensors, conductors, or processing component. The instrument has approximately the same thickness and/or flatness as the production substrate. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2013-01-31 |
20130029434 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING CALIBRATING PROCESS CONDITIONS AND CONFIGURATIONS BY MONITORING PROCESSES - A method of fabricating a semiconductor device includes performing a first period of operation and a second period of operation at first equipment and second equipment. The first period of operation includes performing a first patterning process at each of the first equipment and the second equipment, generating first inspection data of the first equipment and first inspection data of the second equipment, generating first differential data of the second equipment including differentials of the first inspection data of the first equipment and the first inspection data of the second equipment, and calibrating a configuration of the second equipment with reference to the first differential data of the second equipment. | 2013-01-31 |
20130029435 | METHOD FOR FORMING A LASER RESONATOR SO THAT OPTICAL COMPONENTS OF THE LASER RESONATOR ARE ALIGNED - A laser resonator and method for forming the laser resonator are provided. The method comprises placing a housing for the laser resonator in an alignment fixture, attaching a bond plate to an optical component of the laser resonator, attaching a first end of an alignment arm to the bond plate attached to the optical component, attaching a second end of the alignment arm to the alignment fixture such that the optical component is disposed over the housing, aligning, via the alignment fixture and the alignment arm, the optical component relative to the housing, and bonding the aligned optical component to the housing. The first end of the alignment arm may removed once the aligned optical component is bonded to the housing. | 2013-01-31 |
20130029436 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A hard mask made of a material in which the pattern precision is degraded by oxidation, a protective film, which protects the hard mask film from oxidation, a first mask film and a first organic film are sequentially stacked. The first organic film is processed into a first pattern, and the first mask film is firstly etched using the patterned the first organic film as a mask. After the first organic film is removed, a second organic film is formed. The second organic film is processed into a second pattern. The first mask film is secondary etched using the patterned second organic film as a mask so that the surface of the first mask film is exposed but the surface of the protective film is not exposed, thereby selectively patterning only the first mask film. After that, when removing the residual second organic film by ashing, it is possible to ensure the function of the protective film that protects the hard mask film from oxidation. | 2013-01-31 |
20130029437 | METHOD OF MANUFACTURING LIQUID EJECTION HEAD SUBSTRATE - A liquid ejection head substrate including a silicon substrate having a liquid supply port as hollow and slots as through holes connecting the hollow and a liquid channel arranged opposite sides of the substrate. The method includes etching the substrate to form the hollow; forming a first resist on the hollow; etching the first resist on the bottom of the hollow under conditions of securing an equal etching rate to both the silicon substrate and the first resist; forming a second resist on the hollow; patterning the second resist into an etching mask; and etching the substrate using the etching mask to form the through holes. | 2013-01-31 |
20130029438 | METHOD FOR MANUFACTURING WAFER-BONDED SEMICONDUCTOR DEVICE - The invention provides a wafer-bonded semiconductor device wherein warpage generated when wafers are bonded is reduced at a low cost ad through a simple process. | 2013-01-31 |
20130029439 | METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - There is provided a method of manufacturing a light emitting device, the method including: mounting a plurality of light emitting devices on an adhesive layer; arranging upper surfaces of the plurality of light emitting devices to be disposed horizontally using a pressing member; forming a wavelength conversion part covering the plurality of light emitting devices on the adhesive layer by applying a resin including at least one phosphor material; planarizing an upper surface of the wavelength conversion part using the pressing member; and separating the adhesive layer from the plurality of light emitting devices. | 2013-01-31 |
20130029440 | METHOD FOR FABRICATING SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device is disclosed. The semiconductor light-emitting device comprises a multilayer epitaxial structure disposed on a substrate. The substrate has a predetermined lattice direction perpendicular to an upper surface thereof, wherein the predetermined lattice direction is angled toward [0 | 2013-01-31 |
20130029441 | METHODS FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY SUBSTRATE AND DISPLAY PANEL - The present invention provides methods for manufacturing a thin film transistor (TFT) array substrate and a display panel. The method for manufacturing the TFT array substrate comprises the following steps: forming a plurality of gate electrodes, a gate insulating layer, a semiconductor layer, an ohmic contact layer, an electrode layer and a photo-resist layer on a transparent substrate in sequence; using a multi tone mask to pattern the photo-resist layer; forming a plurality of source electrodes and a plurality of drain electrodes at both sides of the channels, respectively; heating the photo-resist layer; etching the semiconductor layer; removing the photo-resist layer; forming a passivation layer on the channels, the source electrodes and the drain electrodes; and forming a pixel electrode layer on the passivation layer. The present invention can reduce an amount of the required masks in the fabrication process, and only one wet etching is required to etch the metal material on the TFT array substrate. | 2013-01-31 |
20130029442 | Liquid Crystal Display and Method for Manufacturing the Same - A liquid crystal display includes a substrate and a display region on the substrate. The display region has one or more gate lines; a gate insulating layer; a semiconductor layer; one or more pairs of source and drain electrodes, each pair being one source electrode and one corresponding drain electrode; and one or more data lines, each comprising one or more of the source electrodes. A passivation layer overlies the data lines and the drain electrodes and has a plurality of contact holes; and one or more color filters overlie the passivation layer and have a plurality of through holes. In the display region, in top view, the semiconductor layer has the same shape as the data lines and the drain electrodes except over each region between each source and corresponding drain electrode, and the contact holes' edges are aligned with the through holes' edges. | 2013-01-31 |
20130029443 | PHOTOALIGNMENT MATERIAL, DISPLAY SUBSTRATE HAVING AN ALIGNMENT LAYER FORMED USING THE SAME, AND TO A METHOD OF MANUFACTURING THE DISPLAY SUBSTRATE - A photoalignment material includes an alignment polymer, a photoalignment additive including a compound represented by the following Chemical Formula 1 and an organic solvent. | 2013-01-31 |
20130029444 | LASER DICING METHOD - A laser dicing method includes: placing a workpiece substrate on a stage; generating a clock signal; emitting a pulse laser beam synchronous with the clock signal; switching irradiation and non-irradiation of the workpiece substrate with the pulse laser beam in a unit of light pulse in synchronization with the clock signal to perform first irradiation of the pulse laser beam on a first straight line by controlling the pulse laser beam using a pulse picker; performing second irradiation of the pulse laser beam on a second straight line, which is adjacent to the first straight line in a substantially parallel fashion, after the first irradiation; and forming a crack reaching a workpiece substrate surface on the workpiece substrate by the first irradiation and the second irradiation. | 2013-01-31 |
20130029445 | METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a method of manufacturing a semiconductor light emitting device, the method including: preparing a substrate including first and second main surfaces opposing each other; forming a plurality of protruding parts in the first main surface of the substrate; forming a light emitting stack on the first main surface on which the plurality of protruding parts are formed; forming a plurality of light emitting structures by removing portions of the light emitting stack formed in regions corresponding to groove parts around the plurality of protruding parts; and separating the substrate along the groove parts. | 2013-01-31 |
20130029446 | METHOD OF FORMING TRANSPARENT ELECTRODE AND FABRICATING ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE - A method of forming a transparent electrode includes forming a first transparent conductive material layer on a base; performing a plasma process on the first transparent conductive material layer such that the upper portion of the first transparent conductive material layer is changed into semitransparent; forming a second transparent conductive material layer on the first transparent conductive material layer; patterning the second transparent conductive material layer and the first transparent conductive material layer; and annealing the patterned second transparent conductive material layer and the patterned first transparent conductive material layer such that the upper portion of the first transparent conductive material layer is changed into transparent. | 2013-01-31 |
20130029447 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, DELAMINATION METHOD, AND TRANSFERRING METHOD - A substrate and a delamination film are separated by a physical means, or a mechanical means in a state where a metal film formed over a substrate, and a delamination layer comprising an oxide film including the metal and a film comprising silicon, which is formed over the metal film, are provided. Specifically, a TFT obtained by forming an oxide layer including the metal over a metal film; crystallizing the oxide layer by heat treatment; and performing delamination in a layer of the oxide layer or at both of the interface of the oxide layer is formed. | 2013-01-31 |
20130029448 | METHODS FOR PRODUCING MATERIALS WITH PHOTO- AND ELECTROLUMINESCENCE PROPERTIES AND SYSTEMS USING SUCH MATERIALS - The invention is directed to a method of preparing polymeric metallomacrocycles having measurable photo- and electroluminescence properties and devices using such materials. In an embodiment, an O-hexyl-3,5-bis(terpyridine)phenol ligand has been synthesized and transformed into a hexagonal Zn(II)-metallomacrocycle by a facile self-assembly procedure capitalizing on terpyridine-Zn(II)-terpyridine connectivity. The material is usable in an OLED device based on the photo- and electro-luminescence characteristics thereof. | 2013-01-31 |
20130029449 | Semiconductor Sensor Structures with Reduced Dislocation Defect Densities and Related Methods for the Same - Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique. | 2013-01-31 |
20130029450 | METHOD FOR MANUFACTURING SOLAR CELL - The present invention provides a method for manufacturing a solar cell capable of suppressing volatilization of selenium and deformation of a substrate during a manufacturing process. According to the present invention, the method for manufacturing the solar cell comprises the steps of: providing a substrate; forming a rear electrode on the substrate; forming a precursor film for a light absorption film on the rear electrode; forming a light absorption film by progressing a crystallization process for the precursor film for the light absorption film; forming a buffer film on the light absorption film; forming a window film on the buffer film, and forming an anti-reflection film on the window film; and partially patterning the anti-reflection film, and forming a grid electrode in a patterned area. Said precursor film for the light absorption film includes Cu—Zn—Sn—S (Cu | 2013-01-31 |
20130029451 | METHOD FOR MAKING A SOLAR CELL - A method for making a solar cell includes: (a) forming over a substrate a photoelectric transformation layer that is made of a chalcopyrite-based photovoltaic material; (b) performing an ion milling treatment, in which ions are injected to an upper surface of the photoelectric transformation layer at an ion incident angle with respect to the upper surface to partially etch the photoelectric transformation layer, so that the photoelectric transformation layer is formed with a plurality of nano-pillar structures, the ion incident angle ranging from 0° to 90°; and (c) forming an electrode unit to transmit electricity from the photoelectric transformation layer. | 2013-01-31 |
20130029452 | METHOD OF FORMING OPTOELECTRONIC CONVERSION LAYER - A method of forming optoelectronic conversion layer includes the following steps. A first substrate is provided, and an electrode layer is formed on the first substrate. A first metal precursor layer including one or plural of metal components is formed on the electrode layer. A second substrate is provided, and a nonmetal precursor layer including at least one nonmetal component is formed on the second substrate. The first substrate and the second substrate are then stacked so that the nonmetal precursor layer and the first metal precursor layer are in contact. A thermal treatment is performed to have the first metal precursor layer react with the nonmetal precursor layer for forming an optoelectronic conversion layer. | 2013-01-31 |
20130029453 | NITROGEN IMPLANTED ULTRAFAST SAMPLING SWITCH - A method of manufacturing a semiconductor device suitable for optoelectronic switching in response to light of wavelengths in the range 1200 nm to 1600 nm, comprising forming an undoped InGaAs layer on an insulative semiconductor substrate and bonded on opposed sides to a pair of electrical contact layers adapted to constitute the electrodes of a switch, comprising forming the bulk point defects by irradiating the InGaAs layer with Nitrogen ions. | 2013-01-31 |
20130029454 | METHOD FOR MAKING PHOTOVOLTAIC DEVICES - A method for making a photovoltaic device is presented. The method includes steps of disposing a window layer on a substrate and disposing an absorber layer on the window layer. Disposing the window layer, the absorber layer, or both layers includes introducing a source material into a deposition zone, wherein the source material comprises oxygen and a constituent of the window layer, of the absorber layer or of both layers. The method further includes step of depositing a film that comprises the constituent and oxygen. | 2013-01-31 |
20130029455 | METHOD FOR MANUFACTURING TWO ADJACENT AREAS MADE OF DIFFERENT MATERIALS - The invention relates to a method for manufacturing adjacent first and second areas of a surface, said areas consisting, respectively, of first and second materials that are different from each other. Said method involves: depositing a first liquid volume that encompasses the first area and comprises a solvent in which the first material is dispersed; depositing a second liquid volume that encompasses the second area and comprises a solvent in which the second material is dispersed; and removing the solvents. According to the invention, the solvents of the first and second volumes are immiscible, and the second volume is simultaneously or consecutively deposited with the deposition of the first volume, before the first volume reaches the second area. | 2013-01-31 |
20130029456 | ANTIMONY AND GERMANIUM COMPLEXES USEFUL FOR CVD/ALD OF METAL THIN FILMS - Antimony, germanium and tellurium precursors useful for CVD/ALD of corresponding metal-containing thin films are described, along with compositions including such precursors, methods of making such precursors, and films and microelectronic device products manufactured using such precursors, as well as corresponding manufacturing methods. The precursors of the invention are useful for forming germanium-antimony-tellurium (GST) films and microelectronic device products, such as phase change memory devices, including such films. | 2013-01-31 |
20130029457 | TCE Compensation for Package Substrates for Reduced Die Warpage Assembly - A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages. | 2013-01-31 |
20130029458 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE HAVING COATING FILM AND METHOD FOR MANUFACTURING THE SAME - A substrate for a semiconductor package includes a ball land disposed on one surface of an insulating layer. A solder resist is applied to the surface of insulating layer while leaving the ball land exposed. A coating film is applied on the exposed surface of the ball land. The coating film includes a high molecular compound having metal particles. In the substrate having the ball land with the coating film formed thereon, it is not necessary to subject the substrate to a UBM formation process. | 2013-01-31 |
20130029459 | METHOD FOR MAKING SCHOTTKY BARRIER DIODE - A method for making a Schottky barrier diode includes the following steps. A first metal layer, a second metal layer and a carbon nanotube composite material are provided. The carbon nanotube composite material is applied on the first metal layer and the second metal layer to form a semiconductor layer. The carbon nanotube composite material includes an insulated polymer and a number of carbon nanotubes dispersed in the insulated polymer. The semiconductor layer is in Schottky contact with the first metal layer and in ohmic contact with the second metal layer. | 2013-01-31 |
20130029460 | METHODS OF FORMING GRAPHENE-CONTAINING SWITCHES - Some embodiments include methods of forming graphene-containing switches. A bottom electrode may be formed over a base, and a first electrically conductive structure may be formed to extend upwardly from the bottom electrode. Dielectric material may be formed along a sidewall of the first electrically conductive structure, while leaving a portion of the bottom electrode exposed. A graphene structure may be formed to be electrically coupled with the exposed portion of the bottom electrode. A second electrically conductive structure may be formed on an opposing side of the graphene structure from the first electrically conductive structure. A top electrode may be formed over the graphene structure and electrically coupled with the second electrically conductive structure. The first and second electrically conductive structures may be configured to provide an electric field across the graphene structure. | 2013-01-31 |
20130029461 | METHODS FOR FABRICATING ANODE SHORTED FIELD STOP INSULATED GATE BIPOLAR TRANSISTOR - A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer. | 2013-01-31 |
20130029462 | METHOD OF MANUFACTURING A THIN-FILM TRANSISTOR - A method of manufacturing a thin film transistor is provided. The method includes forming a lower organic semiconductor layer, forming an upper organic semiconductor layer on the lower organic semiconductor layer, the upper organic semiconductor layer having solubility and conductivity higher than those of the lower organic semiconductor layer, forming a source electrode and a drain electrode spaced apart from each other and respectively overlapping the upper organic semiconductor layer, and dissolving the upper organic semiconductor layer selectively by using the source electrode and the drain electrode as a mask. | 2013-01-31 |
20130029463 | Methods of Forming a PMOS Device with In Situ Doped Epitaxial Source/Drain Regions - Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming extension implant regions in a PMOS region and a NMOS region of a semiconducting substrate for a PMOS device and a NMOS device, respectively and, after forming the extension implant regions, performing a first heating process. The method further includes forming a plurality of cavities in the PMOS region of the substrate, performing at least one epitaxial deposition process to form a plurality of in-situ doped semiconductor layers that are positioned in or above each of said cavities, and forming a masking layer that exposes the NMOS region and covers the PMOS region. The method concludes with the steps of forming source/drain implant regions in the NMOS region of the substrate for the NMOS device and performing a second heating process. | 2013-01-31 |
20130029464 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING NON-OXIDIZING RESIST REMOVAL - Methods are provided for fabricating integrated circuits using non-oxidizing resist removal. In accordance with one embodiment the method includes forming a gate electrode structure overlying a semiconductor substrate and applying and patterning a layer of resist to expose a portion of the semiconductor substrate adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate using the gate electrode structure and the layer of resist as an implant mask. The layer of resist is removed in a non-oxidizing ambient and the implanted conductivity determining ions are activated by thermal annealing. | 2013-01-31 |
20130029465 | MANUFACTURING METHOD OF MEMORY STRUCTURE - The instant disclosure relates to a manufacturing method of memory structure for dynamic random-access memory (DRAM). The method includes the steps of: (a) providing a substrate having a plurality of parallel trenches formed on a planar surface thereof each defining a buried gate, where a first insulating layer is formed on the planar surface of the substrate; (b) forming a gate oxide layer on the surface of each trench that defines the buried gate; (c) disposing a metal filler on the gate oxide layer to fill each of the trenches; (d) removing the metal filler in the upper region of each trench to selectively expose the gate oxide layer; (e) implanting ions at an oblique angle toward the exposed portions of the gate oxide layer in each trench to respectively form a drain electrode and a source electrode in the substrate abreast the gate oxide layer. | 2013-01-31 |
20130029466 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor device, including: a first semiconductor region of a first conductivity type; a second semiconductor region having pairs of first pillar regions of the first conductivity type, and second pillar regions of a second conductivity type alternately provided; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the first conductivity type; and control electrodes each provided within a trench through an insulating film, a sidewall of the trench being formed so as to contact each of the third semiconductor region and the fourth semiconductor region. | 2013-01-31 |
20130029467 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A first groove is formed in a semiconductor substrate. A first conductive film is formed in the first groove and over the semiconductor substrate. The first conductive film is planarized over the semiconductor substrate. The planarized first conductive film is selectively etched to have the planarized first conductive film remain in a lower portion of the first groove. | 2013-01-31 |
20130029468 | Nonvolatile Memory Device and Method for Fabricating the Same - Provided are a nonvolatile memory device and a method for fabricating the same. The method includes sequentially stacking on a semiconductor substrate a first interlayer dielectric film, a first sacrificial layer, a second interlayer dielectric film, and a second sacrificial layer, forming a resistance variable layer and a first electrode penetrating the first and second interlayer dielectric films and the first and second sacrificial layers, forming an upper trench by removing a top portion of the first electrode, filling the upper trench with a channel layer, exposing a portion of a side surface of the resistance variable layer by removing the second sacrificial layer, forming an insulation layer within the channel layer, and forming a second electrode on the exposed resistance variable layer. | 2013-01-31 |
20130029469 | NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory apparatus including a substrate, lower-layer electrode wires provided on the substrate, an interlayer insulating layer provided with contact holes at locations respectively opposite to the lower-layer electrode wires, resistance variable layers which are respectively connected to the lower-layer electrode wires; and non-ohmic devices which are respectively provided on the resistance variable layers. The non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer. One layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer. | 2013-01-31 |
20130029470 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A dummy insulating film is formed over a semiconductor substrate by using a source material that is free of carbon as an essential component. A hole that penetrates the dummy insulating film is formed. A conductive film is formed, which covers at least a side wall of the hole of the dummy insulating film. The dummy insulating film is removed to expose an outer surface of the conductive film. | 2013-01-31 |
20130029471 | REDUCTION OF STI CORNER DEFECTS DURING SPE IN SEMICONDUCTOR DEVICE FABRICATION USING DSB SUBSTRATE AND HOT TECHNOLOGY - A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing. | 2013-01-31 |
20130029472 | GaN BONDED SUBSTRATE AND METHOD OF MANUFACTURING GaN BONDED SUBSTRATE - A gallium nitride (GaN) bonded substrate and a method of manufacturing a GaN bonded substrate in which a polycrystalline nitride-based substrate is used. The method includes loading a single crystalline GaN substrate and a polycrystalline nitride substrate into a bonder; raising the temperature in the bonder; bonding the single crystalline GaN substrate and the polycrystalline nitride substrate together by pressing the single crystalline GaN substrate and the polycrystalline nitride substrate against each other after the step of raising the temperature; and cooling the resultant bonded substrate. | 2013-01-31 |
20130029473 | METHOD OF CLEAVING SUBSTRATE AND METHOD OF MANUFACTURING BONDED SUBSTRATE USING THE SAME - A method of cleaving a substrate and a method of manufacturing a bonded substrate using the same, in which warping in a cleaved substrate is reduced. The method includes the following steps of: forming an ion implantation layer by implanting ions into a substrate; annealing the substrate in which the ion implantation layer is formed; implanting ions again into the ion implantation layer of the substrate; and cleaving the substrate along the ion implantation layer by heating the substrate into which ions are implanted. | 2013-01-31 |
20130029474 | METHOD FOR TRANSFERRING A MONOCRYSTALLINE SEMICONDUCTOR LAYER ONTO A SUPPORT SUBSTRATE - A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization. | 2013-01-31 |
20130029475 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring. | 2013-01-31 |
20130029476 | DICING PROCESS AND DICING APPARATUS - A dicing process is provided for cutting a wafer along a plurality of predetermined scribe lines into a plurality of dies that are releasably adhered to a release film. The dicing process includes: (a) disposing a wafer-breaking carrier on a supporting device, the wafer-breaking carrier having a chipping unit; (b) disposing the wafer above the supporting device such that the chipping unit is at a position corresponding to the scribe lines; and (c) adhering a release surface of the release film to the wafer by applying a force to the release film to contact the chipping unit of the wafer-breaking carrier with the wafer, such that the wafer is split along the scribe lines into the dies. | 2013-01-31 |
20130029477 | APPARATUS INCLUDING 4-WAY VALVE FOR FABRICATING SEMICONDUCTOR DEVICE, METHOD OF CONTROLLING VALVE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE APPARATUS - An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass. | 2013-01-31 |
20130029478 | METHOD OF FABRICATING HIGH-MOBILITY DUAL CHANNEL MATERIAL BASED ON SOI SUBSTRATE - The present invention discloses a method of fabricating high-mobility dual channel material based on SOI substrate, wherein compressive strained SiGe is epitaxially grown on a conventional SOI substrate to be used as channel material of PMOSFET; Si is then epitaixally grown on SiGe, and approaches such as ion implantation and annealing are employed to allow relaxation of part of strained SiGe and transfer strain to the Si layer thereon so as to form strained Si material as channel material of NMOSFET. With simple process and easy realization, this method can provide high-mobility channel material for NMOSFET and PMOSFET at the same time, well meeting the requirement of simultaneously enhancing the performance of NMOSFET and PMOSFET devices and therefore providing potential channel material for CMOS process of the next generation. | 2013-01-31 |
20130029479 | ARRANGEMENT, SYSTEM, AND METHOD FOR PROCESSING MULTILAYER BODIES - The invention relates to a multilayer body arrangement, which comprises at least two multilayer bodies each having at least one surface to be processed as well as at least one device for positioning the multilayer bodies, wherein the device is configured such that the respective surfaces to be processed are opposite each other and thus form a quasi-closed processing space disposed between the surfaces, in which the processing occurs. It further relates to a system for processing multilayer bodies with such a multilayer body arrangement, as well as a method for processing multilayer bodies, wherein the multilayer bodies are disposed such that the respective surfaces to be processed are opposite each other and thus form a quasi-closed processing space disposed between the surfaces, in which the processing occurs. | 2013-01-31 |
20130029480 | FREE FORM PRINTING OF SILICON MICRO- AND NANOSTRUCTURES - A method of making a three-dimensional structure in semiconductor material includes providing a substrate ( | 2013-01-31 |
20130029481 | TEMPLATED CIRCUITRY FABRICATION - A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate. | 2013-01-31 |
20130029482 | SPACER STRUCTURES OF A SEMICONDUCTOR DEVICE - The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width. | 2013-01-31 |
20130029483 | METHOD AND SYSTEM FOR FORMING CONDUCTIVE BUMPING WITH COPPER INTERCONNECTION - A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material. The method further includes depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via, and forming a diffusion barrier layer. Moreover, the method includes depositing and patterning a photoresist layer on the diffusion barrier layer, and at least partially filling the second via with a metal material. The metal material is conductively connected to the copper material through the diffusion barrier layer. The method further includes removing the photoresist and the diffusion barrier layer not covering by the metal material. | 2013-01-31 |
20130029484 | MAINTAINING MASK INTEGRITY TO FORM OPENINGS IN WAFERS - One or more openings in an organic mask layer deposited on a first insulating layer over a substrate are formed. One or more openings in the first insulating layer are formed through the openings in the organic mask using a first iodine containing gas. An antireflective layer can be deposited on the organic mask layer. One or more openings in the antireflective layer are formed down to the organic mask layer using a second iodine containing gas. The first insulating layer can be deposited on a second insulating layer over the substrate. One or more openings in the second insulating layer can be formed using a third iodine containing gas. | 2013-01-31 |
20130029485 | METHOD OF MAKING A DIE WITH RECESSED ALUMIUM DIE PADS - A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer. | 2013-01-31 |
20130029486 | METHOD OF MANUFACTURING AN ELECTRONIC DEVICE HAVING A PLASTIC SUBSTRATE AND CORRESPONDING CARRIER - A method of manufacturing an electronic device on a plastic substrate includes: providing a carrier as a rigid support for the electronic device; providing a metallic layer on the carrier; forming the plastic substrate on the metallic layer, the metallic layer guaranteeing a temporary bonding of the plastic substrate to the carrier; forming the electronic device on the plastic substrate; and releasing the carrier from the plastic substrate. Releasing the carrier comprises immersing the electronic device bonded to the carrier in a oxygenated water solution that breaks the bonds between the plastic substrate and the metallic layer. | 2013-01-31 |
20130029487 | MANUFACTURING METHOD OF DEVICE - A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner surface of the hole and connected to the second support film and the first support film; forming a first opening in the second support film into a first pattern designed such that the connection between the crown-shaped electrode and the second support film is at least partially maintained; removing at least a part of the second sacrificial film through the first opening; forming a second opening in the first support film with use of the first opening; and removing the first sacrificial film through the second opening. This method is able to prevent misalignment of openings between the support films. | 2013-01-31 |
20130029488 | Single Liner Process to Achieve Dual Stress - Methods for imparting a dual stress property in a stress liner layer of a semiconductor device. The methods include depositing a metal layer over a compressive stress liner layer, applying a masking agent to a portion of the metal layer to produce a masked and unmasked region of the metal layer, etching the unmasked region of the metal layer to remove the metal layer in the unmasked region to thereby expose a corresponding portion of the compressive stress liner layer, removing the mask to expose the metal layer from the masked region, and irradiating the compressive stress liner layer to impart a tensile stress property to the exposed portion of the compressive stress liner layer. Methods are also provided for imparting a compressive-neutral dual stress property in a stress liner layer, as well as for imparting a neutral-tensile dual stress property in a stress liner layer. | 2013-01-31 |
20130029489 | POLISHING SLURRY, POLISHING METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The present invention relates to a polishing slurry for performing chemical mechanical polishing on a surface to be polished including a surface made of silicon oxide and a surface made of metal, characterized in that it includes cerium oxide particles, a complexing agent, and water. | 2013-01-31 |
20130029490 | HIGH LATERAL TO VERTICAL RATIO ETCH PROCESS FOR DEVICE MANUFACTURING - A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask. | 2013-01-31 |
20130029491 | METHOD OF HARD MASK CD CONTROL BY AR SPUTTERING - A method for etching features into a silicon based etch layer through a patterned hard mask in a plasma processing chamber is provided. A silicon sputtering is provided to sputter silicon from the silicon based etch layer onto sidewalls of the patterned hard mask to form sidewalls on the patterned hard mask. The etch layer is etched through the patterned hard mask. | 2013-01-31 |
20130029492 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - A plasma processing method and a plasma processing apparatus in which a stable process region can be ensured in a wide range, from low microwave power to high microwave power. The plasma processing method includes making production of plasma easy in a region in which production of plasma by continuous discharge is difficult, and plasma-processing an object to be processed, with the generated plasma, wherein the plasma is produced by pulsed discharge in which ON and OFF are repeated, radio-frequency power for producing the pulsed discharge, during an ON period, is a power to facilitate production of plasma by continuous discharge, and a duty ratio of the pulsed discharge is controlled so that an average power of the radio-frequency power per cycle is power in the region in which production of plasma by continuous discharge is difficult. | 2013-01-31 |
20130029493 | PLASMA ETCHING METHOD, CONTROL PROGRAM AND COMPUTER STORAGE MEDIUM - A plasma etching method, for plasma-etching a target substrate including at least a film to be etched, an organic film to become a mask of the to-be-etched film, and a Si-containing film which are stacked in order from bottom, includes the first organic film etching step, the treatment step and the second organic film etching step when the organic film is etched to form a mask pattern of the to-be-etched film. In the first organic film etching step, a portion of the organic film is etched. In the treatment step, the Si-containing film and the organic film are exposed to plasma of a rare gas after the first organic film etching step. In the second organic film etching step, the remaining portion of the organic film is etched after the treatment step. | 2013-01-31 |
20130029494 | PLASMA ETCHING METHOD, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND PLASMA ETCHING DEVICE - Provided is a plasma etching method increasing the selectivity of a silicon nitride film in relation to the silicon oxide film or silicon functioning as a base. In a plasma etching method setting a pressure in a processing container as a predetermined level by exhausting a processing gas while supplying the processing gas into the processing container, generating plasma by supplying external energy to the processing container, and setting a bias applied to a holding stage holding a substrate in the processing container as predetermined value to selectively etch the silicon nitride film with respect to a silicon and/or silicon oxide film, the processing gas includes a plasma excitation gas, a CHxFy gas, and at least one oxidizing gas selected from the group consisting of O | 2013-01-31 |
20130029495 | REMOVAL OF SILICON NITRIDES DURING MANUFACTURING OF SEMICONDUCTOR DEVICES - A method to remove excess material during the manufacturing of semiconductor devices includes providing a semiconductor wafer comprising silicon nitride deposited thereon and applying a chemical solution to the semiconductor wafer, wherein the chemical solution comprises a combination of sulfuric acid and deionized water. | 2013-01-31 |
20130029496 | Methods and Apparatus for a Gas Panel with Constant Gas Flow - A gas panel according to various aspects of the present invention is configured to deliver a constant flow rate of gases to a reaction chamber during a deposition process step. In one embodiment, the gas panel comprises a deposition sub-panel having a deposition injection line, a deposition vent line, and at least one deposition process gas line. The deposition injection line supplies a mass flow rate of a carrier gas to a reactor chamber. Each deposition process gas line may include a pair of switching valves that are configured to selectively direct a deposition process gas to the reactor chamber or a vent line. The deposition vent line also includes a switching valve configured to selectively direct a second mass flow rate of the carrier gas that is equal to the sum of the mass flow rate for all of the deposition process gases to the reactor chamber or a vent line. The gas panel is configured to substitute the mass flow rate of the deposition vent line with the mass flow rate of the deposition process lines, such that when the deposition vent line is directed to the reactor chamber the deposition process lines are directed to the vent line and when the deposition vent line is directed to the vent line the deposition process lines are directed to the reactor chamber. The substitution of the two mass flow rates maintains a constant mass flow rate of gases to the reactor chamber throughout the deposition process step. | 2013-01-31 |
20130029497 | Method of Crystallizing Amorphous Silicon Films by Microwave Irradiation - A method is developed to crystallize amorphous silicon (a-Si) thin films, in cold environment, by combining microwave-absorbing materials (MAM) and microwave irradiation. The MAM is set on top or around of the a-Si thin film. MAM composes of dielectric, magnetic, semiconductor, ferroelectric and carbonaceous material oxides, carbides, nitrides and borides, which will absorb and concentrate electric or magnetic field of the microwave. The microwave frequency is selected from 1 to 50 GHz, at a power density not less than 5 W/cm | 2013-01-31 |
20130029498 | METHOD FOR REDUCING DIELECTRIC CONSTANT OF FILM USING DIRECT PLASMA OF HYDROGEN - A method for reducing a dielectric constant of a film includes (i) forming a dielectric film on a substrate; (ii) treating a surface of the film without film formation, and (III) curing the film. Step (i) includes providing a dielectric film containing a porous matrix and a porogen on a substrate, step (ii) includes, prior to or subsequent to step (iii), treating the dielectric film with charged species of hydrogen generated by capacitively-coupled plasma without film deposition to reduce a dielectric constant of the dielectric film, and step (iii) includes UV-curing the dielectric film to remove at least partially the porogen from the film. | 2013-01-31 |
20130029499 | METHODS OF THERMALLY PROCESSING A SUBSTRATE - The present invention generally relates to methods for thermally processing substrates. In one embodiment, a substrate having an amorphous thin film thereon is subjected to a first pulse of electromagnetic energy having a first fluence insufficient to complete thermal processing. After a predetermined amount of time, the substrate is then subjected to a second pulse of electromagnetic energy having a second fluence greater than the first fluence. The second fluence is generally sufficient to complete the thermal processing. Exposing the substrate to the lower fluence first pulse before the second pulse reduces damage to a thin film disposed on the substrate. In another embodiment, a substrate is exposed to a plurality of electromagnetic energy pulses. The plurality of electromagnetic energy pulses are spaced at increasing intervals to reduce the rate of recrystallization of a film on the substrate, thus increasing the size of the crystals formed during the recrystallization. | 2013-01-31 |
20130029500 | CONNECTOR AND FABRICATION METHOD THEREOF - The present invention provides a connector including a substrate, at least a conductive via disposed inside the substrate, a pad disposed on one surface of the substrate and electrically connected to the conductive via, a resilient flange disposed on the pad, and an anisotropic conductive adhesive interposed between the pad and the resilient flange to electrically connect the pad with the resilient flange. | 2013-01-31 |
20130029501 | BUS BAR EDGE STRUCTURE OF ELECTRIC JUNCTION BOX - A bus bar edge structure of an electric junction box having a junction block main body, a bus bar-receiving gap arranged on the junction block main body, and a space communicating with the bus bar-receiving gap and arranged in a thickness direction of the bus bar includes a projection piece projecting from an edge of the bus bar at an opening side of the space in the thickness direction of the bus bar. An electric wire led from the junction block main body is guided to the projection piece so as to prevent interference with the edge of the bus bar. The projection piece functions as a press-operating portion configured to insert the bus bar into the bus bar-receiving gap. The projection piece is positioned in an opening of a longitudinal groove arranged in the space so as to prevent the electric wire from entering into the opening. | 2013-01-31 |
20130029502 | Connector Assembly - A connector assembly includes an insertion member that includes a plurality of contact pads, and a housing that defines an opening at a first end configured to receive the insertion member. The upper inside surface and lower inside surface of the housing define a plurality of slots into which are placed electrical contacts. Each electrical contact includes a cross-member, a first and a second extension member, a resilient member, and a mating extension. The first and second extension members extend from respective ends of the cross-member and are positioned within respective slots of the housing. The resilient member extends from the cross member from a position between the first and the second extension members. A mating extension extends from the other side of the cross-member and through an opening defined in the rear wall of the housing. The resilient member is configured to make electrical contact with a contact pad of the insertion member. | 2013-01-31 |
20130029503 | Connector Assembly - A connector assembly includes an insertion member that includes a plurality of contact pads, and a housing that defines an opening at a first end configured to receive the insertion member. The upper inside surface and the lower inside surface of the housing define a group of slots. Electrical contacts are positioned adjacent to one another in the slots of the housing. Each electrical contact includes a cross-member, and a first and a second extension member that extend from respective ends of the cross member. At least one of the first and second extensions is configured as a resilient member configured to make electrical contact with a contact pad of the insertion member. A mating extension extends from the cross-member and through an opening defined in the rear wall of the housing. | 2013-01-31 |
20130029504 | LOCKING DEVICE FOR ELECTRICAL SOCKET - A locking device is provided for an electrical socket. The locking device includes a device body having a projecting member projecting from the device body, wherein the projecting member is adapted for engagement with an aperture provided in an electrical socket. The projecting member has first and second positions. In a first position the projecting member is adapted for engagement with the aperture and the locking device can be connected and disconnected from the socket. In a second position, the projecting member cannot disengage from the aperture and the projecting member is lockable in the second position. The electrical socket may be a power cable receiver on an electrical appliance, or a power supply socket. | 2013-01-31 |
20130029505 | Blockout Device for USB Port - A blockout device for a USB port is disclosed. The blockout device prevents contamination, damage or misuse of the USB port when not in use. The blockout device includes a locking member, a body member and a shell. The locking member has a bottom and a top. The bottom of the locking member includes a plurality of teeth for engaging the USB port. The body member has a top, a bottom and sides defining a channel therein. The locking member is positioned within the channel of the body. The shell has a cavity that receives the locking member and the body member. The locking member and the body member are positioned within the cavity of the shell when the blockout device is installed in the USB port. | 2013-01-31 |
20130029506 | SOCKET PROTECTION DEVICE AND CIRCUIT BOARD ASSEMBLY - A socket protection device includes a fixing member, a cover, a limiting member, and an operation member. The fixing member is secured to a circuit board. The fixing member includes a pair of first connecting blocks. The cover includes a second connecting block, a first latching portion, and a second latching portion. The limiting member is secured to the circuit board. The operation member includes a shaft and an operation rod secured to the shaft. The shaft rotatably connects the cover to the fixing member via the first and second connecting blocks. When the operation rod is pressed to drive the shaft to rotate, the cover is rotated toward the socket. When the cover covers the socket, the first latching portion latches the limiting member, and the second latching portion latches the operation rod. | 2013-01-31 |
20130029507 | PROTECTING PLUG FOR AUDIO JACK - A protecting plug for an audio jack includes a plug member and a decoration member. The plug member has a plug portion matching with an audio jack, a coupling portion, and a flange portion provided between the coupling portion and the plug portion. The decoration member includes a model portion, a coupling hole formed on the model portion, and a decoration connecting portion formed at a boundary surface of the coupling hole. By coupling the coupling portion to the coupling hole and making a receiving surface of the flange portion hold and/or connect with the decoration connecting portion, the plug member is assembled with the decoration member. | 2013-01-31 |
20130029508 | PLUG ELEMENT WITH LOCKING SEAL - The invention relates to a plug element ( | 2013-01-31 |
20130029509 | SELF-LOCKING CONNECTOR CLIP - A clip for connecting a conductor to a circuit interrupter in an electrical device is generally U-shaped and self-locking. The clip has a generally arcuate body and two generally linear legs. The legs extend vertically from the body. The legs have beveled edges that together with the generally arcuate body of the clip and a flat portion of the clip, allow an interlock to be formed between the clip and the conductor when the clip is in close contact with the conductor. | 2013-01-31 |
20130029510 | CONNECTOR WITH LOCKING MECHANISM - A locking mechanism for a connector ( | 2013-01-31 |
20130029511 | CABLE SYSTEM AND METHODS OF ASSEMBLING A CABLE SYSTEM - A cable includes at least one conductor to transmit electrical signals and a shield layer positioned about the at least one conductor. The shield layer shields an environment external to the cable from electromagnetic radiation generated by the electrical signals. The cable also includes a first retention sleeve positioned about the shield layer and a second retention sleeve coupled with the first retention sleeve and to the shield layer. | 2013-01-31 |
20130029512 | PLUG AND JACK SYSTEM AND ELECTRONIC DEVICE USING SAME - An electronic device includes a housing, a circuit board, a display having a plug, a jack defined in the circuit board, a locking plate releasably fixed to the housing. The jack is electrically connected to the plug so the display is electrically connected to the circuit board. After a plug is inserted into the jack, the locking plate is fixed to the housing to impact the plug, thereby preventing the plug from disconnecting from the jack. | 2013-01-31 |
20130029513 | COAXIAL CABLE CONNECTOR HAVING A BREAKAWAY COMPRESSION SLEEVE - An outer sleeve of a coaxial cable connector comprising a tubular body operably attached to a coupling member, a compression portion frangibly connected to the tubular body, wherein the compression portion is configured to break away from the tubular body and displace towards the first end of the tubular body within the tubular body upon an axial compressive force is provided. Moreover, a post configured to receive a prepared end of a coaxial cable, a coupling member, axially rotatable with respect to the post, an outer sleeve engageable with the coupling member, the outer sleeve having a first end and a second end, wherein rotation of the outer sleeve rotates the coupling member, and a compression portion structurally integral with the outer sleeve, wherein the compression portion is configured to break apart from the outer sleeve when axially compressed is further provided. Furthermore, associated methods are also provided. | 2013-01-31 |
20130029514 | MODULAR WIRING SYSTEM - In at least one embodiment, there is an electrical device comprising a functional module comprising a housing having a front face and a back face, and at least three arcuate blades extending out from the housing. At least one of the at least three arcuate blades has a locking section. The functional module can be used in a wiring system comprising at least one wiring module. The wiring module can include a housing having a front face and a back face and at least one opening for receiving at least one of the at least three arcuate blades. The disclosure can also include a wiring module which can be used separately from the functional module wherein the wiring module includes a housing having at least one movable arm. Inside the wiring module is a plurality of contacts disposed in the housing, wherein these contacts are configured to couple to electrical wiring. | 2013-01-31 |
20130029515 | USB3.0 CONNECTOR AND METHOD OF MAKING THE SAME - A USB3.0 connector includes an insulative body, a plurality of first and second terminals, and an outer shell covering the insulative body. The insulative body includes a base that has a base upper wall, a base lower wall, and two base sidewalls. The base lower wall has a rear end notched in a frontward direction to form a plurality of alternating shallow and deep notches to position first and second legs of the first and second terminals, which are bent downwardly. The alternating shallow and deep notches space the first legs apart from the secondlegs, respectively. The number of component parts for assembly is therefore reduced. | 2013-01-31 |
20130029516 | CONNECTOR - There is provided a connector. A lock arm is connected at a leading end-side and a rear end-side of a housing, supported at both ends thereof along an insertion/pulling out direction with respect to an opposite connector housing, and elastically deformable with the connection parts with the housing serving as fulcrums. A locking claw is formed at the lock arm and locked into a locking hole of the opposite connector housing when inserting the housing into the opposite connector housing. The lock arm has a lock release part which releases a locked state of the locking claw to the locking hole by being pressed toward the rear end-side beyond the locking claw. A position of the fulcrum at the rear end-side is arranged at an opposite side to a protruding direction of the locking claw, compared to a position of the fulcrum at the leading end-side. | 2013-01-31 |
20130029517 | TERMINAL FOR ENERGIZATION - A terminal for conduction includes an insulating member that is fixed to a housing and that includes a flange portion that extends along the housing; a first terminal member that is provided to penetrate through the insulating member and that includes a tubular portion, the first terminal member being conductive; and a second terminal member that includes an engagement portion and that is inserted into the tubular portion of the first terminal member, the second terminal member being fixed to the first terminal member through the engagement portion in the tubular portion and extending in an axial direction of the tubular portion. The engagement portion is positioned in a space between one surface and the other surface of the flange portion in the axial direction. | 2013-01-31 |
20130029518 | Receptacle Connector - A receptacle connector having a base part, which has at least one insulation displacement contact for making electrical contact with an electrical conductor, and having a top part, which has at least one conductor infeed opening for in each case one electrical conductor with which contact is to be made, and at least one contact accommodation opening, which in each case opens out into an associated conductor infeed opening, for accommodating an insulation displacement contact of the base part when the top part is fitted onto the base part. The receptacle connector is designed for fitting into a housing. For this purpose, the base part and/or the top part have sealing lips with a contour which is matched to an associated housing wall in order to fit the base part and/or the top part into a housing wall in a sealed manner. | 2013-01-31 |