05th week of 2013 patent applcation highlights part 16 |
Patent application number | Title | Published |
20130026516 | LIGHT-EMITTING DIODE (LED) PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF - A light-emitting diode (LED) package structure and a packaging method thereof are provided. The packaging method includes: forming first conductive layers on a silicon substrate, and forming a reflection cavity and electrode via holes from a top surface of the silicon substrate; forming a reflection layer on predetermined areas of a surface of the reflection cavity, and forming second conductive layers and metal layers on surfaces of the electrode via holes; and mounting a chip and forming an encapsulant, so as to fabricate the LED package structure. In the present invention, there is no need to perform at least two plating processes for connecting upper and lower conductive layers of the silicon substrate in the electrode via holes, and the problem of poor connection of the conductive layers in the electrode via holes can be avoided, thereby making the fabrication processes simplified and time-effective and also improving the overall production yield. | 2013-01-31 |
20130026517 | ORGANIC LUMINANCE DEVICE, METHOD FOR MANUFACTURING SAME AND LIGHTING APPARATUS INCLUDING SAME - An organic luminance device includes a base substrate, a organic luminance multi-layered structure and a cover substrate. Furthermore, a protective film is used to wrap the light emitting surface and at least one lateral surface of the base substrate to prevent the substrate from crack. The protective film may be doped with one or more dopants having a refractive index different from original material of the protective film. | 2013-01-31 |
20130026518 | WAFER LEVEL LED PACKAGE AND METHOD OF FABRICATING THE SAME - Disclosed are a wafer level LED package and a method of fabricating the same. The method of fabricating a wafer level LED package includes: forming a plurality of semiconductor stacks on a first substrate, each of the semiconductor stacks comprising a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active region disposed between the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer; preparing a second substrate comprising first lead electrodes and second lead electrodes arranged corresponding to the plurality of semiconductor stacks; bonding the plurality of semiconductor stacks to the second substrate; and cutting the first substrate and the second substrate into a plurality of packages after the bonding is completed. Accordingly, the wafer level LED package is provided. | 2013-01-31 |
20130026519 | LIGHT-EMITTING DEVICE - A structure of a light-emitting device includes the following components: a substrate; an epitaxial structure on the substrate, the epitaxial structure including at least a first conductivity type semiconductor layer, a light-emitting active layer, and a second conductivity type semiconductor layer; a first electrode on the first conductivity type semiconductor layer; a transparent conductive layer between the first electrode and the first conductivity type semiconductor layer; and a three-dimensional distributed Bragg reflector (DBR) layer between the transparent conductive layer and the first conductivity type semiconductor layer. | 2013-01-31 |
20130026520 | LIGHT-EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - An LED package includes a substrate, an LED chip arranged on the substrate, and a light transmission layer arranged on a light output path of the LED chip. The substrate includes a first electrode and a second electrode separated and electrically insulated from the first electrode. The LED chip is electrically connected to the first electrode and the second electrode of the substrate. The light transmission layer comprises two parallel transparent plates and a fluorescent layer sandwiched between the two transparent plates. The LED package further includes a transparent encapsulation layer sealing the LED chip therein, and in one embodiment, the light transmission layer is located on the encapsulation layer and in another embodiment, the encapsulation layer also seals the light transmission layer therein. A method for manufacturing the LED package is also provided. | 2013-01-31 |
20130026521 | LIGHT EMITTING DEVICES AND METHODS OF MANUFACTURING THE SAME - The inventive concept provides light emitting devices and methods of manufacturing a light emitting device. The light emitting device may include a transparent substrate including a first region and a second region, a first transparent electrode disposed on a first surface of the transparent substrate, a second transparent electrode facing and spaced apart from the first transparent electrode, an organic light emitting layer disposed between the first and second transparent electrodes, an assistant electrode disposed between the first and second transparent electrodes and selectively masking the second region, and a light path changing structure disposed on a second surface of the transparent substrate and selectively masking the second region. | 2013-01-31 |
20130026522 | SURFACE-MOUNT LIGHT EMITTING DEVICE - A surface-mount light emitting device is provided comprising a light emitting element ( | 2013-01-31 |
20130026523 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a first light shielding layer disposed on the second surface of the substrate; and a second light shielding layer disposed on the first light shielding layer and directly contacting with the first light shielding layer, wherein a contact interface is between the first light shielding layer and the second light shielding layer. | 2013-01-31 |
20130026524 | LIGHT EMITTING DIODE - A light emitting diode (LED) is provided. The LED comprises a semiconductor composite layer stacked laterally and a phosphor substrate. The phosphor substrate covers a lateral surface of the semiconductor composite layer. | 2013-01-31 |
20130026525 | LIGHT EMITTING DEVICES, SYSTEMS, AND METHODS OF MANUFACTURING - A light emitting device includes: a substrate; an n layer; an active light emitting region, a p layer; and a support portion configured to provide both mechanical support and improve light transmission disposed over a light emitting side of the device. | 2013-01-31 |
20130026526 | LIGHT-EMITTING DIODE HOUSING COMPRISING FLUOROPOLYMER - A light-emitting diode housing comprising fluoropolymer is disclosed. The light-emitting diode housing supports a light-emitting diode chip and reflects at least a portion of the light emitted from the light-emitting diode chip. | 2013-01-31 |
20130026527 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE LIGHT EMITTING DEVICE - Provided is a light emitting device having strong bonding strength between the light emitting element and the wavelength converting member is provided. In the light emitting device, a light emitting element and a wavelength converting member are bonded. Particularly, the light emitting element has, from the wavelength converting member side, a first region and a second region, the wavelength converting member has, from the light emitting element side, a third region and a fourth region. The first region has an irregular atomic arrangement compared with the second region, the third region has an irregular atomic arrangement compared with the fourth region, and the first region and the third region are directly bonded. | 2013-01-31 |
20130026528 | WATERPROOF TRANSPARENT LED SHIELD STRUCTURE - A waterproof transparent LED shield structure has a singular LED component with a circuit board and an LED lighting component, with the circuit board connected with protruding electric pins. A hard transparent shield has a base board and a shield. The base board covers the front side of the circuit board, and is configured with a rim to rest against the edge of the circuit board. The shield has a circular side wall and a top end and encloses the LED lighting component. A soft waterproof covering body covers and is attached to the outside of the LED component and hard transparent shield. The soft waterproof covering has a seat part and a projecting part. The seat covers the circuit board, the connecting end of the electric pins and the base board and rim, and the protruding end of the electric pins extends out of the seat part. | 2013-01-31 |
20130026529 | LIGHT EMITTING CHIP PACKAGE AND METHOD FOR MAKING SAME - A light emitting chip package includes a substrate, an insulation layer, a patterned electric conductive layer, a light emitting chip, an encapsulation, a plurality of thermal conductors and electrical conductors. The insulation layer is formed on a top surface of the substrate. The patterned electric conductive layer partially covers the insulation layer. The light emitting chip is arranged on the electric conductive layer. The encapsulation covers the light emitting chip and the electric conductive layer. The plurality of thermal conductors is formed at a bottom surface side of the substrate. The plurality of electrical conductors penetrates the insulation layer and connects the conductive layer with the thermal conductor. The plurality of electrical conductors is isolated from each other. | 2013-01-31 |
20130026530 | LIGHT EMITTING DEVICE MODULE - Disclosed is a light emitting device module including a package body, a first lead frame and a second lead frame provided on the package body, a light emitting device electrically connected to the first lead frame and the second lead frame, a first pad and a second pad respectively formed on the lower surfaces of the first lead frame and the second lead frame, and a third pad formed on the lower surface of the package body, wherein at least one of the first pad, the second pad and the third pad includes a plurality of sub-pads. | 2013-01-31 |
20130026531 | NON-POLAR LIGHT EMITTING DIODE HAVING PHOTONIC CRYSTAL STRUCTURE AND METHOD OF FABRICATING THE SAME - A non-polar light emitting diode (LED) having a photonic crystal structure and a method of fabricating the same. A non-polar LED includes a support substrate, a lower semiconductor layer positioned on the support substrate, an upper semiconductor layer positioned over the lower semiconductor layer, a non-polar active region positioned between the lower and upper semiconductor layers, and a photonic crystal structure embedded in the lower semiconductor layer. The photonic crystal structure embedded in the lower semiconductor layer may improve the light emitting efficiency by preventing the loss of light in the semiconductor layer, and the photonic crystal structure is used to improve the polarization ratio of the non-polar LED. | 2013-01-31 |
20130026532 | LIGHT EMITTING DEVICE - A light emitting device of the present invention has a package constituted by a molded article having a light emitting face, a bottom face that is contiguous with the light emitting face, and a rear face that is on the opposite side from the light emitting face, and a pair of leads that are partially embedded in the molded article, protrude from the bottom face, and have ends that bend toward either the light emitting face or the rear face, and a light emitting element that is disposed on one of the pair of leads, the molded article has a front protruding part that protrudes on the light emitting face side, and a rear protruding part that protrudes on the rear face side, between the leads on the bottom face. | 2013-01-31 |
20130026533 | ORGANIC LIGHT-EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An organic light emitting diode display includes a substrate, an organic light emitting diode on the substrate, an organic film configured to cover the organic light emitting diode on the substrate in an organic film deposition area having a first diameter, and an inorganic film configured to cover the organic film on the substrate in an inorganic film deposition area having a second diameter, wherein L | 2013-01-31 |
20130026534 | SILICON LIGHT EMITTING DEVICE AND METHOD OF FABRICATING SAME - A light emitting device ( | 2013-01-31 |
20130026535 | FORMATION OF INTEGRAL COMPOSITE PHOTON ABSORBER LAYER USEFUL FOR PHOTOACTIVE DEVICES AND SENSORS - Methods of forming photoactive devices include infiltrating pores of a solid porous ceramic material with a fluid, which may be a supercritical fluid, carrying at least one single source precursor therein. The single source precursor may be decomposed to form a plurality of particles within the pores of the solid porous ceramic material. Photoactive devices include a solid porous ceramic material exhibiting electrical conductivity, and a plurality of photoactive semiconductor particles within pores of the solid porous ceramic material. | 2013-01-31 |
20130026536 | INSULATED GATE SEMICONDUCTOR DEVICE WITH OPTIMIZED BREAKDOWN VOLTAGE, AND MANUFACTURING METHOD THEREOF - An insulated gate semiconductor device, comprising: a semiconductor body having a front side and a back side opposite to one another; a drift region, which extends in the semiconductor body and has a first type of conductivity and a first doping value; a body region having a second type of conductivity, which extends in the drift region facing the front side of the semiconductor body; a source region, which extends in the body region and has the first type of conductivity; and a buried region having the second type of conductivity, which extends in the drift region at a distance from the body region and at least partially aligned to the body region in a direction orthogonal to the front side and to the back side. | 2013-01-31 |
20130026537 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device is disclosed with layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side. The device can include a drift layer, a first base layer in direct electrical contact to the emitter electrode, a first source region embedded into the first base layer which contacts the emitter electrode and has a higher doping concentration than the drift layer, a first gate electrode in a same plane and lateral to the first base layer, a second base layer in the same plane and lateral to the first base layer, a second gate electrode on top of the emitter side, and a second source region electrically insulated from the second base layer, the second source region and the drift layer by a second insulating layer. | 2013-01-31 |
20130026538 | SEMICONDUCTOR DEVICE HAVING EPITAXIAL STRUCTURES - A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration. | 2013-01-31 |
20130026539 | REPLACEMENT SOURCE/DRAIN FINFET FABRICATION - A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor. | 2013-01-31 |
20130026540 | METHODS AND APPARATUS FOR FORMING SEMICONDUCTOR STRUCTURES - Methods and apparatus for forming semiconductor structures are disclosed herein. In some embodiments, a semiconductor structure may include a first germanium carbon layer having a first side and an opposing second side; a germanium-containing layer directly contacting the first side of the first germanium carbon layer; and a first silicon layer directly contacting the opposing second side of the first germanium carbon layer. In some embodiments, a method of forming a semiconductor structure may include forming a first germanium carbon layer atop a first silicon layer; and forming a germanium-containing layer atop the first germanium carbon layer. | 2013-01-31 |
20130026541 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a high-frequency circuit, it is necessary to block galvanically between active elements such as transistors and between an active element and an external terminal, and thus MIM capacitors or the like are used frequently. Among these MIM capacitors, one coupled to the external terminal is easily affected by static electricity from outside, which easily causes a problem of electro-static breakdown or the like. | 2013-01-31 |
20130026542 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer having a plurality of active regions that are separated by element isolation grooves, a capacitive film having a sidewall covering portion covering a sidewall of the element isolation grooves, and an electrode film laminated on the capacitive film, and a capacitor element is formed by the semiconductor layer, the capacitive film and the electrode film. | 2013-01-31 |
20130026543 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an incident angle. | 2013-01-31 |
20130026544 | FULLY DEPLETED SILICON ON INSULATOR NEUTRON DETECTOR - A method for forming a neutron detector comprises thinning a backside silicon substrate of a radiation detector; and forming a neutron converter layer on the thinned backside silicon substrate of the radiation detector to form the neutron detector. The neutron converter layer comprises one of boron-10 ( | 2013-01-31 |
20130026545 | MULTIPLE WELL DRAIN ENGINEERING FOR HV MOS DEVICES - At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby. | 2013-01-31 |
20130026546 | INTEGRATED CIRCUIT COMPRISING AN ISOLATING TRENCH AND CORRESPONDING METHOD - An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench including an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer including nitrogen or carbon. | 2013-01-31 |
20130026547 | ACTIVE PIXEL SENSOR WITH A DIAGONAL ACTIVE AREA - An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line and a processor based system with such an imaging device. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the fabrication of a smaller imager. The imaging device also may be fabricated to have a diagonal active area to facilitate contact of two adjacent pixels with the single column line and allow linear row select lines, reset lines and column lines. | 2013-01-31 |
20130026548 | IMAGE SENSOR WITH CONTROLLABLE VERTICALLY INTEGRATED PHOTODETECTORS - An image sensor includes front-side and backside photodetectors of a first conductivity type disposed in a substrate layer of the first conductivity type. A front-side pinning layer of a second conductivity type is connected to a first contact. The first contact receives a predetermined potential. A backside pinning layer of the second conductivity type is connected to a second contact. The second contact receives an adjustable and programmable potential. | 2013-01-31 |
20130026549 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING CAPACITOR FOR PROVIDING STABLE POWER AND METHOD OF MANUFACTURING THE SAME - A capacitor and a method of manufacturing the same are provided. A dummy capacitor group is formed in the peripheral circuit area and includes a dummy storage node contact unit, a dielectric, and a dummy plate electrode. A metal oxide semiconductor (MOS) capacitor is formed in the peripheral circuit area and connected to the dummy capacitor group in parallel. Capacitance of the dummy capacitor group may be greater than that of the MOS capacitor. | 2013-01-31 |
20130026550 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides. The guard ring is formed inside the semiconductor region to surround the periphery of the first impurity region. A weak spot is formed on the short side of the rectangular planar structure of the first impurity region. A plurality of electrical contacts are formed in a first portion of the guard ring which faces the long side of the rectangle. A plurality of electrical contracts are not formed in a second portion of the guard ring which faces the weak spot formed on the short side of the rectangle. | 2013-01-31 |
20130026551 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING RESERVOIR CAPACITOR - A semiconductor integrated circuit including a large capacity reservoir capacitor to provide suitable power is provided. The semiconductor integrated circuit includes a semiconductor substrate in which a cell area and a peripheral circuit area are defined, a MOS capacitor formed on the semiconductor substrate corresponding to the peripheral circuit area, and a dummy capacitor group formed on the peripheral circuit area to overlap the MOS capacitor. One electrode of the MOS capacitor and one electrode of the dummy capacitor group are connected to each other and the other electrode of the MOS capacitor and the other electrode of the dummy capacitor group are connected to difference voltage sources from each other. | 2013-01-31 |
20130026552 | SPLIT-GATE FLASH MEMORY EXHIBITING REDUCED INTERFERENCE - A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack. | 2013-01-31 |
20130026553 | NVM Bitcell with a Replacement Control Gate and Additional Floating Gate - Embodiments relate to a nonvolatile memory (“NVM”) bitcell with a replacement metal control gate and an additional floating gate. The bitcell may be created using a standard complementary metal-oxide-semiconductor manufacturing processes (“CMOS processes”) without any additional process steps, thereby reducing the cost and time associated with fabricating a semiconductor device incorporating the NVM bitcell. | 2013-01-31 |
20130026554 | NAND TYPE FLASH MEMORY FOR INCREASING DATA READ/WRITE RELIABILITY - A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are adjacent to each other and formed on the first dielectric layer. Each data storage unit includes at least two floating gates formed on the first dielectric layer, a second dielectric layer formed on the first dielectric layer and between the two floating gates, an inter-gate dielectric layer formed on the two floating gates and the second dielectric layer, at least one control gate formed on the inter-gate dielectric layer, and a third dielectric layer formed on the first dielectric layer and surrounding and tightly connecting with the two floating gates, the inter-gate dielectric layer, and the control gate. | 2013-01-31 |
20130026555 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELLS FORMED TO HAVE DOUBLE-LAYERED GATE ELECTRODES - A nonvolatile semiconductor memory device includes a plurality of floating gate electrodes respectively formed above a semiconductor substrate with first insulating films disposed therebetween, and a control gate electrode formed above the plurality of floating gate electrodes with a second insulating film disposed therebetween. In each of the plurality of floating gate electrodes is formed to have a width of an upper portion thereof in a channel width direction which is smaller than a width of a lower portion thereof in the channel width direction and one of contact surfaces thereof on at least opposed sides which contact the second insulating film is formed to have one surface, and the second insulating film has a maximum film thickness in a vertical direction, the maximum film thickness being set smaller than a distance from a lowest surface to a highest surface of the second insulating film in the vertical direction. | 2013-01-31 |
20130026556 | NAND TYPE FLASH MEMORY FOR INCREASING DATA READ/WRITE RELIABILITY - A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are formed on the first dielectric layer. Each data storage unit includes two floating gates formed on the first dielectric layer, two inter-gate dielectric layers respectively formed on the two floating gates, two control gates respectively formed on the two inter-gate dielectric layers, a second dielectric layer formed on the first dielectric layer, between the two floating gates, between the two inter-gate dielectric layers, and between the two control gates, and a third dielectric layer formed on the first dielectric layer and surrounding and connecting with the two floating gates, the two inter-gate dielectric layers, and the two control gates. | 2013-01-31 |
20130026557 | SONOS NON-VOLATILE MEMORY CELL AND FABRICATING METHOD THEREOF - A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening. | 2013-01-31 |
20130026558 | SEMICONDUCTOR DEVICES INCLUDING VARIABLE RESISTANCE MATERIAL AND METHODS OF FABRICATING THE SAME - The semiconductor device includes an insulating substrate, a channel layer over the insulating substrate, a gate at least partially extending from an upper surface of the channel layer into the channel layer, a source and a drain respectively at opposing sides of the gate on the channel layer, a gate insulating layer surrounding, the gate and electrically insulating the gate from the channel layer, the source, and the drain, and a variable resistance material layer between the insulating substrate and the gate. | 2013-01-31 |
20130026559 | SILICON-CARBIDE MOSFET CELL STRUCTURE AND METHOD FOR FORMING SAME - In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well ( | 2013-01-31 |
20130026560 | SEMICONDUCTOR DEVICE - A parallel p-n layer ( | 2013-01-31 |
20130026561 | Vertical Transistor with Improved Robustness - A transistor is disclosed that includes a semiconductor body having a first horizontal surface. A drift region is arranged in the semiconductor body. A plurality of gate electrodes is arranged in trenches of the semiconductor body. The trenches have a longitudinal direction and extending parallel relative to each other. The longitudinal direction of the trenches extends in a first lateral direction of the semiconductor body. The body regions and the source regions are arranged between the trenches. The body regions are arranged between the drift region and the source regions in a vertical direction of the semiconductor body. In the first horizontal surface, the source regions and the body regions are arranged alternately in the first lateral direction. A source electrode is electrically connected to the source regions and the body regions in the first horizontal surface. | 2013-01-31 |
20130026562 | VERTICAL MEMORY CELL - Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension. | 2013-01-31 |
20130026563 | STRUCTURES AND METHODS FOR FORMING HIGH DENSITY TRENCH FIELD EFFECT TRANSISTORS - A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions. | 2013-01-31 |
20130026564 | Methods of Fabricating Semiconductor Devices - A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer. | 2013-01-31 |
20130026565 | LOW RDSON RESISTANCE LDMOS - A device having a salicide block spacer on a second side of a gate is disclosed. The use of the salicide block spacer indirectly reduces the blocking effects during the implantation processes, thereby lowering the Rdson without compromising the breakdown voltage of the device. | 2013-01-31 |
20130026566 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device according to an embodiment includes: a p-type semiconductor substrate; a p-type first p well which is formed in the semiconductor substrate and in which a bit line connecting transistor configured to connect a bit line of a memory cell and a sense amplifier unit is formed; and an n-type first N well which surrounds the first P well and which is configured to electrically isolate the first P well from the semiconductor substrate. | 2013-01-31 |
20130026567 | FINFET DRIVE STRENGTH MODIFICATION - A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. | 2013-01-31 |
20130026568 | PLANAR SRFET USING NO ADDITIONAL MASKS AND LAYOUT METHOD - A semiconductor power device is supported on a semiconductor substrate with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode. | 2013-01-31 |
20130026569 | METHODS AND APPARATUS RELATED TO HOT CARRIER INJECTION RELIABILITY IMPROVEMENT - In one general aspect, an apparatus can include a substrate, a gate electrode, and a gate dielectric having at least a portion disposed between the gate electrode and the substrate. The apparatus can include a heavily doped drain region disposed within the substrate, and a lightly doped drain region within the substrate and in contact with the heavily doped drain region. The apparatus can also include a medium doped drain region disposed within the lightly doped drain region and having a dopant concentration between a dopant concentration of the heavily doped drain region and a dopant concentration of the lightly doped drain region. | 2013-01-31 |
20130026570 | BORDERLESS CONTACT FOR ULTRA-THIN BODY DEVICES - After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer. | 2013-01-31 |
20130026571 | N-CHANNEL AND P-CHANNEL FINFET CELL ARCHITECTURE WITH INTER-BLOCK INSULATOR - A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks. | 2013-01-31 |
20130026572 | N-CHANNEL AND P-CHANNEL FINFET CELL ARCHITECTURE - A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions. | 2013-01-31 |
20130026573 | BODY CONTACT SOI TRANSISTOR STRUCTURE AND METHOD OF MAKING - The present invention puts forward a body-contact SOI transistor structure and method of making. The method comprises: forming a hard mask layer on the SOI; etching an opening exposing SOI bottom silicon; wet etching an SOI oxide layer through the opening; depositing a polysilicon layer at the opening followed by anisotropic dry etching; depositing an insulating dielectric layer at the opening followed by planarization; forming a gate stack structure by deposition and etching, and forming source/drain junctions of the transistor using ion implantation. By using the present invention, body contact for SOI field-effect transistors can be effectively formed, thereby eliminating floating-body effect in the SOI field-effect transistors, and improving heat dissipation capability of the SOI transistors and associated integrated circuits. | 2013-01-31 |
20130026574 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE - In an inverted staggered type TFT ( | 2013-01-31 |
20130026575 | THRESHOLD ADJUSTMENT OF TRANSISTORS BY CONTROLLED S/D UNDERLAP - Roughly described, an integrated circuit device has formed on a substrate a plurality of transistors including a first subset of at least one transistor and a second subset of at least one transistor, wherein all of the transistors in the first subset have one underlap distance and all of the transistors in the second subset have a different underlap distance. The transistors in the first and second subsets preferably have different threshold voltages, and preferably realize different points on the high performance/low power tradeoff. | 2013-01-31 |
20130026576 | Combined Output Buffer and ESD Diode Device - An integrated circuit ESD protection circuit ( | 2013-01-31 |
20130026577 | SEMICONDUCTOR DEVICE - A high-frequency power amplifier of the type to be mounted in an RF module for mobile phones having high-frequency power field effect transistors and gate protective diodes which are coupled between the gates and the sources of the high-frequency power field effect transistors. The gate protective diodes have an n type region formed over the main surface of a p type epitaxial layer, a first p type region formed at the center of the main surface of the n type region, a second p type region formed over the main surface of the epitaxial layer around the n type region from the periphery of the main surface of the n type region, and p+ type buried layers for coupling the second p type region to a substrate body. The distance between the end portions of the p+ type buried layers and the n+ type region is 7 μm or more. | 2013-01-31 |
20130026578 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a gate dielectric layer on the substrate, and a gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal filling line, a wetting layer, a metal diffusion blocking layer, and a work function layer. The wetting layer is in contact with a sidewall and a bottom surface of the metal filling line. The metal diffusion blocking layer is in contact with the wetting layer and covers the sidewall and the bottom surface of the metal filling line with the wetting layer therebetween. The work function layer covers the sidewall and the bottom surface of the metal filling line with the wetting layer and the metal diffusion blocking layer therebetween. | 2013-01-31 |
20130026579 | Techniques Providing High-K Dielectric Metal Gate CMOS - A method for manufacturing a semiconductor device includes forming a first dummy gate on a substrate, performing a doping process to the substrate, thereby forming a source and a drain at sides of the first dummy gate, performing a first high temperature annealing to activate the source and drain, forming an inter-layer dielectric (ILD) material on the substrate, removing the first dummy gate to create an ILD trench, forming a first high-k dielectric layer within the ILD trench, forming a first dummy cap portion within the ILD trench over the first high-k dielectric layer, performing a second high-temperature annealing to reduce defects in the first high-k dielectric layer, and thereafter, replacing the first dummy cap portion with a first metal gate electrode. | 2013-01-31 |
20130026580 | SEMICONDUCTOR DEVICE - A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions. | 2013-01-31 |
20130026581 | SEMICONDUCTOR DEVICE COMPRISING METAL GATES AND A SILICON CONTAINING RESISTOR FORMED ON AN ISOLATION STRUCTURE - In a semiconductor device comprising sophisticated high-k metal gate structures formed in accordance with a replacement gate approach, semiconductor-based resistors may be formed above isolation structures substantially without being influenced by the replacement gate approach. Consequently, enhanced area efficiency may be achieved compared to conventional strategies, in which the resistive structures may have to be provided on the basis of a gate electrode metal, while, nevertheless, a low parasitic capacitance may be accomplished due to providing the resistive structures above the isolation structure. | 2013-01-31 |
20130026582 | PARTIAL POLY AMORPHIZATION FOR CHANNELING PREVENTION - Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions. | 2013-01-31 |
20130026583 | VIBRATING DEVICE AND ELECTRONIC APPARATUS - A vibrating device has a package having an accommodating space in the interior thereof and a gyro element and an IC chip accommodated in the accommodating space. The package has a plate-like bottom plate having an IC chip mounting area and a vibrating element mounting area. The IC chip mounting area includes an IC chip mounting surface on which the IC chip is mounted. The vibrating element mounting area is arranged in parallel with the IC chip mounting area and includes a vibrating element mounting surface on which the gyro element is mounted. The thickness of the IC chip mounting area is smaller than that of the vibrating element mounting area. The IC chip mounting surface is located closer to a bottom side than the vibrating element mounting surface. | 2013-01-31 |
20130026584 | Micro-Electromechanical System Devices - A micro-electromechanical system (MEMS) device can include a substrate and a first beam suspended relative to a substrate surface. The first beam can include a first portion and a second portion that are separated by an isolation joint made of an insulative material. The first and second portions can each include a first semiconductor and a first dielectric layer. The MEMS device can also include a second beam suspended relative to the substrate surface. The second beam can include a second semiconductor and a second dielectric layer to promote curvature of the second beam. The MEMS device can also include a third beam suspended relative to the substrate surface. The third beam consists essentially of a first material. The second beam is configured to move relative to the third beam in response to an acceleration along an axis perpendicular to the surface of the substrate. | 2013-01-31 |
20130026585 | MRAM Device and Fabrication Method Thereof - According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack. | 2013-01-31 |
20130026586 | CROSS-LOOP ANTENNA - An antenna is provided. This antenna is contained within a package that is secured to an IC (which allows radiation to propagated away for a printed circuit board so as to reduce interference), and this antenna includes two loop antennas that are shorted to ground and that “overlap” and includes a “via wall.” With this configuration, circular polarization can be achieved by varying the relative phases of the input signals, and the “via wall” improves efficiency by reducing surface waves. | 2013-01-31 |
20130026587 | PIXEL SENSOR CELLS AND METHODS OF MANUFACTURING - Pixel sensor cells with an opaque mask layer and methods of manufacturing are provided. The method includes forming a transparent layer over at least one active pixel and at least one dark pixel of a pixel sensor cell. The method further includes forming an opaque region in the transparent layer over the at least one dark pixel. | 2013-01-31 |
20130026588 | PHOTOELECTRIC CONVERSION DEVICE AND METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - The object is to improve the conversion efficiency of a photoelectric conversion device. This object can be achieved by a photoelectric conversion device including an electrode and a semiconductor layer which is provided on one main surface of the electrode and contains a I-III-VI group compound semiconductor, wherein the semiconductor layer includes a connection layer that is located at a position on the one main surface side of the electrode and has a tendency that, the closer to the one main surface, the greater a quotient obtained by dividing an amount of substance of a I-B group element by an amount of substance of a III-B group element becomes. | 2013-01-31 |
20130026589 | MINIATURIZATION ACTIVE SENSING MODULE AND METHOD OF MANUFACTURING THE SAME - A miniaturization active sensing module includes a substrate unit, an active sensing unit, and an optical unit. The substrate unit includes a substrate body, a plurality of first bottom conductive pads disposed on the bottom side of the substrate body, and a plurality of first conductive tracks embedded in the substrate body. The substrate body has at least one first groove formed therein. The active sensing unit includes at least one active sensing chip embedded in the first groove. The active sensing chip has at least one active sensing area and a plurality of electric conduction pads disposed on the top side thereof, and each first conductive track has two ends electrically contacted by one electric conduction pad and one first bottom conductive pad, respectively. The optical unit includes at least one optical element, disposed on the substrate body, for protecting the active sensing area. | 2013-01-31 |
20130026590 | SLOPED STRUCTURE, METHOD FOR MANUFACTURING SLOPED STRUCTURE, AND SPECTRUM SENSOR - A method for manufacturing a sloped structure is disclosed. The method includes the steps of: (a) forming a sacrificial film above a substrate; (b) forming a first film above the sacrificial film; (c) forming a second film having a first portion connected to the substrate, a second portion connected to the first film, and a third portion positioned between the first portion and the second portion; (d) removing the sacrificial film; and (e) bending the third portion of the second film after the step (d), thereby sloping the first film with respect to the substrate. | 2013-01-31 |
20130026591 | SOLID-STATE IMAGE PICKUP APPARATUS - A solid-state image pickup apparatus including a substrate and a solid-state image pickup device. The substrate includes an opening portion. The solid-state image pickup device is mounted as a flip chip on a lower surface of the substrate on a circumference of the opening portion and receives and photo-electrically converts light that is taken in by a lens set on an upper surface of the substrate and enters from the opening portion. The circumference of the opening portion of the substrate is thinner than other portions of the substrate. | 2013-01-31 |
20130026592 | FOCAL PLANE ARRAY AND METHOD FOR MANUFACTURING THE SAME - A method of forming a focal plane array by: forming a first wafer having sensing material provided on a surface, which is covered by a sacrificial layer, the sensing material being a thermistor material defining at least one pixel; providing supporting legs for the pixel within the sacrificial layer, covering them with a further sacrificial layer and forming first conductive portions in the surface of the sacrificial layer that are in contact with the supporting legs; forming a second wafer having read-out integrated circuit (ROIC), the second wafer being covered by another sacrificial layer, into which is formed second conductive portions in contact with the ROIC; bringing the sacrificial oxide layers of the first wafer and second wafer together such that the first and second conductive portions are aligned and bonding them together such that the sensing material is transferred from the first wafer to the second wafer when a sacrificial bulk layer of the first wafer is removed; and removing the sacrificial layers to release the pixel, with the supporting legs underneath it. | 2013-01-31 |
20130026593 | THIN FILM PHOTOVOLTAIC DEVICE WITH ENHANCED LIGHT TRAPPING SCHEME - A thin film photovoltaic device comprising a relief textured transparent cover plate, a layer of transparent conductive oxide having a layer thickness of less than 700 nm, a light absorbing active layer and a reflective back electrode, where the layer of transparent conductive oxide is a non-textured layer. | 2013-01-31 |
20130026594 | IMAGE SENSOR WITH CONTROLLABLE VERTICALLY INTEGRATED PHOTODETECTORS - An image sensor includes front-side and backside photodetectors of a first conductivity type disposed in a substrate layer of the first conductivity type. A front-side pinning layer of a second conductivity type is connected to a first contact. The first contact receives a predetermined potential. A backside pinning layer of the second conductivity type is connected to a second contact. The second contact receives an adjustable and programmable potential. | 2013-01-31 |
20130026595 | SEMICONDUCTOR LIGHT-RECEIVING DEVICE - A semiconductor light-receiving device includes a semiconductor light-receiving element that has a first electrode and a second electrode, a first wiring coupled to the first electrode, and a second wiring coupled to the second electrode, a width of the second wiring being smaller than a width of the first wiring. | 2013-01-31 |
20130026596 | FOCAL PLANE ARRAY AND METHOD FOR MANUFACTURING THE SAME - A method of forming a focal plane array by: preparing a first wafer having sensing material provided on a surface, which is covered by a sacrificial layer; preparing a second wafer including read-out integrated circuit and a contact pad, which is covered by another sacrificial layer into which are formed support legs in contact with the contact pad, the support legs being covered with a further sacrificial layer; bonding the sacrificial layers of the first and second wafers together such that the sensing material is transferred from the first wafer to the second wafer when a sacrificial bulk layer of the first wafer is removed; defining a pixel in the sensing material and forming a conductive via through the pixel for providing a connection between an uppermost surface of the pixel and the supporting legs; and removing the sacrificial layers to release the pixel, with the supporting legs underneath it. | 2013-01-31 |
20130026597 | METHOD OF GENERATING ELECTRICAL ENERGY IN AN INTEGRATED CIRCUIT DURING THE OPERATION OF THE LATTER, CORRESPONDING INTEGRATED CIRCUIT AND METHOD OF FABRICATION - An integrated circuit may include a region containing a thermoelectric material and be configured to be subjected to a temperature gradient resulting from a flow of an electric current in a part of the integrated circuit during its operation, and an electrically conducting output coupled to the region for delivering the electrical energy produced by thermoelectric material. | 2013-01-31 |
20130026598 | SCHOTTKY BARRIER DIODE - A Schottky barrier diode includes a first metal layer, a second metal layer separated form the first metal layer, and a semiconductor layer. The semiconductor layer is in Schottky contact with the first metal layer and in ohmic contact with the second metal layer. The semiconductor layer includes an insulated polymer material and a number of carbon nanotubes dispersed in the insulated polymer material. | 2013-01-31 |
20130026599 | SEMICONDUCTOR DEVICE - A semiconductor device includes an isolation portion penetrating a semiconductor substrate from a first surface to a second surface positioned opposite the first surface. The isolation portion includes a first insulating film and a second insulating film. The first insulating film has a slit portion at a side of the first surface and the slit portion is buried with the second insulating film. The semiconductor device further includes an electrode penetrating the semiconductor substrate that is surrounded by the isolation portion. | 2013-01-31 |
20130026600 | FORMING AIR GAPS IN MEMORY ARRAYS AND MEMORY ARRAYS WITH AIR GAPS THUS FORMED - Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region, having a first dielectric, through a charge-storage structure that is over a semiconductor, the isolation region extending into the semiconductor; forming a second dielectric over the isolation region and charge-storage structure; and forming an air gap in the isolation region so that the air gap passes through the charge-storage structure and so that a thickness of the first dielectric is between the air gap and the second dielectric. | 2013-01-31 |
20130026601 | Semiconductor Device and Method for Manufacturing a Semiconductor - A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface. | 2013-01-31 |
20130026602 | SEMICONDUCTOR DEVICE - A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device | 2013-01-31 |
20130026603 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming an insulating film over a semiconductor substrate, forming a capacitor including a lower electrode, a capacitor dielectric film including a ferroelectric material, and an upper electrode over the insulating film, forming a first protective insulating film over a side surface and upper surface of the capacitor by a sputtering method, and forming a second protective insulating film over the first protective insulating film by an atomic layer deposition method. | 2013-01-31 |
20130026604 | LATERAL AVALANCHE PHOTODIODE STRUCTURE - A lateral avalanche photodiode structure including a substrate, a PN diode and a metal layer is provided. The substrate has at least one first electrode area, at least one light receiving area, and at least one second electrode area which are arranged horizontally. The first electrode area is also an avalanche area, and the light receiving area is between the first electrode area and the second electrode area. The PN diode is disposed in the substrate in the first electrode area. The metal layer is disposed on the substrate and covers the first electrode area and the second electrode area, but does not cover the light receiving area. | 2013-01-31 |
20130026605 | WLCSP for Small, High Volume Die - The disclosed WLCSP solution overcomes the limitations of fan-out WLCSP solutions, and other conventional solutions for WLCSP for small, high volume die, by increasing the width of scribe regions between die on a semiconductor substrate to accommodate bonding structures (e.g., solder balls) that partially extend beyond peripheral edges of the die. The scribe regions can be widened in x and y directions on the wafer. The widened scribe regions can be incorporated into the design of the mask set. | 2013-01-31 |
20130026606 | TSV PILLAR AS AN INTERCONNECTING STRUCTURE - The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch. | 2013-01-31 |
20130026607 | INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE AND METHODS FOR MANUFACTURING THE SAME - A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material. | 2013-01-31 |
20130026608 | PROCESS FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE COMPRISING A FUNCTIONALIZED LAYER ON A SUPPORT SUBSTRATE - The invention relates to a process for manufacturing a semiconductor structure comprising a functionalized layer on a support substrate, comprising the following steps: (a) implanting ionic species in a source substrate comprising the said functionalized layer and a sacrificial buffer layer located under the functionalized layer relative to the direction of implantation, to a depth delimiting the thickness of an upper part of the source substrate comprising the functionalized layer and at least part of the buffer layer; (b) bonding the source substrate to the support substrate; (c) fracturing the source substrate and transferring the upper part of the source substrate to the support substrate; (d) removing the buffer layer by selective etching with respect to the functionalized layer. | 2013-01-31 |
20130026609 | PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE WITH STRESS RELIEF STRUCTURE - An apparatus configured to be coupled onto a substrate, wherein the apparatus comprises a semiconductor substrate and the semiconductor substrate includes a plurality of trenches defined within a side of the semiconductor substrate. The apparatus further comprises an interconnect layer over portions of the side of the semiconductor substrate, wherein the portions of the side of the semiconductor substrate include the plurality of trenches defined within the side of the semiconductor substrate. Each trench is configured to respectively receive a solder ball to provide an interface between i) the interconnect layer and ii) the substrate to which the apparatus is to be coupled. | 2013-01-31 |
20130026610 | LITHOGRAPHY METHOD AND DEVICE - Lithography methods and devices are shown that include a semiconductor structure such as a mask. Methods and devices are shown that include a pattern of mask features and a composite feature. Selected mask features include doubled mask features. Methods and devices shown may provide varied feature sizes (including sub-resolution) with a small number of processing steps. | 2013-01-31 |
20130026611 | SEMICONDUCTOR SUBSTRATE INCLUDING DOPED ZONES FORMING P-N JUNCTIONS - A semiconductor substrate ( | 2013-01-31 |
20130026612 | METHOD OF SHIELDING THROUGH SILICON VIAS IN A PASSIVE INTERPOSER - A passive interposer apparatus with a shielded through silicon via (TSV) configuration is disclosed. The apparatus includes a p-doped substrate, wherein at least an upper portion of the p-doped substrate is heavily p-doped. An interlayer dielectric layer (ILD) is disposed over the upper portion of the p-doped substrate. A plurality of through silicon vias (TSVs) are formed through the ILD and the p-doped substrate. A plurality of shielding lines disposed between the TSVs electrically couple respective second metal contact pads to the upper portion of the p-doped substrate. | 2013-01-31 |
20130026613 | SEMICONDUCTOR DEVICE - A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region. | 2013-01-31 |
20130026614 | STRUCTURE AND METHOD FOR BUMP TO LANDING TRACE RATIO - The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T. | 2013-01-31 |
20130026615 | DOUBLE-SIDE EXPOSED SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device. | 2013-01-31 |