05th week of 2009 patent applcation highlights part 15 |
Patent application number | Title | Published |
20090026512 | CMOS image sensor and method for manufacturing the same - A CMOS image sensor and a method for manufacturing the same improve light-receiving efficiency and maintain a margin in the design of a metal line. The CMOS image sensor includes a transparent substrate including an active area having a photodiode region and a transistor region and a field area for isolation of the active area, a p-type semiconductor layer on the transparent substrate, a photodiode in the p-type semiconductor layer corresponding to the photodiode region, and a plurality of transistors in the p-type semiconductor layer corresponding to the transistor region. | 2009-01-29 |
20090026513 | Method for forming ferroelectric thin films, the use of the method and a memory with a ferroelectric oligomer memory material - In a method for forming ferroelectric thin films of vinylidene fluoride oligomer or vinylidene fluoride co-oligomer, oligomer material is evaporated in vacuum chamber and deposited as a thin film on a substrate which is cooled to a temperature in a range determined by process parameters and physical properties of the deposited VDF oligomer or co-oligomer thin film. In an application of the method of the invention for fabricating ferroelectric memory cells or ferroelectric memory devices, a ferroelectric memory material is provided in the form of a thin film of VDF oligomer or VDF co-oligomer located between electrode structures. A ferroelectric memory cell or ferroelectric memory device fabricated in this manner has the memory material in the form of a thin film of VDF oligomer or VDF co-oligomer provided on at least one of first and second electrode structures, such that the thin film is provided on at least one of the electrode structures or between first and second electrode structures. | 2009-01-29 |
20090026514 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A ferroelectric memory is constituted to comprise a capacitor being formed above a semiconductor substrate ( | 2009-01-29 |
20090026515 | Semiconductor memory device and method of forming the same - Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad. | 2009-01-29 |
20090026516 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor memory device. A pair of neighboring trench capacitors is formed in a substrate. An insulating layer having a pair of connecting structures therein is formed on the substrate, in which the pair of connecting structures is electrically connected to the pair of neighboring trench capacitors. An active layer is formed on the insulating layer between the pair of connecting structures so as to cover the pair of connecting structures. A pair of gate structures is formed on the active layer to electrically connect to the pair of trench capacitors. A semiconductor memory device is also disclosed. | 2009-01-29 |
20090026517 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes: a transistor including source and drain diffusion-layers, a gate insulating film and a gate electrode; first and second plugs formed in a first interlayer-insulating film and connected to the source and drain diffusion-layers, respectively; a third plug extending through a second interlayer-insulating film and connected to the first plug; a first interconnection-wire formed on the second interlayer-insulating film and connected to the third plug; a second interconnection-wire formed on a third interlayer-insulating film and intersecting the first interconnection-wire; a fourth interlayer-insulating film; a hole extending through the fourth, third and second interlayer-insulating films, the hole being formed such that a side surface of the second interconnection-wire is exposed; and a fourth plug filling the hole via an intervening dielectric film and connected to the second plug, wherein a capacitor is formed using the fourth plug, the second interconnection-wire and the dielectric film sandwiched therebetween. | 2009-01-29 |
20090026518 | DRAM CYLINDRICAL CAPACITOR - A structure of a DRAM cylindrical capacitor includes a substrate, a dielectric layer, an amorphous silicon spacer, a polysilicon plug, a HSG layer, a conductive layer and a capacitor dielectric layer. The dielectric layer is disposed on the substrate and includes an opening. The amorphous silicon spacer is disposed on the sidewall of the opening, wherein the polysilicon plug is exposed by the opening. The polysilicon plug includes a notch, and the internal surface of the notch is at the same plane as the internal surface of the amorphous silicon spacer. The HSG layer is disposed on the surface of the amorphous silicon spacer. Furthermore, the conductive layer is disposed on the HSG layer and the capacitor dielectric layer is disposed between the HSG layer and the conductive layer. | 2009-01-29 |
20090026519 | Capacitorless dram and methods of manufacturing and operating the same - A capacitorless DRAM and methods of manufacturing and operating the same are provided. The capacitorless DRAM includes a source, a drain and a channel layer, formed on a substrate. A charge reserving layer is formed on the channel layer. The capacitorless DRAM includes a gate that contacts the channel layer and the charge reserving layer. | 2009-01-29 |
20090026520 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF FOR REDUCING THE AREA OF THE MEMORY CELL REGION - A structure is adopted for a layout of an SRAM cell which provides a local wiring | 2009-01-29 |
20090026521 | SELF-BIASING TRANSISTOR STRUCTURE AND AN SRAM CELL HAVING LESS THAN SIX TRANSISTORS - By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements. | 2009-01-29 |
20090026522 | SEMICONDUCTOR DEVICE COMPRISING TRANSISTOR STRUCTURES AND METHODS FOR FORMING SAME - A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described. | 2009-01-29 |
20090026523 | PARTIALLY GATED FINFET - A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit. | 2009-01-29 |
20090026524 | Stacked Circuits - An integrated circuit includes a first integrated circuit layer including at least one first transistor channel region and having a wafer bonding interface. The integrated circuit may further include at least one second integrated circuit layer including at least one second transistor channel region and being arranged at the wafer bonding interface of the first integrated circuit layer. | 2009-01-29 |
20090026525 | MEMORY AND METHOD FOR FABRICATING THE SAME - A method for fabricating a memory is provided. A tunneling dielectric layer, a first conductive layer, and a mask layer are formed on a substrate. The mask layer, the first conductive layer, the tunneling dielectric layer, and the substrate are patterned to form trenches in the substrate. A passivation layer and isolation structures are formed in sequence to fill the trenches, and the etching rate of the isolation structures is greater than that of the passivation layer. After the mask layer is removed, a second conductive layer is formed on the first conductive layer. Portions of the isolation structures are removed to expose the sidewalls of the first and the second conductive layers. Further, a third conductive layer is formed on the exposed sidewalls of the first and the second conductive layers. An inter-gate dielectric layer and a control gate are formed on the substrate. | 2009-01-29 |
20090026526 | INTEGRATED CIRCUIT DEVICES INCLUDING A MULTI-LAYER STRUCTURE WITH A CONTACT EXTENDING THERETHROUGH AND METHODS OF FORMING THE SAME - Integrated circuit devices have a first substrate layer and a first transistor on the first substrate layer. A first interlayer insulating film covers the first transistor. A second substrate layer is on the first interlayer insulating film and a second transistor is on the second substrate layer. A second interlayer insulating film covers the second transistor. A contact extends through the second interlayer insulating film, the second substrate layer and the first interlayer insulating film. The contact includes a lower contact and an upper contact that contacts an upper surface of the lower contact to define an interface therebetween. The interface is located at a height no greater than a height of a top surface of the second substrate and greater than a height of a bottom surface of the second substrate layer. | 2009-01-29 |
20090026527 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device including: sequentially forming a first insulating film, a first electrode film, a second insulating film, and a second electrode film on a substrate; forming a groove that separates the second electrode film, the second insulating film and the first electrode film; forming an insulating film inside the groove so that an upper surface thereof is positioned between upper surfaces of the second electrode film and the second insulating film; forming an overhung portion on the second electrode film so as to overhang on the insulating film by performing a selective growth process; and forming a low resistance layer at the overhung portion and the second electrode film by performing an alloying process. | 2009-01-29 |
20090026528 | Flash Memory Cell and Method of Manufacturing the Same and Programming/Erasing Reading Method of Flash Memory Cell - Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology. Further, it can reduce the manufacture cost and implement a high-integrated flash memory cell that is advantageous than a conventional flash memory cell in view of charge storage/retention as well as programming time. | 2009-01-29 |
20090026529 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a silicon substrate having a main surface, the main surface including a region in which a groove structure or a concavity and convexity structure is formed, and a nonvolatile memory cell provided on the main surface of the silicon substrate, the nonvolatile memory cell including a first insulating film as a tunnel insulating film provided on the region, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, a control gate provided on the second insulating film. | 2009-01-29 |
20090026530 | METHODS OF FABRICATING DUAL FIN STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES WITH DUAL FINS - Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 2009-01-29 |
20090026531 | METHOD FOR INSULATING A SEMICONDUCTING MATERIAL IN A TRENCH FROM A SUBSTRATE - A method for insulating a semiconducting material in a trench from a substrate, wherein the trench is formed in the substrate and comprising an upper portion and a lower portion, the lower portion being lined with a first insulating layer and filled, at least partially, with a semiconducting material, comprises an isotropic etching of the substrate and the semiconducting material, and forming a second insulating layer in the trench, wherein the second insulating layer covers, at least partially, the substrate and the semiconducting material. | 2009-01-29 |
20090026532 | SHORT CIRCUIT LIMITING IN POWER SEMICONDUCTOR DEVICES - A power semiconductor device includes a semiconductor body. The semiconductor body includes a body region of a first conductivity type for forming therein a conductive channel of a second conductivity type; a gate electrode arranged next to the body region; and a floating electrode arranged between the gate electrode and the body region. | 2009-01-29 |
20090026533 | Trench MOSFET with multiple P-bodies for ruggedness and on-resistance improvements - A vertical semiconductor power device includes a plurality of semiconductor power cells having a drain disposed at a bottom of a semiconductor substrate. Each of the cells includes a gate surrounded by a body region encompassing a source region. The body region further includes multiple body-dopant implanted regions having a non-Gaussian distribution dopant profile for reducing a width of a transition region transitioning between the multiple body-dopant implanted regions and an epitaxial region underneath having a different conductivity type from the multiple body-dopant implanted regions. | 2009-01-29 |
20090026534 | Trench MOSFET and method of making the same - A trench MOSFET structure formed in a semiconductor substrate and method of forming the same are disclosed. The trench MOSFET includes a capacitor having a capacitor dielectric layer formed of an oxide-un-doped poly-oxide in the trench bottom. Firstly, the trenches are formed in a p-well of the epi-layer of an n-type impurity doped substrate through a lithographic and an etch step. Next, a gate oxide layer and an intrinsic polysilicon layer are successively formed, and a HTO layer is deposited on the trench bottom to form the oxide-un-doped poly-oxide dielectric layer. Subsequently a doped polysilicon layer is filled into the trench as a trench gate. Then, processes of source contact regions and gate contacts are followed. Finally a drain contact is formed on a rear surface of the substrate. | 2009-01-29 |
20090026535 | SEMICONDUCTOR DEVICE - The technology of preventing lowering of the element breakdown voltage of a trench gate control type semiconductor element is offered. n | 2009-01-29 |
20090026536 | TRENCH GATE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A trench gate semiconductor device and a method for fabricating the same, which are capable of securing a sufficient margin for a photo process while achieving an enhancement in gate-source leakage characteristics, are disclosed. Embodiments relate to a method for fabricating a trench gate semiconductor device including forming a trench in an upper surface of an epitaxial layer formed over a semiconductor substrate. N type impurity ions may be implanted into a bottom surface of the trench, to form a diffusion layer. To form a well, P-type impurity ions may be implanted into a region beneath the diffusion layer. To form an oxide film buffer, the trench may be filled with an oxide. To form a gate trench, the resulting structure obtained after the filling of the oxide may be etched from the oxide film buffer to the epitaxial layer, in a region where a gate will be formed. NPN junctions may be formed beneath the oxide film buffer at opposite sides of the gate poly. Poly plugs may be formed to electrically connect P type portions of the NPN junctions to upper metal electrodes by filling the source trenches with polysilicon. The upper metal electrodes may be formed over the gate poly and over the poly plugs. | 2009-01-29 |
20090026537 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device formed with a trench portion for providing a concave portion in a gate width direction and with a gate electrode provided within and on a top surface of the trench portion via a gate insulating film. At least a part of a surface of each of the source region and the drain region is made lower than other parts of the surface by removing a thick oxide film formed in the vicinity of the gate electrode. Making lower the part of the surface of each of the source region and the drain region allows current flowing through a top surface of the concave portion of the gate electrode at high concentration to flow uniformly through the entire trench portion, which increase an effective gate width of the concave portion formed so as to have a varying depth in a gate width direction. | 2009-01-29 |
20090026538 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device formed with a trench portion for providing a concave portion having a continually varying depth in a gate width direction and with a gate electrode provided within the trench portion and on a top surface thereof via a gate insulating film. Before the formation of the gate electrode, an impurity is added to at least a part of the source region and the drain region by ion implantation from an inner wall of the trench portion, and then heat treatment is performed for diffusion and activation to form a diffusion region from the surface of the trench portion down to a bottom portion thereof. Current flowing through a top surface of the concave portion of the gate electrode at high concentration can flow uniformly through the entire trench portion. | 2009-01-29 |
20090026539 | Method and Layout of Semiconductor Device with Reduced Parasitics - An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection. | 2009-01-29 |
20090026540 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device includes: a first semiconductor region formed on a substrate and having an upper surface and a side surface; a first impurity region of a first conductivity type formed in an upper portion of the first semiconductor region; a second impurity region of a first conductivity type formed in a side portion of the first semiconductor region; and a gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first semiconductor region. A radius of curvature r′ of an upper corner of a portion of the first semiconductor region located outside the gate insulating film is greater than a radius of curvature r of an upper corner of a portion of the first semiconductor region located under the gate insulating film and is less than or equal to 2 | 2009-01-29 |
20090026541 | VERTICAL FLOATING BODY CELL OF A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a tube-type channel formed over a semiconductor substrate. The tube-type channel is connected to first and second conductive lines. A bias electrode is formed in the tube-type channel. The bias electrode is connected to the semiconductor substrate. An insulating film is disposed between the tube-type channel and the bias electrode. A surrounding gate electrode is formed over the tube-type channel. | 2009-01-29 |
20090026542 | INTEGRATED CIRCUIT INCLUDING A SEMICONDUCTOR ASSEMBLY IN THIN-SOI TECHNOLOGY - An integrated circuit including a semiconductor assembly in thin-film SOI technology is disclosed. One embodiment provides a semiconductor assembly in thin-film SOI technology including a first semiconductor substrate structure of a second conductivity type inverse to a first conductivity type in a semiconductor substrate below a first semiconductor layer, a second semiconductor substrate structure of a second conductivity type in a semiconductor substrate below a second semiconductor layer structure, and a third semiconductor substrate structure of the first conductivity type below the first semiconductor layer structure in the semiconductor substrate and otherwise surrounded by the first semiconductor substrate structure. | 2009-01-29 |
20090026543 | FINFET WITH SUBLITHOGRAPHIC FIN WIDTH - At least one recessed region having two parallel edges is formed in an insulator layer over a semiconductor layer such that the lengthwise direction of the recessed region coincides with optimal carrier mobility surfaces of the semiconductor material in the semiconductor layer for finFETs to be formed. Self-assembling block copolymers are applied within the at least one recessed region and annealed to form a set of parallel polymer block lines having a sublithographic width and containing a first polymeric block component. The pattern of sublithographic width lines is transferred into the semiconductor layer employing the set of parallel polymer block lines as an etch mask. Sublithographic width semiconductor fins thus formed may have sidewalls for optimal carrier mobility for p-type finFETs and n-type finFETs. | 2009-01-29 |
20090026544 | SEMICONDUCTOR DEVICE - A non-insulated DC-DC converter has a power MOS•FET for a highside switch and a power MOS•FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS•FET for the highside switch and the power MOS•FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS•FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other. | 2009-01-29 |
20090026545 | INTEGRATED CIRCUIT EMPLOYING VARIABLE THICKNESS FILM - An integrated circuit that includes: providing a substrate including a support structure, a dielectric layer, and a variable thickness film processed to include the dielectric layer within a recess of the variable thickness film; forming a gate over the variable thickness film; and forming a channel and a source/drain within the variable thickness film. | 2009-01-29 |
20090026546 | SEMICONDUCTOR DEVICE - To provide a technique capable of achieving high integration of semiconductor devices. A standard cell is provided in an n-type well, and includes a p | 2009-01-29 |
20090026547 | Semiconductor device and method of manufacturing the same - A semiconductor device includes an active region extending along a first direction on a semiconductor substrate, the active region having a first sidewall and a second sidewall spaced apart and facing each other, a distance between the first and second sidewalls extending along a second direction, and a gate on the active region, the gate having a pair of body portions extending along the second direction and being spaced apart from each other, the second direction being perpendicular to the first direction, a head portion extending along the first direction to connect the body portions, the head portion overlapping a portion of the first sidewall, and a plurality of tab portions protruding from sidewalls of the body portions, the tab portions extending along the first direction and overlapping a portion of the second sidewall. | 2009-01-29 |
20090026548 | Systems And Methods For Fabricating Nanometric-Scale Semiconductor Devices With Dual-Stress Layers Using Double-Stress Oxide/Nitride Stacks - Systems and methods for fabricating semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks. A method comprises providing NMOS and PMOS regions, selectively forming a dual-stack tensile stress layer over the NMOS region by depositing a tensile silicon nitride layer over the NMOS and PMOS regions, depositing a tensile silicon oxide layer over the tensile silicon nitride layer, removing a portion of the tensile silicon oxide layer from the PMOS region, and removing a portion of the tensile silicon nitride layer from the NMOS region and selectively forming a dual stack compressive stress layer over the PMOS region by depositing a compressive silicon nitride layer over the NMOS and PMOS regions, depositing a compressive silicon oxide layer over the compressive silicon nitride layer, removing a portion of the compressive silicon oxide layer from the NMOS region, and removing a portion of the compressive silicon nitride layer from the NMOS region. | 2009-01-29 |
20090026549 | METHOD TO REMOVE SPACER AFTER SALICIDATION TO ENHANCE CONTACT ETCH STOP LINER STRESS ON MOS - An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors. | 2009-01-29 |
20090026550 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a silicon substrate; and a field effect transistor including a gate insulating film over the silicon substrate, a gate electrode on the gate insulating film, and source and drain regions. The gate electrode includes, in part in contact with the gate insulating film, a crystallized Ni silicide region containing an impurity element of a conductivity type opposite to a conductivity type of a channel region in the field effect transistor. | 2009-01-29 |
20090026551 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: an isolation region formed in a semiconductor substrate; active regions surrounded by the isolation region and including p-type and n-type regions, respectively; an NMOS transistor formed in the active region including the p-type region and including an n-type gate electrode; a PMOS transistor formed in the active region including the n-type region and including a p-type gate electrode; and a p-type resistor formed on the isolation region. The p-type resistor has an internal stress greater than that of the p-type gate electrode. | 2009-01-29 |
20090026552 | METHOD FOR FORMING A TRANSISTOR HAVING GATE DIELECTRIC PROTECTION AND STRUCTURE - A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure. | 2009-01-29 |
20090026553 | Tunnel Field-Effect Transistor with Narrow Band-Gap Channel and Strong Gate Coupling - A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions. | 2009-01-29 |
20090026554 | SOURCE/DRAIN STRESSORS FORMED USING IN-SITU EPITAXIAL GROWTH - A method for forming a semiconductor device is provided. The method includes forming a semiconductor layer. The method further includes forming a gate structure overlying the semiconductor layer. The method further includes forming a high-k sidewall spacer adjacent to the gate structure. The method further includes forming a recess in the semiconductor layer, the recess aligned to the high-k sidewall spacer. The method further includes forming an in-situ doped epitaxial material in the recess, the epitaxial material having a natural lattice constant different from a lattice constant of the semiconductor layer to create stress in a channel region of the semiconductor device. | 2009-01-29 |
20090026555 | Transistor with Dopant-Bearing Metal in Source and Drain - A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are recessed. The recesses are filled with a dopant-bearing metal, and a low-temperature anneal process is used to form doped regions within the workpiece adjacent the dopant-bearing metal regions. A transistor having a small effective oxide thickness and a well-controlled junction depth is formed. | 2009-01-29 |
20090026556 | Nitride semiconductor device and method for producing nitride semiconductor device - A method for producing a nitride semiconductor device according to the present invention includes the steps of: forming an insulating film containing oxygen on the surface of a group III nitride semiconductor; and placing the group III nitride semiconductor under a nitrogen atmosphere in advance of the step of forming the insulating film. A nitride semiconductor device according to the present invention includes a group III nitride semiconductor; and an insulating film containing oxygen formed on the surface of the group III nitride semiconductor, wherein the nitrogen concentration in a region provided with the insulating film is higher than the nitrogen concentration in a region not provided with the insulating film on the surface of the group III nitride semiconductor. | 2009-01-29 |
20090026557 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The method of manufacturing a semiconductor device comprises; forming an HfSiO film | 2009-01-29 |
20090026558 | SEMICONDUCTOR DEVICE HAVING A SENSOR CHIP, AND METHOD FOR PRODUCING THE SAME - A semiconductor sensor device and method is disclosed. In one embodiment, the semiconductor device includes a cavity housing and a sensor chip. In one embodiment, the cavity housing has an opening to the surroundings. The sensor region of the sensor chip faces said opening. The sensor chip is mechanically decoupled from the cavity housing. In one embodiment, the sensor chip is embedded into a rubber-elastic composition on all sides in the cavity of the cavity housing. | 2009-01-29 |
20090026559 | BORON DOPED SHELL FOR MEMS DEVICE - A wafer for use in a MEMS device having two doped layers surrounding an undoped layer of silicon is described. By providing two doped layers around an undoped core, the stress in the lattice structure of the silicon is reduced as compared to a solidly doped layer. Thus, problems associated with warping and bowing are reduced. The wafer may have a pattered oxide layer to pattern the deep reactive ion etch. A first deep reactive ion etch creates trenches in the layers. The walls of the trenches are doped with boron atoms. A second deep reactive ion etch removes the bottom walls of the trenches. The wafer is separated from the silicon substrate and bonded to at least one glass wafer. | 2009-01-29 |
20090026560 | SENSOR PACKAGE - A sensor package is disclosed. One embodiment provides a sensor device having a carrier, a semiconductor sensor mounted on the carrier and an active surface. Contact elements are electrically connecting the carrier with the semiconductor sensor. A protective layer made of an inorganic material covers at least the active surface and the contact elements. | 2009-01-29 |
20090026561 | Micromechanical component and corresponding method for its manufacture - A micromechanical component having a conductive substrate, an elastically deflectable diaphragm including at least one conductive layer, which is provided over a front side of the substrate, the conductive layer being electrically insulated from the substrate, a hollow space, which is provided between the substrate and the diaphragm and is filled with a medium, and a plurality of perforation openings, which run under the diaphragm through the substrate, the perforation openings providing access to the hollow space from a back surface of the substrate, so that a volume of the medium located in the hollow space may change when the diaphragm is deflected. Also described is a corresponding manufacturing method. | 2009-01-29 |
20090026562 | Package structure for optoelectronic device - A package structure for an optoelectronic device. The package structure comprises a device chip interposed between a lower transparent substrate and an upper transparent substrate. The device chip comprises a semiconductor substrate comprising a device region surrounded by a pad region, in which the pad region comprises a plurality of notches along the edges of the semiconductor substrate. A dielectric layer is between the semiconductor substrate and the upper transparent substrate, comprising a plurality of pads formed therein and substantially aligned with the plurality of notches, respectively. A plurality of metal lines is disposed under a bottom surface of the lower transparent substrate. A plurality of solder balls disposed under the plurality of metal lines, respectively. | 2009-01-29 |
20090026563 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes a first wiring layer, a second wiring layer, a substrate contact, and a first contact. The arrangement of the substrate contact with respect to a light-receiving section forming a peripheral pixel is shifted, or not shifted, from the arrangement of the substrate contact with respect to a light-receiving section forming a central pixel, by a shift amount r from the peripheral portion toward the central portion. The arrangement of the first contact with respect to the light-receiving section of the peripheral pixel is shifted from the arrangement of the first contact with respect to the light-receiving section of the central pixel, by a shift amount s | 2009-01-29 |
20090026564 | SEMICONDUCTOR COMPONENT, LIGHTING UNIT FOR MATRIX SCREENS, AND METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT - A semiconductor component, lighting unit for matrix screens, and method for manufacturing a semiconductor component is provided. The semiconductor component includes an integrated circuit, which has at least one light detector provided with a silicon-containing coating, particularly a coating of silicon nitride or silicon dioxide. A layer thickness of the silicon-containing coating, particularly the coating of silicon nitride or silicon dioxide, is selected in such a way that a predefinable, narrow-band, wavelength-selective transmission of light waves, particularly of light waves in a wavelength range from 300 nm to 850 nm, can be achieved. | 2009-01-29 |
20090026565 | Optical Module - The present invention includes: photoelectric conversion element | 2009-01-29 |
20090026566 | Semiconductor device having backside redistribution layers and method for fabricating the same - Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment includes providing a substrate comprising a via formed therein. The substrate has a front side and a backside. The embodiment may further include forming a trench on the backside of the substrate, disposing an insulating material in the trench, and forming a trace over the insulating material in the trench. | 2009-01-29 |
20090026567 | Image sensor package structure and method for fabricating the same - A method for fabricating an image sensor package is disclosed, comprising: providing a wafer having a plurality of image sensor integrated circuits, each of which has a photosensitive active region and at least one first bonding pad; joining a transparent protecting material to the wafer wherein the photosensitive active region of the image sensor integrated circuit is covered by the transparent protecting material; forming a plurality of through holes in the transparent protecting material, the through holes being correspondingly to the first bonding pad of the wafer to expose the first bonding pad; and dicing the wafer to form a plurality of image sensor integrated circuit components. The method for fabricating an image sensor package of the present invention decreases the defects of the photosensitive active region and reduces the size of the package structure. | 2009-01-29 |
20090026568 | OPTICAL COLOR SENSOR SYSTEM - An optical color sensor system is provided including providing a substrate having an optical sensor therein and forming a passivation layer over the substrate. The passivation layer is planarized and color filters are formed over the passivation layer. A planar transparent layer is formed over the color filters and microlenses are formed on the planar transparent layer over the color filters. | 2009-01-29 |
20090026569 | Ultra high-resolution radiation detector (UHRD) and method for fabrication thereof - An ultra high-resolution radiation detector and method for fabrication thereof, has a detector chip, comprising the so-called drift rings and an amplifier integrated with the diode component, centrally located n-type anode on one surface, the depletion region. The detector chip has a circular field of view, the depletion region which also has a circular field of view by ion implanting symmetrical p-n junctions on the surface of the radiation entrance side of the detector chip, said centrally n-type anode located on the opposite surface of the depletion region, and its position is in the region which outer of the depletion region, said centrally n-type anode was surrounded by a plurality of p-type drift electrode rings, which have an gibbous circularity topology; wherein the focus of said p-type drift electrode rings is the position of the anode, said FET (Field-Effect Transistor) was integrated in the position of the detector's anode and directly coupled to the detector's anode. The p-type drift electrode rings is a plurality of drift rings which have gibbous circularity topology, wherein the gibbous circularity topology is encircled by a majority of a large circularity and a small circularity, wherein the maximum of the depletion region is the opposite surface of the region encircled by the outermost p-type drift electrode ring. | 2009-01-29 |
20090026570 | Methods and structures for discharging plasma formed during the fabrication of semiconuctor device - Methods and structures for discharging plasma formed during the fabrication of semiconductor device are disclosed. The semiconductor device includes a wordline, a common ground line and a fuse structure for electrically coupling the wordline and the common ground line until a break signal is applied via the fuse structure. | 2009-01-29 |
20090026571 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes first pixels and second pixels. Each of the first pixels and the second pixels includes a p-type diffusion layer formed in a semiconductor substrate and an n-type diffusion layer formed on the p-type diffusion layer. A first p-type implantation layer is formed on a surface side of the semiconductor substrate on the n-type diffusion layer of the first pixels. A second p-type implantation layer having a lower impurity concentration than the first p-type implantation layer or no p-type implantation layer is formed on a surface side of the semiconductor substrate on the n-type diffusion layer of the second pixels. | 2009-01-29 |
20090026572 | Method of Manufacturing a Semiconductor Device, Method of Manufacturing a SOI Device, Semiconductor Device, and SOI Device - According to one embodiment of the present invention, a SOI device includes a first composite structure including a substrate layer, a substrate isolation layer being disposed on or above the substrate layer, a buried layer being disposed on or above the substrate isolation layer, and a semiconductor layer being disposed on or above the buried layer; a trench structure being formed within the first composite structure; and a second composite structure provided on the side walls of the trench structure, wherein the second composite structure includes a first isolation layer covering the part of the side walls formed by the semiconductor layer and formed by an upper part of the buried layer; and a contact layer covering the isolation layer and the part of the side walls formed by a lower part of the buried layer. | 2009-01-29 |
20090026573 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nonvolatile semiconductor memory device and a method for manufacturing the same that may include forming an isolation pattern in a substrate, and then etching a portion of the isolation pattern to expose a portion of an active region of the substrate, and then forming high-density second-type ion implantation regions spaced apart at both edges of the active region by performing a tilted ion implantation process, and then forming a high-density first-type ion implantation region as a bit line in the active region, and then forming an insulating layer on the substrate including the high-density first-type ion implantation region, the high-density second-type ion implantation regions and the isolation pattern, and then forming a metal interconnection as a word line on the insulating layer pattern and extending in a direction perpendicular to bit line. | 2009-01-29 |
20090026574 | ELECTRICAL FUSE HAVING SUBLITHOGRAPHIC CAVITIES THEREUPON - An electrical fuse and a first dielectric layer thereupon are formed on a semiconductor substrate. Self-assembling block copolymers containing two or more different polymeric block components are applied into a recessed region surrounded by a dielectric template layer. The self-assembling block copolymers are then annealed to form a pattern of multiple circles having a sublithographic diameter. The pattern of multiple circles is transferred into the first dielectric layer by a reactive ion etch, wherein the portion of the first dielectric layer above the fuselink has a honeycomb pattern comprising multiple circular cylindrical holes. A second dielectric layer is formed over the circular cylindrical holes by a non-conformal chemical vapor deposition and sublithographic cavities are formed on the fuselink. The sublithographic cavities provide enhanced thermal insulation relative to dielectric materials to the fuselink so that the electrical fuse may be programmed with less programming current. | 2009-01-29 |
20090026575 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device which substantially prevents repair failure and a method of manufacturing the same. The semiconductor device includes a plurality of first fuses formed apart from each other on a semiconductor substrate, and on which a protective layer is formed; a first insulating layer filled in between the first fuses and configured to expose the protective layer; a plurality of second fuses formed between the first fuses and on the first insulating layer; and a second insulating layer formed on the first insulating layer, wherein the second insulating layer includes a fuse window configured to fully expose the second fuses and the protective layer formed on the first fuses. | 2009-01-29 |
20090026576 | ANTI-FUSE - An anti-fuse is provided. The anti-fuse includes a substrate, a gate disposed over the substrate, a gate dielectric layer sandwiched between the substrate and the gate, and two source/drain regions in the substrate at respective sides of the gate. The gate and the substrate have the same conductive type, but the conductive type of the gate and the substrate is different from that of the two source/drain regions. | 2009-01-29 |
20090026577 | Antifuse element and semiconductor device including same - To provide an antifuse element comprising a gate electrode, a depletion channel region, a gate insulating film between the gate electrode and the channel region, and a diffusion layer region forming a junction with the channel region. An end of the gate electrode coincides substantially with a boundary between the channel region and the diffusion layer region as seen from a planar view, and is formed in a zigzag configuration. The end of the gate electrode is longer than the end with linear configuration and the end of the gate insulating film is likely to be subjected to breakdown. | 2009-01-29 |
20090026578 | Vertical NPN Transistor Fabricated in a CMOS Process With Improved Electrical Characteristics - A vertical NPN bipolar transistor includes a P-type semiconductor structure, an N-well as the collector, a P-Base region in the N-well and an N-type region as the emitter. The transistor further includes P-type region formed in the P-Base region and underneath the field oxide layer where the P-type region has a doping concentration higher than the P-base region. The P-type region functions to inhibit the lateral parasitic bipolar action so that the transistor action is confined to the intrinsic base region vertically underneath the emitter. In one embodiment, the P-type region is a boron field doping region. The boron field doping region can be the same field doping region used to form channel stops for NMOS transistors in a CMOS fabrication process. | 2009-01-29 |
20090026579 | EM RECTIFYING ANTENNA SUITABLE FOR USE IN CONJUNCTION WITH A NATURAL BREAKDOWN DEVICE - A rectenna capable of power conversion from electromagnetic (EM) waves of high frequencies is provided. In one embodiment, a rectenna element generates currents from two sources—based upon the power of the incident EM wave and from an n-type semiconductor, or another electron source attached to a maximum voltage point of an antenna element. The combined current from both sources increases the power output of the antenna, thereby increasing the detection sensitivity of the antenna of a low power signal. Full wave rectification is achieved using a novel diode connected to a gap in the antenna element of a rectenna element. The diode is conductive at forward bias voltage or reverse bias voltage, and rectifies the antenna signal generated by the desired EM wave received by antenna raise from The rectenna element of the present invention may be used as a building block to create large rectenna arrays. | 2009-01-29 |
20090026580 | Semiconductor Device and Manufacturing Method - A semiconductor device and its manufacturing method are disclosed. The semiconductor device includes at least one integrated circuit on a semiconductor substrate having an active side and a back side. The lattice constant of the semiconductor material is increased. The manufacturing method includes stretching the semiconductor lattice in near-surface areas of the back side of the semiconductor substrate. | 2009-01-29 |
20090026581 | FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method includes forming trenches in a semiconductor substrate by etching the semiconductor substrate; and then forming a first ion injection layer in sidewalls of the trenches at an active region of the semiconductor substrate; and then forming a second ion injection layer in a substantially horizontally extending surface of the active region located between the trenches; and then performing a threshold voltage adjusting implant on at least the active region, wherein the first ion injection layer and the second ion injection layer overlap at a portion of the active region to provide the overlapping portion with a higher doping concentration than a non-overlapping portion of the active region; and then forming a gate structure on the active region. Since the ion doping concentration of the surface of an active area between isolation layers is totally uniform, an electric current flows uniformly through the overall surface to prevent leakage current, to improve reliability, and to prolong lifespan of the flash memory device. | 2009-01-29 |
20090026582 | DEPOSITED SEMICONDUCTOR STRUCTURE TO MINIMIZE N-TYPE DOPANT DIFFUSION AND METHOD OF MAKING - In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thickness of this second silicon layer nonetheless tends to include unwanted n-type dopant which has diffused up from lower levels. This surface-seeking behavior diminishes when germanium is alloyed with the silicon. In some devices, it may not be advantageous for the second layer to have significant germanium content. In the present invention, a first heavily n-doped semiconductor layer (preferably at least 10 at % germanium) is deposited, followed by a silicon-germanium capping layer with little or no n-type dopant, followed by a layer with little or no n-type dopant and less than 10 at % germanium. The germanium in the first layer and the capping layer minimizes diffusion of n-type dopant into the germanium-poor layer above. | 2009-01-29 |
20090026583 | Method of Producing 3-D Mold, Method of Producing Finely Processed Product, Method of Producing Fine-Pattern Molded Product, 3-D Mold, Finely Processed Product, Fine-Pattern Molded Product and Optical Component - To provide production methods for a 3-D mold, a finely processed product, and a fine pattern molded product in which the depth and the line width can be formed with high precision, a 3-D mold, a finely processed product, a fine-pattern molded product, and an optical element formed with high precision. | 2009-01-29 |
20090026584 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device which includes fine patterns having various critical dimensions (CDs) by adjusting a thickness of spacer used as an etching mask in Spacer Patterning Technology (SPT). The method for manufacturing a semiconductor device includes forming spacers at a different level over an etching target layer and etching the etching target layer exposed among the spacers. | 2009-01-29 |
20090026585 | Semiconductor Device and Method for Manufacturing the same - A semiconductor device consistent with the present invention includes a semiconductor substrate having a semiconductor chip region and a scribe region; a first insulating layer formed in the semiconductor chip region of the semiconductor substrate; a metal contact plug formed in the first insulating layer; a metal sidewall formed on a side of the first insulating layer in the scribe region; a metallization wiring electrically connected with the substrate via the metal contact plug; and a second insulating layer and a protective layer formed over the metal contact plug and the metal sidewall so as to cover the semiconductor chip region and the scribe region. | 2009-01-29 |
20090026586 | Superjunction Device Having Oxide Lined Trenches and Method for Manufacturing a Superjunction Device Having Oxide Lined Trenches - A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes doping with a dopant of a second conductivity the first sidewall of the mesa, and doping with a dopant of a second conductivity the second sidewall of the mesa. A dopant of the first conductivity is then used to dope the first sidewall of the mesa, and the dopant of the first conductivity is used to dope the second sidewall of the at least one mesa. At least the trenches adjacent to the at least one mesa are then lined with an oxide material and are then filled with one of a semi-insulating material and an insulating material. | 2009-01-29 |
20090026587 | GRADIENT DEPOSITION OF LOW-K CVD MATERIALS - A dielectric layer for a semiconductor device having a low overall dielectric constant, good adhesion to the semiconductor substrate, and good resistance to cracking due to thermal cycling. The dielectric layer is made by a process involving continuous variation of dielectric material deposition conditions to provide a dielectric layer having a gradient of dielectric constant. | 2009-01-29 |
20090026588 | Plasma processing method for forming a film and an electronic component manufactured by the method - A plasma processing method for forming a film on a substrate using a gas processed by a plasma. The plasma processing method for forming a film includes the steps of forming a CF film on the substrate by using a C | 2009-01-29 |
20090026589 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Aiming at providing a semiconductor device advanced in performance of transistors, and improved in reliability, a semiconductor device of the present invention has a semiconductor element, a frame component provided over the semiconductor element, while forming a cavity therein, and a molding resin layer covering around the frame component, wherein the frame component is composed of a plurality of resin films (a first resin film and a second resin film) containing the same resin, and the cavity allows the active region of the semiconductor element to expose therein. | 2009-01-29 |
20090026590 | LEADFRAME PANEL - An improved leadframe panel suitable for use in packaging IC dice is described. The described leadframe panel is configured such that the amount of leadframe material that is removed during singulation of the leadframe panel is reduced. | 2009-01-29 |
20090026591 | SEMICONDUCTOR PACKAGE ADAPTED FOR HIGH-SPEED DATA PROCESSING AND DAMAGE PREVENTION OF CHIPS PACKAGED THEREIN AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first surface from the bonding pad to an end portion of the side surface which meets with the second surface; and a second redistribution pattern disposed over the first redistribution pattern and extending from the side surfaces to the first surface. In an embodiment of the present invention, in which the first redistribution pattern connected with the bonding pad is formed over the semiconductor chip and the second redistribution pattern is formed over the first redistribution pattern, it is capable of reducing a length for signal transfer since the second redistribution pattern is used as an external connection terminal. It is also capable of processing data with high speed, as well as protecting the semiconductor chip having weak brittleness, since the semiconductor package is connected to the substrate without a separate solder ball. | 2009-01-29 |
20090026592 | SEMICONDUCTOR DIES WITH RECESSES, ASSOCIATED LEADFRAMES, AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle. | 2009-01-29 |
20090026593 | THIN SEMICONDUCTOR DIE PACKAGES AND ASSOCIATED SYSTEMS AND METHODS - Thin semiconductor die packages and associated systems and methods are disclosed. A package in accordance with a particular embodiment includes a semiconductor die having die bond sites, a conductive structure positioned proximate to the semiconductor die and having first bond sites and second bond sites spaced apart from the first bond sites, and conductive couplers connected between the first bond sites of the conductive structure and the die bond sites of the semiconductor die. A cover can be positioned adjacent to the semiconductor die, and can include a recess in which the conductive couplers are received. | 2009-01-29 |
20090026594 | Thin Plastic Leadless Package with Exposed Metal Die Paddle - A method of making electronic packages includes providing a leadframe strip that includes a plurality of leadframes, wherein the leadframes comprise a plurality of leads, etching a surface of each of the leadframes to form an opening, wherein each of the leads has a lead tip that connects to a die paddle within the opening, isolating each of the leads from the die paddle, adhering a tape to a bottom side of the leadframe strips, leads, and die paddle, attaching a die to the die paddle, placing ball bumps on each of the lead tips, and connecting the die to the ball bumps. The electronic package includes a leadframe having a plurality of leads, wherein each of the leads has a lead tip, an opening formed within the leadframe, a die paddle that is disposed within the opening and is isolated from each of the lead tips, a tape that is adhered to a back side of the leadframe, leads, and die paddle, and a die, wherein the die is attached to the die paddle and is connected by wires to a bump disposed on each of the lead tips. | 2009-01-29 |
20090026595 | SEMICONDUCTOR DEVICE PACKAGE - A surface of a lead frame of a semiconductor device package, on which a semiconductor chip is mounted, is formed to have a mesh structure, whereby a connecting area between the lead frame and a molding resin can be increased to have strong bonding. Further, only filler particles having a small diameter than the mesh are taken into the vicinity of the lead frame, suppressing the effect of stresses to reduce deformation of the lead frame. | 2009-01-29 |
20090026596 | LEAD FRAME, SEMICONDUCTOR PACKAGE, AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - In certain embodiments, a lead frame includes a paddle, a plurality of inner leads, first outer leads, and a second outer lead. The plurality of inner leads can be arranged at a side face of the paddle. The first outer leads can extend from the inner leads along a first direction and can be arranged at a substantially central portion of the side face of the paddle. Furthermore, each of the first outer leads can have a first area. The second outer lead can be arranged at an edge portion of the side face of the paddle and can be supported by the paddle. The second outer lead can have a second area that is larger than the first area. | 2009-01-29 |
20090026597 | STACKED INTEGRATED CIRCUIT LEADFRAME PACKAGE SYSTEM - A stacked integrated circuit leadframe package system including forming a leadframe, packaging a top integrated circuit on a one side of the leadframe, packaging a bottom integrated circuit on an opposite side of the leadframe, and forming external electrical interconnects on the leadframe. | 2009-01-29 |
20090026598 | Wafer Level Packaging Integrated Hydrogen Getter - A wafer-level package that employs one or more integrated hydrogen getters within the wafer-level package on a substrate wafer or a cover wafer. The hydrogen getters are provided between and among the integrated circuits on the substrate wafer or the cover wafer, and are deposited during the integrated circuit fabrication process. In one non-limiting embodiment, the substrate wafer is a group III-V semiconductor material, and the hydrogen getter includes a titanium layer, a nickel layer, and a palladium layer. | 2009-01-29 |
20090026599 | Memory module capable of lessening shock stress - A memory module capable of lessening shock stresses, primarily comprises a multi-layer printed circuit board (PCB), a plurality of memory packages, and a stress-buffering layer. The memory packages are disposed at least on one of the rectangular surfaces of the PCB. The stress-buffering layer is disposed at least on both short sides of the PCB and extended to the two rectangular surfaces to reduce the impact stresses. Preferably, the stress-buffering layer is further disposed on the other long side of the PCB opposite to the one with disposed gold fingers. | 2009-01-29 |
20090026600 | MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS - Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing. | 2009-01-29 |
20090026601 | SEMICONDUCTOR MODULE - A semiconductor module is disclosed. One embodiment provides a first semiconductor chip having a first contact pad on a first main surface and a second contact pad on a second main surface, a first electrically conductive layer applied to the first main surface, a second electrically conductive layer applied to the second main surface, and an electrically insulating material covering the first electrically conductive layer, wherein a surface of the second electrically conductive layer forms an external contact pad and the second electrically conductive layer has a thickness of less than 200 μm. | 2009-01-29 |
20090026602 | Method For Manufacturing And Making Planar Contact With An Electronic Apparatus, And Correspondingly Manufactured Apparatus - Reliable electrical contact is made with electronic components and effective electrical isolation is produced between the top and bottom of the electronic components. An electronic component is arranged inside a window in a first layer on a substrate. Next, a second layer is put on such that contact areas on the component and contact points on the first layer are freely accessible. Electrical contacts and electrical connecting lines are produced by electrodeposition. The second layer is used to produce bridges over an interval range between the electronic component and the first layer. The bridges have connecting lines formed on them. The second layer can be removed again. Radio-frequency modules can be produces in compact fashion and can be combined with audio-frequency components. | 2009-01-29 |
20090026603 | Electronic component package and method of manufacturing same - An electronic component package includes: a base having a top surface and a side surface; and a plurality of layer portions stacked on the top surface of the base, each of the layer portions including at least one electronic component chip. The base includes a plurality of external connecting terminals, and a retainer for retaining the plurality of external connecting terminals. Each of the external connecting terminals has an end face located at the side surface of the base. At least one of a plurality of electronic component chips that the plurality of layer portions include is electrically connected to at least one of the external connecting terminals. | 2009-01-29 |
20090026604 | Semiconductor plastic package and fabricating method thereof - A semiconductor plastic package and a method of fabricating the semiconductor plastic package are disclosed. A method of fabricating a semiconductor plastic package can include: providing a core board, which includes at least one pad, and which has a coefficient of thermal expansion of 9 ppm/° C. or lower; stacking a build-up insulation layer over the core board; forming an opening by removing a portion of the build-up insulation layer such that the pad is exposed to the exterior; and placing a semiconductor chip in the opening and electrically connecting the semiconductor chip with the pad. This method can be utilized to provide higher reliability in the connection between the semiconductor chip and the circuit board. | 2009-01-29 |
20090026605 | Heat Extraction from Packaged Semiconductor Chips, Scalable with Chip Area - A semiconductor device ( | 2009-01-29 |
20090026606 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device and a method for manufacturing the same are described. The semiconductor device comprises: a heat sink having at least one opening passing through the heat sink; at least one semiconductor chip disposed in the opening, wherein the semiconductor chip includes a first side and a second side on opposite sides; an electricity conducting thin film filling in a first depth portion of the opening, wherein the second side of the semiconductor chip is embedded in the electricity conducting thin film; a heat conducting thick film filling in a second depth portion of the opening, wherein the electricity conducting thin film is directly connected with the heat conducting thick film; at least one wire electrically connecting the semiconductor chip and an external circuit; and an encapsulant covering a portion of the heat sink, the semiconductor chip, the wire and an exposed portion of the electricity conducting thin film. | 2009-01-29 |
20090026607 | Electronic Device and Method of Manufacturing Same - It is proposed a method of manufacturing an electronic system wherein a first substrate comprising first connection elements on a first surface of the first substrate is provided; a second substrate comprising second connection elements on a first surface of the second substrate is provided; a polymer layer is applied to at least one of the two first surfaces; the first connection elements are attached to the second connection elements; and the polymer layer is caused to swell during or after the attachment. | 2009-01-29 |
20090026608 | Crosstalk-Free WLCSP Structure for High Frequency Application - A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the substrate and coupled with the circuitry, a ground ring encircling the signal pin, and a grounded solder bump coupled to the ground ring. | 2009-01-29 |
20090026609 | Semiconductor device and method for manufacturing the same - A semiconductor device includes a semiconductor chip, a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a through electrode formed on an upper surface of the first land electrode to be electrically coupled with the first land electrode using a stud bump, and a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip. | 2009-01-29 |
20090026610 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention provides a semiconductor device having high reliability and a method of manufacturing the same. The semiconductor device of the invention has pad electrodes formed on a semiconductor die near the side surface portion thereof and connected to a semiconductor integrated circuit or the like in the semiconductor die, a supporting body formed on the pad electrodes, an insulation film formed on the side and back surface portions of the semiconductor die, wiring layers connected to the back surfaces of the pad electrodes and extending from the side surface portion onto the back surface portion of the semiconductor die so as to contact the insulation film, and a second protection film formed on the side surface portion of the supporting body. | 2009-01-29 |
20090026611 | ELECTRONIC ASSEMBLY HAVING A MULTILAYER ADHESIVE STRUCTURE - An electronic device comprises a substrate and a number of bump units over the substrate, wherein each of the bump units includes an electrically insulating bump-forming body extending in a first direction, and at least two conductive layers separated from each other on the electrically insulating bump-forming body, the at least two conductive layers extending in a second direction orthogonal to the first direction. | 2009-01-29 |