04th week of 2010 patent applcation highlights part 42 |
Patent application number | Title | Published |
20100022033 | PROCESS FOR WAFER TEMPERATURE VERIFICATION IN ETCH TOOLS - A blank wafer is placed in an etch chamber. A layer is deposited over the blank wafer, comprising providing a deposition gas, forming the deposition gas into a deposition plasma, and stopping the deposition gas. The blank wafer with the deposited layer is removed from the etch chamber. The thickness of the deposited layer is measured. Wafer temperature accuracy is calculated from the measured thickness of the deposited layer. The etch chamber is compensated according to the calculated wafer temperature accuracy. A wafer with an etch layer over the wafer and a patterned mask over the etch layer is placed into the etch chamber. The etch layer is etched in the etch chamber. | 2010-01-28 |
20100022034 | Manufacture of devices including solder bumps - Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly. | 2010-01-28 |
20100022035 | Electronic apparatus and manufacturing method thereof - There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the internal connection terminals, and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals, a wiring substrate on which the plurality of semiconductor apparatuses are stepwise stacked, the wiring substrate electrically connected to the plurality of semiconductor apparatuses, and a sealing resin with which the plurality of semiconductor apparatuses are sealed. | 2010-01-28 |
20100022036 | METHOD FOR FORMING PATTERN, AND TEMPLATE - According to an aspect of the present invention, there is provided a template including: a template substrate; patterns for forming device patterns on a wafer substrate; and a charging monitoring pattern, a size of the charging monitoring pattern being equal to a largest pattern in the patterns for forming the device patterns. | 2010-01-28 |
20100022037 | METHOD FOR FABRICATING CMOS IMAGE SENSOR - A method for fabricating a CMOS image sensor includes developing a semiconductor substrate provided with metal pads with tetramethylammonium hydroxide (TMAH), to etch the metal pads. In accordance with the method, it is possible to realize normal output of materials, which were previously scrapped due to problems including pad corrosion, appearance defects and bonding pad issues which may occur in the process of fabricating CMOS image sensors. As a result, advantageously, it is possible to reduce wafer scrap and improve product yield. | 2010-01-28 |
20100022038 | Method for evaluating semiconductor wafer - The present invention provides a method for evaluating a semiconductor wafer, including at least: forming an oxide film on a front surface of a semiconductor wafer; partially removing the oxide film to form windows at two positions; diffusing a dopant having a conductivity type different from a conductivity type of a semiconductor as an evaluation target through the windows at the two positions and forming diffused portions in the semiconductor as the evaluation target to form PN junctions; and performing leakage current measurement and/or DLTS measurement in a part between the two diffused portions to evaluate the semiconductor wafer. As a result, there is provided the method for evaluating a semiconductor wafer that can perform junction leakage current measurement or DLTS measurement to easily evaluate a quality of the inside of the semiconductor wafer. In particular, there can be provided the method that can evaluate not only a PW or an EPW but also the inside of an SOI layer of an SOI wafer. | 2010-01-28 |
20100022039 | METHOD OF MAKING LIGHT EMITTING DIODES - A method of making LEDs simultaneously includes steps of : a) providing a wafer having LED dies on a substrate; b) forming a passivation layer on the LED dies; c) forming an electrode layer on the passivation layer and the LED dies; d) assembling a conducting board on the electrode layer; e) removing the substrate to expose a light emitting surface of each LED die; f) forming a terminal on the light emitting surface; g) forming a channel at a lateral side of each LED die; h) assembling a cover onto the LED dies; i) wire bonding and encapsulating the LED dies to the LEDs connected with each other; and j) cutting through the interconnected LEDs to form the LEDs separated from each other. | 2010-01-28 |
20100022040 | METHOD FOR PRODUCING LIGHT-EMITTING DEVICE - [Object] To restrain color variation in light emitted from a light-emitting device. | 2010-01-28 |
20100022041 | THIN FILM TRANSISTOR ARRAY PANEL INCLUDING LAYERED LINE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu). | 2010-01-28 |
20100022042 | Method for fabricating an in-plane switching mode liquid crystal display device - An in-plane switching mode liquid crystal display (LCD) device, which reduces loss in transmittance and improves reflectance, and a method for fabricating the same are disclosed. The in-plane switching mode LCD device includes gate and data lines orthogonally crossing each other on a first substrate to define pixel regions having reflection portions and transmission portions; thin film transistors formed at the crossing of the gate and data lines; common electrodes formed at the transmission portions of the pixel regions; reflection electrodes formed at the reflection portions of the pixel regions; pixel electrodes formed parallel with the common electrodes at the transmission portions and formed above the reflection electrodes at the reflection portions; a second substrate facing and attached to the first substrate; a liquid crystal layer interposed between the first and second substrates; and first and second polarizing films respectively attached to outer surfaces of the first and second substrates. | 2010-01-28 |
20100022043 | SEMICONDUCTOR LASER DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing semiconductor laser device capable of reducing κL, with manufacturing restrictions satisfied, is provided. In a distributed-feedback or distributed-reflective semiconductor laser device, immediately before burying regrowth of a diffraction grating, halogen-based gas is introduced to a reactor, and etching is performed on the diffraction grating so that each side wall has at least two or more crystal faces and a ratio of length of an upper side in a waveguide direction to a bottom side parallel to a (100) surface is 0 to 0.3. And, a reactive product formed on side surfaces of the diffraction grating and in trench portions between stripes of the diffraction grating at an increase of temperature for regrowth is removed. Therefore, the diffraction grating with reduced height and a sine wave shape is obtained, thereby κL of the device is reduced. Thus, an oscillation threshold and optical output efficiency can be improved. | 2010-01-28 |
20100022044 | LASER DEVICE, LASER MODULE, SEMICONDUCTOR LASER AND FABRICATION METHOD OF SEMICONDUCTOR LASER - A semiconductor laser has first and second diffractive grating regions. The first diffractive grating region has segments, has a gain, and has first discrete peaks of a reflection spectrum. The second diffractive grating region has segments combined to each other, and has second discrete peaks of a reflection spectrum. Each segment has a diffractive grating and a space region. Pitches of the diffractive grating are substantially equal to each other. A wavelength interval of the second discrete peaks is different from that of the first discrete peaks. A part of a given peak of the first discrete peaks is overlapped with that of the second discrete peaks when a relationship between the given peaks of the first discrete peaks and the second discrete peaks changes. A first segment located in the first diffractive grating region or the second diffractive grating region has an optical length shorter or longer than the other segments of the first diffractive grating region and the second diffractive grating region by odd multiple of half of the pitch of the diffractive grating of the first diffractive grating region. | 2010-01-28 |
20100022045 | SENSOR PLATFORM USING A NON-HORIZONTALLY ORIENTED NANOTUBE ELEMENT - Sensor platforms and methods of making them are described. A platform having a non-horizontally oriented sensor element comprising one or more nanostructures such as nanotubes is described. Under certain embodiments, a sensor element has or is made to have an affinity for an analyte. Under certain embodiments, such a sensor element comprises one or more pristine nanotubes. Under certain embodiments, the sensor element comprises derivatized or functionalized nanotubes. Under certain embodiments, a sensor is made by providing a support structure; providing one or more nanotubes on the structure to provide material for a sensor element; and providing circuitry to electrically sense the sensor element's electrical characterization. Under certain embodiments, the sensor element comprises pre-derivatized or pre-functionalized nanotubes. Under other embodiments, sensor material is derivatized or functionalized after provision on the structure or after patterning. Under certain embodiments, a large-scale array of sensor platforms includes a plurality of sensor elements. | 2010-01-28 |
20100022046 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: the step (a) of forming a vibrating film on a predetermined region of each of a plurality of chips included in a semiconductor wafer; the step (b) of forming, on the semiconductor wafer, an intermediate film containing a sacrifice layer located on the vibrating film of each of the chips; and the step (c) of forming a fixed film on the intermediate film. This method further includes, after the step (c), the step (d) of subjecting the semiconductor wafer to blade dicing to separate the chips, and the step (e) of removing, by etching, the sacrifice layer to provide a cavity between the vibrating film and the fixed film. | 2010-01-28 |
20100022047 | METHOD OF MANUFACTURING SOLAR CELL MODULE AND METHOD OF MANUFACTURING SOLAR CELL - A method of manufacturing the solar cell module | 2010-01-28 |
20100022048 | Semiconductor device and manufacturing method therefor - The present invention relates to a manufacturing method for a semiconductor device, the method includes a process for forming an interlayer film on a substrate, a process for forming an opening in the interlayer, a process for forming a conductive layer which fills the opening, and a process for forming a cap film on the surface of the conductive layer. In the process for forming the cap film, a reduction process for the surface of the conductive layer and the forming of the film are performed simultaneously. | 2010-01-28 |
20100022049 | Mid-IR Microchip Laser: ZnS:Cr2+ Laser with Saturable Absorber Material - A method of fabrication of laser gain material and utilization of such media includes the steps of introducing a transitional metal, preferably Cr | 2010-01-28 |
20100022050 | Standoff Height Improvement for Bumping Technology Using Solder Resist - A semiconductor device is made by disposing a film layer over a substrate having first conductive layer. An opening is formed in the film layer to expose the first conductive layer. A second conductive layer is formed over the first conductive layer. A first bump is formed over the second conductive layer which promotes reflow of the first bump at a eutectic temperature. A standoff bump is formed on the film layer around a perimeter of the substrate. The film layer prevents reflow of the standoff bump at the eutectic temperature. A second bump is disposed between a semiconductor die and the first bump. The second bump is reflowed to electrically connect the semiconductor die to the first bump. After reflow of the second bump, the standoff bump has a height at least 70% of the second bump prior to reflow to maintain separation between the semiconductor die and substrate. | 2010-01-28 |
20100022051 | Method of fabricating electronic device having stacked chips - A method of fabricating an electronic device having stacked chips is provided. The method includes forming a plurality of chips arranged in a row direction and at least one chip arranged in a column direction. A molding layer is formed between the chips. Grooves are formed in the molding layer between the chips arranged in the row direction. Conductive interconnections are formed on the substrate having the grooves. The substrate is sawn along an odd- or even-numbered one of the grooves to be separated into a plurality of unit substrates. At least one of the separated unit substrates is folded along an unsawn groove of the grooves. | 2010-01-28 |
20100022052 | Method for manufacturing package on package with cavity - A manufacturing method of a package on package with a cavity. The method can include forming a first upper substrate cavity in one side of an upper substrate; mounting an upper semiconductor chip on the other side of the upper substrate; forming a lower substrate cavity in one side of a lower substrate; mounting a lower semiconductor chip in the lower substrate cavity formed in the lower substrate; and stacking the upper substrate above the lower substrate such that the first upper substrate cavity accommodates a part of the lower semiconductor chip. The package on package and a manufacturing method thereof can reduce the overall thickness of the package by forming cavities in both upper and lower substrates to accommodate a semiconductor chip mounted in the lower substrate. | 2010-01-28 |
20100022053 | Method for Packaging Components - The invention relates to a method for the manufacture of packaged components. The invention is based here on the problem of facilitating the application of covers with lateral dimensions that are smaller than the lateral dimensions of the functional substrate. For this purpose, a plate-like cover substrate is mounted on a carrier substrate. Then, on the uncovered side of the plate-like cover substrate, trenches are inserted, so that a composite part is obtained with the carrier substrate and individual covering parts that are separated from each other by the trenches, but interconnected by the carrier substrate. The covering parts of the composite part are connected with a functional substrate with a plurality of components. Then, the connection of the covering parts is dissolved with the carrier substrate, and the carrier substrate is removed, so that a composite is obtained with the functional substrate and a plurality of covering parts that cover functional areas. | 2010-01-28 |
20100022054 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes: a build-up wiring layer including a metal wiring layer and an insulation resin layer; and a low thermal expansion material layer having a coefficient of thermal expansion closer to that of a semiconductor chip mounted on the build-up wiring layer as compared with the insulation resin layer of the build-up wiring layer, the low thermal expansion material layer being bonded to an entire region of a rear surface of the build-up wiring layer corresponding to a region of a front surface of the build-up wiring layer on which the semiconductor chip is mounted. | 2010-01-28 |
20100022055 | THIN FILM TRANSISTOR, THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE SAME AND METHOD OF MANUFACTURING THE SAME - A thin film transistor showing desirable contact characteristics during contact with indium tin oxide (ITO) or indium zinc oxide (IZO), in which a first conductive pattern including a gate electrode and a second conductive pattern including a source electrode and a drain electrode are formed without an etching process, a TFT substrate including the TFTs, and a method of manufacturing the same. The thin film transistor includes a gate electrode formed of a first conductive layer, a gate insulating layer covering the gate electrode, a semiconductor layer forming a channel on the gate insulating layer; an ohmic contact layer formed on the semiconductor layer, and a source electrode and a drain electrode formed of a second conductive layer and of a third conductive layer. The second conductive layer includes an aluminum-nickel alloy and nitrogen and is formed on the semiconductor layer. The third conductive layer includes an aluminum-nickel alloy and is formed on the second conductive layer. | 2010-01-28 |
20100022056 | METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR - The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate ( | 2010-01-28 |
20100022057 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A FIN CHANNEL TRANSISTOR - The semiconductor device includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof. The semiconductor device additionally has a fin channel region protruded over the device isolation structure in a longitudinal direction of a gate region; a gate insulating film formed over the semiconductor substrate including the protruded fin channel region; and a gate electrode formed over the gate insulating film to fill up the protruded fin channel region. | 2010-01-28 |
20100022058 | METHOD FOR PREPARING MULTI-LEVEL FLASH MEMORY - A method for preparing a multi-level flash memory comprising the steps of forming a recess in a semiconductor substrate, forming a plurality of storage structures at the sides of the recess, and forming a gate structure having a lower block in the recess and an upper block on the lower block. The storage structures are separated by the gate structure, and each of the storage structures includes a charge-trapping site and an insulation structure surrounding the charge-trapping site. | 2010-01-28 |
20100022059 | Method of fabricating high voltage semiconductor devices with JFET regions containing dielectrically isolated junctions - A high-voltage field-effect device contains an extended drain or “drift” region having a plurality of JFET regions separated by portions of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and at least two sides of each JFET region is lined with an oxide layer. In one group of embodiments the JFET regions extend from the surface of an epitaxial layer to an interface between the epitaxial layer and an underlying substrate, and the walls of each JFET region are lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region and allowing the JFET regions to be accurately located in the drift region. | 2010-01-28 |
20100022060 | BI-AXIAL TEXTURING OF HIGH-K DIELECTRIC FILMS TO REDUCE LEAKAGE CURRENTS - The present invention is directed to methods of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a high-K dielectric material assisted with an ion beam to enable the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric films have a high degree of crystallographic alignment at grain boundaries. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The result is a dielectric film having a high degree of crystallographic alignment at grain boundaries of the film. | 2010-01-28 |
20100022061 | Spacer Shape Engineering for Void-Free Gap-Filling Process - A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer. | 2010-01-28 |
20100022062 | TRANSITOR HAVING A GERMANIUM IMPLANT REGION LOCATED THEREIN AND A METHOD OF MANUFACTURE THEREFOR - The present invention provides a transistor | 2010-01-28 |
20100022063 | METHOD OF FORMING ON-CHIP PASSIVE ELEMENT - Various methods of forming a passive element such as an inductor raised off the surface of the substrate to improve the performance of the passive element are presented. A first wafer may be provided, and passive elements diced from a second wafer. The passive elements are flipped, and then aligned to be bonded on the first wafer such that the passive elements are raised a distance off the first wafer because of the presence of chip connections such as C4 solder bumps. A gap between the passive elements and the first wafer can be filled with underfill or air. If air is used, a hermetic seal around the gap can be created using chip connections such as C4 solder bumps or other known bonding means to seal the gap. | 2010-01-28 |
20100022064 | HIGH VOLTAGE SENSOR DEVICE AND METHOD THEREFOR - In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element includes a conductor overlying a space in a resistor. | 2010-01-28 |
20100022065 | DEEP TRENCH DEVICE WITH SINGLE SIDED CONNECTING STRUCTURE AND FABRICATION METHOD THEREOF - A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed. | 2010-01-28 |
20100022066 | METHOD FOR PRODUCING HIGH-RESISTANCE SIMOX WAFER - A method for producing a high-resistance SIMOX wafer wherein oxygen diffused inside of a wafer by the heat treatment at a high temperature in an oxidizing atmosphere can be reduced to suppress the occurrence of thermal donor. In one embodiment, a heating-rapid cooling treatment is conducted after the heat treatment at a high temperature in an oxidizing atmosphere to implant vacancies from a surface of a wafer into an interior thereof to thereby easily precipitate oxygen diffused inside the wafer during the heat treatment. | 2010-01-28 |
20100022067 | DEPOSITION METHODS FOR RELEASING STRESS BUILDUP - A deposition method for releasing a stress buildup of a feature over a semiconductor substrate with dielectric material is provided. The feature includes lines separated by a gap. The method includes forming a liner layer over the feature on the semiconductor substrate in a chamber. A stress of the liner layer over the feature is released to substantially reduce bending of the lines of the feature. A dielectric film is deposited over the stress-released liner layer to substantially fill the gap of the feature. | 2010-01-28 |
20100022068 | STI FILM PROPERTY USING SOD POST-TREATMENT - A method of forming a shallow trench isolation region includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; filling a precursor into the opening using spin-on; performing a steam cure to the precursor to generate a dielectric material; after the steam cure, performing a chemical mechanical polish (CMP) to the dielectric material; and after the CMP, performing a steam anneal to the dielectric material. | 2010-01-28 |
20100022069 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An oxide film and a liner film are formed on an inner wall of a trench in a semiconductor substrate. After filling an SOD film in the trench, a heat treatment is carried out. Part of the liner film in contact with the SOD film is removed to expose part of the SOD film. A heat treatment is carried out on the SOD film. An isolating region is formed by filling an insulating film in the trench. | 2010-01-28 |
20100022070 | METHOD FOR MANUFACTURING SOI SUBSTRATE - It is an object to provide a method for, after a semiconductor film is separated, reprocessing a separated bond substrate into a reprocessed bond substrate which can be used for manufacturing an SOI substrate. The method for, after a semiconductor film is separated, reprocessing a separated bond substrate into a reprocessed bond substrate which can be used for manufacturing an SOI substrate includes the steps of forming an insulating film over a bond substrate; adding ions from a surface of the bond substrate to form an embrittlement layer; bonding the bond substrate to a glass substrate with the insulating film interposed therebetween; separating, at the embrittlement layer, the bond substrate into a semiconductor film which is bonded to the glass substrate with the insulating film interposed therebetween and a separated bond substrate; performing first wet etching using a solution containing hydrofluoric acid as an etchant on the separated bond substrate; performing second wet etching using an organic alkaline aqueous solution as an etchant on the separated bond substrate; performing thermal oxidation treatment on the separated bond substrate in an oxidizing atmosphere to which a gas containing halogen is added to form an oxide film on a surface of the separated bond substrate; performing third wet etching using a solution containing hydrofluoric acid as an etchant on the oxide film; and forming a reprocessed bond substrate by performing polishing on the separated bond substrate. | 2010-01-28 |
20100022071 | METHOD OF MANUFACTURING SEMICONDUCTOR CHIP - An object is to provide a semiconductor chip manufacturing method capable of removing test patterns in a higher efficiency in simple steps, while a general-purpose characteristic can be secured. | 2010-01-28 |
20100022072 | Semiconductor Fabrication - This document discloses devices fabricated on a semiconductor substrate and methods of fabricating the same. The devices can be memory cells having a tunnel window that is defined by dry-etching oxide to expose the semiconductor substrate and growing a tunnel oxide layer on the exposed semiconductor substrate. The semiconductor substrate can be decontaminated and/or repaired by exposing the semiconductor substrate to an optical irradiated energy source having a predefined energy that is sufficient to break molecular bonds of the contaminants and exposing the semiconductor substrate to a temperature that is sufficient to recrystallize the crystal lattice of the substrate. | 2010-01-28 |
20100022073 | Method of Fabricating CMOS Inverter and Integrated Circuits Utilizing Strained Silicon Surface Channel MOSFETS - A method of fabricating a circuit comprising an nMOSFET includes providing a substrate, depositing a strain-inducing material comprising germanium over the substrate, and integrating a pMOSFET on the substrate, the pMOSFET comprising a strained channel having a surface roughness of less than 1 nm. The strain-inducing material is proximate to and in contact with the pMOSFET channel, the strain in the pMOSFET channel is induced by the strain-inducing material, and a source and a drain of the pMOSFET are at least partially formed in the strain-inducing material. | 2010-01-28 |
20100022074 | SUBSTRATE RELEASE METHODS AND APPARATUSES - The present disclosure relates to methods and apparatuses for fracturing or breaking a buried porous semiconductor layer to separate a 3-D thin-film semiconductor semiconductor (TFSS) substrate from a 3-D crystalline semiconductor template. The method involves forming a sacrificial porous semiconductor layer on the 3-D features of the template. A variety of techniques may be used to fracture and release the mechanically weak porous semiconductor layer without damaging the TFSS substrate layer or the template layer such as pressure variations, thermal stress generation, and mechanical bending. The methods also allow for processing three dimensional features not possible with current separation processes. Optional cleaning and final lift-off steps may be performed as part of the release step or after the release step. | 2010-01-28 |
20100022075 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced. | 2010-01-28 |
20100022076 | Ion Implantation with Heavy Halogenide Compounds - A method of plasma doping includes providing a dopant gas comprising a dopant heavy halogenide compound gas to a plasma chamber. A plasma is formed in the plasma chamber with the dopant heavy halogenide compound gas and generates desired dopant ions and heavy fragments of precursor dopant molecule. A substrate in the plasma chamber is biased so that the desired dopant ions impact the substrate with a desired ion energy, thereby implanting the desired dopant ions and the heavy fragments of precursor dopant molecule into the substrate, wherein at least one of the ion energy and composition of the dopant heavy halogenide compound is chosen so that the implant profile in the substrate is substantially determined by the desired dopant ions. | 2010-01-28 |
20100022077 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device. A method is also provided for the formation of shallow junctions in a semiconductor substrate by diffusion of dopant from an implanted layer contained within a dielectric layer into the semiconductor surface. Further, the ion implanted layer is provided with a second implanted species, such as hydrogen, in addition to the intended dopant species, wherein said species enhances the diffusivity of the dopant in the dielectric layer. | 2010-01-28 |
20100022078 | Aluminum Inks and Methods of Making the Same, Methods for Depositing Aluminum Inks, and Films Formed by Printing and/or Depositing an Aluminum Ink - Aluminum metal ink compositions, methods of forming such compositions, and methods of forming aluminum metal layers and/or patterns are disclosed. The ink composition includes an aluminum metal precursor and an organic solvent. Conductive structures may be made using such ink compositions by printing or coating the aluminum precursor ink on a substrate (decomposing the aluminum metal precursors in the ink) and curing the composition. The present aluminum precursor inks provide aluminum films having high conductivity, and reduce the number of inks and printing steps needed to fabricate printed, integrated circuits. | 2010-01-28 |
20100022079 | SYSTEMS AND METHODS FOR REDUCING CONTACT TO GATE SHORTS - A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the gate and the contact. The insulator may be formed by oxidizing the gate to form a dielectric between the contact and the gate after the contact is formed on the gate. | 2010-01-28 |
20100022080 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing the semiconductor device includes nitridizing a silicon substrate with ammonia while heating the silicon substrate, then heating the silicon substrate in an atmosphere containing nitrogen and oxygen to form a gate insulating film including a silicon-based insulating film containing nitrogen and oxygen, then annealing the silicon substrate in an oxygen atmosphere, and forming a gate electrode on the gate insulating film. | 2010-01-28 |
20100022081 | NON-VOLATILE SONOS-TYPE MEMORY DEVICE - A semiconductor memory device with the thickness of both a tunnel film and a top film provided thereon configured to be in the FN tunneling region (4 nm or more). Data retention characteristics can be improved by configuring both a tunnel film and a top film to have a thickness in the FN tunneling region. Secondly, a high-concentration impurity region of a conductivity type the same as that of the substrate is provided in a substrate region arranged between assist gates provided adjacently to each other. The aforementioned high-concentration impurity region makes a depletion layer extremely thin when bias is applied to the assist gates. Hot holes generated between bands in the depletion region are injected into a charge storage region and the holes and electrons make pairs and disappear, enabling easy data erasing. | 2010-01-28 |
20100022082 | Method for making a nanotube-based electrical connection between two facing surfaces - Facing surfaces made from semiconductor material are formed and then transformed into a porous semiconductor. The porous semiconductor is then transformed into a porous metallic material by silicidation. The porous metallic material then acts as catalyst for growth of the carbon nanotubes which electrically connect the facing surfaces made from porous metallic material. | 2010-01-28 |
20100022083 | CARBON NANOTUBE INTERCONNECT STRUCTURES - A method including forming an interconnect of single-walled carbon nanotubes on a sacrificial substrate; transferring the interconnect from the sacrificial substrate to a circuit substrate; and coupling the interconnect to a contact point on the circuit substrate. A method including forming a nanotube bundle on a circuit substrate between a first contact point and a second contact point, the nanotube defining a lumen therethrough; filling a portion of a length of the lumen of the nanotube bundle with an electrically conductive material; and coupling the electrically conductive material to the second contact point. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board, the microprocessor including a substrate having a plurality of circuit devices with electrical connections made to the plurality of circuit devices through interconnect structures including carbon nanotube bundles. | 2010-01-28 |
20100022084 | Method for Forming Interconnect Structures - Methods of fabricating interconnect structures in a semiconductor integrated circuit (IC) are presented. A preferred embodiment comprises forming interconnect lines and vias through a dual-damascenes process. It includes forming a via dielectric layer, an etch stop layer directly over the via dielectric layer, and a trench dielectric layer over the etch stop layer. The etch stop layer is patterned through a first photolithography and etch process to form openings in the etch stop layer, prior to the formation of the trench dielectric layer. A second photolithography and etch process is performed after formation of the trench dielectric layer to create trench openings in the trench dielectric layer and via openings in the via dielectric layer, where the patterned etch stop layer acts as a hard-mask in forming vias in the via dielectric layer. | 2010-01-28 |
20100022085 | Method of Forming Support Structures for Semiconductor Devices - Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support members may be used to route functional conductive lines for making electrical contact to active areas of the semiconductor device. Dummy support structures may optionally be formed between the functional conductive lines. The support structures may be formed in one or more conductive line layers and semiconductive material layers of a semiconductor device. In other embodiments, support members are not formed in an annular shape, and are formed in insulating layers that do not comprise low dielectric constant (k) materials. | 2010-01-28 |
20100022086 | METHOD OF MANUFACTURING A METAL WIRING STRUCTURE - In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitidation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole. | 2010-01-28 |
20100022087 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes an insulating film formed above an upper surface of a semiconductor substrate and including a contact hole, the contact hole including an upper portion and a lower portion located on the upper portion via a boundary as a first lower end of the upper portion and a first upper end of the lower portion, the boundary including a second inner width same as the first inner width, the lower portion including a second lower end having a third inner width narrower than the second inner width, a first conductive plug made from polycrystalline silicon and formed in the lower portion of the contact hole so that the exposed upper surface of the substrate is in contact with the first conductive plug, and a second conductive plug formed on the first conductive plug and made from a conductive material different from the polycrystalline silicon. | 2010-01-28 |
20100022088 | MULTIPLE EXPOSURE AND SINGLE ETCH INTEGRATION METHOD - A process including forming a silicon layer over a semiconductor wafer having features thereon and then selectively ion implanting in the silicon layer to form ion implanted regions. The step of selectively ion implanting is repeated as many times as necessary to obtain a predetermined number and density of features. Thereafter, the silicon layer is etched to form openings in the silicon layer that were formerly occupied by the ion implanted regions. The opened areas in the silicon layer form a mask for further processing of the semiconductor wafer. | 2010-01-28 |
20100022089 | Method for manufacturing semiconductor device using quadruple-layer laminate - There is provided a laminate used as an underlayer layer for a photoresist in a lithography process of a semiconductor device and a method for manufacturing a semiconductor device by using the laminate. The method comprising: laminating each layer of an organic underlayer film (layer A), a silicon-containing hard mask (layer B), an organic antireflective film (layer C) and a photoresist film (layer D) in this order on a semiconductor substrate. The method also comprises: forming a resist pattern in the photoresist film (layer D); etching the organic antireflective film (layer C) with the resist pattern; etching the silicon-containing hard mask (layer B) with the patterned organic antireflective film (layer C); etching the organic underlayer film (layer A) with the patterned silicon-containing hard mask (layer B); and processing the semiconductor substrate with the patterned organic underlayer film (layer A). | 2010-01-28 |
20100022090 | RESIST UNDERLAYER FILM FORMING COMPOSITION FOR LITHOGRAPHY, CONTAINING AROMATIC FUSED RING-CONTAINING RESIN - There is provided a resist underlayer film forming composition for lithography, which in order to prevent a resist pattern from collapsing after development in accordance with the miniaturization of the resist pattern, is applied to multilayer film process by a thin film resist, has a lower dry etching rate than resists and semiconductor substrates, and has a satisfactory etching resistance relative to a substrate to be processed in the processing of the substrate. A resist underlayer film forming composition used in lithography process by a multiplayer film, comprises a polymer containing a unit structure having an aromatic fused ring, a unit structure having a protected carboxyl group or a unit structure having an oxy ring. A method of forming a pattern by use of the resist underlayer film forming composition. A method of manufacturing a semiconductor device by utilizing the method of forming a pattern. | 2010-01-28 |
20100022091 | METHOD FOR PLASMA ETCHING POROUS LOW-K DIELECTRIC LAYERS - Described herein are methods and apparatuses for etching low-k dielectric layers to form various interconnect structures. In one embodiment, the method includes forming an opening in a resist layer. The method further includes etching a porous low-k dielectric layer with a process gas mixture that includes a fluorocarbon gas and a carbon dioxide (CO | 2010-01-28 |
20100022092 | Method of producing semiconductor device using resist underlayer film by photo-crosslinking curing - There is provided a resist underlayer film forming composition used in a lithography process for producing semiconductor devices. A method of producing a semiconductor device comprising: forming a coating film by applying a resist underlayer film forming composition containing a polymer, a crosslinker and a photoacid generator on a semiconductor substrate; forming an underlayer film by irradiating light to the coating film; and forming a photoresist by applying a photoresist composition on the underlayer film and heating the resultant layer. The polymer polymer is a polymer having a benzene ring or a hetero ring in a main chain or a side chain bonded to the main chain, and the content rate of a benzene ring in the polymer is 30 to 70% by mass. The polymer may be a polymer containing a lactone structure. | 2010-01-28 |
20100022093 | VACUUM PROCESSING APPARATUS, METHOD OF OPERATING SAME AND STORAGE MEDIUM - In a vacuum processing apparatus including a processing chamber having a transfer port, and a transfer chamber connected via a gate chamber to the transfer port, diffusion of a gas remaining in the processing chamber into the transfer chamber is suppressed. In order to suppress diffusion of gas from the processing chamber into the transfer chamber, the gate chamber is provided with a non-reactive gas supply unit and an exhaust port adapted to produce a stream of a non-reactive gas at a region facing the transfer port. This suppresses diffusion of gas from the processing chamber into the transfer chamber through the transfer port. | 2010-01-28 |
20100022094 | ELEVATOR AND APPARATUS AND METHOD FOR PROCESSING SUBSTRATE USING THE SAME - In an apparatus and a method for processing a substrate, a plurality of chucks are disposed parallel with each other in a process chamber. The chucks fully support back surfaces of substrates and have a plurality of through-holes. Supports are disposed through the through-holes and movable in a vertical direction. The substrates are loaded on the chucks or unloaded from the chucks by relative movement between the chucks and the supports. Thus, an unwanted layer may be prevented from being formed on the back surfaces of the substrates while processing the substrates. | 2010-01-28 |
20100022095 | Selective Etching and Formation of Xenon Difluoride - This invention relates to a process for selective removal of materials, such as: silicon, molybdenum, tungsten, titanium, zirconium, hafnium, vanadium, tantalum, niobium, boron, phosphorus, germanium, arsenic, and mixtures thereof, from silicon dioxide, silicon nitride, nickel, aluminum, TiNi alloy, photoresist, phosphosilicate glass, boron phosphosilicate glass, polyimides, gold, copper, platinum, chromium, aluminum oxide, silicon carbide and mixtures thereof. The process is related to the important applications in the cleaning or etching process for semiconductor deposition chambers and semiconductor tools, devices in a micro electro mechanical system (MEMS), and ion implantation systems. Methods of forming XeF | 2010-01-28 |
20100022096 | MATERIAL REMOVAL METHODS EMPLOYING SOLUTIONS WITH REVERSIBLE ETCH SELECTIVITIES - A method for removing (e.g., etching) different dielectric materials from a semiconductor substrate includes exposing the semiconductor substrate to a solution at temperatures below and at or above a set threshold. Below the threshold temperature, the solution removes one dielectric material (e.g., silicon nitride) faster than it removes another, different dielectric material (e.g., silicon oxide). At or above the threshold temperature, the selectivity of the solution is reversed. | 2010-01-28 |
20100022097 | VAPORIZER, SEMICONDUCTOR PRODUCTION APPARATUS AND PROCESS OF SEMICONDUCTOR PRODUCTION - A vaporizer, a semiconductor production apparatus and process capable of improving the efficiency in the use of a raw material gas noticeably, enabling uniform deposition according to the raw material gas used, diminishing maintenance frequency to improve productivity. At the time of ALD operation, carrier gas continues to be supplied to a reaction chamber | 2010-01-28 |
20100022098 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: performing modifying a surface of a semiconductor wafer including a silanol group on the surface with an alkylsilyl group; and fluorinating an alkyl group of the alkylsilyl group with which the surface was modified. | 2010-01-28 |
20100022099 | METHOD OF FORMING NON-CONFORMAL LAYERS - In one aspect, non-conformal layers are formed by variations of plasma enhanced atomic layer deposition, where one or more of pulse duration, separation, RF power on-time, reactant concentration, pressure and electrode spacing are varied from true self-saturating reactions to operate in a depletion-effect mode. Deposition thus takes place close to the substrate surface but is controlled to terminate after reaching a specified distance into openings (e.g., deep DRAM trenches, pores, etc.). Reactor configurations that are suited to such modulation include showerhead, in situ plasma reactors, particularly with adjustable electrode spacing. In another aspect, alternately and sequentially contacting a substrate, the substrate including openings, with at least two different reactants, wherein an under-saturated dose of at least one of the reactants has been predetermined and the under-saturated dose is provided uniformly across the substrate surface, deposits a film that less than fully covers surfaces of the openings, leading to depletion effects in less accessible regions on the substrate surface | 2010-01-28 |
20100022100 | BI-LAYER CAPPING OF LOW-K DIELECTRIC FILMS - A method is provided for processing a substrate surface by delivering a first gas mixture comprising a first organosilicon compound, a first oxidizing gas, and one or more hydrocarbon compounds into a chamber at deposition conditions sufficient to deposit a first low dielectric constant film on the substrate surface. A second gas mixture having a second organosilicon compound and a second oxidizing gas is delivered into the chamber at deposition conditions sufficient to deposit a second low dielectric constant film on the first low dielectric constant film. The flow rate of the second oxidizing gas into the chamber is increased, and the flow rate of the second organosilicon compound into the chamber is decreased to deposit an oxide rich cap on the second low dielectric constant film. | 2010-01-28 |
20100022101 | METHOD FOR CHANGING PHYSICAL VAPOR DEPOSITION FILM FORM - A method for changing a physical vapor deposition film form comprises: providing at least one sample with an active area; delivering the sample to a physical vapor deposition machine with one adjustable angle of one collimator; changing the angle of the collimator in the physical vapor deposition machine; performing physical vapor deposition operation, forming a uniform thin film disposed on one active area of the sample. | 2010-01-28 |
20100022102 | LASER ANNEALING METHOD AND DEVICE - A laser annealing method for executing laser annealing by irradiating a semiconductor film formed on a surface of a substrate with a laser beam, the method including the steps of, generating a linearly polarized rectangular laser beam whose cross section perpendicular to an advancing direction is a rectangle with an electric field directed toward a long-side direction of the rectangle or an elliptically polarized rectangular laser beam having a major axis directed toward a long-side direction, causing the rectangular laser beam to be introduced to the surface of the substrate, and setting a wavelength of the rectangular laser beam to a length which is about a desired size of a crystal grain in a standing wave direction. | 2010-01-28 |
20100022103 | CONNECTOR AND TRANSMISSION WIRE - A connector includes a first contact portion, a second contact portion, a housing and a transmission wire. One of a plug and a receptacle is connected to the first contact portion. The second contact portion is connected to a printed wiring board. The housing holds the first and second contact portions. The transmission wire has one end to which the first contact portion is joined and the other end to which the second contact portion is joined. | 2010-01-28 |
20100022104 | ELECTRICAL CONNECTING APPARATUS - An electrical connecting apparatus comprises a housing having a first recess extending in a first direction in a plane parallel to a board having a conductive portion to be connected to an electrode of a device under test and opened downward and a plurality of slits spaced in the first direction and extending in a second direction intersecting the first direction in the plane, wherein each slit communicates at one end portion in its longitudinal direction with the first recess and is opened at least upward, a plurality of plate-shaped contacts each electrically connecting the conductive portion to the electrode, having on the tip end side of the contact a tip end thrust to the electrode and a curved external surface, and arranged in the housing in a state of extending inside the slit from within the first recess with the external surface being on the lower side, and a probe holder arranged in the first recess and abutting on a part opposite the external surface of the contact so as to contact the external surface of the contact with the conductive portion. Accordingly, scraps scraped away by the tip end of the contact are prevented from reaching the board via the slit. | 2010-01-28 |
20100022105 | Connector for Microelectronic Devices - One embodiment is a connector for making electrical connection to a bulbous terminal, the connector including: a metal tube with a cylindrical wall extending from a mating end, wherein: (a) two or more slots perforate the wall and extend from the mating end along the tube; (b) two or more apertures perforate the wall and are disposed in a circumferential array disposed a distance from the mating end; and (c) each of the two or more slots transects one of the two or more apertures to divide the mating end of the tube into resilient prongs. | 2010-01-28 |
20100022106 | Extension Cord Lock and In Line Tap - An electrical, circuit breaker protected, extension cord in-line tap, securement device for securing tandemly connected electrical extension cords. The securement device includes opposing proximal and distal open-ended hook members each having a hinged locking flap for receiving therein a looped end of the associated extension cord thereby preventing unintended separation of the extension cords. The hook members may comprise a back wall having a plurality of vertical ribs along at least a portion of the back wall. The vertical ribs may be configured to grippingly secure the extension cords. Embodiments of the in-line tap may also include a plurality of circuit breaker protected auxiliary electrical outlets on opposing sides for powering additional extension cords or electrical devices. | 2010-01-28 |
20100022107 | Electronic device with retractable connector - An electronic device with a retractable connector has a housing, an electronic assembly being mounted in the housing and a positioning assembly being mounted between the housing and the electronic assembly. The housing has at least one positioning detent being formed in an inner surface of the housing. The electronic assembly has a circuit board and a connector being mounted on the circuit board and through the connector hole of the housing. The positioning assembly is securely mounted on the circuit board and selectively engages in the positioning detent of the housing. Since positioning structures are formed on the housing and the circuit board, the volume of the electronic device is reduced. In addition, no additional holes are formed through the housing and an original design and an appearance of the housing are kept. | 2010-01-28 |
20100022108 | Apparatus For Plug-In and Plug-Out Protection - A telecommunications plug comprising: a plug body; plug latches mounted on the plug body, the plug latches being movable between a latched and unlatched state; a boot cap having arms extending therefrom, each arm including a camming surface engaging an outside surface of the plug latches, wherein moving the boot cap in a first direction drives the latches towards each other; a cap latch mounted to the boot cap, the cap latch having a distal end positioned between the latches preventing movement of the boot cap in the first direction; the boot cap including an opening for receiving a key to deflect the cap latch allowing movement of the boot cap in the first direction. | 2010-01-28 |
20100022109 | ELECTRICAL CONNECTION APPARATUS - Electrical connection apparatus is provided including engagement means to allow attachment of the apparatus to an electrical appliance or electrical socket in use and at least first and second electrical connection means which can communicate with each other in use to allow the flow of electrical charge therebetween. The apparatus further includes movement means arranged to allow relative movement of the at least first and/or second electrical connection means between a first position, wherein electrical charge can flow therebetween, and a second position, wherein the flow of electrical charge is prevented. The relative movement takes place over a pre-determined time period following actuation or on actuation of said movement means to provide a timing mechanism for the apparatus. | 2010-01-28 |
20100022110 | SYSTEM FOR PROTECTING THE ENGAGABLE ELEMENTS OF A CONNECTOR - A protection system for a connector that comprises two connector elements ( | 2010-01-28 |
20100022111 | 25KV LOADBREAK ELBOW AND BUSHING INCREASED FLASHOVER DISTANCE - A loadbreak connector formed by a power cable elbow and a bushing insert with increased flashover distance is disclosed. The power cable elbow includes a conductive member having an energized portion and a non-energized portion, a cable receiving end, a loadbreak bushing insert receiving end with an elbow cuff that extends beyond the energized portion. The bushing insert includes an insulative outer housing and an insulative interface sleeve. The insulative outer housing has an axial bore with a conductive socket, a first, second end mid-section, and a transition shoulder portion between the second end section and the mid-section. The insulative interface sleeve extends over the outer housing from the mid-section to the second end section. When the power cable elbow is installed on the second end section, the flashover distance from the top of the second end section to the bottom of the elbow cuff is increased. | 2010-01-28 |
20100022112 | ELECTRICAL CONNECTOR ORGANIZER - An electrical connector assembly includes a housing, a receptacle and a receptacle contact. The housing has an interior chamber between a cable end and an interface of the housing. The interface is configured to receive a mating end of a mating electrical connector. The receptacle contact is disposed within a slot of the receptacle and is configured to engage a corresponding contact in the mating electrical connector. The receptacle contact is pivotally mounted in the receptacle and configured to pivot about a pitch axis and along the slot of the receptacle to align with the corresponding contact in the mating electrical connector. Optionally, the receptacle is mounted so as to pivot in the interior chamber and is configured to pivot about a yaw axis within the interior chamber over a predetermined limited range of travel to align the receptacle contact with the corresponding contact in the mating electrical connector. | 2010-01-28 |
20100022113 | CONNECTOR FOR CONNECTION TO A MODULE BOARD - Provided is a connector for connection to a module board including an eject mechanism selectively ejecting a module from a module accommodating section. The eject mechanism includes a locking member that has a locking nib engageable with a recess of a case of the module. The locking member is rotatably supported by a sidewall section of a guide rail member, and thus can stay in an opening of the sidewall section. An eject button of the connector for connection to a module board has an operation section provided with a flange. The flange is pressed against the inner peripheral surface of a housing of an electronic device by a biasing force of coil springs all the time except for when the operation section is pushed in. | 2010-01-28 |
20100022114 | CARD EDGE CONNECTOR AND LATCH THEREOF - This invention relates to a card edge connector and a latch thereof. The connector is used to receive a printed circuit card and includes a housing having two opposite ends, a card slot disposed between two opposite ends. The housing has a first width. The latch as a latch body portion, pivotally mounted on two ends of the housing for ejecting the card, and at least one through hole and a second width. The latch further has a latch head portion, extending from the body portion for latching the card, having at least one through hole and a third width. The second and third widths are substantially the same, and are smaller than the first width of the housing for improving heat dissipation. | 2010-01-28 |
20100022115 | Blanking plug for telecommunications jack - The present invention provides an electrical blanking plug for a telecommunications socket or jack. The blanking plug having at least one electrical conductor positioned on the body of the plug, which conductor on insertion of the plug into a telecommunications jack or socket electrically connects one or more terminals on the jack to short circuit and/or ground one or more electrical telecommunication circuits terminated at the jack. | 2010-01-28 |
20100022116 | CABLE ASSEMBLY WITH LOCKING MEMBER - A cable assembly ( | 2010-01-28 |
20100022117 | Retainer For Printed Circuit Boards - A printed circuit board retaining device for use in securing a printed circuit board in an elongated slot of a rack provides an efficient design allowing for the utilization of an off-the-shelf screw in the device. A screw having a head located within a first end piece interconnects the first end piece, at least one elongated wedge, and a second end piece. A clutch assembly, also retained within the first end piece, is coupled to the screw by a tool configured to engage the screw head. The clutch assembly has a first and second clutch head. The second clutch head being attached to the opposite side of the tool configured to engage the screw head. | 2010-01-28 |
20100022118 | POWER CONNECTOR HAVING AN IMPORVED INTERNAL PRINTED CIRCUIT BOARD - A power connector ( | 2010-01-28 |
20100022119 | CONNECTOR ARTICLE FOR A CABLE, HOLDER FOR A CONNECTOR OF SUCH A CONNECTION ARTICLE, AND KIT FOR CONNECTING CABLES - A connection article is provided for a cable comprising at least one wire. The connection article comprises a holder, at least one connector arranged in the holder and having a first receiving opening for receiving a wire to be connected, and guiding means arranged in front of the first receiving opening of the at least one connector, the first receiving opening defining a cross section and the guiding means comprising at least one guiding passage extending through the guiding means and aligned with the first receiving opening of the at least one connector for guiding a wire into the first receiving opening of the connector. The at least one guiding passage comprises opposite distal and proximal ends, the proximal end facing towards and the distal end facing away from the first receiving opening of the at least one connector. The proximal end has a cross section not larger than the cross section of the first receiving opening of the at least one connector. The distal end has a cross section larger than the cross section of the proximal end. | 2010-01-28 |
20100022120 | COAXIAL CABLE CONNECTOR NUT ROTATION AID - An improved coaxial cable connector nut rotation aid that facilitates rotation of a coaxial cable connector nut found on the end of a coaxial cable. Various embodiments of the invention allow for the coaxial cable connector nut rotation aid to slide from a first end of a coaxial cable to a second end, non-fixedly engaging the threaded connector nut on either end so that a single instance of one aid may be utilized on both ends of the cable. As the aid is slidingly engaged on the cable, it cannot be removed and swallowed by a small child or pet. Other embodiments allow for a combined textured and nut aid that allows for rotation by using a tool or by manual rotation. | 2010-01-28 |
20100022121 | COAXIAL CABLE DEBRAIDING AND COAXIAL CABLE CONNECTOR SEATING TOOL - Coaxial cable debraiding and coaxial cable connector seating tool enables a person to rapidly debraid coaxial cable braided shielding from coaxial cable dielectric and fully seat coaxial cable connector onto stripped coaxial cable without directly contacting braiding or coaxial cable connector with person's fingers. Cavities in tool match diameter and maximum depths of coaxial cable conductor, dielectric and coaxial cable connector and/or coaxial cable connector rotation aid. Inserting stripped coaxial cable into the tool having cavities that match the coaxial cable dimensions and rotating the tool with respect to the cable, the braiding is thus parted from the dielectric in preparation for seating. By placing the coaxial cable connector in alignment with the axis of the tool and cable and pressing the tool along the axis of the cable, the coaxial cable connector is thus fully seated on the cable and is fully prepared for crimping. | 2010-01-28 |
20100022122 | CONNECTOR - An insulative housing | 2010-01-28 |
20100022123 | COAXIAL CONNECTOR HAVING IMPROVED CENTRAL PIN - A coaxial connector ( | 2010-01-28 |
20100022124 | COAXIAL CABLE CONNECTOR - A coaxial cable connector has a nut, a sleeve and a jacket. The nut has a stop ring formed on an inner surface of the nut. The sleeve is mounted in the nut and has a flange formed on the sleeve and abutting the stop ring of the nut. The jacket is mounted securely on the sleeve and has at least one crimp formed on an inner end of the jacket. When a coaxial cable is connected to the connector, the inner end of the jacket is compressed and the at least one crimp presses into the coaxial cable to prevent air entering and damaging the coaxial cable and proving a tight connection to the coaxial cable. | 2010-01-28 |
20100022125 | Hardline Coaxial Cable Connector - A hardline coaxial cable connector includes a body subassembly, a back nut subassembly and a deformable ferrule disposed within the back nut subassembly. The back nut subassembly is rotatable with respect to the body subassembly and a coaxial cable inserted therein. Axial advancement of the back nut subassembly toward the body subassembly causes the ferrule to deform radially inwardly. | 2010-01-28 |
20100022126 | Connector - A connector to be connected to a cable | 2010-01-28 |
20100022127 | ELECTRICAL CONNECTOR - The invention proposes a housing of an electrical connector including a contact holder and a front grid arranged for being mounted together, wherein:—the contact holder includes channels for receiving electrical contacts within, each channel being limited by resilient members stressable by an electrical contact whose position in the channel is not correct;—the front grid comprises a front panel with a plurality of transversal connecting windows for facing corresponding channels of the contact holder; characterized in that the housing includes members for locking the front grid to the contact holder by translating the front grid with respect to the contact holder according to a lateral direction. | 2010-01-28 |
20100022128 | RECEPTACLE AND PLUG CONNECTOR ASSEMBLY - A receptacle and plug connector assembly includes a receptacle having a housing with a plurality of terminals received therein and a plug mated with the receptacle and having an insulator with a plurality of contacts disposed therein. Each terminal has a base portion and two elastic arms extending from the base portion. Free ends of the two elastic arms respectively protrude towards each other to form projections. Each contact has a substantially U-shaped contacting portion received between the elastic arms and pressed by the projections of the elastic arms. Therefore, the terminals of the receptacle contact the contacts of the plug stably. | 2010-01-28 |
20100022129 | CONTACT MODULE FOR AN ELECTRICAL CONNECTOR HAVING PROPAGATION DELAY COMPENSATION - A contact module is provided for an electrical connector. The contact module includes a lead frame. The lead frame includes first and second differential pairs of terminals. Each of the terminals extends between a mating edge portion and a mounting edge portion. A first dielectric body surrounds at least a portion of the first differential pair of terminals. The first dielectric body includes a first dielectric constant. A second dielectric body surrounds at least a portion of the second differential pair of terminals. The second dielectric body includes a second dielectric constant that is different than the first dielectric constant of the first dielectric body. | 2010-01-28 |
20100022130 | ELECTRICAL CONNECTOR - An electrical connector includes a header connector and a socket connector configured to mate with the header connector. The header connector includes a plurality of signal pins and may include a plurality of shield blades. The socket connector includes a plurality of conductive paths, each conductive path being coupled to a signal contact, and may include a plurality of first shields. The plurality of signal pins and the plurality of conductive paths and signal contacts are configured to form a plurality of transmission lines. The plurality of shield blades or the plurality of first shields are configured to be electrically grounded and provide interrupted shielding of the plurality of transmission lines when the header connector and the socket connector are in a mated configuration. | 2010-01-28 |
20100022131 | REGISTERED JACK WITH ENHANCED EMI PROTECTION - An electrical connector has a shield for EMI shielding. The top of the shield has two rows of tabs; two flaps, one on either side of the shield; and a tab on the bottom. The flaps have mounting holes. When the connector is attached to a mounting panel, screws or rivets are mounted through the holes in the flaps and corresponding holes in the mounting panel to secure the connector. The bottom tab and the two rows of top tabs electrically connect the shield to the mounting panel to provide extra EMI protection to the connector. The flaps provide yet another connection to provide EMI protection. The two rows of tabs can be positioned and sized such that the rear row of tabs engages with a flange in the rear of the top of the mounting panel. The electrical connector is preferably an RJ connector. | 2010-01-28 |
20100022132 | Electrical connector having a connecting sheet for resisting electronic interference - An electrical connector includes an insulative housing ( | 2010-01-28 |