04th week of 2011 patent applcation highlights part 60 |
Patent application number | Title | Published |
20110022743 | USB PORT FOR EMPLOYING A PLURALITY OF SELECTABLE DATA TRANSMISSION PRIORITY RULES - A USB port transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one USB transmission from among multiple scheduled USB transmissions based on their types. A selector selects one of the arbiters to select the one USB transmission from among the multiple scheduled USB transmissions. A programmable storage element controls the selector to select the one arbiter. In one embodiment, at least a first arbiter prioritizes header/data packets higher than link commands, and at least a second arbiter prioritizes link commands higher than header/data packets. In one embodiment, at least one arbiter prioritizes flow control and power management link commands higher than header/data packets. In one embodiment, at least a first of the arbiters prioritizes USB LGO_Ux link commands higher than USB LAU/LXU link commands, and at least a second arbiter prioritizes USB LAU/LXU link commands higher than USB LGO_Ux link commands. | 2011-01-27 |
20110022744 | Storage Control Method and Related Storage Control Device for a Computer System - A storage control method for a computer system for automatically executing off line at a proper time includes a storage controller generating a command for accessing a storage device, receiving and transmitting the command through a port multiplier, and the port multiplier performing off line when a ready packet is not received from the storage device or the storage device is absent. | 2011-01-27 |
20110022745 | INTERFACING DEVICE AND METHOD, FOR EXAMPLE FOR SYSTEMS-ON-CHIP - An interface device, such as for a System-on-Chip (SoC) bus, transfers data from an input queue through an output to a target. The interface device includes a buffer network for buffering input data when the target is not available for receiving the data. A multiplexer switches between a first operating condition for directing to the target the data from the input queue, and a second operating condition for directing to the target the buffered data from the buffer network. A finite-state machine selectively switches the multiplexer between the first operating condition and the second operating condition based on an acknowledgement signal received from the target. This indicates the availability of the target for receiving the data. | 2011-01-27 |
20110022746 | METHOD OF DISPATCHING AND TRANSMITTING DATA STREAMS, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A method of dispatching and transmitting data stream, which is used for a memory storage apparatus having a non-volatile memory module and a smart card chip, is provided. The method includes configuring a plurality of logical block addresses, and a plurality of specific logical block addresses are used for storing a specific file. The method also includes receiving a response data unit from the smart card chip and storing the response data unit in a buffer memory. The method also includes, when a logical block address corresponding to a read command from a host system belongs to one of the specific logical block addresses and the buffer memory stores a response data unit, transmitting the response data unit stored in the buffer memory to the host system. Accordingly, the method can make the host system to correctly receive the response data unit from the smart card chip. | 2011-01-27 |
20110022747 | MODULAR COMPUTING SYSTEM - A computing system is provided that includes a plurality of interconnected components. The components include a processing subsystem, an input subsystem, an output subsystem, a storage subsystem, and a power subsystem. Subsets of the plurality of components may be rearranged and interconnected in various configurations to form different computing systems. | 2011-01-27 |
20110022748 | CONFIGURABLE HEALTH-CARE EQUIPMENT APPARATUS - An apparatus, system and method for providing health-care equipment in a plurality of customizable configurations. A configuration includes a selection and arrangement of health-care equipment modules that each provide specialized support for the provision of health care, including the measurement of physiological parameters. Various types of configurations include those adapted to be mounted upon a desk top or a wall surface, or adapted for wheel mounting or hand-carriable mobile configurations. | 2011-01-27 |
20110022749 | SYSTEM CONTROL SERVER, STORAGE SYSTEM, AND SETTING METHOD - An operation mode acquiring unit compares before-expansion connection device information and after-expansion connection device information that are acquired by a device information acquiring unit, recognizes expanded device information on an external storage device that is expanded in a storage system, and acquires an operation mode that is applied to the storage system after the external storage device is expanded from a correspondence storage unit by using the recognized expanded device information. A setting executing unit executes the setting for the storage system accompanied with the expansion of the external storage device on the basis of the after-expansion connection device information acquired by the device information acquiring unit and the operation mode acquired by the operation mode acquiring unit. | 2011-01-27 |
20110022750 | Interface for Bridging Out-Of-Band Information from a Downstream Communication Link to an Upstream Communication Link - A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes the OOB information into one or more symbols (e.g., control characters). A second interface is coupled to the encoder and a second communication link (e.g., a serial transport path). The second interface transmits the symbols on the second communication link. The device also includes mechanisms for preventing false presence detection of terminating devices. | 2011-01-27 |
20110022751 | METHODS AND APPARATUS FOR AN IMPROVED MOTOR CONTROL CENTER - Methods, apparatus, and systems are provided for operating a motor control center. The invention includes determining a hardware configuration of functional modules within a motor control center; downloading the hardware configuration to a programmable logic controller; configuring a program to run on the programmable logic controller based on the hardware configuration; and executing the program. Numerous additional aspects are disclosed. | 2011-01-27 |
20110022752 | METHOD FOR TRANSMITTING DATA IN A CYCLE-BASED COMMUNICATION SYSTEM - In a method for transmitting data from a transmitting user of a cycle-based communication system to a receiving user of the communication system, the data are transmitted via a communication medium in messages that repeat in communication cycles and that respectively include a plurality of data blocks. The receiving user identifies the end of the data blocks in the received messages and subsequently extracts the transmitted data from the identified data blocks. | 2011-01-27 |
20110022753 | SINGLE-WIRE BUS COMMUNICATION PROTOCOL - A method of communication over a single-wire bus between a transmitter device and at least one receiver device, wherein each data bit is transmitted in a frame successively including: a synchronization slot different from a reference voltage of the devices; a first idle slot in a state corresponding to the reference voltage of the circuit; a slot representing the data bit to be transmitted; a second idle slot identical to the first one; a slot intended to contain the state of an optional response bit; and an end slot identical to the idle slot. | 2011-01-27 |
20110022754 | BUS ENHANCED NETWORK ON CHIP - A system that includes multiple modules of an integrated circuit; a network on chip that is coupled to the multiple modules; a bus, coupled in parallel to the network on chip to the multiple modules; wherein a latency of the bus is lower and more predictable than an average latency of the network of chip. | 2011-01-27 |
20110022755 | COMMUNICATION DEVICE, COMMUNICATION SCHEME DETERMINATION METHOD, AND PROGRAM - Provided is a communication device including a first communication unit that is capable of sending a polling-signal in a specific polling cycle and receiving a response-signal sent from a counterpart device in response to the polling-signal, based on a first scheme, a second communication unit that is capable of sending a polling-signal in a longer polling cycle than the first communication unit and receiving a response-signal sent from the counterpart device in response to the polling-signal, based on a second scheme, and a scheme determination unit that waits for reception of the response-signal by the second or the first communication unit for a specific period of time longer than the polling cycle of the second communication unit with a time of the response-signal being received by the first or the second communication unit as a reference, and determines a scheme usable by the counterpart device based on the reception result. | 2011-01-27 |
20110022756 | Data Space Arbiter - A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data space arbiter is programmable in a non-default mode to raise a priority of any of the secondary bus masters to have a priority higher than the priority of the default bus master while maintaining the predetermined priority relationship to only those secondary bus masters for which the priority level also has been raised above the priority of the default bus master. | 2011-01-27 |
20110022757 | Method for Accessing Control Units Arranged in a Vehicle, Control Program and Communication Control Unit - For control unit access, a vehicle to be checked is identified using an identifier. Control and/or monitoring operations covered by the control unit access are selected. A communication link is set up over a selected vehicle communication interface. Communication devices covered by the selected vehicle communication interface are ascertained. Independent control and/or monitoring operations covered by the control unit access are ascertained, where these operations are associated with available communication means and are not dependent on a superordinate control and/or monitoring operation. A control and/or monitoring operation, which has the greatest number of subordinate dependent control and/or monitoring operations, is selected for execution. | 2011-01-27 |
20110022758 | METHOD AND SYSTEM FOR PROCESSING FRAMES IN STORAGE CONTROLLERS - Method and system for transferring data between a computing system and a storage device is provided. The system includes a storage controller including a frame snooper module that detects a TMR and generates a pause signal to a channel that stops the channel from sending any non-data frames to a buffer memory, wherein the channel continues to receive and process data frames while the channel is stopped from sending the command frames to the buffer memory; a counter for counting TMRs; and logic for generating an interrupt if a number of TMRs received exceeds a certain threshold value. The method includes detecting a TMR generating a command to stop a channel from receiving non-data frames while continuing to receive data frames from a Fibre Channel interface; and generating an interrupt to a processor after a certain number of TMRs are received. | 2011-01-27 |
20110022759 | MULTIPROCESSOR SYSTEM - The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt causes is notified. The interrupt request output by the interrupt controller is accepted by one of the processors. The processor accepting the interrupt request determines whether the interrupt cause that the processor must process has occurred, executes an interrupt processing when such interrupt cause has occurred, and notifies the generation of the interrupt request to another processor that processes another interrupt cause of the plurality of interrupt causes sharing the interrupt request when the relevant interrupt cause has not occurred. | 2011-01-27 |
20110022760 | SATISFYING A REQUEST FOR A PHYSICAL IMPORT/EXPORT SLOT WITH A SLOT THAT IS NOT A PHYSICAL IMPORT/EXPORT SLOT - A request for a physical import/export (I/E) slot is satisfied using a tape library slot that is not a physical I/E slot. According to one embodiment, the request for the physical I/E slot, that is associated with the tape library, is received. A different slot, which is not any of the physical I/E slots associated with the tape library, is used to satisfy the request. | 2011-01-27 |
20110022761 | System and Method to Stack an Open NAND Flash Interface Module over a Minicard - A system includes a minicard host connector and an open NAND flash interface host connector. The minicard host connector is configured to receive a minicard. The open NAND flash interface host connector is in physical communication with the minicard host connector and configured to receive an open NAND flash interface card. The open NAND flash interface host connector includes first and second retention arms extending from opposite ends of the open NAND flash interface host connector. The open NAND flash interface host connector is sufficiently wide for the minicard host connector to fit between the first and second retention arms. | 2011-01-27 |
20110022762 | PORTABLE AND MAGNETICALLY PROGRAMMABLE MEDICAL DEVICE SYSTEM - A medical device system includes a portable medical device and a docking unit on which the medical device can be removably mounted. The docking unit is configured to communicate with a controller of the medical device when the medical device is mounted on the docking unit to instruct the controller to execute a selected program. | 2011-01-27 |
20110022763 | PORTABLE AND LIGHT PROGRAMMABLE MEDICAL DEVICE SYSTEM - A medical device system includes a portable medical device and a docking unit on which the medical device can be removably mounted. The docking unit is configured to communicate with a controller of the medical device when the medical device is mounted on the docking unit to instruct the controller to execute a selected program. | 2011-01-27 |
20110022764 | AV RACK SYSTEM - A function for enhancing the operability of a user by strengthening the cooperation of a TV and an external apparatus furthermore by communication is attracting attention. Although various technologies are provided, it is not possible to acquire information such as the state or the type of an apparatus itself by simply connecting the apparatus and to control an AV rack itself. Furthermore, the profile of an electronic apparatus being inserted into the rack and the location of the terminal are limited. The AV rack system of this invention is characterized in that a physical address is allotted to a terminal mounted on an AV rack, and the AV rack is controlled in association with the terminal of a connected electronic apparatus. | 2011-01-27 |
20110022765 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR MAINTAINING A DIRECT CONNECTION BETWEEN AN INITIATOR AND A DRIVE - A system, method, and computer program product are provided for maintaining a direct connection between an initiator and a drive. In operation, a connection is established between an initiator and a drive. Additionally, the connection is determined to be a direct connection between the initiator and the drive. Further, the established direct connection is maintained between the initiator and the drive, such that the established direct connection remains open for information transfer. | 2011-01-27 |
20110022766 | Circuit Arrangement For A Motor Vehicle Data Bus - Transmission and/or reception circuit arrangement for the physical implementation of a motor vehicle data bus system and use thereof, wherein the circuit has a plurality of configurable modes of operation which are a different physical implementation of one or more logic states and also comprises electronic bit generation and/or bit reception circuit elements which are used in each mode of operation, wherein changeover and/or structure elements are present which can be used to change over the circuit arrangement between the modes of operation and/or to operate said circuit arrangement in different modes of operation. | 2011-01-27 |
20110022767 | DMA CONTROLLER WITH INTERRUPT CONTROL PROCESSOR - Provided is a direct memory access (DMA) controller having an interrupt control processor that can process DMA transmission-related interrupts according to a control program modifiable by a user. The DMA controller includes the interrupt control processor that can process a DMA transmission-related interrupt and a DMA request interrupt transmitted from peripheral devices and control the DMA channel through the control program that can be modified by the user, so that DMA channel control and relevant interrupt processing loads caused by a plurality of DMA data transmissions are reduced, and the flexibility of DMA channel control and interrupt processing in control of the DMA controller is provided to the user. | 2011-01-27 |
20110022768 | METHOD AND APPARATUS FOR ENHANCING UNIVERSAL SERIAL BUS APPLICATIONS - A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. | 2011-01-27 |
20110022769 | Translation USB Intermediate Device and Data Rate Apportionment USB Intermediate Device - One aspect of the technology is an apparatus with a USB intermediate device such as a USB hub or a USB composite device. The USB intermediate device includes control circuitry that performs translation between USB 2 communications of the multiple downstream USB 2 ports and USB 3 SuperSpeed communications of the upstream USB 3 port. Another USB intermediate device includes control circuitry that modifies apportionment of the USB 3 maximum data rate among the multiple downstream USB 2 ports, such that the multiple downstream USB 2 ports communicate at a collective data rate exceeding a USB 2 maximum data rate of USB High Speed. Another USB intermediate device includes control circuitry that performs translation and modifies apportionment. Other aspects are a system with a host computer, methods, and computer readable media. | 2011-01-27 |
20110022770 | SYSTEMS AND METHODS FOR PROVIDING A DYNAMICALLY MODULAR PROCESSING UNIT - Systems and methods for providing a modular processing unit. A modular processing unit is provided as a platform that is lightweight, compact, and is configured to be selectively used alone or oriented with one or more additional processing units in an enterprise. In some implementations, a modular processing unit includes a non-peripheral based encasement, a cooling process (e.g., a thermodynamic convection cooling process, a forced air cooling process, and/or a liquid cooling process), an optimized circuit board configuration, optimized processing and memory ratios, and a dynamic back plane that provides increased flexibility and support to peripherals and applications. The modular processing unit is customizable and may be employed in association with all types of computer enterprises. The platform allows for a plethora of modifications that may be made with minimal impact to the modular unit, thereby enhancing the usefulness of the platform across all type of application. | 2011-01-27 |
20110022771 | SYSTEM AND METHOD FOR DISPLAYING ALARM NOTIFICATIONS ON AN ON-SCREEN DISPLAY - A Keyboard, Video, Mouse (KVM) switch that includes one or more input ports to receive events, notifications and/or alarms generated by an external device. The KVM switch receives the events, notification and/or alarms in the form of an external signal. The KVM switch processes the external signals and compares the received external signal to one or more reference signals to identify an event that corresponds to the received external signal. The KVM switch then generates an announcement for display on one or more displays associated at least one user station coupled to the KVM switch. | 2011-01-27 |
20110022772 | CONTROL MODULE WITH CONNECTION DEVICES FOR CONNECTION TO CONNECTION TERMINALS OF A LOAD FEEDER AND LOAD FEEDER - A control module with connection devices for connection to connection terminals of a load feeder is disclosed, wherein the load feeder with the control module is connected to a bus system. In at least one embodiment, the control module includes a device interface for at least one connection, interface being independent of the bus system, with a shut-off element able to be connected to the at least one connection device and with the load feeder able to be shut off by way of the shut-off element independently of the bus system. At least one embodiment of the present invention further relates to a load feeder for turning a load on and off and/or for monitoring thereof, including first connection devices for connecting the load feeder to a bus system, second connection devices for connecting the load and a control module, wherein the control module is plugged into connection terminals of the load feeder for connecting to the load feeder and wherein the control module includes a device interface for at least one connection device, the interface being independent of the bus system, with a shut-off element able to be connected to the at least one connection device and with the load feeder able to be shut off by way of the shut-off element independently of the bus system. | 2011-01-27 |
20110022773 | Fine Grained Cache Allocation - A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag. | 2011-01-27 |
20110022774 | CACHE MEMORY CONTROL METHOD, AND INFORMATION STORAGE DEVICE COMPRISING CACHE MEMORY - According to a cache memory control method of an embodiment, a data write position in a segment of a cache memory is changed to an address to which a lower bit of a logical block address of write data is added as an offset. Then, even if writing is completed within the segment of the cache memory, the remaining regions of the segment is not wasted. | 2011-01-27 |
20110022775 | ASSIGNING A PHYSICAL ADDRESS TO A DATA STORAGE DEVICE - A method of assigning a physical address to a tape-based data storage device is provided. The method includes receiving a first initialization signal from a system controller at an input port associated with a first tape-based data storage device and prohibiting communication at an output port associated with the first tape-based data storage device. The method further includes providing a first confirmation signal to the system controller in response to receiving the first initialization signal and receiving an instruction from the system controller to enable communication at the output port associated with the first tape-based data storage device in response to the first confirmation signal. The method also includes determining a physical address associated with said first tape-based data storage device based on the instruction from the system controller, the physical address enabling communication at the output port of the first tape-based storage device. | 2011-01-27 |
20110022776 | DATA RELIABILITY IN STORAGE ARCHITECTURES - Among other subject matter, storage architectures are provided that store data reliably in connection with a system. The storage architecture ( | 2011-01-27 |
20110022777 | SYSTEM AND METHOD FOR DIRECT MEMORY ACCESS IN A FLASH STORAGE - A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol. | 2011-01-27 |
20110022778 | Garbage Collection for Solid State Disks - Described embodiments provide a method of recovering storage space on a solid state disk (SSD). An index and valid page count are determined for each block of a segment of an SSD. If the valid page count of at least one block in the segment is zero, a quick clean is performed. A quick clean deallocates blocks having zero valid pages and places them in a queue for erasure. Otherwise, a deep clean is performed. A deep clean determines a compaction ratio, N-M, wherein N is a number of partially valid blocks and M is a number of free blocks required to compact the valid data from the N partially valid blocks into M entirely valid blocks. At least one data structure of the SSD is modified to refer to the M entirely valid blocks, and the N partially valid blocks are placed in the queue for erasure. | 2011-01-27 |
20110022779 | Skip Operations for Solid State Disks - Described embodiments provide skip operations for transferring data to or from a plurality of non-contiguous sectors of a solid-state memory. A host layer module sends data to, and receives commands from, a communication link. Received commands are one of read requests or write requests, with commands including i) a starting sector address, ii) a skip mask indicating the span of all sector addresses in the request and the sectors to be transferred, iii) a total number of sectors to be transferred; and, for write requests, iv) the data to be written to the sectors. A buffer stores data for transfer to or from the solid-state memory. A buffer layer module i) manages the buffer, ii) segments the span of the request into a plurality of chunks, and iii) determines, based on the skip mask, a number of chunks to be transferred to or from the solid-state memory. | 2011-01-27 |
20110022780 | RESTORE INDEX PAGE - Techniques for restoring index pages stored in non-volatile memory are disclosed where the index pages map logical sectors into physical pages. Additional data structures in volatile and non-volatile memory can be used by the techniques for restoring index pages. In some implementations, a lookup table associated with data blocks in non-volatile memory can be used to provide information regarding the mapping of logical sectors into physical pages. In some implementations, a lookup table associated with data blocks and a range of logical sectors and/or index pages can be used. | 2011-01-27 |
20110022781 | CONTROLLER FOR OPTIMIZING THROUGHPUT OF READ OPERATIONS - A controller, techniques, systems, and devices for optimizing throughput of read operations in flash memory are disclosed. Various optimizations of throughput for read operations can be performed using a controller. In some implementations, read operations for a multi-die flash memory device or system can be optimized to perform a read request with a highest priority (e.g., an earliest received read request) as soon as the read request is ready. In some implementations, the controller can enable optimized reading from multiple flash memory dies by monitoring a read/busy state for each die and switching between dies when a higher priority read operation is ready to begin. | 2011-01-27 |
20110022782 | FLASH STORAGE WITH ARRAY OF ATTACHED DEVICES - A flash storage system includes a flash storage controller coupled to storage modules of a flash storage array via universal serial buses. Each storage module includes at least one flash memory device. The flash storage controller receives a programming command of a communication protocol and generates universal serial bus commands based on the programming command. The flash storage controller issues the universal serial bus commands to storage modules in the flash storage array via the universal serial buses. The storage modules process the universal serial bus commands to access data in the flash storage devices of the storage modules. | 2011-01-27 |
20110022783 | FLASH STORAGE WITH INCREASED THROUGHPUT - A flash storage system includes a flash storage controller coupled to storage modules of a flash storage array via universal serial buses. Each storage module includes at least one flash memory device. The flash storage controller receives a programming command of a communication protocol and generates universal serial bus commands based on the programming command. The flash storage controller issues the universal serial bus commands to storage modules in the flash storage array via the universal serial buses. The storage modules process the universal serial bus commands to access data in the flash storage devices of the storage modules. | 2011-01-27 |
20110022784 | MEMORY SYSTEM - A memory system according to an embodiment of the present invention comprises: a memory amount required for management table creation is reduced by adopting a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing and a controller that can drive the parallel operation elements in parallel and has a number-of-times-of-erasing managing unit that manages the number of times of erasing in logical block units associated with a plurality of physical blocks driven in parallel. | 2011-01-27 |
20110022785 | METHOD FOR PROGRAMMING A MEMORY-PROGRAMMABLE CONTROLLER WITH RESISTANT STORAGE OF DATA IN MEMORY - The invention relates to a method for programming and/or diagnosis of a memory-programmable controller, having at least one memory-programmable function component. For programming, a predetermined programming system is used. In the context of this programming system variables are predetermined, and information exchange sequences are used for the programming. Results of the programming are output during at least one programming mode via an output device, and input information is at least in part stored permanently in memory. | 2011-01-27 |
20110022786 | FLASH MEMORY STORAGE APPARATUS, FLASH MEMORY CONTROLLER, AND SWITCHING METHOD THEREOF - A flash memory storage apparatus including a multi level cell (MLC) NAND flash memory, a flash memory controller, and a host transmission bus is provided. The MLC NAND flash memory includes a plurality of blocks for storing data, wherein each of the blocks has an upper page and a lower page, and the writing speed of the lower page is faster than that of the upper page. The flash memory controller is electrically connected to the MLC NAND flash memory and is used for executing storage mode switching steps. The host transmission bus is electrically connected to the flash memory controller and is used for communicating with a host. The flash memory storage apparatus provided by the present invention can provide multiple storage modes in order to store different data. | 2011-01-27 |
20110022787 | DATA WRITING METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER USING THE SAME - A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area. | 2011-01-27 |
20110022788 | INTEGRATING DATA FROM SYMMETRIC AND ASYMMETRIC MEMORY - Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component. | 2011-01-27 |
20110022789 | MEMORY DEVICE, HOST DEVICE, MEMORY SYSTEM, MEMORY DEVICE CONTROL METHOD, HOST DEVICE CONTROL METHOD AND MEMORY SYSTEM CONTROL METHOD - A memory card | 2011-01-27 |
20110022790 | SYSTEMS AND METHODS FOR PROVIDING NONLINEAR JOURNALING - In one embodiment, systems and methods are provided for nonlinear journaling. In one embodiment, groups of data designated for storage in a data storage unit are journaled into persistent storage. In one embodiment, the journal data is recorded nonlinearly. In one embodiment, a linked data structure records data and data descriptors in persistent storage. | 2011-01-27 |
20110022791 | High speed memory systems and methods for designing hierarchical memory systems - A system and method for designing and constructing hierarchical memory systems is disclosed. A plurality of different algorithmic memory blocks are disclosed. Each algorithmic memory block includes a memory controller that implements a specific storage algorithm and a set of lower level memory components. Each of those lower level memory components may be constructed with another algorithmic memory block or with a fundamental memory block. By organizing algorithmic memory blocks in various different hierarchical organizations, may different complex memory systems that provide new features may be created. | 2011-01-27 |
20110022792 | SOLID STATE MEMORY DRIVE AND METHOD - A solid state memory drive includes a first interface for receiving solid state memory cartridges; and a second interface for communicatively coupling the solid state memory drive unit with a host system through a drive bay configured to house a cassette tape drive. A host system then includes at least one drive bay configured to receive either the solid state memory drive or a tape cassette drive. A method includes removing a magnetic tape cassette drive from the drive bay; and inserting a solid state memory cartridge drive into the drive bay so as to communicatively interface the solid state memory cartridge drive and the host system. | 2011-01-27 |
20110022793 | Systems And Methods For Accessing Hard Disk Drives - The present disclosure generally pertains to systems and methods for accessing hard disk drives. In one exemplary embodiment, a computer system comprises a hard disk drive (HDD), an operating system, and a translation element. The operating system is configured to transmit an HDD access command, which has a sector count indicating a first number of hard drive sectors to be accessed in response to the HDD access command. The translation element is configured to receive the HDD access command and to translate the HDD access command into a translated access command having a new sector count indicating a second number of hard drive sectors to be accessed in response to the translated access command. The second number is different than the first number, and the translation element is configured to transmit the translated access command to the hard disk drive. | 2011-01-27 |
20110022794 | DISTRIBUTED CACHE SYSTEM IN A DRIVE ARRAY - An apparatus comprising a drive array, a first cache circuit, a plurality of second cache circuits and a controller. The drive array may comprise a plurality of disk drives. The plurality of second cache circuits may each be connected to a respective one of the disk drives. The controller may be configured to (i) control read and write operations of the disk drives, (ii) read and write information from the disk drives to the first cache, (iii) read and write information to the second cache circuits, and (iv) control reading and writing of information directly from one of the disk drives to one of the second cache circuits. | 2011-01-27 |
20110022795 | MANAGEMENT METHOD FOR VIRTUALIZED STORAGE VIEW - Method and system for providing a topology view for a storage system. Storage system includes a storage device, a management server and host devices in communication together. The host devices are used by users. The management server is in control of an administrator. The storage device is divided into logical partitions that are assigned to users. An icon is assigned to each user, each storage unit and to each virtual storage device. The topology view displays the associations between users and physical data storage units or virtual storage devices by drawing a linkage between each user icon and icons for the associated physical or virtual storage devices on a user interface of the management server for viewing by the administrator. Consolidated storage is shown to the administrator as a single element while partitioned storage is shown as multiple elements. | 2011-01-27 |
20110022796 | DISK ARRAY APPARATUS AND METHOD FOR CONTROLLNG THE SAME - An apparatus includes a controller and a plurality of disk drives. The controller has a communication control unit for accepting a data input/output request, a disk controller unit for controlling a disk drive, and a cache memory for temporarily storing data transferred between the communication control unit and the disk controller unit. The plurality of disk drives has different communication interfaces and connected to the disk controller unit to communicate with the disk controller unit. | 2011-01-27 |
20110022797 | STORING OF FREQUENTLY MODIFIED DATA IN AN IC CARD - There is provided a system and method for storing data in an IC card, which is connectable to a host device. The IC card may include a microcontroller comprising a memory for storing data elements modified by a data processing program, when the IC card is operated. The memory may include at least one non-volatile memory unit and at least one volatile memory unit. An exemplary method may comprise determining at least one first data element and modifying the at least one first data element more frequently than at least one second data elements. The exemplary method may additionally comprise storing and modifying the at least one first data element in the volatile memory unit in response to the rate of modifications of the at least one first data element. | 2011-01-27 |
20110022798 | METHOD AND SYSTEM FOR CACHING TERMINOLOGY DATA - A method for caching terminology data, including steps of: receiving a terminology request; determining that the terminology request is related to at least one uncached terminology concept; retrieving a complete concept set of the terminology concept as a cache unit, wherein the complete concept set includes the terminology concept, all other terminology concepts which are directly correlated or indirectly correlated through a non-transitive relationship to the terminology concept, properties of each terminology concept, and the non-transitive relationship between each terminology concept; retrieving transitive relationship information for the complete concept set, the transitive relationship information at least including identifiers of terminology concepts which are correlated through the transitive relationship to each terminology concept in the complete concept set; and caching the cache unit and the transitive relationship information of the cache unit. A corresponding device caches terminology data. | 2011-01-27 |
20110022799 | METHOD TO SPEED UP ACCESS TO AN EXTERNAL STORAGE DEVICE AND AN EXTERNAL STORAGE SYSTEM - A method to speed up access to an external storage device for accessing to the external storage device comprises the steps of:
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20110022800 | SYSTEM AND A METHOD FOR SELECTING A CACHE WAY - A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way. | 2011-01-27 |
20110022801 | APPARATUS, SYSTEM, AND METHOD FOR REDUNDANT WRITE CACHING - An apparatus, system, and method are disclosed for redundant write caching. The apparatus, system, and method are provided with a plurality of modules including a write request module, a first cache write module, a second cache write module, and a trim module. The write request module detects a write request to store data on a storage device. The first cache write module writes data of the write request to a first cache. The second cache write module writes the data to a second cache. The trim module trims the data from one of the first cache and the second cache in response to an indicator that the storage device stores the data. The data remains available in the other of the first cache and the second cache to service read requests. | 2011-01-27 |
20110022802 | Controlling data accesses to hierarchical data stores to retain access order - Data storage circuitry for controlling access to data stored in a memory is disclosed. The data storage circuitry comprises: a data store for storing a subset of the data stored in the memory; access circuitry for receiving access requests and for outputting the requested data, at least some of the received access requests being ordered access requests requiring the accessed data to be output in a same order as the access requests are received in; control circuitry for controlling access to the data; and retrieval circuitry for retrieving the data from the memory; wherein the control circuitry is responsive to an access request received from the access circuitry to access the data store and in response to detecting a miss in the data store when the requested data is not stored in the data store to transmit the access request to the retrieval circuitry; the retrieval circuitry being configured to retrieve requested data from the memory in response to the access request and to store the data in the data store and being responsive to no asserted output inhibit signal associated with the data access request to transmit the retrieved data to the access circuitry for output and being responsive to an asserted output inhibit signal associated with the data access request not to transmit the retrieved data to the access circuitry; the data storage circuitry further comprising detection circuitry for detecting an earlier ordered access request that misses in the data store and a later ordered access request that hits while the earlier ordered access request is pending, the data storage circuitry being configured to halt the later ordered access request and in response to receipt of a subsequent ordered access request while the earlier ordered request is still pending to assert an output inhibit signal associated with the subsequent ordered access request and in response to detection of completion of the earlier ordered access request to deassert the output inhibit signal. | 2011-01-27 |
20110022803 | Two Partition Accelerator and Application of Tiered Flash to Cache Hierarchy in Partition Acceleration - An approach is provided to identify a disabled processing core and an active processing core from a set of processing cores included in a processing node. Each of the processing cores is assigned a cache memory. The approach extends a memory map of the cache memory assigned to the active processing core to include the cache memory assigned to the disabled processing core. A first amount of data that is used by a first process is stored by the active processing core to the cache memory assigned to the active processing core. A second amount of data is stored by the active processing core to the cache memory assigned to the inactive processing core using the extended memory map. | 2011-01-27 |
20110022804 | METHOD AND SYSTEM FOR IMPROVING AVAILABILITY OF NETWORK FILE SYSTEM SERVICE - A method and system for improving availability of a network file system service are disclosed. In one embodiment. a method of a client device for improving an availability of a network file system service in a network of the client device and a file server includes receiving a user request. The method also includes selectively caching data associated with the user request and serviced by the file server to a storage device associated with the client device via a heuristics process which is based on one or more measurable parameters of the network. The method further includes forwarding the data from the file server or the storage device to service the user request. | 2011-01-27 |
20110022805 | Wait-Free Parallel Data Cache - A system and method for managing a data cache in a central processing unit (CPU) of a database system. A method executed by a system includes the processing steps of adding an ID of a page p into a page holder queue of the data cache, executing a memory barrier store-load operation on the CPU, and looking-up page p in the data cache based on the ID of the page p in the page holder queue. The method further includes the steps of, if page p is found, accessing the page p from the data cache, and adding the ID of the page p into a least-recently-used queue. | 2011-01-27 |
20110022806 | METHOD AND SYSTEM OF NUMERICAL ANALYSIS FOR CONTINUOUS DATA - A method of numerical analysis for continuous data includes: providing a temporary storage block; fetching a plurality of data units sequentially from a continuous data to store in the temporary storage block; conducting an analysis step in which the first of the data units is analyzed based on all the data units stored in the temporary storage block and the analysis result is recorded; determining whether the end of the continuous data has been reached, if so, the method terminates; and if not, removing the first of the data units, fetching the next data unit from the continuous data and returning to the analysis step. The above-mentioned method can be implemented in hardware with less temporary storage space and read/write overheads. A system of numerical analysis for continuous data is also disclosed. | 2011-01-27 |
20110022807 | WRITE ONCE RECORDING DEVICE - An access device | 2011-01-27 |
20110022808 | OUTPUT DRIVER, MEMORY HAVING OUTPUT DRIVER, MEMORY CONTROLLER, AND MEMORY SYSTEM - An output driver has a first driver connected between a first power source and an output terminal and a second driver connected between a second power source and the output terminal. One of the first driver and the second driver has two driving parts connected in parallel to each other. The two driving parts and the other of the first driver and the second driver are operated by independent input signals. | 2011-01-27 |
20110022809 | CONSOLIDATED ELECTRONIC CONTROL UNIT AND RELAY PROGRAM IMPLEMENTED IN THE SAME - In a consolidated electronic control unit (ECU) integrally produced by a plurality of conventional ECUs, an inventive relay program is adapted to enable a CPU of the consolidated ECU to rewrite internal and external parameters into the external and internal parameters, respectively, with reference to a correspondence list previously set between the internal parameter and the external parameter. The internal parameter is a parameter that is to be used by a specific program implemented in the consolidated ECU. The external parameter is a parameter that corresponds to the internal parameter and that is to be used by a non specific program implemented in the consolidated ECU. | 2011-01-27 |
20110022810 | DATA STORING METHOD AND DATA STORING SYSTEM - A non-transitory computer-readable medium storing an data storing program executed by an archive device including a first storage unit for storing data and a second storage unit for storing hash value determined from the data, the program causing the archive device to execute a process includes receiving hash value determined from data to be stored from an external device which requests storage of the data, comparing the received hash value with the hash value stored in the second storage unit, and transmitting request information for transmitting the data corresponding to the received hash value to the external device which transmits the hash value when the received hash value has not been stored in the second storage unit. | 2011-01-27 |
20110022811 | INFORMATION BACKUP/RESTORATION PROCESSING APPARATUS AND INFORMATION BACKUP/RESTORATION PROCESSING SYSTEM - To reduce the size of backup data, increase the backup speed, and solve a problem that the amount of unnecessary writing could undesirably increase in a restoration process, which would otherwise require physical disks with a capacity greater than the size of a virtual volume. On a backup server having mounted thereon a virtual volume that is the target to be backed up and restored, read/write access to only the blocks of data areas is performed by a device driver that filters I/O access to a device from a file system on the basis of the data mapping information of the virtual volume, whereby read/write access to unnecessary portions is avoided. Thus, it is possible to reduce the size of backup data, increase the backup speed, and prevent an increase in the amount of unnecessary writing to the virtual volume in a restoration process. | 2011-01-27 |
20110022812 | SYSTEMS AND METHODS FOR ESTABLISHING A CLOUD BRIDGE BETWEEN VIRTUAL STORAGE RESOURCES - Methods and systems for establishing a cloud bridge between two virtual storage resources and for transmitting data from one first virtual storage resource to the other virtual storage resource. The system can include a first virtual storage resource or cloud, and a storage delivery management service that executes on a computer and within the first virtual storage resource. The storage delivery management service can receive user credentials of a user that identify a storage adapter. Upon receiving the user credentials, the storage delivery management service can invoke the storage adapter which executes an interface that identifies a second virtual storage resource and includes an interface translation file. The storage delivery management service accesses the second virtual storage resource and establishes a cloud bridge with the second virtual storage resource using information obtained from the second virtual storage resource and information translated by the storage adapter using the interface translation file. | 2011-01-27 |
20110022813 | DATA STORAGE SYSTEM AND DATA STORAGE PROGRAM - Atomic data are stored in blocks on a hard disk. The blocks are grouped into a committed block aggregate P | 2011-01-27 |
20110022814 | METHODS AND SYSTEM OF POOLING STORAGE DEVICES - A system and method are provided for pooling storage devices in a virtual library for performing a storage operation. A storage management device determines a storage characteristic of a plurality of storage devices with respect to performing a storage operation. Based on a storage characteristic relating to performing the storage operation, the storage management device associates at least two storage devices in a virtual library. The storage management device may continuously monitor the virtual library and detect a change in storage characteristics of the storage devices. When changes in storage characteristics are detected, the storage management device may change associations of the storage device in the virtual library. | 2011-01-27 |
20110022815 | STORAGE ALLOCATION - Techniques for storage allocation of a data record are provided. The techniques include attempting to identify a first location for storing a data record, wherein the data record comprises one or more data record attributes, if the first location is identified, selecting the first location for storing the data record, and if the first location is not identified, identifying a second location for storing the data record using a cost penalty function and selecting the second location for storing the data record based on the cost penalty function. | 2011-01-27 |
20110022816 | REDUNDANT, MULTI-DIMENSIONAL DATA PARTITIONING: METHODS, PROGRAM PRODUCT AND SYSTEM - Horizontal partitioning can handle a transaction by accessing a single node only if the transaction is restricted along the single partitioned dimension. Composite partitioning allows for partitioning along more than one dimension, but can only handle a transaction by accessing a single node if the transaction is limited along all partitioned dimensions. A partitioning method partitions a tuple space along more than one dimension and, by storing tuples redundantly, allows transactions restricted along one or more of the partitioned dimensions to be handled by accessing a single node. Other embodiments include a computer program product and a system for partitioning a tuple space. | 2011-01-27 |
20110022817 | Mapping Processing Logic Having Data-Parallel Threads Across Processors - A method for executing a plurality of data-parallel threads of a processing logic on a processor core includes grouping the plurality of data-parallel threads into one or more workgroups, associating a first workgroup from the one or more workgroups with an operating system thread on the processor core, and configuring threads from the first workgroup as user-level threads within the operating system thread. In an example, a method enables the execution of GPU-kernels that has been previously configured for a GPU, to execute on a CPU such as a multi-core CPU. The mapping of the numerous data-parallel threads to the CPU is done in such a manner as to reduce the number of costly operating system threads instantiated on the CPU, and to enable efficient debugging. | 2011-01-27 |
20110022818 | IOMMU USING TWO-LEVEL ADDRESS TRANSLATION FOR I/O AND COMPUTATION OFFLOAD DEVICES ON A PERIPHERAL INTERCONNECT - An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations. | 2011-01-27 |
20110022819 | INDEX CACHE TREE - Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the location of the first lookup table in non-volatile memory. An index cache tree in volatile memory holds the physical addresses of the most recently written or accessed logical sectors in a compressed format. | 2011-01-27 |
20110022820 | SYSTEMS, DEVICES, AND METHODS FOR ANALOG PROCESSING - A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other. | 2011-01-27 |
20110022821 | System and Methods to Improve Efficiency of VLIW Processors - Exemplary embodiments provide microprocessors and methods to implement instruction packing techniques in a multiple-issue microprocessor. Exemplary instruction packing techniques implement instruction grouping vertically along packed groups of consecutive instructions, and horizontally along instruction slots of a multiple-issue microprocessor. In an exemplary embodiment, an instruction packing technique is implemented in a very long instruction word (VLIW) architecture designed to take advantage of instruction level parallelism (ILP). | 2011-01-27 |
20110022822 | Motion Controller Utilizing a Plurality of Processors - Controlling a motion system using a plurality of processors. First input data may be received which corresponds to a first portion of the motion system. Second input data may be received which corresponds to a second portion of the motion system. Execution of a first function of a plurality of sequential functions may be assigned to a first processor to determine output for the first portion based on the first input data. Execution of the first function may be assigned to a second processor to determine output for the second portion based on the second input data. The first processor executing the first function and the second processor executing the first function may be performed in parallel. The output for the first portion of the motion system may be provided to the first portion. The output for the second portion of the motion system may be provided to the second portion. | 2011-01-27 |
20110022823 | INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD THEREOF - An information processing system includes an execution unit and a decoder. The execution unit includes a plurality of arithmetic units each having a first operation circuit that performs a first operation on a first input value and a second input value, a second operation circuit that performs a second operation on the first input value and the second input value, and a selector that selects and outputs either a first output value output from the first operation circuit or a second output value output from the second operation circuit based on a selection signal. The decoder decodes an operation instruction and determines each value of the selection signal of each arithmetic unit. The decoder determines the value of the selection signal corresponding to the operation instruction with respect to each program. | 2011-01-27 |
20110022824 | Address Generation Unit with Pseudo Sum to Accelerate Load/Store Operations - In an embodiment, an address generation unit (AGU) is configured to generate a pseudo sum from an index portion of two or more operands. The pseudo sum may equal the index if the carry-in of the actual sum to the least significant bit of the index is a selected value (e.g. zero). The AGU may also include circuitry coupled to receive the operands and to generate the actual carry-in to the least significant bit of the index. The AGU may transmit the pseudo sum and the carry-in to a decode block for a memory array. The decode block may decode the pseudo sum into one or more one-hot vectors. The one-hot vectors may be input to muxes, and the one-hot vectors rotated by one position may be the other input. The actual carry-in may be the selection control of the mux. | 2011-01-27 |
20110022825 | CREATING AND MANAGING LINKS TO DEDUPLICATION INFORMATION - In a method of linking to information in a deduplication data sequence, a branching point is identified. The branching point is a place where a branch data sequence diverges from a parent data sequence that has been previously stored in a data deduplication process. A signature value associated with a subsequence of the information represented in the branch data sequence is determined. A branch location where the information of the branch data sequence begins is identified. Link information is stored in association with the branching point. The link information is stored in a computer memory. The link information comprises a link to the branch location and also comprises a portion of the signature value. | 2011-01-27 |
20110022826 | POWER MANAGEMENT APPARATUS AND METHODS - Apparatus and method for power management and especially to power management integrated circuits (PMICs). In one aspect, the invention relates to a PMIC having an internal non-volatile memory (NVM) for storing boot settings for the PMIC. The PMIC also has control circuitry for detecting whether a source of boot settings is available, such as an NVM external to the PMIC, and, if so, using any settings stored in the external source in preference to the relevant settings stored in the internal NVM. The external settings can thus override any internal settings, which is useful for fault diagnosis and/or development. In one aspect the PMIC may have programming circuitry for automatically programming boot settings from an external source into the internal NVM. | 2011-01-27 |
20110022827 | MULTIPLE INTERFACE SUPPORT - Aspects describe multiple interface support that provides dynamic switching between new and old interface revisions. A first interface application is selected from a set of alternative interface applications for an industrial automation system. Support for each interface application included in the set of alternative interface applications is provided. A second interface application is downloaded and associated with the first interface application. The second interface application is enabled during runtime. If needed, the second interface application can be selectively disabled and an operation resumed with the first interface application. | 2011-01-27 |
20110022828 | NON-DISRUPTIVE METHODS FOR UPDATING A CONTROLLER OF A STORAGE SYSTEM - A non-disruptive method for updating firmware in a first controller | 2011-01-27 |
20110022829 | FLASH STORAGE SYSTEM AND METHOD FOR ACCESSING A BOOT PROGRAM - A computing system includes a flash storage device that loads a boot program from a flash storage of the flash storage device to a random access memory of the flash storage device. A processor of the computing system then accesses the boot program from the random access memory and executes the boot program. | 2011-01-27 |
20110022830 | Boot Block - A machine including a processor, a boot block including an immutable segment and a mutable segment, one or more BIOS images stored on the mutable segment of the boot block, and a BIOS manager executed by the processor from the immutable segment of the boot block and configured to determine whether a BIOS of the machine is valid and launch a BIOS replacement process when the BIOS is invalid. | 2011-01-27 |
20110022831 | Method for Operation System Startup - A method for operation system startup includes steps of switching on hardware startup; determining whether there is a trigger signal; reading an initial parameter from a storage device, and loading the initial parameter into a startup program when there is no trigger signal, executing the startup program; and entering operational system. | 2011-01-27 |
20110022832 | MULTI-OPERATING SYSTEM (OS) BOOTING APPARATUS, MULTI-OS BOOTING PROGRAM, RECORDING MEDIUM, AND MULTI-OS BOOTING METHOD - In a multi-OS booting apparatus, when loading the second OS, contents of the second OS is prevented from being referred to by other programs. The first OS | 2011-01-27 |
20110022833 | ALTERING PERFORMANCE OF COMPUTATIONAL UNITS HETEROGENEOUSLY ACCORDING TO PERFORMANCE SENSITIVITY - One or more computational units of a computer system are selectively altered in terms of performance according to which of the one or more computational units has a higher performance sensitivity than others of the computational units. | 2011-01-27 |
20110022834 | SYSTEMS AND METHODS FOR SHARED SECRET DATA GENERATION - Disclosed examples of secure communications involve generating, by a mobile communication network device, a shared secret data having a length of M units. A first operation on groups of one of N units of a randomly generated base shared secret data and one of a plurality of secret values thereby generates a plurality of first operation results. A second operation on a select plurality of the first operation results generates a plurality of second operation results. The randomly generated base shared secret data can have a length of N units, where N is less than M. The shared secret data is constructed from at least one of the first operation results and the plurality of second operation results. | 2011-01-27 |
20110022835 | Secure Communication Using Asymmetric Cryptography and Light-Weight Certificates - Encrypted communications between servers and client devices over an unsecured channel, such as the Internet, without using a public key infrastructure are disclosed. Messages to a client device are encrypted using an encryption key of an authorized individual, regardless of the identity of the user of the client device. Encryption is performed by a system that does not expose encryption keys to the client device or the server, thereby preventing man-in-the-middle attacks against the encryption key. Secure communications are combined with a two-factor protocol for authenticating the identity of an individual. An individual authenticates by generating a cipher using a light-weight certificate that has a shared secret but no other information identifying the individual. Separately, a server generates the same cipher using the shared secret, thereby authenticating the individual's identity to a relying party. | 2011-01-27 |
20110022836 | Method and apparatus for securing the privacy of a computer network - A method and apparatus for secure access to a computer network and for safeguarding the confidentiality and privacy of data stored and distributed by the network is disclosed. The method and apparatus addresses both limiting access to the computer network to those who are authorized to have access as well as the privacy of the information stored in the network. | 2011-01-27 |
20110022837 | Method and Apparatus For Performing Secure Transactions Via An Insecure Computing and Communications Medium - The present invention comprises a user interface hardware implementation and associated method for providing a means to achieve secure transactions between a human user and a remote computing facility or service, wherein the transaction is performed such that intermediate nodes, including the human user's primary computation device (e.g. personal computer, cellphone, etc.) need not be trustworthy while still preserving the privacy and authenticity of communications between the human user and remote computing facility or service. | 2011-01-27 |
20110022838 | Method and system for secure remote login of a mobile device - A system to securely login a mobile device may include a storage means for storing an encrypted file, a certification system to receive the encrypted file from the storage means, and a customer transaction system in communication with the certification system. The system may also include the mobile device to transmit the encrypted file from the storage means to the certification system to allow the mobile device to securely log into the customer transaction system. | 2011-01-27 |
20110022839 | Method and system for establishing a trusted and decentralized peer-to-peer network - The present invention offers a new and improved method and system to establish a trusted and decentralized peer-to-peer network for: the sharing of computer files between and among computing devices; trusted chat sessions; and for other applications of trusted peer-to-peer networks. | 2011-01-27 |
20110022840 | Method and System for Detecting Data modification within computing device - A method and apparatus for detecting data modification in a layered operating system is disclosed. Outbound content indicators at different layers are compared to detect potential outbound data modifications. Likewise, inbound content indicators at different layers are compared to detect potential inbound data modifications. Content indicators include checksum, cryptographic hash, signature, and fingerprint indicators. Embodiments of the present invention enable detection of data modifications across an operating system's kernel and user mode spaces, prevention of modified outbound data from reaching a network, prevention of modified input data from reaching a user application, and detection of malware and faults within an operating system. | 2011-01-27 |
20110022841 | AUTHENTICATION SYSTEMS AND METHODS USING A PACKET TELEPHONY DEVICE - Authentication systems and methods for increasing the security of online account access and transactions by leveraging the use of customer equipment provided by VoIP service providers. A method includes registering a packet telephony device with a packet telephony service provider for subsequent packet telephony communication, where the registration is based at least on an encoded encryption key. On a subsequent request to access an account, instructions are transmitted which require physical access to the packet telephony device to perform. Upon receipt of an indication that the instructions were successfully performed, the request is authenticated and access to the account is granted. Authentication may require a secure connection be automatically established between a web-enabled device and a packet telephony device. The instant disclosure leverages the security in the customer equipment hardware such as a Terminal adaptor (TA) or router so that a compromised account may be recovered. | 2011-01-27 |
20110022842 | CONTENTS TRANSMITTER APPARATUS, CONTENTS RECEIVER APPARATUS AND CONTENTS TRANSMITTING METHOD - For achieving the protection of copyright, by suppressing illegal copy production thereof, in particular, when transmitting contents with using a wired or wireless LAN, as well as, for preventing the transmission of contents from deviating from a range of a personal use thereof, a contents transmitter apparatus and a contents receiver apparatus make an authentication, mutually, before transmitting contents therebetween. At the time when conducting this authentication, measurement is made upon a time-period up to arrival of a receipt confirmation responding to the transmission of an authentication request or a response to the authentication; then, only in the case when this value measured does not exceed a predetermined upper value, the transmission is conducted on the contents encrypted, and at the same time, address information and equipment information unique to the apparatus are registered, thereby conducting the transmission of encrypted contents, but without conducting the time-measurement thereon, when transmitting the contents, again. Also, while conducting the time-measurement periodically, dynamic management is made on the registration information, so that the contents thereof are suitable for the network structure at the present. | 2011-01-27 |