04th week of 2011 patent applcation highlights part 27 |
Patent application number | Title | Published |
20110019438 | LIGHT EMITTING DIODE LAMP - A light emitting diode lamp includes a lamp shade, a light emitting diode light source, a universal joint and a power connector. The light emitting diode light source is disposed in the lamp shade. The universal joint includes a first connecting part and a second connecting part. The first connecting part is fixed to the lamp shade. The second connecting part is rotatably connected to the first connecting part and fixed to the power connector. | 2011-01-27 |
20110019439 | POWER SUPPLY APPARATUS WITH CURRENT-SHARING FUNCTION - A power supply apparatus with a current-sharing function includes a conversion circuit, a square-wave generating circuit, a resonant circuit, and a rectifier-filter circuit. The conversion circuit has two transformers, and each of the transformers has a primary winding and two secondary windings. More particularly, two secondary windings of the different transformers are electrically connected in series and then the two in-series secondary windings are electrically connected in parallel. The square-wave generating circuit is used to switch a DC voltage into a pulsating voltage. The resonant circuit is electrically connected to the square-wave generating circuit, and having a first capacitor and the primary windings of the transformers. The rectifier-filter circuit has at least two switch components and a second capacitor, and electrically connected to the secondary windings of the transformers to rectify an AC output voltage into a DC output voltage, and the DC output voltage is outputted to at least one output terminal. | 2011-01-27 |
20110019440 | BI-DIRECTIONAL DC-DC CONVERTER AND METHOD FOR CONTROLLING THE SAME - A bi-directional DC-DC converter has a transformer for connecting a voltage type full bridge circuit connected to a first power source and a current type switching circuit connected to a second power source. A voltage clamping circuit constructed by switching elements and a clamping capacitor is connected to the current type switching circuit. The converter has a control circuit for cooperatively making switching elements operative so as to control a current flowing in a resonance reactor. | 2011-01-27 |
20110019441 | METHOD AND APPARATUS FOR DIGITAL CONTROL OF A SWITCHING REGULATOR - In one aspect, a power supply regulator includes a feedback terminal, a node, a control circuit, a first current source, and a second current source. The node is coupled to the feedback terminal to provide a feedback state signal in response to a feedback current through the feedback terminal. The feedback state signal has feedback states that represent an output of the power supply. The control circuit is to be coupled to a power switch and to receive the feedback state signal to regulate the output of the power supply. The first current source is coupled to the node to provide a first current to the node. The second current source is coupled to the node to selectively remove a second current from the node to modulate the feedback current and to alter the feedback state of the feedback state signal. | 2011-01-27 |
20110019442 | POWER CONVERTER - The noise generated from a power converter is suppressed by increasing the noise frequency to a level not lower than the maximum frequency of the human audible range. To obtain the frequency of an output current harmonic component as a noise source which has exceeded the maximum frequency of the human audible range, it is adequate to determine that the frequency of a driving carrier wave for the individual converter cells in the power converter, in which the phases of the carrier wave for the converter cells are mutually shifted by a given value between the converter cells, meets the following equation. | 2011-01-27 |
20110019443 | SERIES VOLTAGE COMPENSATOR AND METHOD FOR SERIES VOLTAGE COMPENSATION IN ELECTRICAL GENERATORS - Series voltage compensator connected in series between an electrical generator and an electrical grid that comprises a filter and an electronic power converter per phase. The compensator generates a voltage to dynamically compensate for sudden voltage drops in the electrical grid, with it being additionally possible to control the angle of the voltage in relation to the current with the aim of controlling the reactive power injected (or absorbed) by the series voltage compensator to the grid. | 2011-01-27 |
20110019444 | Method and apparatus for detection and control of dc arc faults - A method and apparatus for managing DC arc faults. At least a portion of the method is performed by a controller comprising at least one processor. In one embodiment, the method comprises analyzing a signature of a signal of a power converter and determining, based on analysis of the signature, whether an arc fault exists. | 2011-01-27 |
20110019445 | METHOD AND APPARATUS FOR CONTROLLING POWER CONVERTER OUTPUT CHARACTERISTICS - A power converter includes a primary winding for providing a primary current, a secondary winding for providing an output current and an output voltage, and a current sense node for receiving a current sense signal related to the primary current. The power converter also includes a control circuit configured to limit the current sense signal to be lower than or equal to a predetermined reference peak current. Moreover, the power converter includes a first circuit configured to modify the current sense signal using a first signal related to the output voltage to cause an variation in the output current. | 2011-01-27 |
20110019446 | METHOD AND APPARATUS FOR A SWITCHING MODE POWER SUPPLY - A controller for a switched mode power supply (SMPS) is provided. The SMPS is equipped with a transformer having a primary side winding, a secondary winding, and an auxiliary winding. The controller includes a detection circuit for detecting a transition from a first output load condition to a second output load condition of the SMPS and a control circuit coupled to the detection circuit and being configured to output one or more control signals in response to the detected output load transition. Depending on the embodiment, the one or more control signals include a first control signal for turning on a power switch to cause a current flow in a primary winding of the SMPS and/or one or more second control signals for turning off one or more functional circuit blocks in the controller. | 2011-01-27 |
20110019447 | Solar motor generator power converter - Modern solar voltaic power conversion for grid compatible usage requires employing complicated active electronic systems designed to control connection, conversion, regulation and safety functions that are absolutely necessary for co-generation applications. This invention inherently and passively performs all of those functions, delivering fully regulated, compatible and fail safe alternating current suitable for supplementing the electrical grid at virtually any point of use and does not use any active electronic devices. This invention dramatically simplifies and improves the art of converting solar voltaic power to common grid power by utilizing an ingenious “Motor-Generator” combination of a common direct current motor and a common induction motor; Two very old devices that have been in common use for over one hundred years. | 2011-01-27 |
20110019448 | SWITCHING POWER SUPPLY APPARATUS - Provided is a switching power supply apparatus capable of suppressing heat generation from a power supply to improve the efficiency of conversion during a power supply operation and accurately detecting only a current flowing through a load to achieve more stabile control. Since a first closed loop made up of a fourth diode ( | 2011-01-27 |
20110019449 | POWER CONVERTER APPARATUS - A power converter apparatus having a configuration of a plurality of unit cells, including a DC capacitor and semiconductor devices, connected in cascade, includes a variable voltage source that is connected with a DC link, and a unit having a function that initially charges up the DC capacitor in the unit cell alone selected at a time of an initial charge. | 2011-01-27 |
20110019450 | High Speed Rectifier Circuit - Provided is a rectifier circuit that includes a depletion mode semiconductor having an output connected to a rectified signal output node of the rectifier circuit and a hot carrier semiconductor diode having a cathode connected to a source node of the depletion mode semiconductor and an anode connected to a gate node of the depletion mode semiconductor. The rectifier may include an alternating current (AC) input node that is connected to the anode of the hot carrier semiconductor diode and the gate node of the depletion mode semiconductor and that is configured to receive an AC input signal. | 2011-01-27 |
20110019451 | Power Supply Auxiliary Circuit - A power supply auxiliary circuit includes a power input unit for receiving an AC input voltage, a voltage regulating unit for dropping the AC input voltage, a rectifying unit for converting the dropped AC input voltage into a DC voltage, a snubber unit for filtering the DC voltage, a power output unit for sending the filtered DC voltage, a switch unit connected between the rectifying unit and a feedback control unit, and the feedback control unit connected between the power output unit and the switch unit for detecting and analyzing the output voltage of the power output unit, and then generating a corresponding control signal to determine a switch state of the switch unit that makes the current from the rectifying unit partially back-flow to the power input unit or not, and further regulates the value of the output voltage of the power output unit. | 2011-01-27 |
20110019452 | AC-DC CONVERTER AND COMPRESSOR DRIVING APPARATUS AND AIR CONDITIONING APPARATUS USING THE SAME - An AC-DC converter is provided which suppresses a harmonic current and improves power factor at low cost. Such an AC-DC converter includes a rectifier connected to an AC power supply via a reactor, capacitors connected in series across the output terminals of the rectifier, a first bidirectional switch having one end connected to one input terminal of the rectifier and the other end connected to a connecting point of capacitors, a second bidirectional switch having one end connected to the other input terminal of the rectifier and the other end connected to the other end of the first bidirectional switch, and a control circuit for actuating the first and second bidirectional switches during a half cycle of the AC power supply so as to control a voltage inputted to the rectifier to a desired output voltage. | 2011-01-27 |
20110019453 | ELECTRIC CIRCUIT FOR CONVERTING DIRECT CURRENT INTO ALTERNATING CURRENT - The invention relates to a DC/AC conversion structure, preferably intended for photovoltaic systems, having a high yield across the entire input voltage range thereof, thereby guaranteeing that direct current is not injected into the alternating current network. In a preferred embodiment, the circuit includes six switching elements (T | 2011-01-27 |
20110019454 | Drive Circuit - The present invention relates to a DC to AC inverter comprising a plurality of voltage controlled switching devices, where one or more of the voltage controlled switching devices is driven by a drive circuit comprising: a bridge switching circuit ( | 2011-01-27 |
20110019455 | LOW COST HIGH DENSITY RECTIFIER MATRIX MEMORY - A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers. | 2011-01-27 |
20110019456 | SENSE AMPLIFIER WITH SHIELDING CIRCUIT - A sense amplifier comprises a sense node, a reference node, a memory input stage circuit, a reference input stage circuit, an output stage circuit, and a shielding circuit. The memory input stage circuit comprises first input node for maintaining a first sense voltage established by a cell current and establishes a second sense voltage on the sense node in response to the first sense voltage. The reference input stage circuit comprises an output node and a second input node, which is for maintaining a first reference voltage established by the reference current and establishes a second reference voltage on the reference node in response to the first reference voltage. The output stage circuit obtains a sense result in response to the second reference voltage and the second sense voltage. The first shielding circuit shields the output node from being interfered with the second reference voltage on the reference node. | 2011-01-27 |
20110019457 | Flash memory - A flash memory includes a controller unit and dies. The dies are connected to a controller unit. Each of the dies includes an upper face and a lower face. Each of the dies includes at least one power supply pad, at least one grounding pad, at least one input/output pad, selection pads and standby/busy pads on each of the upper and lower faces. The power supply pad is connected to the controller unit. The grounding pad is connected to the power supply pad in parallel. The input/output pad is connected to the grounding pad in parallel. The selection pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired. The standby/busy pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired. | 2011-01-27 |
20110019458 | MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR ROUTING THE MEMORY CIRCUITS - A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array. | 2011-01-27 |
20110019459 | Three-Dimensional Mask-Programmable Read-Only Memory with Reserved Space - The present invention discloses a three-dimensional mask-programmable read-only memory with reserved space (3D-MPROM | 2011-01-27 |
20110019460 | MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines. | 2011-01-27 |
20110019461 | F-SRAM Power-Off Operation - A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each read operation. A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each write operation. A process of operating an integrated circuit containing a programmable data storage component including four data ferroelectric capacitors, in which power is removed from a state circuit after each read operation and after each write operation. | 2011-01-27 |
20110019462 | THREE DIMENSIONAL PROGRAMMABLE RESISTANCE MEMORY DEVICE WITH A READ/WRITE CIRCUIT STACKED UNDER A MEMORY CELL ARRAY - A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high resistance state or a low resistance state determined due to the polarity of voltage application in a non-volatile manner. The access element has such a resistance value in an off-state in a certain voltage range that is ten time or more as high as that in a select state. A read/write circuit is formed on a semiconductor substrate as underlying the cell array for data reading and data writing in communication with the cell array. | 2011-01-27 |
20110019463 | Static Random Access Memories and Access Methods Thereof - A static random access memory device capable of preventing stability issues during a write operation is provided, in which a memory cell is coupled to a read word line, a write word line, a read bit line, a write bit line and a complementary write bit line, and a multiplexing unit is coupled to the read bit line, the write bit line and the complementary write bit line. The multiplexing unit applies first and second logic voltages representing a logic state stored in the memory cell to the write bit line and the complementary write bit line, respectively, when the memory cell is not selected to be written by an input signal from a data driver and the read word line is activated, in which the first and second logic voltages are opposite to each other. | 2011-01-27 |
20110019464 | Smart Well Assisted SRAM Read and Write - An integrated circuit containing an array of SRAM cells with NMOS drivers and passgates, and an n-well bias control circuit which biases n-wells in each SRAM column independently. An integrated circuit containing an array of SRAM cells with PMOS drivers and passgates, and a p-well bias control circuit which biases p-wells in each SRAM column independently. A process of operating an integrated circuit containing an array of SRAM cells with NMOS drivers and passgates, and an n-well bias control circuit which biases n-wells in each SRAM column independently. | 2011-01-27 |
20110019465 | MAGNETIC TUNNEL JUNCTION WITH COMPENSATION ELEMENT - A magnetic tunnel junction having a compensation element is disclosed. The magnetic tunnel junction includes a synthetic antiferromagnetic reference element, and a synthetic antiferromagnetic compensation element having an opposite magnetization moment to a magnetization moment of the synthetic antiferromagnetic reference element. A free magnetic layer is between the synthetic antiferromagnetic reference element and the synthetic antiferromagnetic compensation element, and an electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic layer from the synthetic antiferromagnetic reference element. The free magnetic layer includes Co | 2011-01-27 |
20110019466 | Stuck-At Defect Condition Repair for a Non-Volatile Memory Cell - A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition. | 2011-01-27 |
20110019467 | VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION - A memory cell is provided that includes a first conductor, a second conductor, a steering element that is capable of providing substantially unidirectional current flow, and a state change element coupled in series with the steering element. The state change element is capable of retaining a programmed state, and the steering element and state change element are vertically aligned with one another. Other aspects are also provided. | 2011-01-27 |
20110019468 | NON-LINEAR CONDUCTOR MEMORY - A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that is non-selected, and a low resistance when connected to the selected row and column. | 2011-01-27 |
20110019469 | SEMICONDUCTOR MEMORY - A semiconductor memory includes a memory cell array area having a memory cell, a word line contact area adjacent to the memory cell array area, a word line arranged straddling the memory cell array area and the word line contact area, a contact hole provided on the word line in the word line contact area, and a word line driver connected to the word line via the contact hole. A size of the contact hole is larger than a width of the word line, and the lowest parts of the contact hole exist on a position lower than a top surface of the word line and higher than a bottom surface of the word line. | 2011-01-27 |
20110019470 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, in which a multi-bit region including multi-bit memory cells that store data of two or more bits and a region including memory cells that store data of bits that are less than the bits of the data stored in the multi-bit memory cells are installed, is provided, which can perform a high-speed writing and lengthen the life span of the product without increasing the storage capacity of the region of the memory cells storing the data of bits that are less than the bits of the data in the multi-bit memory cells. The semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h≦n) data is stored in a memory MLC of a first region MLB, and i-bit (i2011-01-27 | |
20110019471 | Nonvolatile Memory with Correlated Multiple Pass Programming - A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are correlated. Each programming pass employs a programming voltage in the form of a staircase pulse train with a common step size, and each successive pass has the staircase pulse train offset from that of the previous pass by a predetermined offset level. The predetermined offset level is less than the common step size and may be less than or equal to the predetermined offset level of the previous pass. Thus, the same programming resolution can be achieved over multiple passes using fewer programming pulses than conventional method where each successive pass uses a programming staircase pulse train with a finer step size. The multiple pass programming serves to tighten the distribution of the programmed thresholds while reducing the overall number of programming pulses. | 2011-01-27 |
20110019472 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A nonvolatile semiconductor memory device and a programming method thereof are provided. The programming method includes first programming a cell among a plurality of adjacent memory cells to the highest threshold voltage distribution corresponding to a data state, and subsequently programming the other adjacent cells to the lower threshold voltage distributions corresponding to second and third data states. The second data state and the third data state may have the second highest threshold voltage distribution and the third highest threshold voltage distribution, respectively, or the third highest threshold voltage distribution and the second highest threshold voltage distribution, respectively. | 2011-01-27 |
20110019473 | MEMORY ARRAY AND METHOD OF OPERATING ONE OF A PLURALITY OF MEMORY CELLS - An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of the plurality of bit lines. The device couples the plurality of bit lines together to form a common node for one of the plurality of memory cells. | 2011-01-27 |
20110019474 | FLASH MEMORY DEVICE WITH REDUNDANT COLUMNS - Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches. | 2011-01-27 |
20110019475 | INTERLEAVED FLASH STORAGE SYSTEM AND METHOD - A flash storage system accesses data interleaved among flash storage devices. The flash storage system receives a data block including data portions, stores the data portions in a data buffer, and initiates data transfers for asynchronously writing the data portions into storage blocks interleaved among the flash storage devices. Additionally, the flash storage system may asynchronously read data portions of a data block interleaved among the storage blocks, store the data portions in the data buffer, and access the data portions from the data buffer. | 2011-01-27 |
20110019476 | NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A nonvolatile memory device is provided which includes a plurality of memory blocks, a bias block and a control logic block. The memory blocks are formed in wells, respectively. The bias block biases a well of a selected memory block. The control logic block controls the bias block to pre-charge doping regions of the selected memory block to a junction voltage before word line voltages are applied to the selected memory block in a programming operation. | 2011-01-27 |
20110019477 | NAND TYPE FLASH MEMORY - According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block. | 2011-01-27 |
20110019478 | SENSING OF MEMORY CELLS IN NAND FLASH - An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing. In a source follower sensing or read operation the programmed threshold voltage of a cell in a NAND string of a NAND architecture Flash memory array is read by applying an elevated voltage to the source line, an elevated pass voltage (V | 2011-01-27 |
20110019479 | TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region coupled to a carrier injection line configured to inject charges into the body region through the second region. | 2011-01-27 |
20110019480 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; a first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer to electrically connect the first and second semiconductor pillars; a connection portion conductive layer opposing the connection portion semiconductor layer; a memory layer, an inner insulating film, and an outer insulating film provided between the first and second semiconductor layers and the electrode films and between the connection portion semiconductor layer and the connection portion conductive layer. At least a portion of a face of the connection portion conductive layer opposing the outer insulating film is a curved surface having a recessed configuration on a side of the outer insulating film. | 2011-01-27 |
20110019481 | TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device including the steps of applying a first non-negative voltage potential to a first region via a bit line and applying a second non-negative voltage potential to a second region via a source line. The method may also include applying a third voltage potential to a word line, wherein the word line may be spaced apart from and capacitively to a body region that may be electrically floating and disposed between the first region and the second region. The method may further include applying a fourth positive voltage potential to a third region via a carrier injection line, wherein the third region may be disposed below at least one of the first region, the body region, and the second region. | 2011-01-27 |
20110019482 | TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other. | 2011-01-27 |
20110019483 | ADAPTIVE ERASE AND SOFT PROGRAMMING FOR MEMORY - An erase sequence of a non-volatile storage device includes an erase operation followed by a soft programming operation. The erase operation applies one or more erase pulses to the storage elements, e.g., via a substrate, until an erase verify level is satisfied. The number of erase pulses is tracked and recorded as an indicia of the number of programming-erase cycles which the storage device has experienced. The soft programming operation applies soft programming pulses to the storage elements until a soft programming verify level is satisfied. Based on the number of erase pulses, the soft programming operation time is shortened by skipping verify operations for a specific number of initial soft programming pulses which is a function of the number of erase pulses. Also, a characteristic of the soft programming operation can be optimized, such as starting amplitude, step size or pulse duration. | 2011-01-27 |
20110019484 | Non-Volatile Memory and Method With Improved Sensing Having Bit-Line Lockout Control - In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level. | 2011-01-27 |
20110019485 | Non-Volatile Memory and Method with Shared Processing for an Aggregate of Read/Write Circuits - A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output. | 2011-01-27 |
20110019486 | SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A programming method of a semiconductor memory device includes charging a channel of an inhibit string to a precharge voltage provided to the common source line and boosting the charged channel by providing a wordline voltage to the cell strings. The inhibit string is connected to a program bitline among the bitlines. | 2011-01-27 |
20110019487 | APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES - According to an embodiment of the present invention, a method for detecting word line leakage in a memory device includes coupling a first word line in the memory device to a voltage source while coupling a second word line in the memory device to a ground level voltage. Next, the first word line is decoupled from the voltage source. The method also includes comparing a current of the first word line with a predetermined reference current for determining a leakage condition of the word line. | 2011-01-27 |
20110019488 | DOUBLE-GATE FLOATING-BODY MEMORY DEVICE - A memory device is provided comprising a transistor having a floating body positioned between source and drain regions, the floating body being sandwiched between first and second insulated gates each comprising a gate electrode. A control circuit is arranged to program the state of said floating body to have an accumulation or depletion of majority carriers by applying one of first and second voltage levels between the first gate and at least one of the source and drain regions, and to retain the programmed state of said floating body by applying a third voltage level to the second gate. The voltages are switched over a time duration shorter than 100 ns. | 2011-01-27 |
20110019489 | Apparatus and method for data strobe and timing variation detection of an SDRAM interface - An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal. | 2011-01-27 |
20110019490 | SEMICONDUCTOR MEMORY - A semiconductor storage device includes a memory cell array that stores data and includes a plurality of memory cells two dimensionally arrayed on row and column lines extending along row and column directions, at least one of the memory cells assigned to a redundant memory cell having a lager area size than the other memory cells, the plurality of memory cells and at least one of the redundant memory cells arrayed on at least one of the row lines. | 2011-01-27 |
20110019491 | REDUNDANCY SYSTEM FOR NON-VOLATILE MEMORY - A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping. Defective cells are biased to either “1” or “0” logic states, which are effectively preset to store its biased logic state. A data bit to be stored in a defective cell having a logic state that is complementary to the biased logic state of the cell results in the program data being inverted and programmed. An inversion status bit is programmed to indicate the inverted status of the programmed data. During read out, the inversion status bit causes the stored data to be re-inverted into its original program data states. | 2011-01-27 |
20110019492 | TEST DEVICE AND TEST METHOD FOR RESISTIVE RANDOM ACCESS MEMORY AND RESISTIVE RANDOM ACCESS MEMORY DEVICE - A first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted. | 2011-01-27 |
20110019493 | Semiconductor memory device - Provided is a semiconductor memory device including a plurality of memory cells that are connected to a word line and read data, a plurality of bit line pairs that are connected respectively to the plurality of memory cells, a column selector that selects one of the plurality of bit line pairs according to a column selection signal, a sense amplifier circuit that has an input terminal pair connected to the column selector and is activated according to a sense amplifier activation signal, an offset voltage adjustment circuit that is connected to the sense amplifier circuit and adjusts an offset voltage of the sense amplifier circuit according to the weight control signal, and a weight control circuit that is connected to an output terminal pair of the sense amplifier circuit and outputs a weight control signal with a value corresponding to an output of the activated sense amplifier circuit. | 2011-01-27 |
20110019494 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, element properties of an element property extraction pattern formed on a semiconductor wafer is extracted as element properties of a current control element corresponding to the element property extraction pattern. A supply energy to the current control element is set which is formed between nodes on the semiconductor wafer, based on the extracted element properties. The set supply energy is supplied to the current control element to irreversible control an electrical connection between the nodes through the device breakdown by the current control element. | 2011-01-27 |
20110019495 | DECODER CIRCUITRY PROVIDING FORWARD AND REVERSE MODES OF MEMORY ARRAY OPERATION AND METHOD FOR BIASING SAME - Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks. | 2011-01-27 |
20110019496 | Emulsification equipment - An emulsification equipment is revealed. The emulsification equipment includes an atmospheric pressure container, a stirring unit arranged over the atmospheric pressure container, a temperature control unit disposed outside the atmospheric pressure container, and an ultrasonic vibrating unit set on the bottom of the atmospheric pressure container. Thereby, through the ultrasonic vibration energy generated by the ultrasonic vibrating unit being transferred to liquid, together with stirring of the stirring unit as well as temperature control by the temperature control unit, an emulsion formed by the emulsification equipment is with better refinement and stability. | 2011-01-27 |
20110019497 | FLUID AGITATION METHOD, FLUID AGITATION SYSTEM, AND CARTRIDGE - A fluid agitation method is provided, whereby a swirling flow is generated in a trace amount of fluid, thereby agitating the fluid. The fluid agitation method includes introducing the fluid into an agitation chamber ( | 2011-01-27 |
20110019498 | Mixing Head For Reaction Injection Molded Materials - A mixing head assembly includes a mix head with ejection piston, and multiple hydraulic (or pneumatic) control valve assemblies (up to eight) each with a double-needle subassembly for feeding controlled amounts of material to the mixing chamber of the mix head in predetermined ratios and controlled quantities and at high pressures. The double-needle subassembly accurately and independently controls material flow within the control valve assembly and operates independently from other valve assemblies, thus permitting timed opening for optimal mixing during initiation, continuous mixing, and termination phases. The ejection piston is modified to eliminate longitudinal grooves for recirculating materials. The mixing head assembly is a closed loop system for controlled high pressure impingement mixing of multiple components and includes material recirculation. The present assembly permits accurate mixing (during initial and continuous flow) of multiple components, and allows changing mix materials on the fly, including during injections or between injections | 2011-01-27 |
20110019499 | Beverage Mixing Device with Two Mixed Beverages - A beverage mixing device includes a primary container, a secondary container mounted in the primary container, a diaphragm removably mounted on the secondary container to seal the lower end of the secondary container, a sliding member movably mounted in the secondary container and having a lower end provided with a cutting blade that is movable to penetrate the diaphragm to connect the secondary container to the primary container and an upper end provided with a helical driven portion, and a top cap removably mounted on the primary container and provided with a helical drive portion abutting the helical driven portion of the sliding member to push the sliding member toward the diaphragm by rotation of the top cap relative to the sliding member. | 2011-01-27 |
20110019500 | METHOD, SYSTEM AND LOGGING TOOL FOR ESTIMATING PERMEABILITY OF A FORMATION - The invention relates to the methods for determining the permeability of a geological formation saturated with a liquid and provides for a method, a system and a logging tool for estimating permeability. The method comprises exciting a formation with acoustic energy pulses propagating into the formation, measuring the acoustic response signals produced by the acoustic exciting and the electromagnetic signals produced by said acoustic energy pulses within the formation and separating components from said measured acoustic response signals and said measured electromagnetic signals representing Stoneley waves propagating through the formation. The acoustic response signals and electromagnetic signals representing Stoneley waves propagating through the formation are synthesized. The separated acoustic response signal and electromagnetic signal components and the synthesized Stoneley wave signals are compared. The permeability is determined from differences between the synthesized Stoneley wave signals and the separated acoustic response signal and electromagnetic signal components. | 2011-01-27 |
20110019501 | Acoustic Anisotropy and Imaging by Means of High Resolution Azimuthal Sampling - In an acoustic logging system utilizing one or more acoustic sources, each with a specified radiation pattern around a source orientation, an acoustic signal is transmitted into a formation with a source oriented in a first source orientation. An acoustic waveform is received in response with a receiver oriented in a first direction. The slowness of the formation in the first direction is calculated using the received acoustic waveform. | 2011-01-27 |
20110019502 | PRACTICAL AUTONOMOUS SEISMIC RECORDER IMPLEMENTATION AND USE - Seismic systems and methods are provided to synchronize both source and receiver data using inexpensive timers and/or low energy timers to obtain high resolution seismic data. | 2011-01-27 |
20110019503 | Apparatus For Providing A Digital Wall Calendar - An apparatus for providing a digital wall calendar. The apparatus comprises an upper display module, a lower display module; and a logic and communication module. The upper display module displays an image. The lower display module displays a series of dates. The logic and communication module provides the image and the series of dates to the upper display module and the lower display module. | 2011-01-27 |
20110019504 | TIME PIECE WITH LED LIGHT MEANS - A timepiece with LED lights uses a simple light-medium body with a very rough finish to allow light from LED(s) to pass though input-end(s) of the light-medium body and travel within the body and obtain a very even brightness on all surfaces of the light medium that are seen by a viewer. Combined with a milky/frosted front sheet overlay, the light-medium surface can get perfect area illumination effects. The movement for the time display can include analog indicators with a guilt-in light-medium on the top cover to achieve a super slim LED illumination for the time piece. For night light application, the sealed-unit may consist of prong-means and an LED related circuit sealed within a safety standard plastic material and assembled with the night light body to save a lot of cost enable use of all kinds of materials. The invention may also be adapted to an LCD display timepiece. | 2011-01-27 |
20110019505 | COAXIAL HOROLOGICAL MOVEMENT - Horological movement comprising an energy accumulator ( | 2011-01-27 |
20110019506 | ESCAPEMENT MECHANISM - An escapement mechanism adapted for transmitting mechanical energy pulses from a driving source to an oscillating regulator of a timepiece via a blade spring ( | 2011-01-27 |
20110019507 | CLOCKWORK MECHANISM AND CLOCKWORK TIMEPIECE - A clockwork mechanism includes: a supporting member; a movable member including an engagement hole and movably supported by the supporting member; a drive pin engaging the engagement hole, including a flange portion for preventing the drive pin from disengaging from the engagement hole, and revolving to move the movable member; a biasing member provided in the movable member to partially overlap the engagement hole; and an abutment member abutting the movable member to restrict the movement of the movable member. The flange portion overlaps or does not overlap the biasing member depending on a revolving position of the drive pin. When the movable member abuts the abutment member, the drive pin pushes the biasing member and the movable member is biased toward the abutment member by the biasing member. When the flange portion does not overlap the biasing member, the drive pin moves the movable member to push the biasing member, allowing the drive pin to disengage from the engagement hole. | 2011-01-27 |
20110019508 | SHOCK PROOF WATCH - An arrangement for protecting a watch movement from shocks and vibrations comprises shock absorbers ( | 2011-01-27 |
20110019509 | Limited use data storing device - Embodiments of methods and systems for controlling access to information stored on memory or data storage devices are disclosed. In various embodiments, methods of retrieving information from a data storage device previously deactivated by modification or degradation of at least a portion of the data storage device are disclosed. | 2011-01-27 |
20110019510 | RECORDING HEAD AND RECORDER - A recorder has a recording medium for information recording, a light source, an optical system, a slider, and an optical waveguide. To the optical system, light from the light source enters, and the slider moves relative to the recording medium while not in contact therewith. The optical waveguide is arranged at position facing the recording medium in the slider so that light entering from the optical system is irradiated on the recording medium. Where the mode field diameter of the optical waveguide on the light output side is d and the mode field diameter thereof on the light input side is D, the mode field diameter is converted by smoothly changing the diameter of the optical waveguide to satisfy D>d. | 2011-01-27 |
20110019511 | Optical Memories, Method for Reading and Writing Such Optical Memories, and Device for Reading and Writing Such Memories - The invention concerns a optical data memory, said memory comprising at least one layer of supporting material, said supporting material including molecules having, in a local zone, a collective state of molecules from at least one first collective state of molecules, and a second collective state of molecules. The invention is characterized in that only molecules having the first collective state of molecules in said local zone are capable of generating a second-harmonic signal when they are excited in said local zone by a reading electromagnetic radiation. | 2011-01-27 |
20110019512 | Optical disk reproducing device and optical disk recording and reproducing device - An optical disk reproducing device includes: a signal reproducing section configured to read and decode information recorded on an optical disk by an optical pickup unit, and reproduce the information, wherein the signal reproducing section includes a gain controlled amplifier circuit configured to amplify an radio frequency signal generated from a light receiving element, an automatic gain control circuit configured to control a gain of the gain controlled amplifier circuit, and a signal processing section configured to derive a part of an automatic gain control value generated in the automatic gain control circuit, and generate a control signal for adjusting one of an optical system path and a detection system path for controlling the optical pickup unit. | 2011-01-27 |
20110019513 | SHORT-PULSE LIGHT SOURCE, LASER LIGHT EMISSION METHOD, OPTICAL DEVICE, OPTICAL DISC DEVICE, AND OPTICAL PICKUP - Directed to freely adjusting an emission period of a semiconductor laser. | 2011-01-27 |
20110019514 | Recording and Reproducing Apparatus and Method - A Spare Area kept unused on a disk is available for use other than spare processing, or Defect Management process, and compatibility of the disk is at least secured between different recording apparatuses. This is implemented by recording a SWP_PAC cluster defined as a new item and by recording address information of used addresses in a PAC or TDDS area. | 2011-01-27 |
20110019515 | METHOD OF MANAGING DATA IN OPTICAL DISC APPARATUS - A method of managing data in an optical disc apparatus is provided. The type of a loaded disc is checked, and data corresponding to the checked disc type is read from a compressed file, decompressed and stored in a memory of the optical disc apparatus. Recording-related data respectively corresponding to disc types, manufacturers, and recording speeds are separately compressed in the compressed file. Identification information about the disc types, manufacturers, and recording speeds and information on positions at which the recording-related data about the disc types, manufacturers, and recording speeds are stored may be included in the head of the compressed file. The compressed file may include separately compressed servo data, and information on the position at which the servo data is stored may be included in the head of the compressed file. Accordingly, the optical disc manufacturing cost can be decreased and a data loading time can be reduced. | 2011-01-27 |
20110019516 | SYSTEM AND METHOD FOR PROVIDING CONTENT IN TWO FORMATS ON ONE DRM DISK - A DRM disk such as a Blu-ray stores content in a high resolution version for playing by a disk player. The disk also stores the same content in a lower resolution version for playing by a secondary device such as a Playstation Portable (PSP). The disk can be engaged with the disk player and the lower resolution format transferred to the secondary player through a mechanism such as a removable medium (e.g., a Sony Memory Stick®) or a USB connection or other means in accordance with DRM restrictions on the disk. | 2011-01-27 |
20110019517 | METHOD AND APPARATUS FOR DETERMINING WRITING POWER FOR RECORDING DATA - A method and apparatus for determining an optimal writing power for recording data on a recording medium such as an optical disk, are discussed. The method according to an aspect of the present invention includes (a) performing a plurality of OPC operations on a plurality of areas of the recording medium, the plurality of OPC operations being performed in mutually different manners, the plurality of areas being areas within a power calibration area (PCA) allocated in the recording medium; and (b) determining an optimal writing power for recording data on the recording medium based on writing powers detected via the plurality of OPC operations. | 2011-01-27 |
20110019518 | Device and method for detecting defect signals on an optical disc - A device for detecting defect signals on an optical disc includes a finite state machine (FSM) to control a servo system of an optical disk drive. When the FSM is in a DETECT state and defect signals are greater than thresholds, a detection counter is set to a first predetermined value and the FSM enters an ARM state. In the ARM state, when the detection counter counts zero, the FSM enters a KICK state and the detection counter is set to a second predetermined value. In the KICK state, a flag signal XDFCT is asserted. When the detection counter in the KICK state counts to zero, the FSM enters a WAIT state and the detection counter is set to a third predetermined value. When the flag signal XDFCT is asserted, corresponding servo control signals for the servo system are clamped to a programmable constant voltage. | 2011-01-27 |
20110019519 | OPTICAL DISC RECORDING METHOD AND OPTICAL DISC APPARATUS - This document relates to a method of compensating for a sensitivity variation of a tracking actuator with focusing offset when recording labels on a disc for label recording. A focusing point suitable for the position of an object lens in the circumference direction and/or the radius direction is detected, a tracking sensitivity corresponding to the detected focusing point is obtained based on information about a tracking sensitivity variation according to a focusing point variation, and labels are recorded on a label plane using the detected focusing point and tracking sensitivity. The information may be measured using at least two different types of discs one of which has a distance, between the surface of the disc and a pattern area required for a feed forward servo operation, different from the distance of the other. | 2011-01-27 |
20110019520 | DATA RECORDING EVALUATING METHOD AND OPTICAL DISK RECORDING AND REPRODUCING DEVICE - A novel evaluation index is introduced so as to allow both a total evaluation of data recording and an evaluation of individual detection patterns. A data recording evaluation method includes a step of reproducing the result of data recording performed on an optical disk and identifying a predetermined detection pattern in a reproduction signal, a step of detecting the signal state of the reproduction signal corresponding to the predetermined detection pattern, and a first calculation step of calculating a first recording state evaluation index value based on the detected signal state and a reference condition which is identified from the predetermined detection pattern and adjusted so as to reflect the signal state of the reproduction signal. When there is a plurality of predetermined detection patterns, the method further includes a second calculation step of calculating a second recording state evaluation index value using the first recording state evaluation index value for each of the predetermined detection patterns. Data recording can be evaluated properly using the first and second recording state evaluation index values. | 2011-01-27 |
20110019521 | DEVICE AND METHOD FOR MEASURING VIBRATION CHARACTERISTICS OF HARD DISK SUSPENSION - The signal source generates a signal of a frequency higher than the vibration frequency of the slider of the hard disk drive, and supplies it to one end of the slider and the disk of the hard disk drive. The detector detects a signal output from the other end of the slider and the disk, and outputs a change in the capacitance between the slider and the disk as a voltage when the hard disk drive receives an impact. | 2011-01-27 |
20110019522 | HYBRID LASER DIODE DRIVERS THAT INCLUDE A DECODER - Provided herein are hybrid laser diode drivers (LDDs) that drive a laser diode in response to receiving enable signals from a controller. In accordance with specific embodiments, a hybrid LDD includes a read channel to selectively output a read current, one or more write channel each to selectively output a write current, and an oscillator channel to selectively output an oscillator current. Additionally, in specific embodiments the hybrid LDD includes a decoder that receives the enable signals from the controller, and based on the enable signals, controls timing of the currents output by the read, write and oscillator channels. | 2011-01-27 |
20110019523 | INTEGRATED STANDALONE OPTICAL DISC DUPLICATION AND LABELING SYSTEM - An integrated standalone optical disc duplication and labeling system has an optical disc drive, a main controller and a command module. The optical disc drive is capable of containing an optical disc and performing either a duplication capability or a labeling capability. The main controller is connected to and operates the optical disc drive. The command module is connected to the main controller and is capable of transmitting either a duplication designating command or a labeling designating command to the main controller. The duplication designating command is used to designate the optical disc drive to perform the duplication capability. The labeling designating command is used to designate the optical disc drive to perform the labeling capability. A user acquires a single standalone system that is able to perform both duplication and labeling. | 2011-01-27 |
20110019524 | OPTICAL HEAD AND OPTICAL INFORMATION DEVICE - An optical head comprises: a light source that emits a light beam; an objective lens that condenses, in the form of converging light, the light beam emitted by the light source, onto an information recording medium; a cylindrical lens onto which a reflected light beam that is reflected by the information recording medium is incident, and which generates astigmatism for forming a focus error signal; a light detector that receives the reflected light beam passing through the cylindrical lens; and a holder that holds the cylindrical lens and the light detector. The holder has a first main face and a second main face that extend in directions that intersect the optical axis of the reflected light beam. The cylindrical lens is bonded to the first main face and the light detector is bonded to the second main face. | 2011-01-27 |
20110019525 | HEATER AND MEMORY CELL, MEMORY DEVICE AND RECORDING HEAD INCLUDING THE HEATER - A memory cell includes at least one heater, and at least two leads and a heating element which is formed between at least two leads, a material of the heating element being different from a material of at least two leads such that a location of a hot spot in the heater is controllable based on a polarity of current in the heater and at least one storage medium formed adjacent to at least one heater. | 2011-01-27 |
20110019526 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD FOR CONTROLLING INFORMATION PROCESSING APARATUS, CONTROL PROGRAM OF INFORMATION PROCESSING APPARATUS, AND STORAGE MEDIUM STORING CONTROL PROGRAM OF INFORMATION PROCESSING APPARATUS THEREIN - An optical disk apparatus according to the present invention includes: a sub-data forming section for forming, from data to be recorded into an optical disk ( | 2011-01-27 |
20110019527 | DUAL SIDED OPTICAL STORAGE MEDIA AND METHOD FOR MAKING SAME - A dual sided optical storage medium which comprises a substrate disk having a first information layer readable from one side of the medium through the substrate disk and one or more information layers formed on the non-read side of the first information layer and configured to be read from the other side of the medium. | 2011-01-27 |
20110019528 | REDUCTION OF OUT-OF-BAND EMITTED POWER - OFDM signal transmission of reduced power emission outside a designated transmission bandwidth is disclosed. At least one subcarrier is allocated for an OFDM symbol for non-data. A weighting signal representation is determined based on an initial error signal representation, which is determined from at least part of a first OFDM symbol and part of a second OFDM symbol, the first and second OFDM symbols being consecutive in time. | 2011-01-27 |
20110019529 | INTERFERENCE SUPPRESSION IN UPLINK ACKNOWLEDGEMENT - The present disclosure proposes design of a pico/femto uplink acknowledgement (ACK) channel that improves the interference suppression for pico/femto base stations. The proposed design provides a two-layered cell-separation ACK channel structure for femto/pico cells by using computer generated sequences (CGS) and Discrete Fourier Transform (DFT) spreading. Thereby, ACK channels may be multiplexed across different femto/pico base stations with minimal interference. The proposed scheme is compatible with conventional standards for the base station in the macro cell and does not impose any changes on the macro cell. | 2011-01-27 |
20110019530 | METHOD AND SYSTEM FOR NETWORK COMMUNICATIONS UTILIZING SHARED SCALABLE RESOURCES - Aspects of a method and system for network communications utilizing shared scalable resources are provided. In this regard, networking state information for one or more of a plurality of communication devices may be communicated to a network management device. The network management device may be operable to aggregate the networking state information. The plurality of communication devices may receive aggregated networking state information from the network management device. The plurality of communication devices may route packets based on the received aggregated networking state information. The network management device may be dynamically or manually selected from the plurality of communication devices. The plurality of communication devices may be associated with a sharing domain, and one or more communication devices may be dynamically added to and/or removed from the sharing domain. | 2011-01-27 |
20110019531 | METHOD AND SYSTEM FOR FAULT TOLERANCE AND RESILIENCE FOR VIRTUALIZED MACHINES IN A NETWORK - Hypervisor functions, which may control operations of one or more virtual machines, may be distributed across a plurality of network devices. State information may be stored for the virtual machines on network devices for fault tolerance and resilience. The virtual machines may retrieve stored state information to recover from a fault. The hypervisor may control the storage of the state information. Resources of the network devices may be allocated for fault tolerance and resilience of the virtual machines based on network device parameters, which may include storage capacity, processor usage, access time, communication bandwidth, and/or latency. The state information may include program content, cache content, memory content, and/or register content information, may be stored on a continuous, periodic, or an aperiodic basis, and may be shared among the network devices to enable the processing of data by the virtual machines when a fault occurs, and may be incrementally updated. | 2011-01-27 |
20110019532 | Apparatus and Method for Handling Radio Link Failure in Wireless Communication System - A method and apparatus of handling a radio link failure in a wireless communication system is provided. Upon detecting a radio link failure in a Radio Resource Control (RRC) connected state, a user equipment starts a radio link failure timer of which timer value is selected among at least one timer value for at least one RB. The user equipment attempts a RRC connection re-establishment while the radio link failure timer is running, and transitions to a RRC idle state when the radio link failure timer is expired. | 2011-01-27 |
20110019533 | Network Element Bypass in Computing Computer Architecture - A method and apparatus in accordance with the present invention provides monitoring a self-adjusting multi-tier processing system. At least one computing resource of one of the tiers of the self-adjusting multi-tier processing system is dynamically bypassed based on at least one predetermined criterion, wherein dynamically bypassing energizes or de-energizes a bypass control switch that operates to route data between tiers of the system in a manner that excludes the at least one computing resource. | 2011-01-27 |
20110019534 | Systems and Methods of Multicast Reconfiguration Using Cross-Layer Information - Systems and methods of multicast configuration are provided. A particular method includes detecting a failure in the data network at a first node of a data network. The method also includes determining an alternate route from the first node to a data source of the data network. The alternate route includes a second node as an upstream node. The method further includes determining whether the alternate route would create a loop in the data network. The method includes setting a state of the first node to a waiting-to-join the second node state when the alternate route would create a loop. | 2011-01-27 |
20110019535 | COMPUTER PROGRAM, APPARATUS, AND METHOD FOR MANAGING NETWORK - In response to a route-changing event, original routes on the network are changed to new routes. A destination-reachable range is identified as a range from which packets can reach an information processing device specified by a destination address. Modification of forwarding data is performed for a neighbor communication device which is located outside the destination-reachable range and adjacent to a communication device in the destination-reachable range, so as to enable forwarding of packets to that communication device in the destination-reachable range. The modified forwarding data is then transmitted to the neighbor communication device. The modification made to the forwarding data results in an additional destination-reachable range, which is thus added to the destination-reachable range. Another cycle of processing is then performed on the basis of the expanded destination-reachable range. | 2011-01-27 |
20110019536 | METHOD FOR MANAGING ETHERNET RING NETWORK OF VLAN-BASED BRIDGE - There is provided a method for managing an Ethernet ring network of a VLAN-based bridge that includes: registering a major-ring VID (VLAN ID) in a ring port filtering database of a ring protection link owner node in accordance with a request for registering the major ring VID (VLAN ID) from an ERP (Ethernet Ring Protection) controller mounted on the ring protection link owner node of a major ring; delivering, by the ring protection link owner node, a VID registration message to other nodes which belong to the major ring through a ring port; receiving the VID registration message through the ring port and registering the major ring VID in a ring port filtering database of each node itself, by each node which belongs to the major ring; and delivering, by each node which belongs to the major ring, the VID registration message to other nodes which belong to the major ring through the ring port. | 2011-01-27 |
20110019537 | METHOD OF ROUTING A DATA PACKET VIA A ROUTER IN A PACKET COMMUNICATIONS NETWORK SUPPORTED BY A TRANSPORT NETWORK - The invention relates to a method of routing a data packet via a router ( | 2011-01-27 |