04th week of 2015 patent applcation highlights part 43 |
Patent application number | Title | Published |
20150024486 | EMBRYONIC STEM CELL SPECIFIC MICRORNAS PROMOTE INDUCED PLURIPOTENCY - The methods of the present application describe that introduction of physiologically relevant miRNAs can enhance or modulate somatic cell reprogramming, generating induced pluripotent stem cells (iPS cells). These miRNAs did not further enhance reprogramming in the presence of cMyc. Furthermore, unlike previously described methods of generating iPS cells, such as through the introduction of genetic elements using viruses, the methods of the present invention reduce the risk of activating oncogenes in the iPS cells. The methods of the invention generate iPS cells that can be free of genetic modifications and thus have greater potential for use as therapeutic agents than those generated by existing methods. | 2015-01-22 |
20150024487 | CRYOPRESERVATION STORAGE DEVICE FOR CELL COLLECTION BAG, AND USING METHOD THEREOF - The present invention relates to a cryopreservative device comprising an outer case, one or more layers of space for the cryo-bags, and two or more Teflon cryopreservative bags. The outer case has a cover lip for opening and closing. The Teflon cryopreservative bags are filled with a freezing resistant. In the present invention, the cryo-bags and the Teflon cryopreservative bags are crossly stacked in the cryopreservation device. The Teflon cryopreservative bags are designed to directly contact with the cryo-bags in order to obtain the effect of slow cell freezing. | 2015-01-22 |
20150024488 | NUCLEIC ACID COMPLEX - The present invention relates to a complex comprising a cationic block copolymer and a nucleic acid, the cationic block copolymer having at least a tri-block structure comprising a cationic block and two hydrophilic blocks, or a hydrophilic block and two cationic blocks. | 2015-01-22 |
20150024489 | Device for enhancing immunostimulatory capabilities of T-cells - T-cells are generated with enhanced immunostimulatory capabilities for use in self therapy treatment protocols, by utilizing a biodegradable device with a biodegradable support that has one or more agents that are reactive to T-cell surface moieties. The biodegradable devices are mixed with the T-cells sufficiently so that the one or more agents cross-link with the T-cells' surface moieties and deliver a signal to the T-cells to enhance immunostimulatory capabilities. | 2015-01-22 |
20150024490 | CHEMICALLY LABILE PEPTIDE-PRESENTING SURFACES FOR CELLULAR SELF-ASSEMBLY - Methods of cell culture using patterned SAM arrays are disclosed. Advantageously, the disclosed methods use SAM arrays presenting adhesion peptides to grow confluent monolayers that can invaginate to form an embryoid body. | 2015-01-22 |
20150024491 | NEURONAL CULTURE MEDIUM AND METHOD FOR PRODUCING IN VIVO-LIKE AND ENHANCED SYNAPTOGENESIS NEURON MODEL - An object of the present invention is to develop and provide a method for producing a neuron model having reproduced in vivo properties by improving a cell culture medium composition and a cell culture medium composition necessary for the production of such neuron model. According to the present invention, cell culture is carried out in vitro using a medium for producing in vivo-like and enhanced synaptogenesis neuron model supplemented with a medium supplement for producing in vivo-like and enhanced synaptogenesis neuron model comprising any or any combination of NT-3, potassium or a salt thereof, and FGF2. | 2015-01-22 |
20150024492 | Cell Expansion System and Methods of Use - Cell expansion systems and methods of use are provided. The cell expansion systems generally include a hollow fiber cell growth chamber, and first and second circulation loops (intracapillary loops and extracapillary loops) associated with the interior of the hollow fibers and exterior of the hollow fibers, respectively. Detachable flow circuits and methods of expanding cells are also provided. | 2015-01-22 |
20150024493 | METHOD FOR PREPARING A PATTERNED SUBSTRATE AND USE THEREOF IN IMPLANTS FOR TISSUE ENGINEERING - A method for preparing a patterned substrate is provided. The method includes melt-spinning at least one biocompatible polymer to form fibers; collecting the fibers on a substrate such that the fibers are aligned on the substrate; and applying a binding agent to the aligned fibers to bond the fibers into the aligned arrangement to obtain the patterned substrate in form of an aligned fiber mat. Use of the patterned substrate in an implant for tissue engineering is also provided. | 2015-01-22 |
20150024494 | DEFINED CELL CULTURING SURFACES AND METHODS OF USE - In one aspect, there is provided a cell culturing substrate including:
| 2015-01-22 |
20150024495 | DEVICE AND METHOD FOR ENGINEERING LIVING TISSUES - A device for assembling aggregations of adherent cells includes a gripper moveable within an assembly vessel that fixes aggregations of adherent cells at a membrane of the gripper and, by movement of the gripper, assembles aggregations of cells on a separate membrane within the vessel, thereby creating a three-dimensional assembly of aggregations of cells that fuse and can be employed in surgical procedures as a unitary tissue of adherent cells. The aggregations of cells, as assembled, can assume three-dimensional configurations distinct from any one of the component aggregations of cells assembled. | 2015-01-22 |
20150024498 | CLDN5 Mini-Promoters - Isolated polynucleotides comprising a CLDN5 mini-promoter are provided. The mini-promoter may be operably linked to an expressible sequence, e.g. reporter genes, genes encoding a polypeptide of interest, regulatory RNA sequences such as miRNA, siRNA, anti-sense RNA, etc., and the like. In some embodiments a cell comprising a stable integrant of an expression vector is provided, which may be integrated in the genome of the cell. The mini-promoter may also be provided in a vector, for example in combination with an expressible sequence. The polynucleotides find use in a method of expressing a sequence of interest, e.g. for identifying or labeling cells, monitoring or tracking the expression of cells, etc. | 2015-01-22 |
20150024499 | MODIFIED CASCADE RIBONUCLEOPROTEINS AND USES THEREOF - A clustered regularly interspaced short palindromic repeat (CRISPR)-associated complex for adaptive antiviral defence (Cascade); the Cascade protein complex comprising at least CRISPR-associated protein subunits Cas7, Cas5 and Cas6 which includes at least one subunit with an additional amino acid sequence possessing nucleic acid or chromatin modifying, visualising, transcription activating or transcription repressing activity. The Cascade complex with additional activity is combined with an RNA molecule to produce a ribonucleoprotein complex. The RNA molecule is selected to have substantial complementarity to a target sequence. Targeted ribonucleoproteins can be used as genetic engineering tools for precise cutting of nucleic acids in homologous recombination, non-homologous end joining, gene modification, gene integration, mutation repair or for their visualisation, transcriptional activation or repression. A pair of ribonucleotides fused to FokI dimers may be used to generate double-strand breakages in the DNA to facilitate these applications in a sequence-specific manner. | 2015-01-22 |
20150024500 | METHODS AND COMPOSITIONS FOR PRODUCING DOUBLE ALLELE KNOCK OUTS - The present invention provides a method and compositions utilizing the CRISPR system to disrupt a target gene in eukaryotic cells to produce double allele knock outs. The method finds use in producing afucosylated antibodies with enhanced ADCC activity. | 2015-01-22 |
20150024501 | INTEGRATED CHEMICAL INDICATOR DEVICE - A chemical indicator device for use in detecting exposure to an oxidizing agent, such as hydrogen peroxide, comprising a substrate or support upon which is disposed a chemical indicator composition (ink) for detecting an oxidizing agent, such as hydrogen peroxide. The chemical indicator composition further comprises an indicator dye that achieves a distinct range of different color changes with clear transitions between colors, upon exposure to different doses of the oxidizing agent, thus allowing for both a qualitative and semi-quantitative assessment of exposure to the agent. | 2015-01-22 |
20150024502 | METHODS OF STABILIZING TOTAL ORGANIC CARBON (TOC) LEVELS IN NON-ACIDIFIED STANDARDS FOR TOC ANALYZERS AT ROOM TEMPERATURE - Methods for stabilizing reference standards used in total organic carbon (TOC) analysis of water and pharmaceutical samples are disclosed. The methods include adding a preservative to TOC reference standards. The preservative is selected from the group consisting of copper (II) sulfate and hydrogen sulfite. Compositions of the stabilized reference standards are also disclosed. | 2015-01-22 |
20150024503 | METHOD OF ANALYZING HEMOGLOBINS - An object of the present invention is to provide a method for analyzing hemoglobins which can accurately separate hemoglobins in a short time by liquid chromatography. | 2015-01-22 |
20150024504 | Methods and Compositions for Detection and Analysis of Polynucleotides Using Light Harvesting Multichromophores - Methods, compositions and articles of manufacture for assaying a sample for a target polynucleotide are provided. A sample suspected of containing the target polynucleotide is contacted with a polycationic multichromophore and a sensor polynucleotide complementary to the target polynucleotide. The sensor polynucleotide comprises a signaling chromophore to receive energy from the excited multichromophore and increase emission in the presence of the target polynucleotide. The methods can be used in multiplex form. Kits comprising reagents for performing such methods are also provided. | 2015-01-22 |
20150024505 | APPARATUS FOR EVALUATING CARBONATE SOLUBILITY - A method and apparatus of determining solubility of compounds at non-ambient conditions is disclosed. The compound of interest is placed in a reaction vessel which can withstand the non-ambient conditions, and is allowed to react with an acid at those conditions for a pre-determined time. The reaction is quickened thereby stopping the reaction, after which the conditions are permitted to return to ambient and the solubility of the compound is then determined gravimetrically. | 2015-01-22 |
20150024506 | RELEASE REAGENT FOR VITAMIN D COMPOUNDS - A reagent composition for releasing vitamin D compounds bound to vitamin D-binding protein, an in vitro method for the detection of a vitamin D compound in which the vitamin D compound is released from vitamin D-binding protein by the use of this reagent composition and the reagent mixture obtained in this manner. The use of the disclosed reagent composition to release vitamin D compounds as well as a kit for detecting a vitamin D compound which contains the reagent composition for releasing vitamin D compounds in addition to common detecting reagents. | 2015-01-22 |
20150024507 | BIOMARKER SENSING BASED ON NANOFLUIDIC AMPLIFICATION AND RESONANT OPTICAL DETECTION - Provided is a sensor platform that includes a substrate, a plurality of nanochannels disposed on the substrate, and a plurality of electrodes, a waveguide disposed on the substrate and an analysis chamber and a reference chamber disposed on the substrate. Each electrode extends substantially across a width of the plurality of nanochannels. At least one analysis optical resonator is disposed in the analysis chamber and is optically coupled to at least a portion of the waveguide. The at least one analysis optical resonator is in fluid communication with at least one of the plurality of nanochannels. At least one reference optical resonator is disposed in the reference chamber and is optically coupled to at least a portion of the waveguide. The at least one reference optical resonator is in fluid communication with at least one other of the plurality of nanochannels. | 2015-01-22 |
20150024508 | APPARATUS AND METHOD FOR COMPENSATING pH MEASUREMENT ERRORS DUE TO PRESSURE AND PHYSICAL STRESSES - A pH sensing apparatus includes an ion-sensing cell that includes a first half-cell including a first Ion-Sensitive Field Effect Transistor (ISFET) exposed to a surrounding solution; and a second reference half-cell exposed to the surrounding solution. The pH sensing apparatus further includes a pressure sensitivity compensation loop including a Non Ion-Sensitive Field Effect Transistor (NISFET). The pH sensing apparatus is configured to compensate for at least one of pressure and physical stresses using signals from the ion-sensing cell and feedback from the pressure sensitivity compensation loop. The pH sensing cell further includes a processing device configured to calculate a final pH reading compensated to minimize the at least one of pressure and physical stresses. | 2015-01-22 |
20150024509 | METHOD AND APPARATUS FOR MEASURING CHEMICAL ION CONCENTRATION USING A FEEDBACK- CONTROLLED TITRATOR - There is provided a method and device for measuring an ion concentration of a sample. The method comprises exposing a chemical sensor to the sample to provide an electrical output signal | 2015-01-22 |
20150024510 | PERFORMING CHEMICAL REACTIONS AND/OR IONIZATION DURING GAS CHROMATOGRAPHY-MASS SPECTROMETRY RUNS - A gas chromatography-mass spectrometry (GC-MS) method that includes performing a first GC-MS run on a sample using a gas chromatography-mass spectrometry system. Performing the first GC-MS nm includes i) passing a first flow of a carrier gas carrying a first portion of the sample through a gas chromatograph to provide a first effluent; ii) generating first ions under protonation conditions by passing the first effluent through an atmospheric pressure ionization source; iii) passing the first ions through a mass spectrometer; and iv) recording first GC-MS data for the first ions. The method also include performing a second GC-MS run on the sample using the gas chromatography-mass spectrometry system. | 2015-01-22 |
20150024511 | FUNCTIONALIZED LIPID MODIFICATION OF SOLID PHASE SURFACES FOR USE IN CHROMATOGRAPHY - A solid phase for use in separation has been modified using an aqueous phase adsorption of a headgroup-modified lipid to generate analyte specific surfaces for use as a stationary phase in separations such as high performance liquid chromatography (HPLC) or solid phase extraction (SPE). The aliphatic moiety of the lipid adsorbs strongly to a hydrophobic solid surface, with the hydrophilic and active headgroups orienting themselves toward the more polar mobile phase, thus allowing for interactions with the desired solutes. The surface modification approach is generally applicable to a diversity of selective immobilization applications such as protein immobilization clinical diagnostics and preparative scale HPLC as demonstrated on capillary-channeled fibers, though the general methodology could be implemented on any hydrophobic solid support material. | 2015-01-22 |
20150024512 | METHOD FOR SELECTIVELY QUANTIFYING A-BETA AGGREGATES - The invention relates to methods for selectively quantifying A-beta aggregates, comprising the immobilization of anti-A-beta antibodies on a substrate, application of the sample to be tested onto the substrate, addition of probes labeled for detection, which mark these by specific binding to A-beta aggregates and detection of the marked aggregates. | 2015-01-22 |
20150024513 | NOVEL METHOD FOR DETECTING ANTIGEN, AND APPARATUS USING SAME - The present invention provides a method for detecting an antigen in an analysis sample, the method including: (a) contacting an analysis sample with a detection antibody with which a marker generating a detectable signal is combined and which specifically binds to the antigen; (b) contacting a capture antibody with the resultant product of step (a), the capture antibody specifically binding to an antigen to be detected; (c) contacting the detection antibody, with which the marker generating a detectable signal is combined, with a reference substance which is bound to a surface of a solid substrate and which includes an epitope to which the detection antibody specifically binds; (d) measuring signals generated from the markers of the resultant product of step (b) and the resultant product of step (c); and (e) analyzing the measured signals to determine the presence or absence and amount of the antigen in the analysis sample. The method for detecting an antigen of the present invention can control the flow and the reaction time of an analysis sample, thereby improving sensitivity and minimizing the influences by the concentration of the analysis sample or the temperature of the detection reaction, and thus improving stability, reliability, and reproducibility of data, when compared with the conventional method for detecting an antigen. Accordingly, the method and apparatus for detecting an antigen of the present invention can be easily operated without specialized skills, thereby instantly obtaining the presence or absence and amount of detection antigen in the analysis sample through on-site diagnosis. | 2015-01-22 |
20150024514 | METHOD AND DEVICE FOR DETECTING ANALYTES - The present invention relates to a method for determining analytes and to a device suitable for this purpose. | 2015-01-22 |
20150024515 | SYSTEMS, METHODS, AND APPARATUS FOR MINIMIZING CROSS COUPLED WAFER SURFACE POTENTIALS - This disclosure describes systems, methods, and apparatus for reducing a DC bias on a substrate surface in a plasma processing chamber due to cross coupling of RF power to an electrode coupled to the substrate. This is brought about via tuning of a resonant circuit coupled between the substrate and ground based on indirect measurements of harmonics of the RF field level at a surface of the substrate. The resulting reduction in DC bias allows a lower ion energy than possible without this resonant circuit and tuning thereof. | 2015-01-22 |
20150024516 | Electrostatic Phosphor Coating Systems and Methods for Light Emitting Structures and Packaged Light Emitting Diodes Including Phosphor Coating - Methods are disclosed including applying a layer of binder material onto an LED structure. A luminescent solution including an optical material suspended in a solution is atomized using a flow of pressurized gas, and the atomized luminescent solution is sprayed onto the LED structure including the layer of binder material using the flow of pressurized gas. | 2015-01-22 |
20150024517 | PLASMA ETCHER CHUCK BAND - A plasma etch tool includes a wafer chuck with a chuck base and at least one functional component layer attached to the chuck base. A perimeter of the functional component layer has a polymer material permanently attached to it that extends to within 2 millimeters of a top surface of the chuck. The top surface of the wafer chuck contacts a bottom surface of a semiconductor wafer during an etch process for forming an integrated circuit. The polymer material is protected from an etch ambient by a plasma etcher chuck band installed around the perimeter of the functional component layer, extending over a portion of the chuck base. An integrated circuit may be formed by installing the plasma etcher chuck band on the chuck of the plasma etch tool, and subsequently performing an etch process in the plasma etch tool on a semiconductor wafer containing the partially formed integrated circuit. | 2015-01-22 |
20150024518 | METHOD OF FORMING A SELECTIVELY ADJUSTABLE GATE STRUCTURE - The present disclosure relates to a method of forming a gate structure that can be selectively adjusted to reduce critical-dimension (CD) variations. In some embodiments, the method is performed by forming a gate structure having a first length over a semiconductor substrate. The first length of the gate structure is measured and compared to a target length. If the first length differs from the target length by an amount that is greater than a threshold value, the first length is adjusted to converge upon the target length. By selectively adjusting the length of the gate structure, critical-dimension (CD) variations can be reduced, thereby increasing yield and reducing cost. | 2015-01-22 |
20150024519 | METHOD FOR PRODUCING ORGANIC ELECTROLUMINESCENT ELEMENT - A method for producing an organic electroluminescent element including: a first producing process of stacking at least a first electrode layer, a dielectric layer, and a second electrode layer on a substrate in this order, the organic electroluminescent element having a light-emitting portion that is in contact with an inner surface of a concave portion formed to penetrate the dielectric layer; measuring a temperature distribution of the organic electroluminescent element while causing the light-emitting portion to emit light by applying a voltage to the first electrode layer and the second electrode layer of the organic electroluminescent element produced in the first producing process, and obtaining temperature irregularity information of the organic electroluminescent element; and a second producing process of adjusting concave portion density on the basis of the temperature irregularity information, and reducing temperature irregularity of the organic electroluminescent element. | 2015-01-22 |
20150024520 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND MANUFACTURING DEVICE - A marker which is a reference of a coordinate position defining a region of a chip that is manufactured in a semiconductor substrate is formed. A crystal defect on the semiconductor substrate is detected. The coordinate position of the detected crystal defect is detected on the basis of the marker. Therefore, it is possible to detect the position of a semiconductor chip including the crystal defect among the semiconductor chips manufactured on the semiconductor substrate. As a result, it is possible to easily detect the position of the semiconductor device including the position of the crystal defect on the semiconductor substrate. | 2015-01-22 |
20150024521 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - There is provided a plasma processing apparatus which compares a plurality of patterns detected using an interference light intensity pattern using a wavelength from at least one preset film of the plurality of film layers as a parameter and an intensity pattern using a wavelength of light from the other film as a parameter and an light intensity pattern from inside the processing chamber which is detected during processing of the film to be processed; and compares a film thickness corresponding to one of the plurality of patterns having a minimum difference obtained by the comparison and a target film thickness; and determines that the thickness of the film to be processed reaches the target film thickness. | 2015-01-22 |
20150024522 | ORGANOMETAL MATERIALS AND PROCESS - Coating compositions are used to deposit films on electronic device substrates, which films are subjected to conditions that form an oxymetal precursor material layer on a matrix precursor material layer, and then such layers are cured to form a cured oxymetal layer disposed on a cured matrix layer. | 2015-01-22 |
20150024523 | A METHOD FOR PRODUCING AN RFID TRANSPONDER BY ETCHING - A method for producing a radio frequency identification transponder includes
| 2015-01-22 |
20150024524 | Methods for Manufacturing Isolated Deep Trench and High-Voltage LED Chip - A method for manufacturing a deep isolation trench ( | 2015-01-22 |
20150024525 | LED LIGHTING APPARATUS AND METHOD FOR FABRICATING WAVELENGTH CONVERSION MEMBER FOR USE IN THE SAME - A method of forming a light-emitting diode (LED) lighting apparatus, including forming an LED on a printed circuit board, and forming a wavelength conversion member on the LED, the wavelength conversion member being spaced apart from the LED. Forming the wavelength conversion member includes transfer molding a wavelength conversion layer on a light-transmitting member, and disposing the wavelength conversion member on the LED, the wavelength conversion layer being disposed between the LED and the light-transmitting member. | 2015-01-22 |
20150024526 | OPTICAL DEVICE STRUCTURE USING GAN SUBSTRATES AND GROWTH STRUCTURES FOR LASER APPLICATIONS - Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed. | 2015-01-22 |
20150024527 | METHOD FOR PRODUCING SPOT-SIZE CONVERTOR - A method for producing a spot-size convertor includes the steps of preparing a substrate; forming a stacked semiconductor layer including first and second core layers on the substrate; forming a mesa structure by etching the stacked semiconductor layer using a first mask, the mesa structure including a side surface and a bottom portion of the first core layer; forming a protective mask covering the side surface; etching the bottom portion using the protective mask to form a top mesa; and forming a bottom mesa by etching the second core layer using a second mask. The top mesa includes the first core layer and a portion having a mesa width gradually reduced in a first direction of a waveguide axis. The bottom mesa includes the second core layer and a portion having a mesa width gradually reduced in a second direction opposite to the first direction. | 2015-01-22 |
20150024528 | APPARATUS AND METHOD FOR MANUFACTURING ORGANIC LIGHT-EMITTING DIODE DISPLAY - Provided are an apparatus for manufacturing an OLED display and a method of manufacturing OLED display. According to another aspect of the present invention, there is provided the method of manufacturing an OLED display which includes placing a substrate having rows and columns of pixels through on a stage, ejecting organic light-emitting ink to the pixels through on the substrate by using a print head placed above the stage, and sequentially covering pixels through coated with the organic light-emitting ink with a cover plate placed above the stage. | 2015-01-22 |
20150024529 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a base substrate, a data line to transmit a data signal, a gate line disposed on the base substrate and insulated from the data line, and a pixel electrically connected to the gate line and/or the data line via a thin film transistor. At least one of the data line and the gate line includes a lower conductive layer and an upper conductive layer. The lower conductive layer includes a zinc oxide doped with a doping material. The upper conductive layer is disposed on the lower conductive layer and includes a copper, and the upper conductive layer includes crystals in which growth directions are dispersed by the doping material. | 2015-01-22 |
20150024530 | METHOD OF MANUFACTURING AN OXIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A DISPLAY DEVICE HAVING THE SAME - Disclosed is a method of manufacturing an oxide semiconductor device, including: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming an active pattern on the gate insulating layer; forming a first mask pattern on the gate insulating layer and the active pattern; forming an insulating interlayer on the gate insulating layer, the active pattern, and the first mask pattern; forming a second mask pattern on the insulating interlayer, the second mask pattern comprising an opening that exposes a region where the first mask pattern is formed; forming contact holes exposing portions of the active pattern by patterning the insulating interlayer using the first mask pattern and the second mask pattern; and forming a source electrode and a drain electrode on the gate insulating layer by filling the contact holes, the drain electrode spaced apart from the source electrode. | 2015-01-22 |
20150024531 | P-TYPE DOPING LAYERS FOR USE WITH LIGHT EMITTING DEVICES - A light emitting diode (LED) comprises an n-type Group III-V semiconductor layer, an active layer adjacent to the n-type Group III-V semiconductor layer, and a p-type Group III-V semiconductor layer adjacent to the active layer. The active layer includes one or more V-pits. A portion of the p-type Group III-V semiconductor layer is in the V-pits. A p-type dopant injection layer provided during the formation of the p-type Group III-V layer aids in providing a predetermined concentration, distribution and/or uniformity of the p-type dopant in the V-pits. | 2015-01-22 |
20150024532 | ELECTRICALLY CONDUCTIVE POLYMERS - An electrically conductive film suited to use as a transparent anode, a method of forming the film, and an electronic device comprising the film are disclosed. The device includes a conductive polymer electrode defining first and second surfaces and having an electrical conductivity gradient between the first and second surfaces. A second electrode is spaced from the second surface by at least one organic material layer, such as a light emitting layer. | 2015-01-22 |
20150024533 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes depositing a light reflecting layer over a substrate. The method also includes forming a protection layer over the light reflecting layer. The method further includes forming an anti-reflective coating (ARC) layer over the protection layer. The method additionally includes forming an opening in the ARC layer, the protection layer and the light reflecting layer exposing the substrate. The method also includes removing the ARC layer in a wet solution comprising H2O2, the ARC layer being exposed to the H | 2015-01-22 |
20150024534 | TWO DEGREE OF FREEDOM DITHERING PLATFORM FOR MEMS SENSOR CALIBRATION - Systems and methods for two degree of freedom dithering for micro-electromechanical system (MEMS) sensor calibration are provided. In one embodiment, a method for a device comprises forming a MEMS sensor layer, the MEMS sensor layer comprising a MEMS sensor and an in-plane rotator to rotate the MEMS sensor in the plane of the MEMS sensor layer. Further, the method comprises forming a first and second rotor layer and bonding the first rotor layer to a top surface and the second rotor layer to the bottom surface of the MEMS sensor layer, such that a first and second rotor portion of the first and second rotor layers connect to the MEMS sensor. Also, the method comprises separating the first and second rotor portions from the first and second rotor layers, wherein the first and second rotor portions and the MEMS sensor rotate about an in-plane axis of the MEMS sensor layer. | 2015-01-22 |
20150024535 | SEMICONDUCTOR SENSOR DEVICE WITH FOOTED LID - A semiconductor sensor device is packaged using a footed lid instead of a pre-molded lead frame. A semiconductor sensor die is attached to a first side of a lead frame. The die is then electrically connected to leads of the lead frame. A gel material is dispensed onto the sensor die. The footed lid is attached to the substrate such that the footed lid covers the sensor die and the electrical connections between the die and the lead frame. A molding compound is then formed over the substrate and the footed lid such that the molding compound covers the substrate, the sensor die and the footed lid. | 2015-01-22 |
20150024536 | MEMS Device and Method of Manufacturing a MEMS Device - MEMS devices with a rigid backplate and a method of making a MEMS device with a rigid backplate are disclosed. In one embodiment, a device includes a substrate and a backplate supported by the substrate. The backplate includes elongated protrusions. | 2015-01-22 |
20150024537 | ULTRASONIC TRANSDUCER, BIOLOGICAL SENSOR, AND METHOD FOR MANUFACTURING AN ULTRASONIC TRANSDUCER - A method for manufacturing an ultrasonic transducer includes: forming a piezoelectric element by laminating a lower electrode, a piezoelectric body, and an upper electrode on a first face of a support film; affixing a reinforcing substrate that covers the piezoelectric element to the first face of the support film; forming a photosensitive resin substrate to a second face of the support film that is on an opposite side from the first face; forming an opening in the resin substrate by irradiating the resin substrate with light; and removing the reinforcing substrate. | 2015-01-22 |
20150024538 | VAPOR DISPENSING APPARATUS AND METHOD FOR SOLAR PANEL - An apparatus includes a manifold coupled to a vapor source, the manifold having a plurality of nozzles, an inner cylinder, and an outer cylinder containing the inner cylinder with a space defined between the inner and outer cylinders. One of the inner cylinder or outer cylinder is rotatable with respect to the other of the inner cylinder or outer cylinder. The outer cylinder has an inlet coupled to the manifold to receive vapor from the nozzles. The outer cylinder has an outlet for dispensing the vapor. | 2015-01-22 |
20150024539 | FORMULATION OF COLLOIDAL TITANIUM-OXIDE SOLUTIONS COMPOSITION FOR COATING AND PRINTING METHODS, AND IMPROVEMENT OF THE OUTPUT AND LIFESPAN OF ORGANIC P-I-N/N-I-P PHOTOVOLTAIC CELLS - The invention relates to a method for preparing a colloidal nanoparticle solution, including: (a) dissolving a titanium-oxide precursor, referred to as a precursor, in one or more solvents, referred to as precursor solvents; and (b) chemically converting, preferably by means of hydrolysis, said titanium-oxide precursor and said precursor solvent into a colloidal-solution solvent so as to form titanium-oxide nanoparticles that are dispersed in the colloidal-solution solvent, said colloidal solution having a dynamic viscosity of between 4 and 54 cP at 20° C. and 101,325 Pa. | 2015-01-22 |
20150024540 | Device and Method for Producing Thin Films - In an apparatus for producing thin layers on substrates for solar cell production, wherein the thin layers are applied by an APCVD process at temperatures of more than 250° C., the substrates are conveyed on a horizontal conveyor path and coated by means of an APCVD coating in continuous operation. The conveyor path has conveyor rollers, which consist of a temperature-resistant, non-metallic material, preferably of ceramic. A heating device and/or a purge gas feeding device is/are arranged on that side of the conveyor path which is remote from the coating apparatus. | 2015-01-22 |
20150024541 | METHOD FOR FABRICATING PHOTOVOLTAIC CELLS WITH PLATED CONTACTS - The disclosed technology relates generally to photovoltaic cells, and more particularly to photovoltaic cells with plated metal contacts. In one aspect, a method of fabricating a photovoltaic cell with a metal contact pattern on a surface of a semiconductor substrate includes locally smoothening portions of the surface of the semiconductor substrate by using a first laser, at predetermined locations. The method additionally includes doping the surface of the semiconductor substrate to form an emitter region. The method additionally includes forming a dielectric layer on the surface of the semiconductor substrate, and subsequently forming openings through the dielectric layer by using a second laser, thereby locally exposing the underlying surface of the semiconductor substrate at the predetermined locations. The method further includes forming metal contacts at exposed regions of the surface of the semiconductor substrate by plating. | 2015-01-22 |
20150024542 | SEGMENTED THIN FILM SOLAR CELLS - Use of chemical mechanical polishing (CMP) and/or pure mechanical polishing to separate sub-cells in a thin film solar cell. In one embodiment the CMP is only used to separate the active, thin film layer into sub-cells, with scribing still being used to achieve sub-cell separation in conductive layers above and below the active, thin film layer. Also, the active layer may be placed over a series of protrusions so that the CMP removes the active layer that is over the protrusion, while leaving intact the flat, planar portions of the active layer. In this way, the removed active layer, from over the protrusions then becomes the division between sub-cells in the active layer. | 2015-01-22 |
20150024543 | Preparation of Copper Selenide Nanoparticles - A process for producing copper selenide nanoparticles by effecting conversion of a nanoparticle precursor composition comprising copper and selenide ions to the material of the copper selenide nanoparticles in the presence of a selenol compound. Copper selenide-containing films and CIGS semiconductor films produced using copper selenide as a fluxing agent are also disclosed. | 2015-01-22 |
20150024544 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to manufacture a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. A crystalline oxide semiconductor film is formed, without performing a plurality of steps, as follows: by utilizing a difference in atomic weight of plural kinds of atoms included in an oxide semiconductor target, zinc with low atomic weight is preferentially deposited on an oxide insulating film to form a seed crystal including zinc; and tin, indium, or the like with high atomic weight is deposited on the seed crystal while causing crystal growth. Further, a crystalline oxide semiconductor film is formed by causing crystal growth using a seed crystal with a hexagonal crystal structure including zinc as a nucleus, whereby a single crystal oxide semiconductor film or a substantially single crystal oxide semiconductor film is formed. | 2015-01-22 |
20150024545 | STACKED PACKAGE STRUCTURE AND METHOD OF MANUFACTURING A PACKAGE-ON-PACKAGE DEVICE - A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package. | 2015-01-22 |
20150024546 | System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack - A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside. | 2015-01-22 |
20150024547 | EMI Package and Method for Making Same - An integrated circuit structure includes a substrate, a photosensitive molding on a first side of the substrate, a via formed in the molding, and a conformable metallic layer deposited over the first side of the substrate and in the via. A through via may be formed through the substrate aligned with the via in the molding with an electrically conductive liner deposited in the through via in electrical contact with the conformable metallic layer. The integrated circuit structure may further include a connector element such as a solder ball on an end of the through via on a second side of the substrate opposite the first side. The integrated circuit structure may further include a die on the first side of the substrate in electrical contact with another through via or with a redistribution layer. | 2015-01-22 |
20150024548 | COMPUTER READABLE MEDIUM ENCODED WITH A PROGRAM FOR FABRICATING 3D INTEGRATED CIRCUIT DEVICE USING INTERFACE WAFER AS PERMANENT CARRIER - A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer. | 2015-01-22 |
20150024549 | ALIGNMENT OF INTEGRATED CIRCUIT CHIP STACK - The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. | 2015-01-22 |
20150024550 | METHODS FOR PRODUCING SEMICONDUCTOR DEVICES - A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier. | 2015-01-22 |
20150024551 | SEMICONDUCTOR CHIP BONDING APPARATUS AND METHOD OF FORMING SEMICONDUCTOR DEVICE USING THE SAME - A method of manufacturing a semiconductor device includes: providing a first substrate that includes internal wiring, the first substrate including an array of chip mounting regions that includes a first chip mounting region; placing the first substrate on a first carrier line; providing a first semiconductor chip; placing the first semiconductor chip on a first moveable tray; vertically aligning the first chip mounting region of the first substrate with the first semiconductor chip, and performing initial bonding of the first semiconductor chip to the first chip mounting region of the first substrate; and performing subsequent bonding on the initially-bonded first semiconductor chip and first mounting region of the first substrate, thereby more strongly bonding the first semiconductor chip to the first substrate at the first mounting region. The initial bonding occurs after performing a subsequent bonding of at least one other semiconductor chip on the first substrate. | 2015-01-22 |
20150024552 | SUBSTRATE, CHIP PACKAGE AND METHOD FOR MANUFACTURING SUBSTRATE - A substrate includes a first wiring substrate, a second wiring substrate, and an adhesive sheet. The first wiring substrate includes a number of first connecting pads and a first penetrating room. The second wiring substrate includes a number of second connecting pads. The adhesive sheet includes a number of through holes and a second penetrating room. The through holes are filled with a conducting material. The adhesive sheet and the first wiring substrate are orderly pressed on the second wiring substrate. The conducting material is connected to the first connecting pads and the second connecting pads. The first penetrating room of the first wiring substrate and the second penetrating room of the adhesive sheet cooperatively form a receiving recess. | 2015-01-22 |
20150024553 | POWER MODULE PACKAGE - An integrated power module includes a substantially planar insulated metal substrate having at least one cut-out region; at least one substantially planar ceramic substrate disposed within the cut-out region, wherein the ceramic substrate is framed on at least two sides by the insulated metal substrate, the ceramic substrate including a first metal layer on a first side and a second metal layer on a second side; at least one power semiconductor device coupled to the first side of the ceramic substrate; at least one control device coupled to a first surface of the insulated metal substrate; a power overlay electrically connecting the at least one semiconductor power device and the at least one control device; and a cooling fluid reservoir operatively connected to the second metal layer of the at least one ceramic substrate, wherein a plurality of cooling fluid passages are provided in the cooling fluid reservoir. | 2015-01-22 |
20150024554 | Chip To Package Interface - In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip disposed within an encapsulant, and a first coil disposed in the semiconductor chip. A dielectric layer is disposed above the encapsulant and the semiconductor chip. A second coil is disposed above the dielectric layer. The first coil is magnetically coupled to the second coil. | 2015-01-22 |
20150024555 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on which a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration. | 2015-01-22 |
20150024556 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes an input electrode provided on a front surface of a semiconductor substrate of a first conductivity type and an output electrode provided on a rear surface of the semiconductor substrate. The device has reduced deterioration of electrical characteristics when manufactured by a method including introducing impurities into the rear surface of the semiconductor substrate; activating the impurities using a first annealing process to form a first semiconductor layer, which is a contact portion in contact with the output electrode, in a surface layer of the rear surface; radiating protons to the rear surface; and activating the protons radiated using a second annealing process to form a second semiconductor layer of the first conductivity type, which has a higher impurity concentration than the semiconductor substrate, in a region that is deeper than the first semiconductor layer from the rear surface of the semiconductor substrate. | 2015-01-22 |
20150024557 | SEMICONDUCTOR DEVICE HAVING LOCAL BURIED OXIDE - There is set forth herein a semiconductor device fabricated on a bulk wafer having a local buried oxide region underneath a channel region of a MOSFET. In one embodiment the local buried oxide region can be self-aligned to a gate, and a source/drain region can be formed in a bulk substrate. A local buried oxide region can be formed in a semiconductor device by implantation of oxygen into a bulk region of the semiconductor device followed by annealing. | 2015-01-22 |
20150024558 | ASYMMETRICAL REPLACEMENT METAL GATE FIELD EFFECT TRANSISTOR - An asymmetrical field effect transistor (FET) device includes a semiconductor substrate, a buried oxide layer disposed on the semiconductor substrate, an extended source region disposed on the buried oxide layer and a drain region disposed on the buried oxide layer. The asymmetrical FET device also includes a silicon on insulator region disposed between the extended source region and the drain region and a gate region disposed above the extended source region and the silicon on insulator region. | 2015-01-22 |
20150024559 | SYSTEM AND METHOD FOR INTEGRATED CIRCUITS WITH CYLINDRICAL GATE STRUCTURES - A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern. A method is provided for manufacturing the integrate circuits system with a GAAC transistor including forming an SOI layer wire pattern on the buried oxide layer of an SOI wafer; forming a cavity underneath the middle section of the wire pattern and shaping the middle section to cylindrically shaped channel; forming a gate electrode surrounding the cylindrical channel region with an interposed gate dielectric layer, the gate electrode being positioned on the buried oxide layer vertically towards the wire pattern; forming the source/drain regions at the two opposite end sections of the wire pattern on either sides of the gate electrode and channel. | 2015-01-22 |
20150024560 | GATE ENCAPSULATION ACHIEVED BY SINGLE-STEP DEPOSITION - When forming spacer structures enclosing a gate electrode structure of a transistor, a common problem is given by the thickness variation of the spacer structure obtained as a result of a first deposition process performed in a first chamber and a second, subsequent process performed in a second chamber. The present disclosure provides a method for forming spacers of a well-defined thickness. The method relies on a single deposition step performed by means of an atomic layer deposition. The deposition is performed in two stages performed at different temperatures. | 2015-01-22 |
20150024561 | METHOD FOR FABRICATING A FINFET IN A LARGE SCALE INTEGRATED CIRCUIT - Systems and methods of fabricating a FinFET in large scale integrated circuit are disclosed. One illustrative method relates to a dummy gate process, wherein the fin structure is only formed in the gate electrode region by performing a photolithography process and an etching of a first dummy gate on a flat STI surface using chemical mechanical polishing, forming drain and source regions, depositing a medium dielectric layer, polishing the medium dielectric layer till the top of the first dummy gate is exposed through the chemical mechanical polishing process again, removing the dummy gate material via a dry etching and a wet etching, and continuously etching the STI dielectric layer with the hard mask formed by the medium dielectric layer, thereafter performing the deposition of real gate dielectric and gate electrode material to complete the device structure. | 2015-01-22 |
20150024562 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor. | 2015-01-22 |
20150024563 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - The upper end of a gate electrode is situated below the surface of a semiconductor substrate. An insulating layer is formed over the gate electrode and over the semiconductor substrate situated at the periphery thereof. The insulating layer has a first insulating film and a low oxygen permeable insulating film. The first insulating film is, for example, an NSG film and the low oxygen permeable insulating film is, for example, an SiN film. Further, a second insulating film is formed over the low oxygen permeable insulating film. The second insulating film is, for example, a BPSG film. The TDDB resistance of a vertical MOS transistor is improved by processing with an oxidative atmosphere after forming the insulating layer. Further since the insulating layer has the low oxygen permeable insulating film, fluctuation of the threshold voltage of the vertical MOS transistor can be suppressed. | 2015-01-22 |
20150024564 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes forming a first gate oxide film in each of a first region and a second region by thermally oxidizing a silicon substrate, forming a CVD oxide film on the first gate oxide film, implanting fluorine into each of the first region and the second region through the CVD oxide film and the first gate oxide film, removing the CVD oxide film from the first gate oxide film in the second region, removing the first gate oxide film from the second region, and forming a second gate oxide film in the second region by thermally oxidizing the silicon substrate. | 2015-01-22 |
20150024565 | METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN - A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets. | 2015-01-22 |
20150024566 | Finlike Structures and Methods of Making Same - Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer. | 2015-01-22 |
20150024567 | Defect Reduction for Formation of Epitaxial Layer in Source and Drain Regions - The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown silicon-containing layer with reduced number of particles on surface of recesses. The described mechanisms also reduce the effect of the residual particles on the epitaxial growth. The mechanisms include controlled etch of a native oxide layer on the surfaces of recesses to reduce creation of particles, and pre-CDE etch to remove particles from surface. The mechanisms also include reduced etch/deposition ratio(s) of initial CDE unit cycle(s) of CDE process to reduce the effect of residual particles on the formation of the epitaxially grown silicon-containing layer. With the application of one or more of the mechanisms, the quality of the epitaxial layer is improved. | 2015-01-22 |
20150024568 | SPACER REPLACEMENT FOR REPLACEMENT METAL GATE SEMICONDUCTOR DEVICES - A method comprising steps of removing a first dielectric material, including a hard mask layer and one or more spacer material layers, from a semiconductor device having a sacrificial gate whose sidewalls being covered by said spacer material layers, and a raised source and a raised drain region with both, together with said sacrificial gate, being covered by said hard mask layer, wherein the removing is selective to the sacrificial gate, raised source region and raised drain region and creates a void between each of the raised source region, raised drain region and sacrificial gate. The method includes depositing a conformal layer of a second dielectric material to the semiconductor device, wherein the second material conforms in a uniform layer to the raised source region, raised drain region and sacrificial gate, and fills the void between each of the raised source region, raised drain region and sacrificial gate. | 2015-01-22 |
20150024569 | INTEGRATED CIRCUITS AND METHODS OF FORMING INTEGRATED CIRCUITS - A method of forming an integrated circuit includes forming a gate electrode over a substrate, forming a recess in the substrate and adjacent to the gate electrode, forming a diffusion barrier structure in the recess, forming an N-type doped silicon-containing structure over the diffusion barrier structure and thermally annealing the N-type doped silicon-containing structure. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode and the second portion is distant from the gate electrode. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate and the second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate. | 2015-01-22 |
20150024570 | SCALING OF BIPOLAR TRANSISTORS - Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor. | 2015-01-22 |
20150024571 | RESISTIVE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A resistive memory device capable of implementing a multi-level cell (MLC) and a fabrication method thereof are provided. The resistive memory device includes a lower electrode connected to a switching device and including a first node and a second node formed on a top thereof to be spaced at a fixed interval, a phase-change material pattern formed on the first node and the second node, an upper electrode formed on the phase-change material pattern, a conductive material layer formed on a top and outer sidewall of the upper electrode, a first contact plug formed on one edge of the upper electrode to be connected to the upper electrode and the conductive material layer, and a second contact plug formed on the other edge of the upper electrode to be connected to the upper electrode and the conductive material layer. | 2015-01-22 |
20150024572 | PROCESS FOR FACILTIATING FIN ISOLATION SCHEMES - Semiconductor fabrication methods are provided which include facilitating fabricating semiconductor fin structures by: providing a wafer with at least one fin extending above a substrate, the at least one fin including a first layer disposed above a second layer; mechanically stabilizing the first layer; removing at least a portion of the second layer of the fin(s) to create a void below the first layer; filling the void, at least partially, below the first layer with an isolation material to create an isolation layer within the fin(s); and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the fin(s), and a fin device(s) of a second architectural type in a second fin region of the fin(s), where the first architectural type and the second architectural type are different fin device architectures. | 2015-01-22 |
20150024573 | METHODS OF FORMING REPLACEMENT FINS FOR A FINFET SEMICONDUCTOR DEVICE BY PERFORMING A REPLACEMENT GROWTH PROCESS - Various methods are disclosed herein for forming alternative fin materials that are in a stable or metastable condition. In one case, a stable replacement fin is grown to a height that is greater than an unconfined stable critical thickness of the replacement fin material and it has a defect density of 10 | 2015-01-22 |
20150024574 | TEMPORARY BONDING ADHESIVE COMPOSITIONS AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - A temporary bonding adhesive composition includes a first compound including a thermosetting polyorganosiloxane and a second compound including a thermoplastic polyorganosiloxane. | 2015-01-22 |
20150024575 | Wafer Alignment Methods in Die Sawing Process - A method includes forming a molding compound molding a lower portion of an electrical connector of a wafer therein. The molding compound is at a front surface of the wafer. The molding compound covers a center region of the wafer, and leaves an edge ring of the wafer not covered. An opening is formed to extend from the front surface of the wafer into the wafer, wherein the opening is in the edge ring of the wafer. A backside grinding is performed on the wafer until the opening is revealed through a back surface of the wafer. The method further includes determining a position of a scribe line of the wafer using the opening as an alignment mark, and sawing the wafer from a backside of the wafer by sawing through the scribe line. | 2015-01-22 |
20150024576 | Dicing Sheet with Protective Film-Forming Layer, and Method for Producing Chip - A dicing sheet with a protective film-forming layer includes a protective film-forming layer on an adhesive layer of an adhesive sheet with a peel strength adjusting layer being interposed therebetween. The adhesive sheet is composed of a base film and the adhesive layer. The dicing sheet with a protective film-forming layer may also include a laminate of the peel strength adjusting layer and the protective film-forming layer is arranged in the inner circumferential part of the adhesive sheet; the adhesive layer is exposed in the outer circumferential part of the adhesive sheet; and the peel strength between the peel strength adjusting layer and a protective film that is obtained by curing the protective film-forming layer is 0.05-5 N/25 mm. | 2015-01-22 |
20150024577 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device in which the threshold is corrected is provided. In a semiconductor device including a plurality of transistors each includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit for supplying a signal to the gate electrode and a circuit for supplying a signal to the source or drain electrode are electrically separated from each other. The process is performed in the state where the potential of the former circuit is set higher than the potential of the latter circuit. | 2015-01-22 |
20150024578 | METHODS FOR ETCHING DIELECTRIC MATERIALS IN THE FABRICATION OF INTEGRATED CIRCUITS - Methods for etching dielectric materials in the fabrication of integrated circuits are disclosed herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate. The gate electrode structure includes a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface. The method further includes forming a layer of a second dielectric material over the layer of the first dielectric material. The first dielectric material is different than the second dielectric material. Still further, the method includes applying an etchant to the second material that fully removes the second material from the sidewall vertical surfaces while only partially removing the second material from the horizontal top surface and while substantially not removing any of the layer of the first dielectric material. | 2015-01-22 |
20150024579 | Method Of Improving Ion Beam Quality In An Implant System - A method for improving the ion beam quality in an ion implanter is disclosed. In some ion implantation systems, contaminants from the ion source are extracted with the desired ions, introducing contaminants to the workpiece. These contaminants may be impurities in the ion source chamber. This problem is exacerbated when mass analysis of the extracted ion beam is not performed, and is further exaggerated when the desired feedgas includes a halogen. | 2015-01-22 |
20150024580 | Method For Implant Productivity Enhancement - A method of processing a workpiece is disclosed, where the ion chamber is first coated with the desired dopant species and another species. Following this conditioning process, a feedgas, which comprises fluorine and the desired dopant, is introduced to the chamber and ionized. Ions are then extracted from the chamber and accelerated toward the workpiece, where they are implanted without being first mass analyzed. The other species used during the conditioning process may be a Group 3, 4 or 5 element. The desired dopant species may be boron. | 2015-01-22 |
20150024581 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device in which an electrode structure is formed on a silicon carbide semiconductor substrate, includes forming a Schottky layer including a metal selected from the group titanium, tungsten, molybdenum, and chrome on a front surface of the silicon carbide semiconductor substrate; heating the Schottky layer to form a Schottky electrode which has a Schottky contact with the silicon carbide semiconductor substrate; and forming a surface electrode composed of aluminum or aluminum including silicon on a surface of the Schottky electrode, while heating at a temperature range effective for the surface electrode to closely cover any uneven portion of the Schottky electrode, and provide a surface electrode having a predetermined reflectance or less that is suitable for use in an automatic wire bonding apparatus for image recognition such as positioning. | 2015-01-22 |
20150024582 | METHOD OF MAKING A GAS DISTRIBUTION MEMBER FOR A PLASMA PROCESSING CHAMBER - A method of making a Si containing gas distribution member for a semiconductor plasma processing chamber comprises forming a carbon member into an internal cavity structure of the Si containing gas distribution member. The method includes depositing Si containing material on the formed carbon member such that the Si containing material forms a shell around the formed carbon member. The Si containing shell is machined into the structure of the Si containing gas distribution member wherein the machining forms gas inlet and outlet holes exposing a portion of the formed carbon member in an interior region of the Si containing gas distribution member. The method includes removing the formed carbon member from the interior region of the Si containing gas distribution member with a gas that reacts with carbon, dissociating the carbon atoms, which may thereby be removed from the interior region of the Si containing gas distribution member leaving a shaped internal cavity in the interior region of the Si containing gas distribution member. | 2015-01-22 |
20150024583 | METHOD OF MANUFACTURING LIQUID CRYSTAL DISPLAY - A method of manufacturing a liquid crystal display includes disposing a gate electrode and a light blocking member on a substrate, disposing a source electrode and a drain electrode on the gate electrode to form a thin film transistor, disposing a data line on the light blocking member, disposing an organic layer on the thin film transistor and the data line, exposing a first convex part of the organic layer to light in a first area corresponding to the thin film transistor during an exposure process, and exposing a second convex part of the organic layer to the light in a second area corresponding to the data line during the exposure process using a mask. The mask includes a first transflective part aligned with the first area and a second transflective part aligned with the second area during the exposure process. | 2015-01-22 |
20150024584 | METHODS FOR FORMING INTEGRATED CIRCUITS WITH REDUCED REPLACEMENT METAL GATE HEIGHT VARIABILITY - Methods for fabricating integrated circuits with reduced replacement metal gate height variability are provided. In an embodiment, a method includes providing a semiconductor substrate with a fin supported thereon and forming a conformal material layer overlying the fin and the semiconductor substrate. A trench is etched within the conformal material layer such that the trench exposes a surface of the fin and the semiconductor substrate. A conductive gate structure is formed within the trench, the conformal material layer is removed, and spacers are formed on the sidewalls of the conductive gate. | 2015-01-22 |
20150024585 | SYSTEMS AND METHODS FOR FABRICATING GATE STRUCTURES FOR SEMICONDUCTOR DEVICES - A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed. | 2015-01-22 |
20150024586 | METHOD FOR PRODUCING A MONOCRYSTALLINE METAL/SEMICONDUCTOR COMPOUND - In the method for producing a monocrystalline metal-semiconductor compound on the surface of a semiconducting functional layer, initially a supply layer comprising the metal is applied to the functional layer. Thereafter, the reaction between the metal and the functional layer is triggered by way of annealing. The supply layer ends at no greater than a layer thickness of 5 nm from the surface of the functional layer, or it transitions at no greater than this layer thickness into a region in which the metal diffuses more slowly than in the region that directly adjoins the functional layer. This measure advantageously allows diffusion flow of the metal into the functional layer to be prevented. This depends precisely on whether the metal-semiconductor compound is monocrystalline. The supply layer can comprise at least two layers made of the metal or an alloy of the metal, which are separated from each other by a diffusion barrier, but can also comprise a layer that is made of the metal and that directly adjoins the functional layer and at least one layer made of an alloy of the metal. | 2015-01-22 |
20150024587 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. An etch-target layer is formed on a substrate. A photoresist layer is formed on the etch-target layer. A first exposure process is performed using a first photo mask to form a plurality of first-irradiated patterns in the photoresist layer. The first photo mask includes a plurality of first transmission regions. Each first transmission region has different optical transmittance. A second exposure process is performed using a second photo mask to form a plurality of second-irradiated patterns in the photoresist layer. The second photo mask includes a plurality of second transmission regions. Each second transmission region has different optical transmittance. A photoresist pattern is formed from the photoresist layer by removing the plurality of first-irradiated and second-irradiated patterns from the photoresist layer. A lower structure is formed from the etch-target layer by etching the etch-target layer using the photoresist pattern. | 2015-01-22 |