04th week of 2009 patent applcation highlights part 37 |
Patent application number | Title | Published |
20090023217 | Integrated chemical indicator device - A chemical indicator device for use in detecting exposure to an oxidizing agent, such as hydrogen peroxide, comprising a substrate or support upon which is disposed a chemical indicator composition (ink) for detecting an oxidizing agent, such as hydrogen peroxide. The chemical indicator composition further comprises an indicator dye that achieves a distinct range of different color changes with clear transitions between colors, upon exposure to different doses of the oxidizing agent, thus allowing for both a qualitative and semi-quantitative assessment of exposure to the agent. | 2009-01-22 |
20090023218 | TEST METHOD FOR DETERMINING ETCH PERFORMANCE OF COATED SUBSTRATE - The present invention provides a test method for simulating outdoor exposure conditions for testing a coated substrate to evaluate environmental etching of paint caused by acid rain. The test method requires that the test substrate have an acid solution having a pH of less than 6.0 applied thereto by spray or in atomized droplets. The substrate is held in a substantially horizontal position of less than 15° to the horizontal and exposed to heat of above a black panel temperature of 30° C. and light during testing. The light source must emit light in the spectral distribution of at least visible and ultraviolet light, including the spectral distribution of sunlight. Following exposure to testing the substrate is evaluated for environmental etch. | 2009-01-22 |
20090023219 | SPECIMEN GATHERING DEVICE AND METHOD OF USE - A kit is provided for gathering biological specimens. The kit generally comprises a self-contained specimen gathering device including a protective housing and a preservation solution. Also provided is a method of gathering specimens and a holistic method of deterring crime using the kit. | 2009-01-22 |
20090023220 | Method for discriminating between prostatic cancer and benign prostatic hyperplasia - The present invention provides a method for accurately discriminating between prostate carcinoma and benign prostatic hyperplasia based on a glycan structure of prostate specific antigen (PSA). The method of the present invention includes the steps of: purifying PSA from a sample derived from a subject; preparing a PSA derivative from the PSA; labeling the PSA derivative; and analyzing the labeled PSA derivative by the mass spectrometry method, in which the subject is identified as having prostate carcinoma when the ratio of the signal intensity of fucose-unbound glycan to the signal intensity of fucose-bound glycan in the labeled PSA derivative is greater than 1.0, and identified as having benign prostatic hyperplasia when the ratio is 1.0 or less. | 2009-01-22 |
20090023221 | Oligonucleotide probes useful for detection and analysis of microrna precursors - The invention relates to ribonucleic acids and oligonucleotide probes useful for detection and analysis of microRNA precursors and their targets. The invention furthermore relates to oligonucleotide probes for detection and analysis of other non-coding RNAs, mRNAs, mRNA splice variants, allelic variants of single transcripts, mutations, deletions, or duplications of particular exons in transcripts, e.g., alterations associated with human disease, such as cancer. | 2009-01-22 |
20090023222 | Temperature-Adjusted Analyte Determination For Biosensor System - A biosensor system determines analyte concentration from an output signal generated by an oxidation/reduction reaction of the analyte. The biosensor system adjusts a correlation for determining analyte concentrations from output signals at one temperature to determining analyte concentrations from output signals at other temperatures. The temperature-adjusted correlation between analyte concentrations and output signals at a reference temperature may be used to determine analyte concentrations from output signals at a sample temperature. | 2009-01-22 |
20090023223 | PLUG FLOW SYSTEM FOR IDENTIFICATION AND AUTHENTICATION OF MARKERS - Devices and methods for extraction, identification, authentication, and quantification of one or more covert markers in a material are disclosed. An extraction system includes a first plug flow mixer for mixing a first fluid bearing a marker and transfer agent into a plug flow. The mixing and flowing of the immiscible liquids causes transfer of the marker from the fluid to the transfer agent. A splitter having filters of different surface energies separates the two immiscible liquids, the transfer agent bearing the marker. A second plug flow can be used to transfer the marker to a second transfer agent. The transferred marker is detected to authenticate the original fluid. The marker can be further isolated, activated, or reacted to perform detection, identification or authentication. With the device, a number of independent processing and analytic steps are combined onto a single, portable unit. | 2009-01-22 |
20090023224 | Vascular endothelial growth factor 2 - Disclosed are human VEGF-2 antibodies, antibody fragments, or variants thereof. Also provided are processes for producing such antibodies. The present invention relates to methods and compositions for preventing, treating or ameliorating a disease or disorder comprising administering to an animal, preferably a human, an effective amount of one or more VEGF-2 antibodies or fragments or variants thereof. | 2009-01-22 |
20090023225 | Methods and devices for analyte detection - Methods for detecting one or more analytes, such as a protein, in a fluid path are provided. The methods include resolving, immobilizing and detecting one or more analytes in a fluid path, such as a capillary. Also included are devices and kits for performing such assays. | 2009-01-22 |
20090023226 | Variant Integrin Polypeptides and Uses Thereof - Polypeptides comprising all or part of a variant integrin α subunit A domain and its flanking region are described. In solution or in membrane-associated form, the A domain polypeptides of the invention exists predominantly in a high affinity conformation. In the polypeptides of the invention, referred to as variant integrin polypeptides, a crucial isoleucine or glutamic acid residue is altered. For example, the glutamic acid can be either deleted or replaced with different amino acids residue, e.g., glutamine, aspartic acid, or alanine The variant integrin polypeptides of the invention selectively impair binding of activation-dependent ligands, but not independent ligands. They are useful in screening assays for the identification of molecules that enhance binding of variant polypeptides with impaired binding. In addition, they are useful in distinguishing between activation-dependent ligands and activation-independent ligands. They are also useful for generating antibodies, e.g., monoclonal antibodies, which bind to the impaired form of an integrin. Some such antibodies recognize an epitope that is either not present or not accessible on an integrin that is in the high affinity conformation. The variant integrin polypeptides of the invention can be derived from any integrin α subunit that could be used therapeutically. | 2009-01-22 |
20090023227 | METHOD - The invention provides a method of measuring the affinity of first and second biomolecules in which a first biomolecule is tethered by a first tether portion having a first tether portion length and a second biomolecule is tethered by a second tether portion having a second tether portion length, the method comprising determining binding of adjacent first and second biomolecules to each other, varying at least one of the first and second tether lengths and determining binding of the first and second biomolecules. The invention also provides apparatus suitable for use in the method of the invention. | 2009-01-22 |
20090023228 | Dual-acting Imidazole antihypertensive agents - The invention is directed to compounds having the formula: | 2009-01-22 |
20090023229 | METHOD FOR MANAGING UV IRRADIATION FOR CURING SEMICONDUCTOR SUBSTRATE - A method for managing UV irradiation for curing a semiconductor substrate, includes: passing UV light through a transmission glass window provided in a chamber for curing a semiconductor substrate placed in the chamber; monitoring an illuminance upstream of the transmission glass window and an illuminance downstream of the transmission glass window; determining a timing and/or duration of cleaning of the transmission glass window, a timing of replacing the transmission glass window, a timing of replacing a UV lamp, and/or an output of the UV light based on the monitored illuminances. | 2009-01-22 |
20090023230 | METHODS AND APPARATUS FOR DEPOSITING AN ANTI-REFLECTION COATING - Systems, methods, and apparatus are provided for depositing an anti-reflection film on a substrate. A substrate is transported to a metrology tool. A characteristic of the substrate is measured, via the metrology tool. A recipe for an anti-reflection film is determined, based on the measured characteristic. The substrate is transported from the metrology tool to a process chamber. The recipe is employed to form an anti-reflection film on the substrate within the process chamber. Numerous other aspects are provided. | 2009-01-22 |
20090023231 | Semiconductor Device Manufacturing Method and Method for Reducing Microroughness of Semiconductor Surface - Surface treatment is performed with a liquid, while shielding a semiconductor surface from light. When the method is employed for surface treatment in wet processes such as cleaning, etching and development of the semiconductor surface, increase of surface microroughness can be reduced. Thus, electrical characteristics and yield of the semiconductor device are improved. | 2009-01-22 |
20090023232 | ORGANIC ELECTROLUMINESCENCE ELEMENT, PROCESS FOR PREPARATION OF THE SAME, AND ELECTRODE FILM - An organic electroluminescence element has a layered structure on a surface of a transparent substrate. The layered structure comprises an organic material layer including a light-emitting organic material layer, an opaque electrode layer, an insulating layer, a metal layer and a resin film in order. The organic electroluminescence element is improved in durability because moisture is prevented from permeating into a light-emitting element. | 2009-01-22 |
20090023233 | METHOD OF MANUFACTURING DISPERSION TYPE AC INORGANIC ELECTROLUMINESCENT DEVICE AND DISPERSION TYPE AC INORGANIC ELECTROLUMINESCENT DEVICE MANUFACTURED THEREBY - Disclosed herein is a method of preparing a low resistance metal line, is a method of manufacturing a dispersion type AC inorganic electroluminescent device and a dispersion type AC inorganic electroluminescent device manufactured thereby, in which a light-emitting layer and a dielectric layer between a lower electrode and an upper electrode are simultaneously formed through a single process using spin coating, thereby simplifying the overall manufacturing process and decreasing the manufacturing cost, and furthermore, the contact interface between the light-emitting layer and the dielectric layer is increased, therefore increasing the brightness of the device. | 2009-01-22 |
20090023234 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGE - A method for manufacturing light emitting diode (LED) package first fabricates a silicon submount with at least one groove by wet etching, wherein a reflective layer, a transparent insulation layer and a metal bump are successively formed in the silicon submount. An LED die is mounted in the groove of the silicon submount. A protective glue is applied to fill the groove and provides a flat top face. A phosphor layer is formed on the flat top face by printing. The phosphor layer is formed with excellent uniformity due to the flat top face, and provides uniform wavelength conversion effect. Alternatively, a phosphor plate is manufactured in advance and selected with desired color temperature parameter. The phosphor plate with desired color temperature parameter is attached to the flat top face of the protective glue instead of printing. | 2009-01-22 |
20090023235 | Method and Apparatus for Improved Printed Cathodes for Light-Emitting Devices - Rapid thermal processing of printed cathodes for light-emitting polymer devices (LEPDs) to prevent detrimental cathode ink/LEP layer interactions is described herein. The ink layer printed cathode can be thinned curing fabrication using high mesh count screens, calendered mesh screens, high squeegee pressures, high hardness squeegees, high squeegee angles and combinations thereof. Alone, or in combination with, a thinned ink layer, the printed cathode can be cured using reduced time hot plate processing, infrared processing, heated gas flow processing, or combinations thereof. | 2009-01-22 |
20090023236 | Method for manufacturing display device - A method for manufacturing display devices including thin film transistors with high reliability in a high yield is provided. A gate insulating film is formed over a gate electrode; a microcrystalline semiconductor is formed over the gate insulating film; the microcrystalline semiconductor film is irradiated with a laser beam from the surface side thereof, whereby the crystallinity of the microcrystalline semiconductor film is improved. Then, a thin film transistor is formed using the microcrystalline semiconductor film whose crystallinity is improved. Further, a display device including the thin film transistor is manufactured. | 2009-01-22 |
20090023237 | INTEGRATED OPTICAL ISOLATOR - There is provided an integrated optical isolator has a structure obtained by integrating a semiconductor laser and an optical isolator, simple manufacturing steps, efficiently absorbs a backward propagation light of the optical isolator, and prevents a stray light from being generated. In an integrated optical isolator in which a semiconductor waveguide layer is layered on a compound semiconductor substrate, a semiconductor laser is formed on a one-side part of the semiconductor waveguide layer, and an optical isolator is formed on an other-side part, a laser current injection electrode is arranged on an upper portion of an active layer of a certain semiconductor waveguide layer in the semiconductor laser, terminal absorbing layers are arranged at the backward propagation light output waveguide output end of the optical isolator on both sides of the semiconductor laser. | 2009-01-22 |
20090023238 | Method to form an optical grating and to form a distributed feedback laser diode with the optical grating - A method for forming a grating with an adjustable pitch and a method for forming a DFB-LD with an optical grating whose pitch is adjustable during the process are disclosed. The method of the invention; first prepares a mold with a pattern to form the grating; second, pushes the mold against the resin as deforming the mold; and third, hardens the mold. The resin with a periodic pattern whose pitch is adjustable during the process is available. | 2009-01-22 |
20090023239 | LIGHT EMITTING DEVICE PROCESSES - Light-emitting devices, and related components, processes, systems and methods are disclosed. | 2009-01-22 |
20090023240 | Semiconductor laser device and manufacturing method of the same - This provides a semiconductor laser device of a high light output efficiency, which is high in current confinement effect, small in leak current, and favorable in temperature property, and indicates a low threshold current, and can effectively confine laser light to a stripe region, and is favorable in beam profile. | 2009-01-22 |
20090023241 | CLEAN RATE IMPROVEMENT BY PRESSURE CONTROLLED REMOTE PLASMA SOURCE - The present invention generally comprises a method for cleaning a large area substrate processing chamber. As chamber volume increases, it has surprisingly been found that simply scaling up the cleaning conditions may not effectively clean silicon from the exposed chamber surfaces. Undesired silicon deposits on exposed chamber surfaces may lead to contamination in solar panel formation. Increasing the pressure of the chamber to about 10 Torr or greater while maintaining the chamber at a temperature between about 150 degrees Celsius and 250 degrees Celsius increases plasma cleaning effectiveness such that silicon deposits are removed from the chamber. The combination of high pressure and low temperature may reduce substrate contamination without sacrificing substrate throughput in solar panel fabrication. | 2009-01-22 |
20090023242 | VACUUM JACKET FOR PHASE CHANGE MEMORY ELEMENT - A memory device including a phase change element and a vacuum jacket. The device includes a first electrode element; a phase change element in contact with the first electrode element; an upper electrode element in contact with the phase change element; a bit line electrode in contact with the upper electrode element; and a dielectric fill layer surrounding the phase change element and the upper electrode element, spaced from the same and sealed by the bit line electrode to define a vacuum jacket around the phase change element and upper electrode element. | 2009-01-22 |
20090023243 | METHOD AND APPARATUS FOR FABRICATING INTEGRATED CIRCUIT DEVICE USING SELF-ORGANIZING FUNCTION - In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions | 2009-01-22 |
20090023244 | Etching/bonding chamber for encapsulated devices and method of use - A method for activating a getter at low temperature for encapsulation in a device cavity containing a microdevice comprises etching a passivation layer off the getter material while the device wafer and lid wafer are enclosed in a bonding chamber. A plasma etching process may be used, wherein by applying a large negative voltage to the lid wafer, a plasma is formed in the low pressure environment within the bonding chamber. The plasma then etches the passivation layer from the getter material, which is directly thereafter sealed within the device cavity of the microdevice, all within the etching/bonding chamber. | 2009-01-22 |
20090023245 | FLIP CHIP MOUNTING METHOD AND BUMP FORMING METHOD - The invention involves mounting a solder resin composition ( | 2009-01-22 |
20090023246 | EMBEDDED CHIP PACKAGE PROCESS - An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer. | 2009-01-22 |
20090023247 | METHOD FOR FORMING SIDE WIRINGS - After plural semiconductor elements are stacked to form a stacked body P, side wirings are formed on the side surface of the stacked body P, thereby manufacturing a semiconductor apparatus in which the respective semiconductor elements are electrically connected to one another. In this case, as the semiconductor element, a semiconductor element | 2009-01-22 |
20090023248 | METHOD OF PACKAGING A SEMICONDUCTOR DIE - A method of packaging a semiconductor die includes the steps of providing a flange ( | 2009-01-22 |
20090023249 | Wire bonded wafer level cavity package - A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges bounding the lid, at least one of the edges including one or more outer portions and one or more recesses extending laterally inwardly from the outer portions, with the contacts being aligned with the recesses and exposed through them. | 2009-01-22 |
20090023250 | APPARATUS AND METHOD FOR PRODUCING SEMICONDUCTOR MODULES - An apparatus and method for producing semiconductor modules is disclosed. One embodiment provides for bonding at least one semiconductor die onto a carrier including a support film strip, the support film having applied an adhesive layer to one of its surfaces to attach the semiconductor die, and a pressure tool to press the semiconductor die and the support film strip onto the carrier to permanently contact the at least one semiconductor die to the carrier. | 2009-01-22 |
20090023251 | Method for manufacturing semiconductor device - An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated. | 2009-01-22 |
20090023252 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING A HEAT SINK WITH A BORED PORTION - A heatsink plate is to be fixed to a substrate with sufficient strength, so as to prevent the heatsink plate from being stripped off, to thereby secure reliability on the performance of the semiconductor chip. The heatsink plate has both the upper and lower surfaces of the fixing section sandwiched by an adhesive resin. Such structure provides an increased adhesion area between the heatsink plate and the upper surface of the substrate, thereby securing greater fixing strength compared with the conventional structure in which simply the lower surface of the heatsink plate and the upper surface of the substrate are adhered to each other. Accordingly, the heatsink plate can be fixed to the upper surface of substrate with greater strength. | 2009-01-22 |
20090023253 | Semiconductor Device and Method of Making Same - A method for manufacturing a semiconductor device that includes a housing, formed of a polyamide-series thermoplastic resin, and a semiconductor package sealed in the housing, which is formed of a thermosetting epoxy resin. The surface of the package is modified by UV-irradiation to have adhesive properties to polyamide. A plurality of connector terminals extend from the package and housing in parallel. A portion of the terminals is also sealed in the housing together with the package. Thus, the device is easily produced by insert molding and has excellent moisture resistance. | 2009-01-22 |
20090023254 | METHOD OF FORMING INORGANIC INSULATING LAYER AND METHOD OF FABRICATING ARRAY SUBSTRATE FOR DISPLAY DEVICE USING THE SAME - A method of forming an inorganic insulating layer on a substrate comprises supplying a mixed gas between the substrate and a target, and generating a plasma between the substrate and the target. The target comprises a silicon-based material. The method further comprises depositing a plurality of ions from the plasma on the substrate. | 2009-01-22 |
20090023255 | Method for Reshaping Silicon Surfaces with Shallow Trench Isolation - A method for making a semiconductor device by reshaping a silicon surface with a sacrificial layer is presented. In the present invention the steps of forming a sacrificial dielectric layer and removing the sacrificial dielectric layer are repeated multiple times in order to remove sharp edges from the silicon surface near the field oxides. Another aspect of the present invention includes making a MOSFET transistor that incorporates the forming and removing of multiple sacrificial layers into the process. | 2009-01-22 |
20090023256 | METHOD FOR FABRICATING EMBEDDED STATIC RANDOM ACCESS MEMORY - The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask. | 2009-01-22 |
20090023257 | METHOD OF CONTROLLING METAL SILICIDE FORMATION - Methods of processing silicon substrates to form metal silicide layers thereover having more uniform thicknesses are provided herein. In some embodiments, a method of processing a substrate includes providing a substrate having a plurality of exposed regions comprising silicon, wherein at least two of the plurality of exposed regions have a different rate of formation of a metal silicide layer thereover; doping at least one of the exposed regions to control the rate of formation of a metal silicide layer thereover; and forming a metal silicide layer upon the exposed regions of the substrate, wherein the metal silicide layer has a reduced maximum thickness differential between the exposed regions. | 2009-01-22 |
20090023258 | METHOD OF MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTORS - A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented. | 2009-01-22 |
20090023259 | Method of Producing Non Volatile Memory Device - A method of forming a floating gate structure is disclosed, and includes modifying the etch chemistry of a plasma treated reactive ion etch process using an inert atom to physically damage a dielectric region. The damaged dielectric region is subsequently etched using a wet etch process. | 2009-01-22 |
20090023260 | TECHNIQUE FOR FORMING THE DEEP DOPED COLUMNS IN SUPERJUNCTION - A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench having a first extending portion extending from the top main surface towards the heavily doped region. Each trench has two sidewall surfaces in parallel alignment with each other. A blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanted into the sidewall surfaces to form P type doped regions. The blocking layer is then removed. The bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled. | 2009-01-22 |
20090023261 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes the steps of forming a dummy gate insulating film and a dummy gate electrode, forming source and drain regions, forming a first insulating film, forming a second insulating film, removing the second insulating film, simultaneously removing the first insulating film and the second insulating film that remains, while planarizing the first insulating film and the second insulating film that remains, forming a gate electrode trench by removing the dummy gate electrode and the dummy gate insulating film, forming a gate insulating film, and forming a gate electrode, wherein a field effect transistor is formed by the method. | 2009-01-22 |
20090023262 | Method for fabricating semiconductor device - To provide a fine transistor of high precision. A method for fabricating a transistor comprises the step of forming a gate electrode ( | 2009-01-22 |
20090023263 | METHOD TO MANUFACTURE A THIN FILM RESISTOR - A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on the insulating layer to form an insulative body. The process further includes performing a second dry etch process on the resistive material layer to form a resistive body. The resistive body and the insulative body have substantially identical perimeters. | 2009-01-22 |
20090023264 | METHOD OF MAKING PLANAR-TYPE BOTTOM ELECTRODE FOR SEMICONDUCTOR DEVICE - A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers. | 2009-01-22 |
20090023265 | ETCHING SOLUTION FOR REMOVAL OF OXIDE FILM, METHOD FOR PREPARING THE SAME, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided are an anionic surfactant-containing etching solution for removal of an oxide film, preparation methods thereof, and methods of fabricating a semiconductor device using the etching solution. The etching solution includes a hydrofluoric acid (HF), deionized water, and an anionic surfactant. The anionic surfactant is a compound in which an anime salt is added as a counter ion, as represented by R | 2009-01-22 |
20090023266 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, includes forming a structure wherein a first alignment mark is provided in a first alignment-mark arrangement area of a first layer, a second alignment mark is provided in a second alignment-mark arrangement area of a second layer, a dummy pattern is provided above the first alignment-mark arrangement area, and substantially no dummy pattern is provided above the second alignment-mark arrangement area, and aligning a third layer provided above the structure by using the second alignment mark. | 2009-01-22 |
20090023267 | METHOD OF REDUCING ROUGHNESS OF A THICK INSULATING LAYER - A method for reducing roughness of an exposed surface of an insulator layer on a substrate, by depositing an insulator layer on a substrate wherein the insulator layer includes an exposed rough surface opposite the substrate, and then smoothing the exposed rough surface of the insulator layer by exposure to a gas plasma in a chamber. The chamber contains therein a gas at a pressure of greater than 0.25 Pa but less than 30 Pa, and the gas plasma is created using a radiofrequency generator applying to the insulator layer a power density greater than 0.6 W/cm | 2009-01-22 |
20090023268 | ISOLATION METHOD OF ACTIVE AREA FOR SEMICONDUCTOR DEVICE - An isolation method of active area for semiconductor forms an isolated active area in a substrate. The substrate is a p-type silicon substrate. A pad oxide layer is formed on the substrate. A patterned sacrificial layer and an upper mask layer are formed on the pad oxide layer, where the upper mask layer is formed over the isolation region of the substrate. A gap is formed between the patterned sacrificial layer and the upper mask layer. An implantation process is performed to dope ions into the substrate through the gap, which forms an n-type barrier to surround the active areas. Lastly, the patterned sacrificial layer is stripped, and an anodization process is utilized to convert p-type bulk silicon into porous silicon. Then, an oxidation process is performed to oxidize the porous silicon to form a silicon dioxide isolation region for the active areas. | 2009-01-22 |
20090023269 | Method for producing soi wafer - Hydrogen gas is ion-implanted into a silicon wafer for active layer via an insulating film, and thus ion-implanted wafer is then bonded with a supporting wafer via an insulating film interposed therebetween. This bonded wafer is heated to 500° C., so that a part of the bonded wafer is cleaved and separated, thereby producing an SOI wafer. Subsequently, thus-obtained SOI wafer is subjected to a heat treatment in an argon gas atmosphere. After that, the SOI wafer is subjected to an oxidation process in an oxidizing atmosphere, and thus formed oxide film is removed using an HF solution. Consequently, the surface of the SOI wafer is recrystallized and thus planarized. | 2009-01-22 |
20090023270 | Method for manufacturing SOI wafer - There is disclosed a method for manufacturing an SOI wafer comprising at least: implanting a hydrogen ion, a rare gas ion, or both the ions into a donor wafer formed of a silicon wafer or a silicon wafer having an oxide film formed on a surface thereof from a surface of the donor wafer, thereby forming an ion implanted layer; performing a plasma activation treatment with respect to at least one of an ion implanted surface of the donor wafer and a surface of a handle wafer, the surface of the handle wafer is to be bonded to the ion implanted surface; closely bonding these surfaces to each other; mechanically delaminating the donor wafer at the ion implanted layer as a boundary and thereby reducing a film thickness thereof to provide an SOI layer, and performing a heat treatment at 600 to 1000° C.; and polishing a surface of the SOI layer for 10 to 50 nm based on chemical mechanical polishing. | 2009-01-22 |
20090023271 | Glass-based SOI structures - A method of forming a semiconductor on glass structure includes: establishing an exfoliation layer on a semiconductor wafer; contacting the exfoliation layer of the semiconductor wafer to a glass substrate; applying pressure, temperature and voltage to the semiconductor wafer and the glass substrate, without a vacuum atmosphere, such that a bond is established therebetween via electrolysis; and applying stress such that the exfoliation layer separates from the semiconductor wafer and remains bonded to the glass substrate. | 2009-01-22 |
20090023272 | METHOD OF PRODUCING BONDED WAFER - There is provided a method of producing a bonded wafer by bonding two silicon wafers for active layer and support layer to each other and then thinning the wafer for active layer, in which nitrogen ions are implanted from the surface of the wafer for active layer to form a nitride layer in the interior of the wafer for active layer before the bonding. | 2009-01-22 |
20090023273 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device comprising forming a transistor on a semiconductor substrate, forming an interlayer insulating film on the semiconductor substrate to cover the transistor, forming a passivation film on the interlayer insulating film, and annealing the semiconductor substrate having the passivation film in a gas atmosphere comprising at least one gas selected from the group of boron, silicon and hydrogen. | 2009-01-22 |
20090023274 | Hybrid Chemical Vapor Deposition Process Combining Hot-Wire CVD and Plasma-Enhanced CVD - Hybrid chemical vapor deposition systems for depositing a semiconductor-containing thin film over a substrate comprise a reaction space, a substrate support member configured to permit movement of a substrate in a longitudinal direction and a plasma-generating apparatus disposed in the reaction space and configured to form plasma-excited species of a vapor phase chemical. The systems further comprise a hot wire unit disposed in the reaction space and configured to heat and decompose a vapor phase chemical. The hot wire unit can be a filament. The systems can further comprise an additional reaction space proximate the reaction space. The additional reaction space can comprise a plasma-generating apparatus configured to form plasma-excited species of a vapor phase chemical and a hot wire unit configured to heat and decompose a vapor phase chemical. | 2009-01-22 |
20090023275 | METHOD FOR FORMING SILICON WELLS OF DIFFERENT CRYSTALLOGRAPHIC ORIENTATIONS - A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer. | 2009-01-22 |
20090023276 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming an impurity diffusion layer in a surface of a semiconductor substrate, wherein the forming the impurity diffusion layer comprises irradiating material including M | 2009-01-22 |
20090023277 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, the method includes forming an isolation layer defining an active region over a substrate, forming a conductive layer over the substrate including the isolation layer, patterning the conductive layer to form a conductive pattern over the active region defined on both sides of a gate region, forming insulation spacers on a sidewall of the conductive pattern, forming a conductive layer for a gate electrode and a gate hard mask layer over the resulting structure including the conductive pattern, and patterning the gate hard mask layer and the conductive layer for the gate electrode to form a gate in the gate region of the substrate. | 2009-01-22 |
20090023278 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory device that may include forming a dielectric film pattern on a semiconductor substrate; etching the semiconductor substrate using the dielectric film pattern as a mask to form a trench; forming a first dielectric film on the semiconductor substrate including the trench; performing a wet etching process on the semiconductor substrate formed with the first dielectric film; forming a second dielectric film on the semiconductor substrate; performing a planarization process on the first and second dielectric films; and removing the dielectric film pattern. Therefore, a generation of void may be prevented when forming a device isolation film and also when forming an interlayer dielectric film. | 2009-01-22 |
20090023279 | METHOD OF FABRICATING FLASH MEMORY DEVICE - The present invention relates to a method of fabricating a flash memory device and includes forming an air-gap having a low dielectric constant between word lines and floating gates. Further, a tungsten nitride (WN) layer is formed on sidewalls of a tungsten (W) layer for a control gate. Hence, the cross section of the control gate that is finally formed can be increased while preventing abnormal oxidization of the tungsten layer in a subsequent annealing process. The method of the present invention can improve interference between neighboring word lines and, thus improve the reliability of a device. Accordingly, a robust high-speed device can be implemented. | 2009-01-22 |
20090023280 | METHOD FOR FORMING HIGH-K CHARGE STORAGE DEVICE - Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking layer preferably comprised of a lower hafnium oxide storage layer and an upper oxide storage layer. We form a gate electrode over the top blocking layer. We pattern the layers to form a gate structure and form source/drain regions to complete the memory device. In a second example embodiment, we form a floating gate non-volatile memory device comprised of: a bottom tunnel layer comprised essentially of silicon oxide; a charge storage layer comprised of a tantalum oxide; a top blocking layer comprised essentially of silicon oxide; and a gate electrode. The embodiments also comprise anneals and nitridation steps. | 2009-01-22 |
20090023281 | SOLDER BUMP FORMING METHOD - A solder bump forming method of carrying out a reflow treatment over a conductive ball mounted on a plurality of pads, thereby forming a solder bump, includes a metal film forming step of forming a metal film capable of chemically reacting to a tackifying compound on the pads, an organic sticking layer forming step of causing a solution containing the tackifying compound to chemically react to the metal film, thereby forming an organic sticking layer on the metal film, and a conductive ball mounting step of supplying the conductive ball on the pads having the organic sticking layer formed thereon, thereby mounting the conductive ball on the pads through the metal film. | 2009-01-22 |
20090023282 | CONDUCTIVE BALL MOUNTING METHOD AND APPARATUS - There is provided a method of mounting conductive balls on pads on a substrate. The method includes: (a) placing the substrate having the pads coated with an adhesive over a container for containing the conductive balls therein and whose top surface is open such that the pads faces the top surface of the container; and (b) throwing up the conductive balls in the container by moving the container up and down at a given stroke, thereby allowing the conductive balls to adhere to the adhesive coated on the pads. Step (b) is repeatedly performed. | 2009-01-22 |
20090023283 | INTERCONNECTION PROCESS - An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening. | 2009-01-22 |
20090023284 | Integrated Wafer Processing System for Integration of Patternable Dielectric Materials - The present disclosure relates to an integrated wafer processing apparatus for fabricating semiconductor chips. This integrated wafer processing system combines the lithography patterning steps and irradiation curing steps of the patternable dielectric into one system. The patternable low-k material of the present disclosure also functions as a photoresist, i.e. is a photo-patternable low-k dielectric material. | 2009-01-22 |
20090023285 | METHOD OF FORMING CONTACT OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming a contact of a semiconductor device. According to a method of forming a contact of a semiconductor device in accordance with an aspect of the present invention, first and second insulating layers are sequentially formed over a semiconductor substrate. A contact hole is formed by sequentially etching the first and second insulating layers. An aperture portion of the contact hole is widened by etching the second insulating layer. A conductive material is gap-filled over an entire surface including the contact hole, thus forming a contact. | 2009-01-22 |
20090023286 | DIELECTRIC INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME - Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N | 2009-01-22 |
20090023287 | INTERCONNECTION PROCESS - An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening. | 2009-01-22 |
20090023288 | METHOD OF MANUFACTURING NANOELECTRODE LINES USING NANOIMPRINT LITHOGRAPHY PROCESS - Provided are a method of manufacturing nanoelectrode lines. The method includes the steps of: sequentially forming an insulating layer, a first photoresist layer, and a drop-shaped second photoresist on a substrate; disposing an imprint mold having a plurality of molding patterns over the second photoresist; applying pressure to the mold to allow the second photoresist to flow into the mold patterns; irradiating ultraviolet (UV) light onto the mold to cure the second photoresist; removing the mold from the cured second photoresist and patterning the second photoresist; patterning the first photoresist layer using the patterned second photoresist as a mask; patterning the insulating layer; and forming a metal layer between the patterned insulating layers. In this method, metal electrode lines are formed between insulating layers using an imprint lithography process, so that nanoelectronic devices can be freed from crosstalk between the metal electrode lines. | 2009-01-22 |
20090023289 | CONDUCTOR REMOVAL PROCESS - A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns. | 2009-01-22 |
20090023290 | Planarization method - A planarization method is provided. The method includes the steps of providing a substrate with a first region and a second region, and having a plurality of protrusions of different densities on a surface of said substrate; forming a first dielectric layer on the substrate to fill spaces between the plurality of protrusions; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is formed with a protruding tip having a height higher than heights of the protrusions; and partially removing said first dielectric layer and said second dielectric layer to planarize said first dielectric layer and said second dielectric layer and expose top surfaces of said protrusions. | 2009-01-22 |
20090023291 | Polishing Methods - A chemical-mechanical polishing (CMP) method includes applying a solid abrasive material to a substrate, polishing the substrate, flocculating at least a portion of the abrasive material, and removing at least a majority portion of the flocculated portion from the substrate. Applying solid abrasive material can include applying a CMP slurry or a polishing pad comprising abrasive material. Such a method can further include applying a surfactant comprising material to the substrate to assist in effectuating flocculation of the abrasive material to the surfactant comprising material may be cationic which includes, for example, a quaternary ammonium substituted salt. Also, for example, the surfactant comprising material may be applied during polishing, brush scrubbing, pressure spraying or buffing. | 2009-01-22 |
20090023292 | PHOTOELECTRIC CONVERSION DEVICE AND METHOD FOR PRODUCING PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device according to the present invention has a plurality of photoreceiving portions provided in a substrate, an interlayer film overlying the photoreceiving portion, a large refractive index region which is provided so as to correspond to the photoreceiving portion and has a higher refractive index than the interlayer film, and a layer which is provided in between the photoreceiving portion and the large refractive index region, and has a lower etching rate than the interlayer film, wherein the layer of the lower etching rate is formed so as to cover at least the whole surface of the photoreceiving portion. In addition, the layer of the lower etching rate has a refractive index in between the refractive indices of the large refractive index region and the substrate. Such a configuration can provide the photoelectric conversion device which inhibits the lowering of the sensitivity and the variation of the sensitivity among picture elements. | 2009-01-22 |
20090023293 | IMPLEMENTING STATE-OF-THE-ART GATE TRANSISTOR, SIDEWALL PROFILE/ANGLE CONTROL BY TUNING GATE ETCH PROCESS RECIPE PARAMETERS - In accordance with the invention, there are methods of controlling the sidewall angle of a polysilicon gate from batch to batch while maintaining current bottom critical dimension control performance. The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time of one or more etch steps during the formation of the gate, developing a statistical model for the sidewall angle as a function of one or more of polysilicon density, polythickness, and etcher, and predicting a sidewall angle using the statistical model for a given polydensity, a given polythickness, and a given etcher. The method can also include comparing the predicted sidewall angle with a target sidewall angle and determining an optimized RF bias power and optimized etch time of one or more etch steps during the formation of the gate using the correlation to match the target sidewall angle. | 2009-01-22 |
20090023294 | METHOD FOR ETCHING USING ADVANCED PATTERNING FILM IN CAPACITIVE COUPLING HIGH FREQUENCY PLASMA DIELECTRIC ETCH CHAMBER - A method for etching wafers using advanced patterning film (APF) to reduce bowing and improve bottom-to-top ratios includes providing a wafer having an APF layer into a processing chamber, wherein the processing chamber is configured with a power source operating at about 162 MHz, supplying a process gas into the chamber, applying a source power using the 162 MHz power source, and applying a bias power to the wafer. The process gas comprises hydrogen gas (H2), nitrogen gas (N2), and carbon monoxide gas (CO). The ratio of H2:N2 is about 1:1. Additionally, the wafer temperature is adjusted to improve the etching characteristics. | 2009-01-22 |
20090023295 | Manufacturing method for semiconductor chips - By performing plasma etching on the second surface of a semiconductor wafer on the first surface of which an insulating film is placed in dividing regions and on the second surface of which a mask for defining the dividing regions are placed, the second surface being located opposite from the first surface, the insulating film is exposed from an etching bottom portion by removing portions that correspond to the dividing regions. Subsequently, by continuously performing the plasma etching in the state in which the exposed surfaces of the insulating film are charged with electric charge due to ions in the plasma, corner portions put in contact with the insulating film are removed. Subsequently, by removing the mask and thereafter performing plasma etching on the second surface, corner portions located on the second surface side are removed. | 2009-01-22 |
20090023296 | Plasma Etching Method - This invention relates to a method for conducting an etching process which uses a plasma of a process gas. This etching process is conducted on a wafer W including a substrate | 2009-01-22 |
20090023297 | METHOD AND APPARATUS FOR HMDS TREATMENT OF SUBSTRATE EDGES - A system for dispensing an adhesion promoting chemical includes a support plate configured to support a substrate and a dispense nozzle in fluid communication with a source of the adhesion promoting chemical, for example, HMDS. The dispense nozzle is positioned adjacent a peripheral portion of the substrate and at a first radial distance. The system also includes an exhaust aperture in fluid communication with a system exhaust. The exhaust aperture is positioned adjacent to dispense nozzle and at a second radial distance greater than the first radial distance. | 2009-01-22 |
20090023298 | INVERSE SELF-ALIGNED SPACER LITHOGRAPHY - Ultrafine dimensions, smaller than conventional lithographic capabilities, are formed employing an efficient inverse spacer technique comprising selectively removing spacers. Embodiments include forming a first mask pattern over a target layer, forming a spacer layer on the upper and side surfaces of the first mask pattern leaving intermediate spaces, depositing a material in the intermediate spacers leaving the spacer layer exposed, selectively removing the spacer layer to form a second mask pattern having openings exposing the target layer, and etching the target layer through the second mask pattern. | 2009-01-22 |
20090023299 | Reduction of defects formed on the surface of a silicon oxynitride film - Methods for reducing defects on the surface of a silicon oxynitride film are disclosed. In one embodiment, the methods include forming a silicon oxynitride film on a semiconductor substrate and heating the silicon oxynitride film to increase a hydrophilicity of a surface of the silicon oxynitride film prior to treating the surface of the silicon oxynitride film with a hydrofluoric acid. | 2009-01-22 |
20090023300 | METHOD OF FORMING SHADOW LAYER ON THE WAFER BEVEL - A method of forming a shadow layer on a wafer bevel region is provided. First, a substrate having the wafer bevel region and a central region is provided. Thereafter, an upper insulator and a lower insulator are provided. The upper insulator is disposed on an upper surface of the substrate and at least covers the central region. The lower insulator is disposed on a lower surface of the substrate and at least covers the central region. A shadow layer is then formed on the upper surface which is not covered by the upper insulator and on the lower surface which is not covered by the lower insulator. Next, the upper insulator and the lower insulator are removed. | 2009-01-22 |
20090023301 | FILM DEPOSITION APPARATUS, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, AND METHOD OF COATING THE FILM DEPOSITION APPARATUS - A method of manufacturing a semiconductor device has supplying a first reactant gas into buffer chamber provided in a reaction chamber of the film deposition apparatus to form a first film over an inner wall surface of the buffer chamber, and supplying a second reactant gas into the reaction chamber to form a second film over a semiconductor substrate. | 2009-01-22 |
20090023302 | PROTECTIVE INSERTS TO LINE HOLES IN PARTS FOR SEMICONDUCTOR PROCESS EQUIPMENT - Inserts are used to line openings in parts that form a semiconductor processing reactor. In some embodiments, the reactor parts delimit a reaction chamber. The reactor parts may be formed of graphite. A layer of silicon carbide is deposited on surfaces of the openings in the reactor parts and the inserts are placed in the openings. The inserts are provided with a hole, which can accept another reactor part such as a thermocouple. The insert protects the walls of the opening from abrasion caused by insertion of the other reactor part into the opening. | 2009-01-22 |
20090023303 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-charge-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-charge-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate. | 2009-01-22 |
20090023304 | Reorientable Electrical Receptacle - There is provided systems and methods for a reorientable electrical outlet. In one embodiment, a system includes a housing configured to be coupled to an electrical power source, the housing having a first rotation stop, and an electrical plug receptacle, mountable within the housing, the insert having a second rotation stop, the first and second rotation stops configured to cooperate with each other to limit rotation of the insert within the aperture at a number of degrees, wherein the plug receptacle is configured to receive an electrical plug. | 2009-01-22 |
20090023305 | MULTIPLE USE ELECTRIC CURRENT CONNECTOR ASSEMBLY FOR VEHICLES - An electric current connector assembly for a vehicle includes a first connector and a second connector. The first connector comprises a first end portion of a first busbar and a first end portion of a second busbar. The second connector is electrically coupled to the first connector. The second connector comprises a second end portion of the first busbar and a second end portion of the second busbar. | 2009-01-22 |
20090023306 | INTERFACE ASSEMBLIES FOR USE WITH INVERTERS OF VEHICLES - An interface assembly for an inverter of a vehicle includes an interface, a plurality of busbars, a communication medium, and a clip. The interface is for communicating with one or more vehicle systems outside of the interface assembly. The plurality of busbars are configured to receive and transport electric current. The communication medium is electrically coupled between the plurality of busbars and the interface. The communication medium is configured to provide information to the interface based at least in part on the electric current transported by the plurality of busbars. The clip assembly is electrically coupled between the plurality of busbars and the communication medium. | 2009-01-22 |
20090023307 | Electrical junction box - An electrical junction box reduces the number of components to be contained in an electrical junction box and simplifies a structure of the box. The electrical junction box has a casing assembly including an upper casing and a lower casing. A laminated unit including bus bars and insulation plates is contained in the upper casing, while a first printed circuit board, a second printed circuit board and a spacer made of an insulation resin material are contained in the lower casing. The first printed circuit board is disposed on one side of the spacer, while the second printed circuit board is disposed on the other side of the spacer. Shorter size fixing bars and longer size fixing bars project from an inner surface on a top wall of the upper casing. The shorter size fixing bars penetrate the laminated unit, first printed circuit board and spacer. Screws are inserted upward into the shorter size fixing bars via through-holes in the spacer to secure the unit, first printed circuit board, and spacer to the shorter bars. Longer size fixing bars penetrate the laminated unit, first printed circuit board, spacer, second printed circuit board, and lower casing. Screws are inserted upward into the longer size fixing bars via through-holes in the lower casing to secure the unit, first and second printed circuit boards, spacer, and lower casing to the longer bars. | 2009-01-22 |
20090023308 | Card edge connector with an improved latch - A card edge connector ( | 2009-01-22 |
20090023309 | CONFIGURABLE PRINTED CIRCUIT BOARD - According to an example embodiment of the invention, a configurable printed circuit board (PCB) includes one or more separable portions for supporting modules for interfacing with the PCB. The separable portions extend from an edge portion of a main body of the PCB, and are disposed between the main body of the PCB and a protective portion. A scored portion is provided at a boundary between the main body of the PCB and the separable portions, the separable portions being separable by being broken off from the main body of the PCB at the scored portion. According to an example embodiment of the invention, a method of configuring a PCB having one or more separable portions of the PCB includes securing the PCB and separating the one or more separable portions of the PCB from another portion of the PCB. | 2009-01-22 |
20090023310 | CONTACT ELEMENT FOR PRESS FITTING INTO A HOLE OF A PRINTED CIRCUIT BOARD - The invention relates to a contact element for pressing into a hole of a printed circuit board, said contact element comprising a rod-shaped press-fit zone comprising an insertion region and an adjacent deformable region. The width of the deformable region is larger than the diameter of the hole, and the width of the insertion region is smaller than the diameter of the hole. The deformable region comprises a front region and a rear region that both have a closed opening, said openings being separated by a crossbar extending transversally to the insertion direction of the contact element. Said crossbar extends at least in one part at a pointed angle of between 5 and 85 degrees to the insertion direction, and is thus subjected to an elastic force when the limbs are pressed together, creating a steadily increasing compression force for pressing the limbs against the wall of the opening. | 2009-01-22 |
20090023311 | TERMINAL ASSEMBLY WITH PIN-RETAINING SOCKET - Socket terminal assemblies and intercoupling components are configured to electrically connect a contacting area of an integrated circuit with a corresponding connection region of a substrate. The socket terminal assembly includes a socket shell, a pin, and a resilient member. The socket shell includes a portion defining an interior cavity and a protrusion extending inwardly relative to the portion, the protrusion defining an opening into the cavity within the socket shell. The pin includes a first portion having a first outer dimension and defining an interior cavity within the pin, and a second portion having a second outer dimension that is smaller than the first outer dimension. The first pin portion is received within the cavity of the socket shell with the second pin portion extending through the opening and out of the socket shell. In addition, the resilient member is interposed between the socket shell and the pin. | 2009-01-22 |
20090023312 | Electrical Connector - In some embodiments, an electrical connector comprises a male body and a female body. The male body comprises a first insulating base and a plurality of male terminals. Each male terminal includes a male contact. The female body comprises a second insulating base and a plurality of female terminals. Each female terminal includes a female contact arranged to engage a male contact so as to form a circuit. The male contact is formed with a protrusion extending from a side surface. The female contact is bent to form an arc-shaped convex surface that abuts the male contact, and engages the protrusion of the male contact. | 2009-01-22 |
20090023313 | JUNCTION BOX TO BE MOUNTED ON MOTOR VEHICLE - A junction box has a casing assembly including an upper casing and a lower casing, a laminated unit including bus bars and insulation plates, and first and second printed circuit boards contained in the casing assembly. The first printed circuit board is used as a higher current circuit having thick-film conductors. The second printed circuit board is used as a middle or lower current circuit having thin-film conductors with thicknesses smaller than those of the thick-film conductors on the first printed circuit board. Board relays are mounted on a part of different peripheral portions on both sides of the first printed circuit board or a part of peripheral portion of either side of the first printed circuit board. The board relays are disposed in the casing assembly to be opposed to a first heat generating element containing space defined between a front side of the first printed circuit board and an inner surface of a top wall of the upper casing, and a second heat generating element containing space defined between a rear side of the first printed circuit board and an inner surface of a bottom wall of the lower casing. | 2009-01-22 |
20090023314 | ELECTRICAL CONNECTOR AND ELECTRICAL CONNECTING DEVICE USING THE SAME - An electrical connector comprises: an insulating body having at least one containing hole; at least one binding pad disposed on the bottom of the insulating body near at least one side of the containing hole; and at least one terminal correspondingly disposed in the containing hole. Wherein the terminal comprises a soldering portion provided with solder and protruding out of the bottom of the containing hole, and a solder retaining area for retaining the solder is formed between the soldering portion and the binding pad. The solder retaining area can retain more solder near the soldering portion of the terminal to solder the terminal to a circuit board efficiently, so as to improve the quality of soldering and ensure fine electric conductivity. | 2009-01-22 |
20090023315 | CONNECTION SYSTEM, IN PARTICULAR ELECTRICAL CONNECTION SYSTEM - A connection system, in particular an electrical connection system, having a male connector and having a female connector has a bayonet-type connection for connecting the male connector and the female connector. The bayonet-type connection has at least one axially extending insertion channel and at least one adjoining latching position, which is offset in the circumferential direction with respect thereto, in the female connector, the end side of the female connector, which end side is provided for connection to the male connector, being covered by a cover, which is arranged adjustably in the female connector such that, when the male connector is positioned on it, the opening is released by this male connector in order to produce the connection. | 2009-01-22 |
20090023316 | LEVER-FITTING TYPE CONNECTOR | 2009-01-22 |