03rd week of 2010 patent applcation highlights part 43 |
Patent application number | Title | Published |
20100015684 | FACTOR VII: REMODELING AND GLYCOCONJUGATION OF FACTOR VII - The invention includes methods and compositions for remodeling a peptide molecule, including the addition or deletion of one or more glycosyl groups to a peptide, and/or the addition of a modifying group to a peptide. | 2010-01-21 |
20100015685 | LACTOBACILLUS N-DEOXYRIBOSYL TRANSFERASES, CORRESPONDING NUCLEOTIDE SEQUENCES AND THEIR USES - The invention concerns novel polypeptides and their fragments, isolated from | 2010-01-21 |
20100015686 | Variant Alpha-Amylases from Bacillus Subtilis and Methods of Uses, Thereof - Alpha-amylases from | 2010-01-21 |
20100015687 | Tetracycline Repressor Regulated Oncolytic Viruses - The present invention is directed oncolytic Herpes simplex-1 viruses whose replication is controlled using a tetracycline operator/repressor system. The invention also includes DNA sequences used in making the viruses and methods in which these viruses are used in the treatment of cancer patients with solid tumors. | 2010-01-21 |
20100015688 | NOVEL MICROORGANISM CAPABLE OF DEGRADING DIPHENYLARSINIC ACID - Disclosed are: a microorganism capable of degrading diphenylarsinic acid; a method for degrading diphenylarsinic acid by using the microorganism; a method for clean-up of a contaminated soil by using the microorganism; an agent for degrading diphenylarsinic acid, which comprises the microorganism; and a cleaning agent for a contaminated soil or groundwater, which comprises the microorganism. Specifically disclosed are: a microorganism belonging to the genus | 2010-01-21 |
20100015689 | Method For Composting And Treating Food Waste By Using Wood Chips And Apparatus Therefor - The present invention relates to a method of composting and treating food waste by using wood chips and an apparatus therefor. The method and apparatus for the composting and treatment of food waste in accordance with the present invention can recycle food waste as an organic compost by using wood chips in an eco-friendly manner and convert effluents generated from said food waste into an effluent satisfying water quality suitable for discharging by a combined biological and chemical process. Therefore, the present invention can be effectively used for recycling and treating food waste. | 2010-01-21 |
20100015690 | USE OF FLUID ASPIRATION/DISPENSING TIP AS A MICROCENTRIFUGE TUBE - A fluid aspirating/dispensing member includes a sample cavity for sample acquisition and a sealable cavity that, once sealed, permits the separation of particles from the remainder of a fluid sample within the sample cavity after centrifugation or other separation means. The fluid aspirating/dispensing members, either individually or as part of an array, increase the efficiency of sample processing before analysis by a clinical analyzer. | 2010-01-21 |
20100015691 | Apparatus for Hemolyzing a Blood Sample and for Measuring at Least One Parameter Thereof - An apparatus for hemolyzing a blood sample and for measuring at least one parameter thereof comprises a sample chamber for accommodation of the blood sample, the sample chamber having a first sidewall and an opposite second sidewall. The apparatus also comprises ultrasonic generator for generating ultrasonic waves in the first and second sidewalls so as to cause the blood sample provided between the first and second sidewall to be hemolyzed. Further, the apparatus comprises an optical measuring device for measuring the at least one parameter in the hemolyzed blood sample when the hemolyzed blood sample is provided between the first and second sidewalls. The ultrasonic generator of the apparatus comprises a first ultrasonic generator for generating ultrasonic waves in the first sidewall and a second ultrasonic generator for generating ultrasonic waves in the second sidewall. | 2010-01-21 |
20100015692 | Small Volume In Vitro Sensor and Methods of Making - A sensor utilizing a non-leachable or diffusible redox mediator is described. The sensor includes a sample chamber to hold a sample in electrolytic contact with a working electrode, and in at least some instances, the sensor also contains a non-leachable or a diffusible second electron transfer agent. The sensor and/or the methods used produce a sensor signal in response to the analyte that can be distinguished from a background signal caused by the mediator. The invention can be used to determine the concentration of a biomolecule, such as glucose or lactate, in a biological fluid, such as blood or serum, using techniques such as coulometry, amperometry, and potentiometry. An enzyme capable of catalyzing the electrooxidation or electroreduction of the biomolecule is typically provided as a second electron transfer agent. | 2010-01-21 |
20100015693 | COMPOSTING CAGE - Offloading apparatus ( | 2010-01-21 |
20100015694 | FILTERED PETRI DISH - A petri dish includes a cover and base, the cover having at least one circular opening in the top of the cover. A number of securing members are connected to the underside of the cover around the opening to secure at least one filter under the opening, the filter(s) being used to prevent any contaminants from the air from entering the petri dish. A guard member such as a plastic disc is disposed under the filter(s) to prevent any oil in the base of the petri dish from contaminating the filter(s). A sealing member is provided on a peripheral edge of the base to seal the petri dish when the petri dish is closed. | 2010-01-21 |
20100015695 | METHOD AND APPARATUS FOR AMPLIFYING NUCLEIC ACIDS - A method and apparatus for amplifying nucleic acids. The method includes introducing into a reaction vessel via different inlet channels a reactant aqueous solution containing reactants for nucleic acid amplification and a fluid that is phase-separated from the reactant aqueous solution and does not participate in amplification reaction, creating a plurality of reactant aqueous solution droplets surrounded by the fluid by contacting the reactant aqueous solution with the fluid in the reaction vessel, and amplifying the nucleic acids in the reactant aqueous solution droplets. The apparatus includes a substrate, a reaction vessel formed inside of the substrate, at least one first inlet channel formed inside the substrate, connected to an end of the reaction vessel, and allowing introduction of a reactant aqueous solution containing reactants for nucleic acid amplification into the reaction vessel, a second inlet channel formed inside the substrate, connected to the end of the reaction vessel, and allowing introduction of a fluid that is phase-separated from the reactant aqueous solution and does not participate in amplification reaction into the reaction vessel, and a heating unit installed on the substrate in such a way to thermally contact with the substrate and heating the substrate. | 2010-01-21 |
20100015696 | DISPOSABLE BIOREACTOR - A disposable material processing apparatus, useable as a bioreactor or fermenter, includes a hollow tank ( | 2010-01-21 |
20100015697 | MICRO-FLUIDIC CELL MANIPULATION AND HOLDING DEVICE - A micro-fluidic manipulation device is formed using a plastic material or glass. There is at least one well in the device. The well has a base and a side wall and is dimensioned to receive a cell. There is at least one base fluid port in the base of the well and side fluid ports in the side wall. Each of the base fluid port and the side fluid ports are of a cross sectional area to prevent a cell passing therethrough. Selected flow of fluid through the base port in use assists in supporting a cell in the well and selected flow of fluid through the base port and the side ports in use assists in rotating the cell in the well. The well can have a retention section and a loading section, the loading section being above and larger than the retention section. The loading section can have a loading channel extending to it or alternatively an access hatch. The side fluid ports open into a lower region of the loading section. | 2010-01-21 |
20100015698 | Human Chondroitinase Glycoprotein (CHASEGP), Process for Preparing the Same, and Pharmaceutical Compositions Comprising Thereof - The invention relates to the discovery of novel Chondroitinase Glycoproteins (CHASEGPs), methods of manufacture, and potential uses in conditions where removal of chondroitin sulfates may be of therapeutic benefit. Chondroitinase Glycoproteins require both a substantial portion of the catalytic domain of the CHASEGP polypeptide and asparagine-linked glycosylation for optimal chondroitinase activity. The invention also includes carboxy-terminal deletion variants of CHASEGP that result in secreted variants of the protein to facilitate manufacture of a recombinant CHASEGP. Further described are suitable formulations of a substantially purified recombinant CHASEGP glycoprotein derived from a eukaryotic cell that generate the proper glycosylation required for its optimal activity. CHASEGP is useful for the degradation of glycosaminoglycans and chondroitin sulfate proteoglycans under clinical conditions where their removal is of therapeutic value. | 2010-01-21 |
20100015699 | VECTORS AND METHODS FOR TISSUE SPECIFIC SYNTHESIS OF PROTEIN IN EGGS OF TRANSGENIC HENS - Vectors and methods are provided for introducing genetic material into cells of a chicken or other avian species. More particularly, vectors and methods are provided for transferring a transgene to an embryonic chicken cell, so as to create a transgenic hen wherein the transgene is expressed in the hen's oviduct and the transgene product is secreted in the hen's eggs and/or those of her offspring. In a preferred embodiment, the transgene product is secreted in the egg white. | 2010-01-21 |
20100015700 | USE OF THE ADENOVIRAL E2 LATE PROMOTER - The invention relates to a nucleic acid construct comprising an adenoviral E2 late promoter or a fragment thereof and a nucleic acid. The nucleic acid is selected from the group of transgenes, genes and nucleic acids which are respectively different from adenoviral nucleic acid controlled by an E2 late promoter. The invention also relates to the uses of said nucleic acid construct. | 2010-01-21 |
20100015701 | NOVEL FLUORESCENT PROTEINS AND METHODS FOR USING SAME - The present invention provides nucleic acid molecules encoding novel red fluorescent proteins from | 2010-01-21 |
20100015702 | Generation, Characterization and Isolation of Neuroepithelial Stem Cells and Lineage Restricted Intermediate Precursor - Multipotent neuroepithelial stem cells and lineage-restricted oligodendrocyte-astrocyte precursor cells are described. The neuroepithelial stem cells are capable of self-renewal and of differentiation into neurons, astrocytes, and oligodendrocytes. The oligodendrocyte-astrocyte precursor cells are derived from neuroepithelial stem cells, are capable of self-renewal, and can differentiate into oligodendrocytes and astrocytes, but not neurons. Methods of generating, isolating, and culturing such neuroepithelial stem cells and oligodendrocyte-astrocyte precursor cells are also disclosed. | 2010-01-21 |
20100015703 | ANTIBODY TO MAMMALIAN CYTOKINE-LIKE POLYPEPTIDE-10 - A mammalian cytokine-like polypeptide, called Mammalian Cytokine-like polypeptide-10, (Zcyto10), polynucleotides encoding the same, antibodies which specifically bind to the polypeptide, and anti-idiotypic antibodies which bind to the antibodies. Zcyto10 is useful for promoting the healing of wounds and for stimulating the proliferation of platelets. | 2010-01-21 |
20100015704 | PROCESS FOR THE ENRICHMENT OF MELANOCYTES BY MEANS OF MODIFIED SURFACES - The present invention relates to processes for obtaining melanocytes from a cell suspension, in particular from an epidermal cell suspension, by means of a culture vessel, wherein at least a part of the surface of the culture vessel facing the culture space, is modified, in particular functionalized, in particular by means of a low-pressure plasma process. Furthermore, the present invention relates to culture vessels which are modified, in particular functionalized, in particular by means of a low-pressure plasma process and are suitable for obtaining melanocytes and the use of such culture vessels for obtaining melanocytes. | 2010-01-21 |
20100015705 | Generation of Clonal Mesenchymal Progenitors and Mesenchymal Stem Cell Lines Under Serum-Free Conditions - Methods for obtaining multipotent mesenchymal stem cells under serum-free conditions and methods for identifying multipotent mesenchymal progenitor cells are disclosed. | 2010-01-21 |
20100015706 | NUCLEIC ACID COMPOUNDS FOR INHIBITING HIF1A GENE EXPRESSION AND USES THEREOF - The present disclosure provides meroduplex ribonucleic acid molecules (mdRNA) capable of decreasing or silencing HIF1A gene expression. An mdRNA of this disclosure comprises at least three strands that combine to form at least two non-overlapping double-stranded regions separated by a nick or gap wherein one strand is complementary to a HIF1A mRNA. In addition, the meroduplex may have at least one uridine substituted with a 5-methyluridine, a nucleoside is a locked nucleic acid, or optionally other modifications, and any combination thereof. Also provided are methods of decreasing expression of a HIF1A gene in a cell or in a subject to treat a HIF1A-related disease. | 2010-01-21 |
20100015707 | SHORT INTERFERING RIBONUCLEIC ACID (siRNA) FOR ORAL ADMINISTRATION - Short interfering ribonucleic acid (siRNA) for oral administration, said siRNA comprising two separate RNA strands that are complementary to each other over at least 15 nucleotides, wherein each strand is 49 nucleotides or less, and wherein at least one of which strands contains at least one chemical modification. | 2010-01-21 |
20100015708 | RIBONUCLEIC ACIDS WITH NON-STANDARD BASES AND USES THEREOF - The present disclosure provides a ribonucleic acid comprising a double-stranded region having at least one base pair comprising a 5-methyluridine base paired with a 2,6-diaminopurine and methods for preparing the same. Also provided are methods for treating or preventing a disease or disorder by inducing RNAi. | 2010-01-21 |
20100015709 | Regulating Stem Cell Differentiation By Controlling 2D and 3D Matrix Elasticity - Provided are methods for the selection and regulation of the mechanical properties of 2D or 3D biocompatible substrates or tissue microenvironments as a technique to regulate in vitro differentiation, cell shape and/or lineage commitment of anchorage-dependent cells, such as mesenchymal stem cells into, e.g., neurogenic-, myogenic-, and osteogenic-type cells. Substrate mechanical properties include elasticity, tension, adhesion, and myosin-based contractile mechanisms. Inhibitors can be introduced to further regulate differentiation. | 2010-01-21 |
20100015710 | Methods and Compositions for Isolating, Maintaining and Serially Expanding Human Mesenchymal Stem Cells - Compositions and methods for isolating and expanding human mesenchymal stem/progenitor cells through multiple passages in defined serum-free environments are provided. The culture media compositions includes a basal medium supplemented with a nutrient mixture such as Ham's F12 nutrient mixture, glutamine, buffer solutions such as sodium bicarbonate and hepes, serum albumin, a lipid mixture, insulin, transferrin, putrescine, progesterone, fetuin, hydrocortisone, ascorbic acid or its analogues such as ascorbic acid-2-phosphate, fibroblast growth factor and transforming growth factor β, and are free of serum or other undefined serum substitutes such as platelet lysate. Methods employing these compositions and protein-coated surfaces for the isolation of mesenchymal stem/progenitor cells from human bone marrow and other tissues such as adipose tissue are also provided. Finally, methods are also provided for serially expanding these cells through multiple passages without losing mesenchymal stem cell-specific proliferative, phenotypical and differentiation characteristics. | 2010-01-21 |
20100015711 | Differentiation of Pluripotent Stem Cells - The present invention is directed to methods to differentiate pluripotent stem cells. In particular, the present invention is directed to methods and compositions to differentiate pluripotent stem cells into cells expressing markers characteristic of the definitive endoderm lineage comprising culturing the pluripotent stem cells in medium comprising a sufficient amount of GDF-8 to cause the differentiation of the pluripotent stem cells into cells expressing markers characteristic of the definitive endoderm lineage. | 2010-01-21 |
20100015712 | SIDE POPULATION CELLS ORIGINATED FROM HUMAN AMNION AND THEIR USES - Cells which may be differentiated at least into nerve cells, which are useful for therapies of brain metabolic diseases, are disclosed. The cells are side population cell separated from human amniotic mesenchymal cell layer, in which expressions of Oct-4 gene, Sox-2 gene and Rex-1 gene are observed by RT-PCR, and which are vimentin-positive and CK19-positive in immunocytostaining. | 2010-01-21 |
20100015713 | COMPONENTS OF CELL CULTURE MEDIA PRODUCED FROM PLANT CELLS - The present invention comprises the production of components of cell culture media produced from plant cells and cell culture media containing the same. Heterologous DNA comprising genes encoding the desired component are introduced into plant cells, especially rice, which then produce the desired component. The component can be isolated from the plant cell and combined with other components to form the required cell culture medium. | 2010-01-21 |
20100015714 | MEASUREMENT OF SOIL POLLUTION - A soil sample of fixed volume is mixed with a drying agent (MgSO | 2010-01-21 |
20100015715 | MICROFLUIDIC DEVICE INCLUDING STRUCTURE THAT INCLUDES AIR VENT AND VALVE, AND METHOD OF TRANSFERRING FLUID USING THE SAME - A microfluidic device and a method of transferring a liquid material using the microfluidic device are provided. The microfluidic device includes a chamber storing a sealed liquid material, and a structure that flows air to the chamber, when the structure is rotated to generate centrifugal force, so that the liquid material may be transferred from the chamber. | 2010-01-21 |
20100015716 | METHOD FOR OIL DILUTION RATIO EVALUATION THROUGH RADIOACTIVITY MEASUREMENT - The present invention relates to a method for evaluating the dilution ratio of the lubricating oil of an internal-combustion engine operating with a fuel containing at least part of at least one biofuel, wherein the radioactivity of an oil sample is measured so as to subsequently evaluate the ratio of dilution of the oil by the fuel. | 2010-01-21 |
20100015717 | Mass Tags for Quantitive Analysis - The present invention relates generally to novel protein modification reagents for fractionation and quantitative (differential) profiling of proteins in a complex mixture. The reagents react with amino acids or other protein components or structures and function as mass tags. The present invention provides methods of making the protein modification reagents and methods of using the protein modification reagents for quantitative analysis of proteins. | 2010-01-21 |
20100015718 | SUBSTRATE FOR ANALYZING COVERAGE OF SELF-ASSEMBLED MOLECULES AND ANALYZING METHOD USING THE SAME - Provided are a substrate for analyzing the coverage of self-assembled molecules and a method for analyzing the coverage of the self-assembled molecules in nanowire and nanochannel patterned on solid surface, solid surface, or bulk solid surface by using the nanoparticles. According to the method, the presence of specific functional groups of self-assembled molecules and the degree of reaction can be analyzed by introducing nanoparticles to a biomaterial immobilization substrate including self-assembled molecules and measuring the number of gold nanoparticles existing on the surface. The substrate for analyzing the coverage of self-assembled molecules includes: a biomaterial immobilization substrate; a self-assembled molecular layer formed on the substrate and having a functional group capable of reacting with an amine group; a capture DNA molecule having an amine group bounded to the self-assembled molecular layer; and a probe DNA molecule bound to the capture DNA molecule and having nanoparticles attached to on the surface. | 2010-01-21 |
20100015719 | NOVEL MIXTURES FOR ASSAYING NUCLEIC ACID, NOVEL METHOD OF ASSAYING NUCLEIC ACID WITH THE USE OF THE SAME AND NUCLEIC ACID PROBE TO BE USED THEREFOR - [Problems] To provide a novel mixture for assaying a target nucleic acid, characterized by enabling a nucleic acid assay while: 1) requiring no step of diluting the target nucleic acid; 2) requiring no procedure of changing a probe concentration depending on a concentration of the target nucleic acid. | 2010-01-21 |
20100015720 | Dynamic desalter simulator - A small-scale dynamic simulator for crude oil refinery desalters has a pressurized oil deviblis configured to hold a supply of crude oil and a water deviblis configured to hold a supply of wash water. At least one chemical feed pump selectively adds emulsion breaker chemicals to the desalter simulator and a low shear metering pump is configured to pump crude oil and wash water through the desalter simulator. An emulsion forming device forms a crude oil-wash water emulsion that is then received in a desalter vessel. The desalting vessel is fitted with electric grids which simulate those found in electric desalters. The emulsion is resolved within the desalter vessel with the assistance of the emulsion breaker chemicals so the wash water and crude oil form distinct phases, with substantially desalted crude oil removed from an upper portion of the desalter vessel and substantially oil-free wash water removed from a bottom portion of the desalter vessel. A portion of the desalter vessel is substantially transparent to allow visualization of the demulsification process and at least one light source is positioned adjacent to the desalter vessel to aid in visualization of a rag layer formed in the desalter vessel. A heated jacket surrounds the desalter vessel to maintain the desalter vessel at the desired temperature. | 2010-01-21 |
20100015721 | Detection of Promiscuous Small Submicrometer Aggregates - The invention provides methods for the detection of aggregating molecules that are capable of promiscuous or non-specific binding to proteins in a time efficient manner without the use of labels. | 2010-01-21 |
20100015722 | Detection Apparatus - IMS apparatus has an inlet with a preconcentrator opening into a reaction region where analyte molecules are ionized and passed via a shutter to a drift region for collection and analysis. A pump and filter arrangement supplies a flushing flow of clean gas to the housing in opposition to ion flow. A pressure pulser connects with the housing and is momentarily switched to cause a short drop in pressure, in the housing to draw in a bolus of analyte sample from the preconcentrator. Just prior to admitting a bolus of sample, the pump is turned off so that the flushing flow drops substantially to zero, thereby prolonging the time the analyte molecules spend in the reaction region. | 2010-01-21 |
20100015723 | Antagonists of Interleukin-15 - Antagonists of mammalian interleukin-15 (“IL-15”) are disclosed and include muteins of IL-15 and modified IL-15 molecules that are each capable of binding to the IL-15Rα-subunit and that are incapable of transducing a signal through either the β- or γ-subunits of the IL-15 receptor complex. Also included are monoclonal antibodies against IL-15 that prevent IL-15 from effecting signal transduction through either the β- or γ-subunits of the IL-15 receptor complex. Methods of treating various disease states are disclosed, including treating allograft rejection and graft-versus-host disease. | 2010-01-21 |
20100015724 | LYSINE ACETYLATION SITES - The invention discloses 332 novel acetylation sites identified in various cancers, peptides (including AQUA peptides) comprising a acetylation site of the invention, antibodies specifically bind to a novel acetylation site of the invention, and diagnostic and therapeutic uses of the above. | 2010-01-21 |
20100015725 | LUMINESCENT 1-HYDROXY-2-PYRIDINONE CHELATES OF LANTHANIDES - The present invention provides luminescent complexes between a lanthanide ion and an organic ligand which contains 1,2-hydroxypyridinone units. The complexes of the invention are stable in aqueous solutions and are useful as molecular probes, for example in medical diagnostics and bioanalytical assay systems. The invention also provides methods of using the complexes of the invention. | 2010-01-21 |
20100015726 | SINGLE COLUMN IMMUNOLOGICAL TEST ELEMENTS - A plurality of individual single column test elements are provided for use in a clinical testing apparatus. Each test element is defined by a single test column that includes a quantity of a test material, such as gel material or a bead matrix, including a cover strip used to access the contents of the test column. Individual test elements can be stored, retained and dispensed for testing patient samples. | 2010-01-21 |
20100015727 | METHOD FOR DETERMINING TRANSPORT ACTIVITY OF A TRANSPORT PROTEIN - The present invention relates to a method for determining transport activity of a transport protein and its use for the identification of compounds which can modulate said transport activity. | 2010-01-21 |
20100015728 | Assay Device and Method - A method for detecting an analyte can include binding an analyte with a first reagent which is associated with a magnetic particle, allowing analyte to interact with an excess amount of a second reagent capable of interacting with the analyte, and magnetically separating a portion of analyte-bound second reagent from excess second reagent. After the magnetic separation, the interaction of the analyte and the second reagent can be disrupted to produce a detectable form of the second reagent, which can be detected. A device and system suited to performing the method are also described. | 2010-01-21 |
20100015729 | METHODS OF FORMING A THIN FERROELECTRIC LAYER AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME - In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved. | 2010-01-21 |
20100015730 | Magnetic self-assembly for integrated circuit packages - An integrated circuit package may include a substrate and an integrated circuit. The substrate may include at least one region, and a first magnetic material associated with the at least one region. The integrated circuit may have a second magnetic material associated therewith. The second magnetic material may be attracted to the first magnetic material to coupled the integrated circuit to the at least one region of the substrate. The IC package may be utilized in an RFID tag of an RFID system. An associated method for assembling an integrated circuit to a substrate is also provided. | 2010-01-21 |
20100015731 | Method of low-k dielectric film repair - An apparatus, system and method for repairing a carbon depleted low-k material in a low-k dielectric film layer includes identifying a repair chemistry having a hydrocarbon group, the repair chemistry configured to repair the carbon depleted low-k material and applying the identified repair chemistry meniscus to the low-k dielectric film layer such that the carbon depleted low-k material in the low-k dielectric film layer is sufficiently exposed to the repair chemistry meniscus substantially repairing the low-k material. The repaired low-k material exhibits substantially equivalent low-k dielectric characteristics of the low-k dielectric film layer. | 2010-01-21 |
20100015732 | SEMICONDUCTOR CHIP REPAIR BY STACKING OF A BASE SEMICONDUCTOR CHIP AND A REPAIR SEMICONDUCTOR CHIP - Base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet, which provides the same functionality as one of the at least one non-functional chiplet is designed to provide, is vertically stacked. The at least one repair semiconductor chiplet provides the functionality that the at least one non-functional chiplet is designed to provide to the base semiconductor chip. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional. In case a first attempt to repair the base semiconductor chip by stacking repair semiconductor chips is unsuccessful, additional repair semiconductor chips may be subsequently stacked to fully repair the base semiconductor chip. | 2010-01-21 |
20100015733 | METHOD AND DEVICE FOR MONITORING A HEAT TREATMENT OF A MICROTECHNOLOGICAL SUBSTRATE - A method of monitoring a heat treatment of a microtechnological substrate includes placement of the substrate to be treated in a heating zone and applying a heat treatment to the substrate, under predetermined temperature conditions, while monitoring the change over the course of time in the vibratory state of the substrate, and detecting a fracture in the substrate by detecting a peak characteristic in the vibratory state over the course of time. | 2010-01-21 |
20100015734 | Formation of Through-Wafer Electrical Interconnections and Other Structures Using a Thin Dielectric Membrane - Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a preexisting semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes. | 2010-01-21 |
20100015735 | OBSERVATION METHOD OF WAFER ION IMPLANTATION DEFECT - An analysis method of wafer ion implant is presented, the steps of the method comprises: (a) cleave a wafer for analysis, and (b) from these pieces of wafers determine which ones are wafer with defect and set an insulator on the wafer with defect, (c) finally, use scanning electron microscope to observe whether the ion implant on the wafer with defect was correct or not. Whereby, engineers can take less time to analyze whether the ion implant of the wafer is correct or not with 100% repeatability. | 2010-01-21 |
20100015736 | METHOD OF FABRICATING A CHIP - A method of fabricating a chip may include the step of providing a first electrical part. The method may also include the step of forming a shell with the first electrical part embedded in a first side portion of the shell and a cavity in a second side portion of the shell. The method may include the step of testing the embedded first electrical part to determine whether the first electrical part is defective or functional. The method may also include the steps of providing a second electrical part, inserting the second electrical part within the cavity of the shell second side portion, establishing electrical communication between the first and second electrical parts if a test result of the first electrical part indicates that the first electrical part is functional, and finishing the chip. Also, the method may include the step of rejecting the first electrical part if the test result of the first electrical part indicates that the first electrical part is defective. | 2010-01-21 |
20100015737 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, AND METHOD OF MANUFACTURING BASE MATERIAL - It is an object of the invention to provide a lightweight semiconductor device having a highly reliable sealing structure which can prevent ingress of impurities such as moisture that deteriorate element characteristics, and a method of manufacturing thereof. A protective film having superior gas barrier properties (which is a protective film that is likely to damage an element if the protective film is formed on the element directly) is previously formed on a heat-resistant substrate other than a substrate with the element formed thereon. The protective film is peeled off from the heat-resistant substrate, and transferred over the substrate with the element formed thereon so as to seal the element. | 2010-01-21 |
20100015738 | Light emitting elements and methods of fabricating the same - Methods of fabricating light emitting elements and light emitting devices, light emitting elements and light emitting devices are provided. In some embodiments, the methods of fabricating a light emitting element includes forming a buffer layer on at least one first substrate, bonding the at least one first substrate on a second substrate, wherein the buffer layer is placed between each of the first substrate and the second substrate and the second substrate is larger than the first substrate, exposing the buffer layer, and sequentially forming a first conductive layer, a light emitting layer, and a second conductive layer on the exposed buffer layer. | 2010-01-21 |
20100015739 | SEMICONDUCTOR LIGHT EMITTING DEVICE HAVING IMPROVED LUMINANCE AND MANUFACTURING METHOD THEREOF - In the semiconductor light emitting device manufacturing method, a surface of a substrate, on which the semiconductor light emitting device is to be manufactured, is etched, thus forming a plurality of deep trenches. Semiconductor films are sequentially grown on the surface of the substrate in which the deep trenches are formed. The deep trenches are formed to have predetermined depth, so that, even if the semiconductor films are grown on the surface of the substrate, voids are formed in regions of the substrate in which the trenches are formed, and the voids are used as reflectors for light generated by the semiconductor light emitting device. | 2010-01-21 |
20100015740 | Liquid crystal display device and fabricating method thereof - A liquid crystal display device, including: first and second substrates; a gate line on the first substrate; a data line crossing the gate line having a gate insulating film therebetween to define a pixel area; a pixel electrode formed of a transparent conductive film in a pixel hole passing through the gate insulating film in the pixel area; and a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer defining a channel between the source electrode and the drain electrode, wherein the semiconductor layer overlaps with a source and drain metal pattern including the data line, the source electrode and the drain electrode; and wherein the drain electrode protrudes from the semiconductor layer toward inside of the pixel electrode to be connected to the pixel electrode. | 2010-01-21 |
20100015741 | FABRICATION PROCESS FOR SILICON RIDGE WAVEGUIDE RING RESONATOR - An embodiment of a method for manufacturing an optical ring resonator device is disclosed. The method forms a ring resonator waveguide on a semiconductor substrate, forms an unoriented electro-optic polymer cladding over the ring resonator waveguide, and forms electrodes on the semiconductor substrate. The unoriented electro-optic polymer cladding is configured to change orientation under an applied electric field, and the electrodes are coupled to the optical ring resonator for manipulation of the electric field applied to the oriented electro-optic polymer cladding for rapid voltage tuning of its index. | 2010-01-21 |
20100015742 | METHOD FOR FABRICATING LIGHT EMITTING DIODE CHIP - A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode. | 2010-01-21 |
20100015743 | ETCHED-FACET RIDGE LASERS WITH ETCH-STOP - A photonic device incorporates an epitaxial structure having an active region, and which includes a wet etch stop layer above, but close to, the active region. An etched-facet ridge laser is fabricated on the epitaxial structure by dry etching followed by wet etching. The dry etch is designed to stop before reading the depth needed to form the ridge. The wet etch completes the formation of the ridge and stops at the wet etch stop layer. | 2010-01-21 |
20100015744 | Micro-Electromechanical Device and Method of Making the Same - A method of manufacturing a cantilever-based micro-electromechanical device comprising the steps of providing a first conductive material layer on a substrate to from a plurality of electrodes. Then, depositing a sacrificial material layer on the electrodes and substrate, thereby defining a non-exposed surface and an exposed surface of the sacrificial material. The method comprises the steps of patterning and etching the sacrificial material layer such that at least a portion of at least one electrode is exposed and spuner etching the sacrificial material layer such that the exposed surface of the sacrificial material layer comprises edges which are incongruous with the edges of the non-exposed surface. The method then involves forming a cantilever structure. Finally, the method comprises the step of removing at least a portion of the sacrificial material layer such that at least a portion of the cantilever structure is suspended. | 2010-01-21 |
20100015745 | METHOD AND STRUCTURE FOR A CMOS IMAGE SENSOR USING A TRIPLE GATE PROCESS - A method of forming a CMOS image sensor device, the method includes providing a semiconductor substrate having a P-type impurity characteristic including a surface region. The method form a first thickness of silicon dioxide in a first region of the surface region, a second thickness of silicon dioxide in a second region of the surface region, and a third thickness of silicon dioxide in a third region of the surface region. The method includes forming a first gate layer overlying the second region and a second gate layer overlying the third region, while exposing a portion of the first thickness of silicon dioxide. An N-type impurity characteristic is formed within a region within a vicinity underlying the first thickness of silicon dioxide in the first region of the surface region to cause formation of a photo diode device characterized by the N-type impurity region and the P-type substrate. | 2010-01-21 |
20100015746 | Method of Manufacturing Image Sensor - Provided is a method in which a photodiode layer is formed on a metal interconnection layer, and a hard mask layer is formed on the photodiode layer. Then, a photoresist pattern is formed on the hard mask layer to define a contact hole region, and a first hole is formed in the hard mask layer through an etching process. Next, an ion implantation etching layer is formed in the photodiode layer using the photoresist pattern as an ion implantation mask, and a second hole is formed by etching the ion implantation etching layer. A third hole is formed to expose the metal interconnection by etching a region of the metal interconnection layer corresponding to the second hole. | 2010-01-21 |
20100015747 | METHODS OF FABRICATING IMAGE SENSORS INCLUDING IMPURITY LAYER ISOLATION REGIONS - Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation region walls, wherein at least some of the logic isolation region walls are free of the impurity layer. The impurity layer and/or the less sloped logic isolation region walls may also be provided for NMOS devices in the logic region but not for PMOS devices in the logic region. Doped sacrificial layers may be used to fabricate the impurity layer. | 2010-01-21 |
20100015748 | Image Sensor and Method for Manufacturing the Same - A method for manufacturing an image sensor includes forming first to third photodiodes and first to third color filters corresponding thereto; forming a photoresist film including photosensitive materials on the upper surfaces of the first to third color filters; forming a first exposed part by exposing the photoresist film with a first exposure energy using a first pattern mask with a first light transmitting part having a first width at boundaries between the individual color filters; forming a second exposed part overlapping a portion of the first exposed part by exposing the photoresist film with a second exposure energy smaller than the first exposure energy using a second pattern mask with a second light transmitting part having a second width wider than the first width; and forming microlenses by developing the photoresist film. | 2010-01-21 |
20100015749 | RAPID THERMAL OXIDE PASSIVATED SOLAR CELL WITH IMPROVED JUNCTION - A method of manufacturing a solar cell is provided. One surface of a semiconductor substrate is doped with a n-type dopant. The substrate is then subjected to a thermal oxidation process to form an oxide layer on one or both surfaces of the substrate. The thermal process also diffuses the dopant into the substrate, smoothing the concentration profile. The smoothed concentration gradient enables the oxide layer to act as a passivating layer. Anti-reflective coatings may be applied over the oxide layers, and a reflective layer may be applied on the surface opposite the doped surface to complete the solar cell. | 2010-01-21 |
20100015750 | Process of manufacturing solar cell - A process of manufacturing a solar cell is disclosed. The process comprises steps of (a) providing a semiconductor substrate, (b) forming a dielectric layer with amorphous silicon structure on the semiconductor substrate, (c) partially removing the dielectric layer with amorphous silicon structure to expose parts of the semiconductor substrate, (d) simultaneously forming a heavily doped region on a surface of the exposed semiconductor substrate and a lightly doped region on a surface of the unexposed semiconductor substrate using the dielectric layer with amorphous silicon structure as a translucent barrier layer, (e) removing the dielectric layer with amorphous silicon structure, (f) forming an anti-reflection coating on the semiconductor substrate, and (g) forming a first electrode on the anti-reflection coating and coupled with the heavily doped region. | 2010-01-21 |
20100015751 | HYBRID HETEROJUNCTION SOLAR CELL FABRICATION USING A METAL LAYER MASK - Embodiments of the invention contemplate the formation of a high efficiency solar cell using a novel processing sequence to form a solar cell device. In one embodiment, the methods include the use of various etching and patterning processes that are used to define active regions of the device and regions where the device and/or contact structure is to be located on a surface of a solar cell substrate. The method generally includes the steps of forming one or more layers on a backside of a solar cell substrate to prevent attack of the backside surface of the substrate, and provide a stable supporting surface, when the front side regions of a solar cell are formed. In one embodiment, the one or more layers are a metalized backside contact structure that is formed on the backside of the solar cell substrate. In another embodiment, the one or more layers are a chemical resistant dielectric layer that is formed over the backside of the solar cell substrate. | 2010-01-21 |
20100015752 | Methods of Preparing Photovoltaic Modules - Methods of preparing photovoltaic modules, as well as related components, systems, and devices, are disclosed. | 2010-01-21 |
20100015753 | High Power Efficiency, Large Substrate, Polycrystalline CdTe Thin Film Semiconductor Photovoltaic Cell Structures Grown by Molecular Beam Epitaxy at High Deposition Rate for Use in Solar Electricity Generation - Solar cell structures formed using molecular beam epitaxy (MBE) that can achieve improved power efficiencies in relation to prior art thin film solar cell structures are provided. A reverse p-n junction solar cell device and methods for forming the reverse p-n junction solar cell device using MBE are described. A variety of n-p junction and reverse p-n junction solar cell devices and related methods of manufacturing are provided. N-intrinsic-p junction and reverse p-intrinsic-n junction solar cell devices are also described. | 2010-01-21 |
20100015754 | METHOD AND APPARATUS TO FORM THIN LAYERS OF PHOTOVOLTAIC ABSORBERS - A method and a system are provide for forming planar precursor structures which are subsequently converted into thin film solar cell absorber layers. A precursor structure is first formed on the front surface of the foil substrate and then planarized through application of force or pressure by a smooth surface to obtain a planar precursor structure. The precursor structure includes at least one of a Group IB material, Group IIIA material and Group VIA material. The planar precursor structures are reacted to form planar and compositionally uniform thin film absorber layers for solar cells. | 2010-01-21 |
20100015755 | MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - In a step of forming an InGeSbTe film which contains GeSbTe made of germanium (Ge), antimony (Sb) and tellurium (Te) as its base material and to which indium (In) is added, an InGeSbTe film is formed by sputtering on a semiconductor substrate while keeping a temperature of the semiconductor substrate between an in-situ crystallization temperature of GeSbTe serving as the base material and an in-situ crystallization temperature of InGeSbTe. As a result, it is possible to suppress the failure that the phase separation occurs in the InGeSbTe film during the following manufacturing process. | 2010-01-21 |
20100015756 | HYBRID HETEROJUNCTION SOLAR CELL FABRICATION USING A DOPING LAYER MASK - Embodiments of the invention contemplate the formation of a high efficiency solar cell using a novel processing sequence to form a solar cell device. In one embodiment, the methods include forming a doping layer on a back surface of a substrate, heating the doping layer and substrate to cause the doping layer diffuse into the back surface of the substrate, texturing a front surface of the substrate after heating the doping layer and the substrate, forming a dielectric layer on the back surface of the substrate, removing portions of the dielectric layer from the back surface to from a plurality of exposed regions of the substrate, and depositing a metal layer over the back surface of the substrate, wherein the metal layer is in electrical communication with at least one of the plurality of exposed regions on the substrate, and at least one of the exposed regions has dopant atoms provided from the doping layer. | 2010-01-21 |
20100015757 | BRIDGE RESISTANCE RANDOM ACCESS MEMORY DEVICE AND METHOD WITH A SINGULAR CONTACT STRUCTURE - A resistance random access memory in a bridge structure is disclosed that comprises a contact structure where first and second electrodes are located within the contact structure. The first electrode has a circumferential extending shape, such as an annular shape, surrounding an inner wall of the contact structure. The second electrode is located within an interior of the circumferential extending shape and separated from the first electrode by an insulating material. A resistance memory bridge is in contact with an edge surface of the first and second electrodes. The first electrode in the contact structure is connected to a transistor and the second electrode in the contact structure is connected to a bit line. A bit line is connected to the second electrode by a self-aligning process. | 2010-01-21 |
20100015758 | Nonvolatile Memory Device and Fabrication Method Thereof - A nonvolatile memory device and a method for its fabrication may ensure uniform operating characteristics of ReRAM. The ReRam may include a laminated resistance layer that determines phase of ReRAM on an upper edge of a lower electrode for obtaining a stable threshold drive voltage level. | 2010-01-21 |
20100015759 | POP Semiconductor Device Manufacturing Method - The objective of the invention is to prevent electrostatic destruction of semiconductor chips during resin molding. With the semiconductor device manufacturing method, a substrate 400 that includes on the surface multiple semiconductor chips 410 and liquid resin 434 supplied to multiple semiconductor devices is supported by an electrically insulated lower die 200. An upper die 110 in which multiple shape-forming parts (cavities) 112 are formed is pressed against lower die 200 through the medium of a polymer release film 300, and liquid resin 434 on the substrate is molded. | 2010-01-21 |
20100015760 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Of three chips ( | 2010-01-21 |
20100015761 | Thermally Enhanced Single Inline Package (SIP) - In a method and system for fabricating a thermally enhanced semiconductor device ( | 2010-01-21 |
20100015762 | Solder Interconnect - Various solder interconnect methods and apparatus are disclosed. In aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a circuit board with plural solder joints whereby an interstitial space is left between the semiconductor chip and the circuit board. The semiconductor chip and the circuit board are heated at a first temperature lower than a melting point of constituents of the plural solder joints to liberate contaminants from the interstitial space. The semiconductor chip and the circuit board are heated again at a second temperature higher than a melting point of at least one the constituents but not all of the constituents of the plural solder joints to shrink grain sizes of the at least one constituent. An underfill is placed in the interstitial space. | 2010-01-21 |
20100015763 | RESCUE STRUCTURE AND METHOD FOR LASER WELDING - A rescue structure to repair an open wire includes a first metal layer having at least a rescue line, an isolation layer formed on the first metal layer, and a second metal layer formed on the isolation layer. The second metal layer has at least a signal line crossing the rescue line to form an enlarged intersection node. The intersection node is particularly arranged far from the side where the rescue line is used for signal transmission. | 2010-01-21 |
20100015764 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a TFT including at least one LDD region in a self-alignment manner without forming a sidewall spacer and increasing the number of manufacturing steps. A photomask or a reticle provided with an assist pattern that is formed of a diffraction grating pattern or a semi-transmitting film and has a function of reducing light intensity is employed in a photolithography step of forming a gate electrode, an asymmetrical resist pattern having a region with a thick thickness and a region with a thickness thinner than that of the above region on one side is formed, a gate electrode having a stepped portion is formed, and an LDD region is formed in a self-alignment manner by injecting an impurity element to the semiconductor layer through the region with a thin thickness of the gate electrode. | 2010-01-21 |
20100015765 | SHALLOW AND DEEP TRENCH ISOLATION STRUCTURES IN SEMICONDUCTOR INTEGRATED CIRCUITS - A semiconductor structure fabrication method. The method includes providing a semiconductor structure which includes a first semiconductor layer and a dielectric bottom portion in the first semiconductor layer. A second semiconductor layer on the first semiconductor layer is formed. The first and second semiconductor layers include a semiconductor material. A dielectric top portion and a first STI (Shallow Trench Isolation) region are formed in the second semiconductor layer. The dielectric top portion is in direct physical contact with the dielectric bottom portion. | 2010-01-21 |
20100015766 | COMPLEMENTARY STRESS MEMORIZATION TECHNIQUE LAYER METHOD - A process of forming a CMOS integrated circuit by forming a first stressor layer over two MOS transistors of opposite polarity, removing a portion of the first stressor layer from the first transistor, and forming a second stressor layer over the two transistors. A source/drain anneal is performed, crystallizing amorphous regions of silicon in the gates of the two transistors, and subsequently removing the stressor layers. A process of forming a CMOS integrated circuit by forming two transistors of opposite polarity, forming a two stressor layers over the transistors, annealing the integrated circuit, removing the stressor layers, and siliciding the transistors. A process of forming a CMOS integrated circuit with an NMOS transistor and a PMOS transistor using a stress memorization technique, by removing the stressor layers with wet etch processes. | 2010-01-21 |
20100015767 | CELL REGION LAYOUT OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONTACT PAD USING THE SAME - A cell region layout of a semiconductor device formed by adding active regions in the outermost portion of a cell region, and a method of forming a contact pad using the same are provided. The layout and the method include a first active region formed at the outermost portion of the cell region, and having the same shape as that of an inner active region located inwardly from the outermost portion of the cell region, and a third active region formed by adding at least two second active regions having shapes different from that of an inner active region. Further, an insulating layer fills a portion below a bit line passing the third active region. A lifting phenomenon occurring where an active region is not formed can be prevented by adding the active regions at the outermost portion of the cell region, and a bridge phenomenon occurring when bit lines or a bit line contact and a gate line electrically contact can be suppressed by filling a portion below a bit line with an insulating layer. | 2010-01-21 |
20100015768 | Method of fabricating semiconductor device having a junction extended by a selective epitaxial growth (SEG) layer - In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls of a channel region of the protrusion. | 2010-01-21 |
20100015769 | Power Device With Trenches Having Wider Upper Portion Than Lower Portion - A method of forming a semiconductor device includes the following. A masking layer with opening is formed over a silicon layer. The silicon layer is isotropically etched through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each of which includes a middle portion and outer portions extending directly underneath the masking layer. The outer portions form outer sections of corresponding trenches. Additional portions of the silicon layer are removed through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches. A first doped region of a first conductivity type is formed in an upper portion of the silicon layer. An insulating layer is formed within each trench, and extends directly over a portion of the first doped region adjacent each trench sidewall. Silicon is removed from adjacent each trench until, of the first doped region, only the portions adjacent the trench sidewalls remain. The remaining portions of the first doped region adjacent the trench sidewalls form source regions which are self-aligned to the trenches. | 2010-01-21 |
20100015770 | Double gate manufactured with locos techniques - This invention discloses a method for manufacturing a trenched semiconductor power device that includes step of opening a trench in a semiconductor substrate. The method further includes a step of opening a top portion of the trench first then depositing a SiN on sidewalls of the top portion followed by etching a bottom surface of the top portion of the trench then silicon etching to open a bottom portion of the trench with a slightly smaller width than the top portion of the trench. The method further includes a step of growing a thick oxide layer along sidewalls of the bottom portion of the trench thus forming a bird-beak shaped layer at an interface point between the top portion and bottom portion of the trench. | 2010-01-21 |
20100015771 | METHOD OF FABRICATING STRAINED SILICON TRANSISTOR - A method of fabricating a strained silicon transistor is provided. Amorphous silicon is formed below the transistor region before the transistor is formed. By using the tensile/compressive strainer, amorphous silicon is recrystallized to form a strained silicon layer. In addition, the dopants in the well can be driven in and activated by using the same annealing process with the amorphous silicon recrystallization. | 2010-01-21 |
20100015772 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance. | 2010-01-21 |
20100015773 | SONOS MEMORY DEVICE HAVING CURVED SURFACE AND METHOD FOR FABRICATING THE SAME - A new SONOS memory device is provided, in which a conventional planar surface of multi-dielectric layers (ONO layers) is instead formed with a curved surface such as a cylindrical shape, and included is a method for fabricating the same. | 2010-01-21 |
20100015774 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer. | 2010-01-21 |
20100015775 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH RECESS GATE - A method for fabricating a semiconductor device with a recess gate includes providing a substrate, forming an isolation layer over the substrate to define an active region, forming mask patterns with a first width opening exposing a region where recess patterns are to be formed, and a second width opening smaller than the first width and exposing the isolation layer, forming a passivation layer along a height difference of the mask patterns, etching the substrate using the passivation layer and the mask patterns as an etch barrier to form recess patterns, removing the passivation layer and the mask patterns, and forming gate patterns protruding from the substrate to fill the recess patterns. | 2010-01-21 |
20100015776 | Shallow Trench Isolation Corner Rounding - A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in a hydrogen ambient, which rounds the corners of the shallow trench isolation through silicon migration. | 2010-01-21 |
20100015777 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, includes forming an amorphous silicon film above a semiconductor substrate, partially removing each of the amorphous silicon film and the semiconductor substrate, thereby forming an element isolation trench in a surface of the semiconductor substrate, forming an insulating film above the amorphous silicon film so that the element isolation trench is filled with the insulating film, polishing the insulating film by a chemical-mechanical polishing method with the amorphous silicon film serving as a stopper, thereby planarizing an upper surface of the insulating film, and thermally-treating the amorphous silicon film, thereby converting to a polysilicon film after polishing the insulating film. | 2010-01-21 |
20100015778 | METHOD OF FORMING FINNED SEMICONDUCTOR DEVICES WITH TRENCH ISOLATION - A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure. Thereafter, at least a portion of the dielectric material and at least a portion of the spacers are etched away to expose an upper section of the first conductive fin structure and an upper section of the second conductive fin structure, while preserving the dielectric material in the isolation trench. Following these steps, the fabrication of the devices is completed in a conventional manner. | 2010-01-21 |
20100015779 | METHOD FOR PRODUCING BONDED WAFER - There is provided a bonded wafer having excellent thickness uniformity after thinning but also good surface roughness and being less in defects. | 2010-01-21 |
20100015780 | TRANSFER METHOD WITH A TREATMENT OF A SURFACE TO BE BONDED - A method for minimizing or avoiding contamination of a receiving handle wafer during transfer of a thin layer from a donor wafer. This method includes providing a donor wafer and a receiving handle wafer, each having a first surface prepared for bonding and a second surface, with the donor wafer providing a layer of material to be transferred to the receiving handle wafer. Next, at least one of the first surfaces is treated to provide increased bonding energy when the first surfaces are bonded together; the surfaces are then bonded together to form an intermediate multilayer structure; and a portion of the donor wafer is removed to transfer the thin layer to the receiving handle wafer and form the semiconductor structure. This method avoids or minimizes contamination of the second surface of the receiving handle wafer by treating only the first surface of the donor wafer prior to bonding by exposure to a plasma, and by conducting any thermal treatments after plasma activation at a temperature of 300° C. to 500° C. in order to avoid diffusion of impurities into the transfer layer. | 2010-01-21 |
20100015781 | SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - In a semiconductor substrate | 2010-01-21 |
20100015782 | Wafer Dicing Methods - Semiconductor wafer dicing methods are disclosed. These methods include forming etch patterns between adjacent semiconductor dice to be separated. Various etch processes can be used to form the etch patterns. The etch patterns generally reach a pre-determined depth into the wafer substrate significantly beyond the wafer top layer where pre-fabricated semiconductor dice are embedded. Semiconductor dice may be separated from a post-etch, large-sized, frangible wafer through wafer grinding, mechanical cleaving, and laser dicing approaches. Preferred embodiments result in reduced wafer-dicing related device damage and improved product yield. | 2010-01-21 |
20100015783 | METHOD OF CUTTING AN OBJECT TO BE PROCESSED - A method of cutting an object which can accurately cut the object is provided. An object to be processed | 2010-01-21 |