03rd week of 2012 patent applcation highlights part 13 |
Patent application number | Title | Published |
20120012831 | COMPOUND HAVING BENZOTRIAZOLE RING STRUCTURE AND ORGANIC ELECTROLUMINESCENT ELEMENT - A compound having a benzotriazole ring structure and a formula (1): | 2012-01-19 |
20120012832 | AROMATIC AMINE DERIVATIVE AND ORGANIC ELECTROLUMINESCENT ELEMENT USING SAME - There are provided an aromatic monoamine derivative having a fluorene structure-containing organic group and an aromatic hydrocarbon group-containing organic group, and an organic electroluminescent element containing an organic thin film layer composed of a single layer or plural layers while including at least a light emitting layer, the organic thin film layer being between a cathode and an anode, wherein at least one layer of the organic thin film layer, particularly a hole transport layer, contains the aromatic amine derivative alone or as a component of a mixture. An organic electroluminescent element which maintains high luminous efficiency even if exposed to a high temperature environment, and has a low driving voltage and a long emission lifetime, and an aromatic amine derivative capable of realizing the organic electroluminescent element are provided. | 2012-01-19 |
20120012833 | LIGHT-EMITTING ELEMENT MATERIAL PRECURSOR AND PRODUCTION METHOD THEREFOR - A light emitting device material precursor represented by the Formula (1): | 2012-01-19 |
20120012834 | ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE, METHOD FOR PRODUCING SAME, COLOR FILTER SUBSTRATE AND METHOD FOR PRODUCING SAME - The present invention provides an organic EL display device and a color filter substrate that can be manufactured inexpensively and easily and that allow reducing the size of pixel regions, and also provides a manufacturing method of the organic EL display device and a manufacturing method of the color filter substrate. The organic EL display device of the present invention is an organic EL display device which comprises a substrate in which a plurality of pixel regions of first to third colors is disposed within a display area, and in which a functional material layer comprising an organic emissive layer is disposed at each of the plurality of pixel regions, wherein first to third partition parts are disposed on the substrate within the display area, first to third frame-like structures are disposed on the substrate outside the display area, the pixel region of the first color is disposed within a first demarcation region demarcated by the first partition part, the pixel region of the second color is disposed within a second demarcation region demarcated by the second partition part, the pixel region of the third color is disposed within a third demarcation region demarcated by the third partition part, the first demarcation region is connected to the interior of the first frame-like structure, the second demarcation region is connected to the interior of the second frame-like structure, and the third demarcation region is connected to the interior of the third frame-like structure. | 2012-01-19 |
20120012835 | Metal Oxide Semiconductor Thin Film Transistors - A top gate and bottom gate thin film transistor (TFT) are provided with an associated fabrication method. The TFT is fabricated from a substrate, and an active metal oxide semiconductor (MOS) layer overlying the substrate. Source/drain (S/D) regions are formed in contact with the active MOS layer. A channel region is interposed between the S/D regions. The TFT includes a gate electrode, and a gate dielectric interposed between the channel region and the gate electrode. The active MOS layer may be ZnOx, InOx, GaOx, SnOx, or combinations of the above-mentioned materials. The active MOS layer also includes a primary dopant such as H, K, Sc, La, Mo, Bi, Ce, Pr, Nd, Sm, Dy, or combinations of the above-mentioned dopants. The active MOS layer may also include a secondary dopant. | 2012-01-19 |
20120012836 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process. | 2012-01-19 |
20120012837 | SEMICONDUCTOR DEVICE - A semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of write cycles. The semiconductor device includes a memory cell including a first transistor, a second transistor, and an insulating layer placed between a source region or a drain region of the first transistor and a channel formation region of the second transistor. The first transistor and the second transistor are provided to at least partly overlap with each other. The insulating layer and a gate insulating layer of the second transistor satisfy the following formula: (t | 2012-01-19 |
20120012838 | SWITCHING ELEMENT - A switching element of LCDs or organic EL displays which uses a thin film transistor device, includes: a drain electrode, a source electrode, a channel layer contacting the drain electrode and the source electrode, wherein the channel layer comprises indium-gallium-zinc oxide having a transparent, amorphous state of a composition equivalent to InGaO | 2012-01-19 |
20120012839 | OXIDE THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME - A method for fabricating a liquid crystal display (LCD) device include: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate; forming a primary active layer having a tapered portion to a side of a channel region of the primary active layer on the gate insulating layer, and forming source and drain electrodes on the primary active layer; and forming a secondary active layer made of amorphous zinc oxide-based semiconductor on the source and drain electrodes and being in contact with the tapered portion of the primary active layer, wherein the primary active layer is etched at a low selectivity during a wet etching of the source and drain electrodes, to have the tapered portion. | 2012-01-19 |
20120012840 | Thin-film Transistor (TFT) With A Bi-layer Channel - In at least some embodiments, a thin-film transistor (TFT) includes a gate electrode and a gate dielectric covering the gate dielectric. The TFT also includes a source electrode and a drain electrode adjacent the gate dielectric. The TFT also includes a bi-layer channel between the source electrode and the drain electrode, the bi-layer channel having a zinc indium oxide (ZIO) layer positioned adjacent the gate dielectric and a zinc tin oxide (ZTO) layer that covers the ZIO layer. | 2012-01-19 |
20120012841 | Through-silicon via testing structure - A through-silicon via (TSV) testing structure is disclosed herein and includes a plurality of controllers, a plurality of transmitters and a plurality of receivers. The controllers are configured to output a first controlling signal and a second controlling signal. The transmitters are respectively connected to the output end of the through-silicon via and one of the controllers, and output a testing output signal in accordance with the first controlling signal and the second controlling signal. The receivers are respectively connected to the input end of the through-silicon via and another one of the controllers, and input a testing input signal in accordance with the first controlling signal and the second controlling signal. | 2012-01-19 |
20120012842 | SEMICONDUCTOR DEVICE HAVING FUNCTION OF TRANSMITTING/RECEIVING - In one embodiment, a semiconductor device includes an integrated circuit formed in an area enclosed by dicing lines formed in a matrix manner, and a signal wiring formed on at least one of the dicing lines. The integrated circuit includes a transmitter circuit having a signal output pad, a receiver circuit having a signal input pad and an internal circuit to process data inputted to the transmitter circuit and outputted from the receiver circuit. The signal wiring electrically connects the signal output pad and the signal input pad. | 2012-01-19 |
20120012843 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DESIGNING THE SAME - Unless layers over a TEG pattern are removed, a test using the TEG pattern is conducted. Multiple wiring layers are formed over a first TEG pattern. A wiring and multiple dummy patterns are formed in each of the wiring layers. An electrode pad is formed in an uppermost wiring layer. In a planar view, the first TEG pattern eliminates overlap with all of the wirings and the dummy patterns. | 2012-01-19 |
20120012844 | SEMICONDUCTOR MEMORY APPARATUS FOR CONTROLLING PADS AND MULTI-CHIP PACKAGE HAVING THE SAME - A semiconductor memory apparatus includes a first pad group located along a first edge of a plurality of banks, a second pad group located along a second edge of the plurality of banks opposite the first pad group, and a pad control section configured to provide first and second bonding signals and to implement control operation in response to a test mode signal and a bonding option signal to selectively employ signals from the first and second pad groups. | 2012-01-19 |
20120012845 | SEMICONDUCTOR DEVICE - A semiconductor device with a novel structure is provided, which can hold stored data even when no power is supplied and which has no limitations on the number of writing operations. A semiconductor device is formed using a material which enables off-state current of a transistor to be reduced significantly; e.g., an oxide semiconductor material which is a wide-gap semiconductor. With use of a semiconductor material which enables off-state current of a transistor to be reduced significantly, the semiconductor device can hold data for a long period. In a semiconductor device with a memory cell array, parasitic capacitances generated in the nodes of the first to the m-th memory cells connected in series are substantially equal, whereby the semiconductor device can operate stably. | 2012-01-19 |
20120012846 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device and a display device which can be manufactured through a simplified process and the manufacturing technique. Another object is to provide a technique by which a pattern of wirings or the like which is partially constitutes a semiconductor device or a display device can be formed with a desired shape with controllability. | 2012-01-19 |
20120012847 | DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor. | 2012-01-19 |
20120012848 | Organic light-emitting display device and method of manufacturing the same - An organic light-emitting display device and method of manufacturing the same, the device including a first substrate; a second substrate facing the first substrate; an organic light-emitting unit formed by laser-induced thermal imaging, the organic light emitting unit being on the first substrate; a coupling member coupling the first substrate and the second substrate; and a supporting element on the first substrate, the supporting element having a height greater than a height of a thickest portion of the organic light-emitting unit and less than a height of the coupling member. | 2012-01-19 |
20120012849 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display device capable of preventing outgassing from a pixel defining layer (PDL) or a planarization layer and method of manufacturing the same. | 2012-01-19 |
20120012850 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS - An organic light emitting display apparatus in which image quality can be improved. The organic light emitting display apparatus includes: a substrate; a first electrode disposed on the substrate; a pixel definition layer formed on the first electrode and having an opening portion through which a region of the first electrode is exposed; an intermediate layer connected to the first electrode through the opening portion and including an organic emission layer; a second electrode electrically connected to the intermediate layer; and an inorganic planarization pattern portion disposed between the substrate and the first electrode and formed to at least correspond to the opening portion. | 2012-01-19 |
20120012851 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A pixel TFT formed in a pixel region is formed on a first substrate by a channel etch type reverse stagger type TFT, and patterning of a source region and a drain region, and patterning of a pixel electrode are performed by the same photomask. A driver circuit formed by using TFTs having a crystalline semiconductor layer, and an input-output terminal dependent on the driver circuit, are taken as one unit. A plurality of units are formed on a third substrate, and afterward the third substrate is partitioned into individual units, and the obtained stick drivers are mounted on the first substrate. | 2012-01-19 |
20120012852 | METHOD OF MANUFACTURING THIN FILM TRANSISTOR - The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist | 2012-01-19 |
20120012853 | TFT ARRANGEMENT FOR DISPLAY DEVICE - A new TFT arrangement is demonstrated, which enables prevention of TFT to be formed over a joint portion between the adjacent SOI layers prepared by the process including the separation of a thin single crystal semiconductor layer from a semiconductor wafer. The TFT arrangement is characterized by the structure where a plurality of TFTs each belonging to different pixels is gathered and arranged close to an intersection portion of a scanning line and a signal line. This structure allows the distance between regions, which are provided with the plurality of TFTs, to be extremely large compared with the distance between adjacent TFTs in the conventional TFT arrangement in which all TFTs are arranged in at a regular interval. The formation of a TFT over the joint portion can be avoided by the present arrangement, which leads to the formation of a display device with a negligible amount of display defects. | 2012-01-19 |
20120012854 | ACTIVE MATRIX SUBSTRATE, DISPLAY PANEL, DISPLAY DEVICE, AND LASER IRRADIATION METHOD - In an active matrix substrate ( | 2012-01-19 |
20120012855 | SOLID-STATE LIGHT EMITTERS HAVING SUBSTRATES WITH THERMAL AND ELECTRICAL CONDUCTIVITY ENHANCEMENTS AND METHOD OF MANUFACTURE - Solid-state lighting devices (SSLDs) including a carrier substrate with conductors and methods of manufacturing SSLDs. The conductors can provide (a) improved thermal conductivity between a solid-state light emitter (SSLE) and a package substrate and (b) improved electrical conductivity for the SSLE. In one embodiment, the conductors have higher thermal and electrical conductivities than the carrier substrate supporting the SSLE. | 2012-01-19 |
20120012856 | GaN Light Emitting Diode and Method for Increasing Light Extraction on GaN Light Emitting Diode Via Sapphire Shaping - A method for enhancing light extraction efficiency of GaN light emitting diodes is disclosed. By cutting off a portion from each end of bottom of a sapphire substrate or forming depressions on the bottom of the substrate and forming a reflector, light beams emitted to side walls of the substrate can be guided to the light emitting diodes. | 2012-01-19 |
20120012857 | WIDE-GAP SEMICONDUCTOR SUBSTRATE AND METHOD TO FABRICATE WIDE-GAP SEMICONDUCTOR DEVICE USING THE SAME - A wide-gap semiconductor substrate includes a narrow-gap semiconductor layer, a wide-gap semiconductor layer and an alignment mark. The narrow-gap semiconductor layer has a main surface. The wide-gap semiconductor layer is epitaxially grown on the narrow-gap semiconductor layer. The alignment mark is preliminarily carved in a prescribed position on the main surface so that the alignment mark is preliminarily buried in the wide-gap semiconductor substrate. | 2012-01-19 |
20120012858 | SEMICONDUCTOR DEVICE - A semiconductor device includes source fingers and drain fingers provided on an active region of a nitride semiconductor layer alternately, gate fingers having a side edge and a distal edge, a first insulation film provided on the nitride semiconductor layer and covers a top face, the side and distal edges of the gate fingers, field plates provided on the first insulation film between the gate fingers and the drain fingers, a minimum distance between the side face of the first insulation film located on the side edge of the gate fingers and the field plate being at least 100 nm, and field plate interconnections provided on the first insulation film and located outside of the active region and electrically connected with the source fingers and the field plates, a minimum distance between the side face of the first insulation film located on the distal edge of the gate fingers and the field plate interconnections being at least 100 nm. | 2012-01-19 |
20120012859 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a light emitting device and a method of manufacturing the same. A light emitting device includes an active layer; a first conductive semiconductor layer on the active layer; a second conductive semiconductor layer on the active layer so that the active layer is disposed between the first and second conductive semiconductor layers; and a photonic crystal structure comprising a first light extraction pattern on the first conductive semiconductor layer having a first period, and second light extraction pattern on the first conductive semiconductor layer having a second period, the first period being greater than λ/n, and the second period being identical to or smaller than λ/n, where n is a refractive index of the first conductive semiconductor layer, and λ is a wavelength of light emitted from the active layer. | 2012-01-19 |
20120012860 | SIC SEMICONDUCTOR DEVICE - A SiC semiconductor device includes a reverse type MOSFET having: a substrate; a drift layer and a base region on the substrate; a base contact layer and a source region on the base region; multiple trenches having a longitudinal direction in a first direction penetrating the source region and the base region; a gate electrode in each trench via a gate insulation film; an interlayer insulation film covering the gate electrode and having a contact hole, through which the source region and the base contact layer are exposed; a source electrode coupling with the source region and the base region through the contact hole; a drain electrode on the substrate. The source region and the base contact layer extend along with a second direction perpendicular to the first direction, and are alternately arranged along with the first direction. The contact hole has a longitudinal direction in the first direction. | 2012-01-19 |
20120012861 | SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type, each formed in a region extending from the surface of the semiconductor layer to a halfway portion of the same in the thickness direction, and each spaced apart from each other in a direction perpendicular to the thickness direction; source regions of the first conductivity type, each formed on the surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film. In the semiconductor layer, trenches extending between two neighboring source regions are formed by digging from the source of the semiconductor layer, the inside surface of the trenches are covered by the gate insulating film, and the gate electrodes comprise surface-facing parts, which face the surface of the semiconductor layer, and buried parts, which are buried in the trenches. | 2012-01-19 |
20120012862 | METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; and connecting the base substrate and SiC substrate to each other by forming an intermediate layer, which is made of carbon that is a conductor, between the base substrate and the SiC substrate. | 2012-01-19 |
20120012863 | INDIRECT-BANDGAP-SEMICONDUCTOR, LIGHT-EMITTING DIODE - An indirect-bandgap-semiconductor, light-emitting diode. The indirect-bandgap-semiconductor, light-emitting diode includes a plurality of portions including a p-doped portion of an indirect-bandgap semiconductor, an intrinsic portion of the indirect-bandgap semiconductor, and a n-doped portion of the indirect-bandgap semiconductor. The intrinsic portion is disposed between the p-doped portion and the n-doped portion and forms a p-i junction with the p-doped portion, and an i-n junction with the n-doped portion. The p-i junction and the i-n junction are configured to facilitate formation of at least one hot electron-hole plasma in the intrinsic portion when the indirect-bandgap-semiconductor, light-emitting diode is reverse biased and to facilitate luminescence produced by recombination of a hot electron with a hole. | 2012-01-19 |
20120012864 | LED ARRAY PACKAGE WITH A COLOR FILTER - A light source includes a substrate, a light emitting diode on the substrate within a cavity, a plate over the cavity, a phosphor layer on the plate, and a color filter on the plate between the phosphor layer and the cavity. | 2012-01-19 |
20120012865 | LED ARRAY PACKAGE WITH A HIGH THERMALLY CONDUCTIVE PLATE - A light source includes a substrate, a light emitting diode on the substrate, and a plate supporting member attached to the substrate and surrounding the light emitting diode to form a cavity. In addition, the light source includes a plate on the plate supporting member such that a distance between the plate and the substrate is approximately less than or equal to 1 mm. Furthermore, the light source includes a phosphor layer on the plate opposite the cavity. | 2012-01-19 |
20120012866 | BACKLIGHT MODULE AND LIGHT-EMITTING SOURCE PACKAGE STRUCTURE THEREOF - The present invention provides a backlight module and a light-emitting source package structure thereof. The light-emitting source package structure comprises: a heat-dissipation base, at least one chip and a heat-dissipation fixing element. The heat-dissipation base has a connection hole. The heat-dissipation fixing element further has a connection post and a heat-dissipation fin with an abutting surface, and the connection post of the heat-dissipation fixing element passes through a through hole of a fixed plate to fix in the connection hole, so that for closely aligning the abutting surface of the heat-dissipation fin and can abut against the fixed plate. Thus, and the heat-dissipation base and the heat-dissipation fixing element are stably fixed on the both sides of the fixed plate to ensure the tightly abutting relationship with the fixed plate and enhance the assembly reliability. Meanwhile, the heat-dissipation fin can additionally increase the heat-dissipation efficiency of the heat-dissipation fixing element. Thus, the temperature of the chip can be surely lowered to prevent from lowing the working efficiency of the chip. Hence, it is advantageous for the chip to stably work, and the lifetime thereof can be increased. | 2012-01-19 |
20120012867 | MULTI-DIMENSIONAL LIGHT-EMITTING DEVICE - The present application provides a multi-dimensional light-emitting device electrically connected to a power supply system. The multi-dimensional light-emitting device comprises a substrate, a blue light-emitting diode array and one or more phosphor layers. The blue light-emitting diode array, disposed on the substrate, comprises a plurality of blue light-emitting diode chips which are electrically connected. The multi-dimensional light-emitting device comprises a central area and a plurality of peripheral areas, which are arranged around the central area. The phosphor layer covers the central area. When the power supply system provides a high voltage, the central area and the peripheral areas of the multi-dimensional light-emitting device provide a first light and a plurality of second lights, respectively. The first light and the second lights are blended into a mixed light. | 2012-01-19 |
20120012868 | LIGHT EMITTING CHIP PACKAGE MODULE AND LIGHT EMITTING CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A light emitting chip package module includes a substrate, a light emitting chip package structure, and a magnetic device. The substrate has a surface. The light emitting chip package structure is disposed on the surface of the substrate. The light emitting chip package structure includes a carrier, a light emitting chip, and a sealant. The light emitting chip is disposed on and electrically connected to the carrier. The sealant is disposed on the carrier and covers the light emitting chip. The magnetic device is disposed next to the light emitting chip package structure to apply a magnetic field to the light emitting chip. | 2012-01-19 |
20120012869 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND DISPLAY DEVICE - A light emitting device includes a light emitting structure comprising a first semiconductor layer, an active layer and a second semiconductor layer, with an roughness formed in a surface of the first semiconductor layer; a phosphor layer arranged on the first semiconductor layer; and an adhesive activation layer arranged between the first semiconductor layer and the phosphor layer, wherein the adhesive activation layer fills a concave part of the roughness and a boundary surface between the adhesive activation layer and the phosphor layer is level. | 2012-01-19 |
20120012870 | Method of Manufacturing An Electric Optical Device in Which External Connection Terminals Are Formed - An electro-optical device includes an effective display region including a pixel, the pixel including a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode; and a wiring line connected to the second electrode at a position to the periphery of the effective display region, the wiring line including a first wiring layer and a second wiring layer that are electrically connected to each other and that overlap each other, the first wiring layer and the second wiring layer both extending in a direction in which an edge of the effective display region extends, the first wiring layer and the second wiring layer extending in the direction a distance that is longer than a distance in which the edge of the effective display region extends in the direction. | 2012-01-19 |
20120012871 | LIGHT EMITTING DEVICE - The present disclosure relates to methods for performing wafer-level measurement and wafer-level binning of LED devices. The present disclosure also relates to methods for reducing thermal resistance of LED devices. The methods include growing epitaxial layers consisting of an n-doped layer, an active layer, and a p-doped layer on a wafer of a growth substrate. The method further includes forming p-contact and n-contact to the p-doped layer and the n-doped layer, respectively. The method further includes performing a wafer-level measurement of the LED by supplying power to the LED through the n-contact and the p-contact. The method further includes dicing the wafer to generate diced LED dies, bonding the diced LED dies to a chip substrate, and removing the growth substrate from the diced LED dies. | 2012-01-19 |
20120012872 | LED PACKAGE STRUCTURE - An LED package structure includes a transparent substrate having a supporting face and a light-emergent face opposite to the supporting face, a housing disposed on the supporting face, two electrodes disposed on the housing, an LED chip disposed on the supporting face and electrically connected to the two electrodes, a reflecting layer covering the LED chip to reflect light emitted by the LED chip toward the transparent substrate, and a phosphor layer formed on the light-emergent face of the substrate. The phosphor layer includes a plurality of layers each having a specific light wavelength conversion range to generate a light with a predetermined color. | 2012-01-19 |
20120012873 | LIGHT EMITTING DIODE PACKAGE FOR MICROMINIATURIZATION - A light emitting diode package includes a metal thin film with a first surface and a second surface opposite to the first surface. The metal thin film further defines a first part and a second part electrically insulated from the first part. A light emitting diode die is formed on the first part of the metal thin film. The light emitting diode die includes a first electrode and a second electrode. The light emitting diode die is sealed within a glass encapsulation and the second surface of the metal thin film is exposed to the outside of the glass encapsulation for electrically connecting with an external power. | 2012-01-19 |
20120012874 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a substrate, a first semiconductor layer, a light emitting layer, a second semiconductor layer, and a translucent electrode. The substrate includes a first region provided along periphery of a first major surface and a second region provided on center side of the first major surface as viewed from the first region. The first semiconductor layer is provided on the first major surface of the substrate. The light emitting layer is provided on the first semiconductor layer. The second semiconductor layer is provided on the light emitting layer. The translucent electrode is provided on the second semiconductor layer. A reflectance in the second region is higher than a reflectance in the first region. | 2012-01-19 |
20120012875 | COMPONENT FOR LIGHT-EMITTING DEVICE, LIGHT-EMITTING DEVICE AND PRODUCING METHOD THEREOF - A component for a light-emitting device includes a fluorescent layer that is capable of emitting fluorescent light and a housing that is connected to the fluorescent layer for housing a light-emitting diode. | 2012-01-19 |
20120012876 | LIGHT EMITTING DEVICE - The present invention provides a light emitting device which can be improved in reliability and moreover which can be manufactured with low cost. A surface-mount type light emitting device | 2012-01-19 |
20120012877 | Quantum Dot White and Colored Light-Emitting Devices - A light-emitting device comprising a population of quantum dots (QDs) embedded in a host matrix and a primary light source which causes the QDs to emit secondary light and a method of making such a device. The size distribution of the QDs is chosen to allow light of a particular color to be emitted therefrom. The light emitted from the device may be of either a pure (monochromatic) color, or a mixed (polychromatic) color, and may consist solely of light emitted from the QDs themselves, or of a mixture of light emitted from the QDs and light emitted from the primary source. The QDs desirably are composed of an undoped semiconductor such as CdSe, and may optionally be overcoated to increase photoluminescence. | 2012-01-19 |
20120012878 | LIGHT EMITTING DEVICE HAVING A LATERAL PASSIBATION LAYER - Provided are a light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a light emitting structure comprising a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer, and a passivation layer protecting a surface of the light emitting structure. The passivation layer includes a first passivation layer on a top surface of the light emitting structure and a second passivation layer having a refractive index different from that of the first passivation layer, the second passivation layer being disposed on a side surface of the light emitting structure. The second passivation layer has a refractive index greater than that of the first passivation layer. | 2012-01-19 |
20120012879 | LEADFRAME-BASED PACKAGES FOR SOLID STATE LIGHT EMITTING DEVICES AND METHODS OF FORMING LEADFRAME-BASED PACKAGES FOR SOLID STATE LIGHT EMITTING DEVICES - A modular package for a light emitting device includes a leadframe including a first region having a top surface, a bottom surface and a first thickness and a second region having a top surface, a bottom surface and a second thickness that is less than the first thickness. The leadframe further includes an electrical lead extending laterally away from the second region, and the package further includes a thermoset package body on the leadframe and surrounding the first region. The thermoset package body may be on both the top and bottom surfaces of the second region. A leak barrier may be on the leadframe, and the package body may be on the leak barrier. Methods of forming modular packages including thermoset package bodies on leadframes are also disclosed. | 2012-01-19 |
20120012880 | LIGHT EMITTING DEVICE MODULE AND LIGHTING SYSTEM INCLUDING THE SAME - Disclosed herein is a light emitting device module comprising: a heat transfer member having a cavity; first conductive layer and second conductive layer contacting the heat transfer member via an insulating layer, the first conductive layer and the second conductive layer being electrically isolated from each other in accordance with exposure of the insulating layer or exposure of the heat transfer member; and at least one light emitting diode electrically connected to the first conductive layer and second conductive layer, the at least one light emitting device is thermally contacted to an exposed portion of the heat transfer member, wherein the heat transfer member has an exposed portion disposed within the cavity between the first conductive layer and the second conductive layer. | 2012-01-19 |
20120012881 | LIGHT EMITTING DEVICE MODULE AND LIGHTING SYSTEM INCLUDING THE SAME - Disclosed herein is a semiconductor light emitting device module comprising: a substrate; at least one support disposed on a surface of the substrate; a heat transfer member disposed on the substrate and the support, the heating transfer member having a cavity formed in at least a portion of the heat transfer member; first conductive layer and second conductive layer contacting the heat transfer member via an insulating layer, the first conductive layer and the second conductive layer being electrically isolated from each other in accordance with exposure of the insulating layer or exposure of the heat transfer member; and at least one semiconductor light emitting device electrically connected to the first conductive layer and the second conductive layer, the at least one semiconductor light emitting device is thermally contacted an exposed portion of the heat transfer member. | 2012-01-19 |
20120012882 | LIGHT EMITTING DIODE DEVICES AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) device includes a stacked epitaxial structure, a heat-conductive plate and a seed layer. The stacked epitaxial structure sequentially includes a first semiconductor layer (N—GaN), a light emitting layer, and a second semiconductor layer (P—GaN). The heat-conductive plate is disposed on the first semiconductor layer, and the seed layer is disposed between the first semiconductor layer and the heat-conductive plate. Also, the present invention discloses a manufacturing method thereof including the steps of: forming at least one temporary substrate, which is made by a curable polymer material, on an LED device, and forming at least a heat-conductive plate on the LED device. | 2012-01-19 |
20120012883 | METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE AND FILM FORMATION SUBSTRATE - In a method for manufacturing a light-emitting device according to an embodiment of the present invention, one surface of a first substrate including a reflective layer including an opening, a light absorption layer formed over the reflective layer to cover the opening in the reflective layer, a protective layer formed over the light absorption layer and including a groove at a position overlapped with the opening in the reflective layer, and a material layer formed over the protective layer and a deposition surface of a second substrate are disposed to face each other and light irradiation is performed from the other surface side of the first substrate, so that an EL layer is formed in a region on the deposition surface of the second substrate, which is overlapped with the opening in the reflective layer. | 2012-01-19 |
20120012884 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device according to an embodiment includes: a substrate; an n-type semiconductor layer formed on the substrate; an active layer formed on a first region of the n-type semiconductor layer, and emitting light; a p-type semiconductor layer formed on the active layer; a p-electrode formed on the p-type semiconductor layer, and including a first conductive oxide layer having an oxygen content lower than | 2012-01-19 |
20120012885 | LEAD FRAME - A lead frame enabling simultaneous burn-in testing of plural LEDs while the LEDs are mounted thereon is disclosed. The lead frame according to embodiments of this disclosure may enable burn-in testing of LEDs before packaging. | 2012-01-19 |
20120012886 | LIGHT EMITTING DIODE, FRAME SHAPING METHOD THEREOF AND IMPROVED FRAME STRUCTURE - A single material tape is shaped into first, second and third frames isolated from and disposed opposite each other, and a press forming process is performed to thin bottoms of first and second wire-bonding sectors extending from the first and second frames. The thickness of each of the first and second wire-bonding sectors is smaller than that of the third frame, so that the thicker third frame can be exposed out of a glue body to achieve the better dissipation effect, and at least one side surface between the two frames isolated from and disposed opposite each other is formed with a slot portion. When the frame is applied to the light emitting diode and fixed to the glue body, the slot portion can increase the bonding property between the frame and the glue body, and the structural strength therebetween can be increased. | 2012-01-19 |
20120012887 | Light-Emitting Device - It is an object of the present invention is to provide a light-emitting device in which high luminance can be obtained with low power consumption by improving the extraction efficiency. A light-emitting device of the invention comprises an insulating film, a plurality of first electrodes being in contact with the insulating film and formed on the insulating film to be in parallel, an electroluminescent layer formed over the plurality of first electrodes, and a plurality of second electrodes intersecting with the plurality of first electrodes and formed over the electroluminescent layer in parallel, wherein the insulating film contains nitrogen and silicon and the first electrodes contain a conductive transparent oxide material and silicon oxide. | 2012-01-19 |
20120012888 | LIGHT EMITTING DEVICE - A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving. | 2012-01-19 |
20120012889 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR PRODUCING SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element ( | 2012-01-19 |
20120012890 | Organic light emitting diode (OLED) display - An organic light emitting diode (OLED) display device that includes: a first substrate having a first area and a second area adjacent to the first area; an organic light emitting diode (OLED) disposed on the first area of the first substrate; a second substrate facing the first substrate such that the OLED is interposed between the first substrate and the second substrate so as to expose the second area of the first substrate; and a sealant disposed between the first substrate and the second substrate to attach and seal the first substrate to the second substrate, wherein the sealant surrounds the OLED by a predetermined distance and having a first width of one portion closer to the second area that is larger than a second width of an other portion which is farther from the second area. | 2012-01-19 |
20120012891 | VOLTAGE-CONTROLLED BIDIRECTIONAL SWITCH - A voltage-controlled vertical bi-directional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well in which is formed a MOS transistor, the first P-type well and the gate of the MOS transistor being connected to a control terminal, said N-type region being connected to a main terminal of the MOS transistor, and the second main terminal of the MOS transistor being connected to the rear surface voltage of the switch. | 2012-01-19 |
20120012892 | HIGH DENSITY THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD - Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device. | 2012-01-19 |
20120012893 | SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor transistor without variation in threshold voltage of an FET and a method of manufacturing the semiconductor transistor, the semiconductor transistor includes: a substrate; a first compound semiconductor layer formed above the substrate; a second compound semiconductor layer formed on the first compound semiconductor layer and having a bandgap larger than a bandgap of the first compound semiconductor layer; an oxygen-doped region formed by doping at least part of the second compound semiconductor layer with oxygen; a third compound semiconductor layer formed on the second compound semiconductor layer; a source electrode electrically connected to the first compound semiconductor layer; a drain electrode electrically connected to the first compound semiconductor layer; and a gate electrode formed on and in contact with the oxygen-doped region. | 2012-01-19 |
20120012894 | PERFORMANCE OF NITRIDE SEMICONDUCTOR DEVICES - A method of forming a transistor over a nitride semiconductor layer includes surface-treating a first region of a nitride semiconductor layer and forming a gate over the first region. Surface-treating the first region can cause the transistor to have a higher intrinsic small signal transconductance than a similar transistor formed without the surface treatment. A portion of the bottom of the gate can be selectively etched. A resulting transistor can include a nitride semiconductor layer having a surface-treated region and a gate formed over or adjacent to the surface-treated region. | 2012-01-19 |
20120012895 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor. | 2012-01-19 |
20120012896 | Integrated Circuit Cell Architecture Configurable for Memory or Logic Elements - An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other. | 2012-01-19 |
20120012897 | Vertically Fabricated BEOL Non-Volatile Two-Terminal Cross-Trench Memory Array with Two-Terminal Memory Elements and Method of Fabricating the Same - A non-Flash non-volatile cross-trench memory array formed using an array of trenches formed back-end-of-the-line (BEOL) over a front-end-of-the-line (FEOL) substrate includes two-terminal memory elements operative to store at least one bit of data that are formed at a cross-point of a first trench and a second trench. The first and second trenches are arranged orthogonally to each other. At least one layer of memory comprises a plurality of the first and second trenches to form a plurality of memory elements. The non-volatile memory can be used to replace or emulate other memory types including but not limited to embedded memory, DRAM, SRAM, ROM, and FLASH. The memory is randomly addressable down to the bit level and erase or block erase operation prior to a write operation are not required. | 2012-01-19 |
20120012898 | SOLID STATE IMAGING DEVICE - A solid state imaging device includes: a semiconductor substrate having photoelectric conversion regions arranged in matrix, charge transfer regions, and element-separating regions; an insulating film on the semiconductor substrate; transfer electrodes provided in one-to-one with the photoelectric conversion regions and disposed on the insulating film at locations corresponding to the charge transfer regions; and wiring portions each connecting transfer electrodes adjacent in a row direction. The charge transfer regions are doped with impurities so that, in any charge transfer region, a potential of each portion corresponding to an upstream edge of a transfer electrode in the charge transfer direction is lower than the potential of the remaining portions. Each wiring portion connects into a respective transfer electrode at a location offset downstream from the upstream edge of the transfer electrode in the charge transfer direction. The location of each element-separating region corresponds to a respective wiring portion. | 2012-01-19 |
20120012899 | Distance measuring sensor including double transfer gate and three dimensional color image sensor including the distance measuring sensor - Provided are a distance measuring sensor including a double transfer gate, and a three dimensional color image sensor including the distance measuring sensor. The distance measuring sensor may include first and second charge storage regions which are spaced apart from each other on a substrate doped with a first impurity, the first and second charge storage regions being doped with a second impurity; a photoelectric conversion region between the first and second charge storage regions on the substrate, being doped with the second impurity, and generating photo-charges by receiving light; and first and second transfer gates which are formed between the photoelectric conversion region and the first and second charge storage regions above the substrate to selectively transfer the photo-charges in the photoelectric conversion region to the first and second charge storage regions. | 2012-01-19 |
20120012900 | SEMICONDUCTOR BIO-SENSORS AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening. | 2012-01-19 |
20120012901 | Selective Functionalization by Joule Effect Thermal Activation - The invention relates to a method for functionalizing a conductive or semiconductor material (M) by covalent grafting of receptor molecules (R) to its surface, said method comprising the following steps: (i) applying, across the terminals of a source electrode and a drain electrode located on either side of the material (M), sufficient potential difference to thermally activate the material (M) with respect to the grafting reaction of the molecules (R); and (ii) placing the material (M) thus activated in contact with a liquid or gaseous medium containing receptor molecules (R), thereby obtaining a material (M) functionalized by covalently grafted receptor molecules (R). | 2012-01-19 |
20120012902 | Semiconductor Device Including a Channel Stop Zone - A semiconductor device as described herein includes a body region of a first conductivity type adjoining a channel region of a second conductivity at a first side of the channel region. A gate control region of the first conductivity type adjoins the channel region at a second side of the channel region opposed to the first side, the channel region being configured to be controlled in its conductivity by voltage application between the gate control region and the body region. A source zone of the second conductivity type is arranged within the body region and a channel stop zone of the second conductivity type is arranged at the first side, the channel stop zone being arranged at least partly within at least one of the body region and the channel region. The channel stop zone includes a maximum concentration of dopants lower than a maximum concentration of dopants of the source zone. | 2012-01-19 |
20120012903 | METHOD FOR MAKING A DISILICIDE - Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height. | 2012-01-19 |
20120012904 | METAL-OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates. | 2012-01-19 |
20120012905 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is disclosed which includes a silicide substrate, a nitride layer, two STIs, and a strain nitride. The silicide substrate has two doping areas. The nitride layer is deposited on the silicide substrate. The silicide substrate and the nitride layer have a recess running through. The two doping areas are at two sides of the recess. The end of the recess has an etching space bigger than the recess. The top of the silicide substrate has a fin-shaped structure. The two STIs are at the two opposite sides of the silicide substrate (recess). The strain nitride is spacer-formed in the recess and attached to the side wall of the silicide substrate, nitride layer, two STIs. The two doping areas cover the strain nitride. As a result, the efficiency of semiconductor is improved, and the drive current is increased. | 2012-01-19 |
20120012906 | Si-Ge-Si SEMICONDUCTOR STRUCTURE HAVING DOUBLE GRADED JUNCTIONS AND METHOD FOR FORMING THE SAME - A Si—Ge—Si semiconductor structure having double compositionally-graded hetero-structures is provided, comprising: a substrate; a buffer layer or an insulation layer formed on the substrate; a strained SiGe layer formed on the buffer layer or the insulation layer, wherein a Ge content in a central portion of the strained SiGe layer is higher than the Ge content in an upper surface or in a lower surface of the strained SiGe layer, and the Ge content presents a compositionally-graded distribution from the central portion to the upper surface and to the lower surface respectively. According to the present disclosure, a compositionally-graded hetero-structure replaces an abrupt hetero-structure so as to form a triangular hole carrier potential well, so that most of hole carriers may be distributed in the strained SiGe layer with high Ge content and a reduction of the carrier mobility caused by interface scattering may be avoided, thus further improving a performance of a device. | 2012-01-19 |
20120012907 | Memory layout structure and memory structure - A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines. | 2012-01-19 |
20120012908 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a source electrode, a drain electrode, a gate electrode and a gate power feeding line. The gate electrode is disposed between said source electrode and said drain electrode. The gate power feeding line is connected to both ends of said gate electrode. | 2012-01-19 |
20120012909 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER - A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection. | 2012-01-19 |
20120012910 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To prevent two contacts that have different heights, share at least one interlayer insulating film and are disposed close to each other from being short-circuited to each other due to misalignment thereof, a semiconductor device according to the invention has a recess in an interlayer insulating film in which a first contact having a lower height, the recess being formed by the upper surface of the first contact, and a silicon nitride sidewall is formed in the recess to extend from the upper surface of the first contact and along the side surface of the recess. | 2012-01-19 |
20120012911 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises: a semiconductor substrate including a cell region and a peripheral region; an insulating film formed on the top portion of the semiconductor substrate of the cell region; a bit line contact hole including the etched insulating film to expose the semiconductor substrate; a bit line contact plug buried in the bit line contact plug; and a bit line formed on the top portion of the bit line contact plug to have the same width as that of the bit line contact plug. The thickness of the insulating film around a cell bit line is minimized so as to vertically form a profile of the cell bit line, thereby improving an overlay margin of a storage node contact and an active region. | 2012-01-19 |
20120012912 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current. | 2012-01-19 |
20120012913 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a vertical transistor and a method for manufacturing the same may reduce a cell area in comparison with a conventional layout of 8F2 and 6F2. Also, the method does not require forming a bit line contact, a storage node contact or a landing plug, thereby decreasing the process steps. The semiconductor device including a vertical transistor comprises: an active region formed in a semiconductor substrate; a bit line disposed in the lower portion of the active region; a word line buried in the active region; and a capacitor disposed over the upper portion of the active region and the word line. | 2012-01-19 |
20120012914 | Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor constructions comprising compositions containing iridium and tantalum. The compositions containing iridium and tantalum can be utilized as barrier materials, and in some aspects can be utilized as barriers to copper diffusion. | 2012-01-19 |
20120012915 | SEMICONDUCTOR MEMORY HAVING ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. | 2012-01-19 |
20120012916 | Stacked gate nonvolatile semiconductor memory and method for manufacturing the same - A stacked gate nonvolatile semiconductor memory includes at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate. The memory cell transistor includes a floating gate made of a semiconductor material below an interlayer insulating layer and a control gate made of a silicide above the interlayer insulating layer. The selective gate transistor includes a semiconductor layer made of the semiconductor material, a silicide layer made of the silicide and a conductive layer made of a conductive material not subject to silicide process which is formed through the interlayer insulating film so as to electrically connect the semiconductor layer and the silicide layer. | 2012-01-19 |
20120012917 | Semiconductor device and method for manufacturing the same - It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto. | 2012-01-19 |
20120012918 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and the method for manufacturing the same, wherein the structure comprising a semiconductor substrate: a flash memory device formed on the semiconductor substrate; wherein the flash memory device comprising: a channel region formed on the semiconductor substrate; a gate stack structure formed on the channel region; wherein the gate stack structure comprises: a first gate dielectric layer formed on the channel region; a first conductive layer formed on the first gate dielectric layer; a second gate dielectric layer formed on the first conductive layer; a second conductive layer formed on the second gate dielectric layer; a heavily doped first-conduction-type region and a heavily doped second-conduction-type region at both sides of the channel region respectively, wherein the first conduction type is opposite to the second conduction type in the type of conduction. | 2012-01-19 |
20120012919 | NONVOLATILE FLASH MEMORY STRUCTURES INCLUDING FULLERENE MOLECULES AND METHODS FOR MANUFACTURING THE SAME - Embodiments of tunneling barriers and methods for same can embed molecules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding C | 2012-01-19 |
20120012920 | VERTICAL NON-VOLATILE MEMORY DEVICE - A vertical non-volatile memory device includes a semiconductor pattern disposed on a substrate; and a plurality of transistors of first through n-th layers that are stacked on a side of the semiconductor pattern at predetermined distances from each other, wherein the transistors are spaced apart and insulated from one another at the predetermined distances via air gap, where n is a natural number equal to or greater than 2. | 2012-01-19 |
20120012921 | MEMORY ARRAYS HAVING SUBSTANTIALLY VERTICAL, ADJACENT SEMICONDUCTOR STRUCTURES AND THE FORMATION THEREOF - Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of the respective strings in series. For some embodiments, two dielectric pillars may be formed from a dielectric formed in a single opening, where each of the dielectric pillars has a pair of memory-cell strings adjacent thereto and where at least one memory cell of one of the strings on one of the pillars and at least one memory cell of one of the strings on the other pillar are commonly coupled to an access line. | 2012-01-19 |
20120012922 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. Upon forming source or drain at a lower part of the pillar pattern, a silicon oxide layer (barrier layer) is formed inside the pillar pattern to prevent the pillar pattern from being electrically floated. Furthermore, impurities are diffused to a vertical direction (longitudinal direction) of the pillar pattern to overlay junction between the semiconductor substrate and source or drain formed at a lower part of the pillar pattern that leads to improvement of a current characteristic. | 2012-01-19 |
20120012923 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The present invention relates to a semiconductor device and a method for forming the same. The semiconductor device includes: a vertical pillar protruded from a semiconductor substrate; a first junction region provided at an upper part of the vertical pillar; a second junction region provided in a lower part of the vertical pillar to be separated apart from the first junction region; and a gate oxidation layer in which a thickness thereof in a surface of the vertical pillar in which the first junction region is provided being thicker than that in a surface of the vertical pillar in which the first junction region is not provided. The present invention forms a gate oxidation layer using the oxidation rate difference without a mask process to minimize GIDL that leads to improvement in the characteristic of a semiconductor device. | 2012-01-19 |
20120012924 | Vertical Transistor Component - A vertical transistor component is produced by providing a semiconductor body with a first surface and a second surface, producing at least one gate contact electrode in a trench, the trench extending from the first surface through the semiconductor body to the second surface, and producing at least one gate electrode connected to the at least one gate contact electrode in the region of the first surface. | 2012-01-19 |
20120012925 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The method etches a gate metal material of a sidewall of the active region connected to the storage node contact deeper than a gate metal material of a sidewall of the active region connected to the bit line contact in a buried gate structure to prevent GILD and to reduce resistance of a buried gate, thereby improving refresh characteristics of the semiconductor device. | 2012-01-19 |
20120012926 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor memory device includes defining an active region having a shape protruding upward by forming a trench in a semiconductor substrate; forming an open region obtained by selectively exposing a lower side portion of the active region while forming a sidewall layer along the shape of the active region; covering the open region with a silicon layer; forming an impurity region in the lower side portion of the active region; forming a barrier metal layer on the silicon layer and the active region; forming a bit line metal layer buried in the entire active region; and forming a buried bit line having the barrier metal layer, the bit line metal layer and a silicide metal layer formed between the silicon layer and the barrier metal layer by etching the bit line metal layer up to a portion at which the impurity region is formed. | 2012-01-19 |
20120012927 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a cell gate trench with a bottom face and first/second side faces; a field-shield gate trench narrower than the cell gate trench; a first upper diffusion layer between the cell gate trench and the field-shield gate trench; a second upper diffusion layer on the opposite side of the cell gate trench from the first upper diffusion layer; a third upper diffusion layer on the opposite side of the field-shield gate trench from the first upper diffusion layer; a lower diffusion layer on the bottom face of the cell gate trench; first and second storage elements electrically connected to the first and second upper diffusion layers, respectively; a bit line electrically connected to the lower diffusion layer; a word line covering first and second side faces via a gate insulating film; and a field-shield gate electrode in the field-shield gate trench via a gate insulating film. | 2012-01-19 |
20120012928 | TRANSISTOR INCLUDING BULB-TYPE RECESS CHANNEL AND METHOD FOR FABRICATING THE SAME - A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer. | 2012-01-19 |
20120012929 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, a control electrode, a first main electrode, a second main electrode, and a sixth semiconductor layer of the first conductivity type. The second semiconductor layer and the third semiconductor layer are alternately provided on the first semiconductor layer in a direction substantially parallel to a major surface of the first semiconductor layer. The fourth semiconductor layer is provided on the second semiconductor layer and the third semiconductor layer. The fifth semiconductor layer is selectively provided on a surface of the fourth semiconductor layer. The control electrode is provided in a trench via an insulating film. The trench penetrates through the fourth semiconductor layer from a surface of the fifth semiconductor layer and is in contact with the second semiconductor layer. The first main electrode is connected to the first semiconductor layer. The second main electrode is connected to the fourth semiconductor layer and the fifth semiconductor layer. The sixth semiconductor layer is provided between the fourth semiconductor layer and the second semiconductor layer. An impurity concentration of the sixth semiconductor layer is higher than an impurity concentration of the second semiconductor layer. | 2012-01-19 |
20120012930 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, and first and second transistors. The substrate has a first conductivity type. The first and second transistors are provided on the substrate. The first and second transistors each include a gate electrode provided on the substrate, a gate insulating film provided between the substrate and the gate electrode, a source and a drain region of a second conductivity type, and a high-concentration channel region of the first conductivity type. The source and drain regions are provided in regions of an upper portion of the substrate. A region directly under the gate electrode is interposed between the regions. The high-concentration channel region is formed on a side of the source region of the region of the upper portion directly under the gate electrode. The high-concentration channel region has an effective impurity concentration higher than that of the upper portion. | 2012-01-19 |