| 03rd week of 2013 patent applcation highlights part 23 |
| Patent application number | Title | Published |
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| 20130016505 | LED Module for SpotlightsAANM Gianordoli; StefanAACI FurstenfeldAACO ATAAGP Gianordoli; Stefan Furstenfeld AT - Set of a plurality of LED emitters, wherein the LED emitters in the set generate a different luminous efficacy, and have a standard housing. | 2013-01-17 |
| 20130016506 | AVIAN HOUSE LIGHTING APPARATUS AND METHOD - In an embodiment, the invention is directed to a lighting system for an avian house comprising a feeding or watering system and a source of LED lighting that emits light having a color selected from the group consisting of white, blue, or green, wherein the LED lighting is attached to the feeding or watering system at a height which corresponds to eye level to of the avian species to be fed or watered. The invention is also directed to a method for attract an avian species to a feeding or watering system using an LED lighting system. | 2013-01-17 |
| 20130016507 | D Shaped Induction Lamp RetrofitAANM Yeh; JohnAACI OxnardAAST CAAACO USAAGP Yeh; John Oxnard CA US - A retrofit for a conventional HID light fixture, used for either low bay or high bay applications. The retrofit replaces the conventional HID light fixture with an induction lamp system. The HID bulb within the dome is replaced with two D-shaped induction lamps. The HID ballast is replaced with two ballasts for each of the D-shaped induction lamp, and is preferably kept in the original ballast housing. It is possible to independently turn on and off as well as dim each of the two D-shaped induction lamps independently. | 2013-01-17 |
| 20130016508 | VARIABLE THICKNESS GLOBEAANM PROGL; CURTAACI RaleighAAST NCAACO USAAGP PROGL; CURT Raleigh NC USAANM DIXON; MARKAACI MorrisvilleAAST NCAACO USAAGP DIXON; MARK Morrisville NC US - A variable thickness globe for a lighting device comprises a wall including a curved outer surface and an inner surface. A thickness of the wall between the curved outer surface and the inner surface varies over a predetermined extent of the wall. | 2013-01-17 |
| 20130016509 | LED LAMPAANM Van de Ven; Antony PaulAACI Hong KongAACO CNAAGP Van de Ven; Antony Paul Hong Kong CN - A lamp comprises an LED assembly comprising at least a first LED operable to emit light at least of a first color, and at least a second LED operable to emit light at least of a second color. An enclosure is configured so that the light emitted from the first LED is mixed with the light emitted from the second LED in the enclosure. The enclosure has an internal reflector wall. The light is emitted from the lamp through a diffuser lens. A trim piece may be secured to the lamp where the trim piece may be formed at least partially of a thermally conductive material. A method of making an LED lamp comprises providing at least a first LED operable to emit light of a first color and at least a second LED operable to emit light of a second color is also provided. | 2013-01-17 |
| 20130016510 | MODULAR LED ILLUMINATION APPARATUS - An illumination module that can be retrofitted to a common cobra head and shoebox style street and parking lot pole mounted light housings. This module can reduce the energy requirements by as much as 85%. The module also eliminates the typical required heat sinks. A self contained insect repulsion module that is “insect-tuned” is provided. This repulsion module is set at a frequency that discourages any infestation. A back-up photocell module turns the light “OFF” when the ambient light is above a certain threshold if the primary photocell fails. A lens housing structure substantially reduces extraneous upward and side illumination. The module can be retrofitted using only two simple steps, taking only about ten minutes using only common hand tools. | 2013-01-17 |
| 20130016511 | COOLING FOR LED ILLUMINATION DEVICEAANM Mansfield; Matthew ArthurAACI New South WalesAACO AUAAGP Mansfield; Matthew Arthur New South Wales AUAANM Mansfield; James RichardAACI New South WalesAACO AUAAGP Mansfield; James Richard New South Wales AU - An LED illumination device comprising a lens assembly, a circuit board having at least one LED and a housing to retain said circuit board and said lens assembly, and wherein said circuit board comprises a plurality of pores adjacent said at least one LED to facilitate airflow over a large surface area of said circuit board in the vicinity of said at least one LED. | 2013-01-17 |
| 20130016512 | SEMICONDUCTOR LAMPAANM Breidenassel; NicoleAACI Bad AbbachAACO DEAAGP Breidenassel; Nicole Bad Abbach DEAANM Hoetzl; GuenterAACI RegensburgAACO DEAAGP Hoetzl; Guenter Regensburg DE - In various embodiments, a semiconductor lamp may include at least one semiconductor light source; a driver for operating the at least one semiconductor light source and at least one heat sink for cooling the at least one semiconductor light source and the driver; wherein the at least one heat sink may include a first heat sink, which is thermally connected to the at least one semiconductor light source and a second heat sink, which is thermally connected to the driver; wherein the first heat sink and the second heat sink are thermally insulated from one another. | 2013-01-17 |
| 20130016513 | T-BAR LAMPAANM Sung; Yung-ChengAACI Hsinchu CityAACO TWAAGP Sung; Yung-Cheng Hsinchu City TWAANM Wu; Chung-PanAACI HsinchuAACO TWAAGP Wu; Chung-Pan Hsinchu TW - A T-bar lamp including a T-bar lamp housing and at least a light engine module is provided. The T-bar lamp housing has an opening. The light engine module is fixed in the T-BAR lamp housing, and the light engine module at least includes a chip on board (COB) type LED light source. | 2013-01-17 |
| 20130016514 | DAZZLERSAANM Stacey; Craig DanielAACI WhitchurchAACO GBAAGP Stacey; Craig Daniel Whitchurch GBAANM Charlton; David WesleyAACI ReadingAACO GBAAGP Charlton; David Wesley Reading GB - A dazzler arrangement is disclosed in which the strength of the dazzle beam is modulated in accordance with the range of a target to be dazzled. A stray detection beam is transmitted alongside the dazzle beam to allow detection of a secondary object approaching or at the periphery of the dazzle beam, whereupon the dazzle beam is attenuated or inhibited. | 2013-01-17 |
| 20130016515 | APERTURE ADJUSTING METHOD AND DEVICEAANM CHANG; Jong-hyeonAACI Suwon-siAACO KRAAGP CHANG; Jong-hyeon Suwon-si KR - An aperture adjusting device for adjusting an aperture through which light is transmitted. The aperture adjusting device includes: a chamber; a first fluid and a second fluid disposed within the chamber. The first fluid and second fluid are not mixed with each other. The first fluid transmits light and the second fluid blocks or absorbs light. A first electrode unit is disposed on an inner surface of the chamber, and includes one or more electrodes to which a voltage may be applied to form an electric field in the chamber. An aperture within the chamber through which light is transmitted is adjustable by adjusting an interfacial location between the first fluid and the second fluid by modifying the electric field. | 2013-01-17 |
| 20130016516 | LIGHTING DEVICES AND METHODS OF INSTALLING LIGHT ENGINE HOUSINGS AND/OR TRIM ELEMENTS IN LIGHTING DEVICE HOUSINGS - A lighting device, comprising a housing and at least one mounting clip. The housing comprises an electrical connection region engageable in an electrical receptacle. The mounting clip is pivotable from a first position, where an end region of the mounting clip does not extend beyond a periphery of the housing, to a second position, where the end region extends beyond the housing periphery. Also, a lighting device, comprising a housing, a trim element and at least one mounting clip. The mounting clip is pivotable, such that if the mounting clip is in a second position and then the trim element is rotated, the mounting clip will pivot to a third position, where the mounting clip engages the housing such that the trim element is biased toward a ceiling or other structure in which the lighting device is mounted. Also, methods of installing housings and/or trim elements. | 2013-01-17 |
| 20130016517 | Aircraft Washlight System - Aircraft washlight systems having an asymmetric lens are disclosed. An example vehicle cabin illumination system includes a light source located one side of a surface of a vehicle cabin, and an asymmetric lens through which the light passes to illuminate the surface with a substantially uniform light distribution. | 2013-01-17 |
| 20130016518 | DEBRIS PROTECTOR FOR VEHICLE LAMP ASSEMBLYAANM Voigt; Derik ThomasAACI DublinAAST OHAACO USAAGP Voigt; Derik Thomas Dublin OH USAANM Wright; AaronAACI OstranderAAST OHAACO USAAGP Wright; Aaron Ostrander OH USAANM Massaro; Nick A.AACI DublinAAST OHAACO USAAGP Massaro; Nick A. Dublin OH USAANM Gress; Adam PatrickAACI West MansfieldAAST OHAACO USAAGP Gress; Adam Patrick West Mansfield OH USAANM Weirup; JamisonAACI MarysvilleAAST OHAACO USAAGP Weirup; Jamison Marysville OH USAANM Fisher; Nathan M.AACI DublinAAST OHAACO USAAGP Fisher; Nathan M. Dublin OH USAANM Glazier; Joshua T.AACI HilliardAAST OHAACO USAAGP Glazier; Joshua T. Hilliard OH US - A debris protector for use with a vehicle lamp assembly installed to an opening in a vehicle body panel or garnish to prevent the migration of accumulated road debris through a gap between the lamp assembly and the body panel opening. Such a debris protector is generally in the form of a cover element that is installable along an upper, hidden portion of a vehicle lamp assembly and an inner surface of a corresponding vehicle body panel or garnish to prevent road debris from accumulating on the lamp assembly near the body panel opening. Such a debris protector may also include a seal that is located between the cover element and the rear surface of a body panel or garnish to assist with the debris blocking function of the cover element. | 2013-01-17 |
| 20130016519 | LIGHT SOURCE MODULEAANM KUO; Heng-ShengAACI New Taipei CityAACO TWAAGP KUO; Heng-Sheng New Taipei City TW - A light source module includes a casing, a light-guiding rod, a light-emitting assembly and a heat-dissipating reflective shroud. The casing has a chamber and a transparent opening in communication with the chamber. The light-guiding rod has a light-exiting surface and a light-transmitting surface opposite to the light-exiting surface. The light-guiding rod is disposed in the chamber with the light-exiting surface facing the transparent opening. The light-emitting assembly is provided on one side of the light-guiding rod to emit light toward the interior of the light-guiding rod. The heat-dissipating reflective shroud is assembled with the casing to cover the light-transmitting surface of the light-guiding rod. The interior of the heat-dissipating reflective shroud has a reflective surface for reflecting the light passing through the light-transmitting surface back toward the light-exiting surface to exit the transparent opening. The heat-dissipating reflective shroud has double effects of heat dissipation and light reflection. | 2013-01-17 |
| 20130016520 | COMPACT LIGHT HOMOGENIZER - Provided are assemblies and processes for achieving desirable homogenization and mixing of one or more light sources. The assemblies include the use of diffusers and light pipes in a particular configuration that allows very good homogenization performance while reducing the requisite length of light pipe. In particular, a length of a light-pipe homogenizer can be substantially reduced by diffusing the light after it has been partially pre-mixed by a light pipe. Additional mixing can take place after diffusion. For example, a diffuser can be positioned within a light pipe or sandwiched between two light pipes. In some embodiments, the diffuser is placed at a point along a light pipe where the light from each source or each portion of a single source substantially covers the diffuser approximately equally. Consequently, a rate of homogenization can be increased, thereby reducing the required length of the complete homogenization system. | 2013-01-17 |
| 20130016521 | BACKLIGHT UNIT AND DISPLAY APPARATUS USING THE SAMEAANM Jung; Sang HyeokAACI SeoulAACO KRAAGP Jung; Sang Hyeok Seoul KRAANM Kim; Moon JeongAACI SeoulAACO KRAAGP Kim; Moon Jeong Seoul KRAANM Kim; Jeong HwanAACI SeoulAACO KRAAGP Kim; Jeong Hwan Seoul KR - Disclosed are a backlight unit and a display apparatus using the same. The backlight unit includes a light guide plate including first and second grooves, and light source modules disposed within the second grooves. The first grooves are disposed on the upper surface of the light guide plate, and the second grooves are disposed on the lower surface of the light guide plate, and the first grooves are disposed between light sources of the light source module. | 2013-01-17 |
| 20130016522 | DISPLAY APPARATUSAANM BAEK; Seung HwanAACI SeoulAACO KRAAGP BAEK; Seung Hwan Seoul KRAANM SHIN; Myeong-JuAACI SeoulAACO KRAAGP SHIN; Myeong-Ju Seoul KRAANM LEE; YeongbaeAACI Bucheon-siAACO KRAAGP LEE; Yeongbae Bucheon-si KR - A display apparatus includes a backlight unit which generates first light including first blue light, first green light and first red light and a display panel which receives the first light to display an image, where the backlight unit includes: a light emitting diode which generates an ultraviolet ray; a fluorescent substance layer disposed on the light emitting diode, where the fluorescent substance layer includes: a blue fluorescent substance layer which receives the ultraviolet ray and emits blue light; a green fluorescent substance layer which receives the ultraviolet ray and emits green light; and a red fluorescent substance layer which receives the ultraviolet ray and emits red light; and a first band-pass filter which receives the blue light, the green light and the red light and outputs the first blue light, the first green light and the first red light. | 2013-01-17 |
| 20130016523 | DISPLAY DEVICE, ELECTRONIC APPARATUS AND LIGHTING DEVICEAANM URANO; NobutakaAACI Chino-shiAACO JPAAGP URANO; Nobutaka Chino-shi JPAANM MOMOSE; YoichiAACI Matsumoto-shiAACO JPAAGP MOMOSE; Yoichi Matsumoto-shi JP - In a lighting device of a display device, a plurality of light emitting elements are mounted on a surface of a light source substrate, and the light source substrate is supported by a light source support member by means of a positioning (fixing) structure such as a metal screw. The plurality of light emitting elements are divided into a plurality of blocks, and the emission light amount can be controlled with respect to each of the blocks. Although the head of the screw is exposed on the surface of the light source substrate, the screw is located between adjacent ones of the blocks. Therefore, even though the illuminating light intensity becomes partially discontinuous owing to the presence of the screw, degradation of display quality originating from such discontinuity can be suppressed. | 2013-01-17 |
| 20130016524 | DISPLAY DEVICE, ELECTRONIC APPARATUS AND ILLUMINATION DEVICEAANM MOMOSE; YoichiAACI Matsumoto-shiAACO JPAAGP MOMOSE; Yoichi Matsumoto-shi JPAANM URANO; NobutakaAACI Chino-shiAACO JPAAGP URANO; Nobutaka Chino-shi JP - An illumination device of a display device is configured such that heat of light-emitting elements is dissipated via a light source substrate, a light source support member made of a metal, and a first frame made of a metal. The illumination device also includes a second frame made of a resin that is disposed such that a closed space is formed along the light source support member between the frame and the light source support member. The second frame has an opening portion that communicates with the closed space, and the first frame and a third frame each has an opening portion at a position that overlaps the opening portion of the second frame, thereby allowing heat of the light-emitting elements to be dissipated through the closed space and an opening which is formed by opening portions. | 2013-01-17 |
| 20130016525 | FLAT ILLUMINATING DISPLAY DEVICE AND LIGHT-EMITTING MEANS THEREFOR - Flat illuminating display device with light emitting means to illuminate a film for display of an image applied to a display area, wherein the light emitting means are embodied as at least one light coupling unit arranged laterally at a translucent film thus forming a light duct, wherein the light such fed into the adjacent edge area into the film is reflected by a reflective layer, which is applied on at least one side, to homogeneously spread within the film, wherein a reflection screen to obtain a light emission is provided opposite of the display area to create said display area. | 2013-01-17 |
| 20130016526 | LIGHTING ASSEMBLY WITH CONTROLLED CONFIGURABLE LIGHT REDIRECTION - A lighting assembly has an edge-lit light guide having a light output surface through which light is extracted by light extracting optical elements. The extracted light has a maximum intensity at low light ray angles relative to the light output surface. A light redirecting member has an arrangement of light redirecting optical elements configured to redirect the extracted light incident thereon to provide a pattern of redirected light. A light focusing member has light focusing optical elements having an angular acceptance range. The redirected light has light ray angles within the angular acceptance range of the light focusing optical elements and is perceived as a pattern of light. The extracted light not redirected by the light redirecting member has light ray angles outside the angular acceptance range of the light focusing optical elements and is not perceived, or is perceived as background light. | 2013-01-17 |
| 20130016527 | LIGHT GUIDE FOR BACKLIGHT - The present invention provides a light guide for an electronically addressable display (such as an LCD) that mixes optical signals from a plurality of emitters, and mixes these signals to produce, for positions on the display, position-unique signals. A stylus or other receiving device may determine its position relative to the electronically addressable display by analyzing the position-unique signals. | 2013-01-17 |
| 20130016528 | ENHANCED COLOR GAMUT LED BACKLIGHTING UNIT - A method for operating a backlighting unit adapted for illuminating a printed graphic with light emitted from an illumination surface of a light guide. The method includes the step of arranging a plurality of LEDs so that light emitted therefrom impinges upon an input surface of the light guide. The method specifically requires that the LEDs emit light that is roughly equivalent to solar illumination of 6500K CCT yet enhanced in the blue and the red portions of the spectrum thereby producing light in the range of 7500K CCT to 9000K CCT. | 2013-01-17 |
| 20130016529 | SURFACE LIGHT SOURCE DEVICE AND ELECTRONIC DEVICE PROVIDED WITH SAMEAANM Nishioka; SumitoAACI Osaka-shiAACO JPAAGP Nishioka; Sumito Osaka-shi JPAANM Takayama; TakeshiAACI Osaka-ShiAACO JPAAGP Takayama; Takeshi Osaka-Shi JPAANM Sakai; KeijiAACI Osaka-ShiAACO JPAAGP Sakai; Keiji Osaka-Shi JPAANM Ikuta; KazuyaAACI Osaka-ShiAACO JPAAGP Ikuta; Kazuya Osaka-Shi JPAANM Ishimura; RyojiAACI Osaka-ShiAACO JPAAGP Ishimura; Ryoji Osaka-Shi JPAANM Ishizaka; TakuyaAACI Osaka-ShiAACO JPAAGP Ishizaka; Takuya Osaka-Shi JP - A light source module ( | 2013-01-17 |
| 20130016530 | CONTROLLERS FOR POWER CONVERTERSAANM LIPCSEI; LaszloAACI CampbellAAST CAAACO USAAGP LIPCSEI; Laszlo Campbell CA USAANM GHERGHESCU; AlinAACI Santa ClaraAAST CAAACO USAAGP GHERGHESCU; Alin Santa Clara CA USAANM POPOVICI; CatalinAACI Santa ClaraAAST CAAACO USAAGP POPOVICI; Catalin Santa Clara CA US - In a controller for a power converter, a control terminal can provide a control signal to control a power converter. A cycle of the control signal includes a first time interval and a second time interval. The control circuitry can increase a primary current flowing through a primary winding of transformer circuitry and a secondary current flowing through a secondary winding of the transformer circuitry in the first time interval, and can terminate the increasing of the primary current in the second time interval. The control circuitry can also control the first time interval to be inversely proportional to an input voltage provided to the primary winding. | 2013-01-17 |
| 20130016531 | POWER SUPPLY DEVICE AND METHOD OF CONTROLLING POWER SUPPLY DEVICEAANM ASO; ShinjiAACI Niiza-shiAACO JPAAGP ASO; Shinji Niiza-shi JP - The present invention includes: a power factor correction circuit configured to correct a power factor; a DC/DC converter configured to convert an output voltage of the power factor correction circuit to a different direct-current voltage; an input voltage detector configured to detect an input voltage inputted into the power factor correction circuit; and a power factor correction circuit output voltage controller configured to generate a voltage instruction for controlling the output voltage of the power factor correction circuit, based on a value of the detected input voltage, an output current value to a load connected to an output of the DC/DC converter or an output power value of the load, as well as a set value of an input voltage short break output hold time, and to output the voltage instruction to the power factor correction circuit. | 2013-01-17 |
| 20130016532 | SWITCH CONTROL FOR A POWER CONVERTERAANM Svensson; AndreasAACI TibroAACO SEAAGP Svensson; Andreas Tibro SE - The present invention relates to a power converter ( | 2013-01-17 |
| 20130016533 | RESONANT CONVERTER CONTROLAANM Halberstadt; HansAACI GroesbeekAACO NLAAGP Halberstadt; Hans Groesbeek NL - Consistent with an example embodiment there is a method of controlling a resonant power converter; the power converter includes first and second series connected switches connected between a supply voltage line and a ground line and a resonance circuit, having a capacitor and an inductor. The resonance circuit is connected to a node connecting the first and second switches. The method comprises repeated sequential steps of closing the first switch to start a conduction interval; sampling a voltage across the capacitor to obtain a sampled voltage level; and opening the first switch to end the conduction interval when a voltage across the capacitor crosses a voltage level determined by addition of the sampled voltage level with a predetermined voltage difference; wherein controlling the predetermined voltage difference determines a power output of the resonant power converter. | 2013-01-17 |
| 20130016534 | RESONANT CONVERTERAANM ISHIKURA; KeitaAACI SaitamaAACO JPAAGP ISHIKURA; Keita Saitama JPAANM ASO; ShinjiAACI SaitamaAACO JPAAGP ASO; Shinji Saitama JP - A resonant converter includes: a first switching element and a second switching element, which are connected in series; a series resonant circuit, which includes a primary coil of a transformer having leakage inductance and a current resonant capacitor, and which is connected in parallel to one of the first switching element and the second switching element; a rectifying-and-smoothing circuit, which is connected to a secondary coil of the transformer, wherein an output voltage is to be supplied to a load; and a clamp circuit, which clamps a voltage between both ends of the current resonant capacitor to a predetermined voltage value, wherein, when an output current supplied from the rectifying-and-smoothing circuit to the load is higher than the predetermined current value, an output characteristic is set so that, as the output current is increased, the output voltage is decreased. | 2013-01-17 |
| 20130016535 | Controller for a Power Converter and Method of Operating the Same - A control system for a power converter with reduced power dissipation at light loads and method of operating the same. In one embodiment, the control system includes a first controller configured to control a duty cycle of a power switch to regulate an output characteristic of the power converter. The control system also includes a second controller configured to provide a signal in response to a dynamic change of the output characteristic to the first controller to initiate the duty cycle for the power switch. | 2013-01-17 |
| 20130016536 | Device and Method for Global Maximum Power Point Tracking - A device, system, and method for global maximum power point tracking comprises monitoring an output power of a DC power source while executing a maximum power point tracking algorithm and adjusting a maximum power point tracking command signal in response to the output power being less than a reference output power. The command signal is adjusted until the output power exceeds a previous output power by a reference amount. The command signal may be a voltage command signal, a current command signal, an impedance command signal, a duty ratio command signal, or the like. | 2013-01-17 |
| 20130016537 | METHOD FOR CONTROLLING A FREQUENCY CONVERTER AND FREQUENCY CONVERTERAANM DENG; HENGAACI BrandeAACO DKAAGP DENG; HENG Brande DK - A method for controlling a frequency converter is provided. The converter includes a rectifier, an inverter which is connected via a DC link to the rectifier, a rectifier controller and an inverter controller. A minimal rectifier DC link voltage for the rectifier controller is determined, a minimal inverter DC link voltage for the inverter controller is determined, a minimal DC link voltage as the maximum of the minimal rectifier DC link voltage and the minimal inverter DC link voltage is determined, and an optimal DC link voltage reference based on the minimum of the minimal DC link voltage and a maximal allowed DC link voltage is determined. The rectifier controller and/or the inverter controller is/are controlled based upon the optimal DC link voltage reference. | 2013-01-17 |
| 20130016538 | AC/DC CONVERTER DEVICEAANM Fujita; TakayukiAACI ShigaAACO JPAAGP Fujita; Takayuki Shiga JP - A command value is a current command value with a triangular-like waveform having a cycle that is ⅓ of a cycle of a three-phase voltage. A carrier has a triangular-like waveform having a cycle shorter than the cycle of the command value. Comparison result signals are pulse signals indicating a result of the comparison between the carrier and the command value. In a region of a phase of 30 to 90 degrees, a portion of the comparison result signal present in this region is employed as a gate signal. In a region of a phase of 270 to 330 degrees, a portion of the comparison result signal present in this region is employed as the gate signal. | 2013-01-17 |
| 20130016539 | POWER FACTOR CORRECTION CIRCUITAANM NISHIBORI; KoheiAACI Kitasaku-gunAACO JPAAGP NISHIBORI; Kohei Kitasaku-gun JPAANM CHALERMBOON; NadthawutAACI Kitasaku-gunAACO JPAAGP CHALERMBOON; Nadthawut Kitasaku-gun JP - A power factor correction circuit includes: the first series circuit consisting of the first rectifier element and the first switching element; the second series circuit consisting of the second rectifier element and the second switching element; the first/second reactors; and the first/second current detectors. The first/second current detectors have each the first/second transformers, both primary parts of which consist of the first/second reactors. The first and the second switching elements are controllable based on the first output signal according to the reactor current from the secondary side of the first transformer and the second output signal according to the reactor current from the secondary side of the second transformer so as to apply a desired DC voltage to the load circuit. | 2013-01-17 |
| 20130016540 | POWER CONVERTER COMPRISING AN INVERTER MODULE USING NORMALLY ON FIELD-EFFECT TRANSISTORSAANM BARAUNA; Allan PierreAACI VernonAACO FRAAGP BARAUNA; Allan Pierre Vernon FR - The invention relates to a power converter comprising: | 2013-01-17 |
| 20130016541 | AC/DC CONVERTER STATION AND A METHOD OF OPERATING AN AC/DC CONVERTER STATIONAANM Norrga; StaffanAACI StockholmAACO SEAAGP Norrga; Staffan Stockholm SEAANM Jonsson; Tomas UAACI VasterasAACO SEAAGP Jonsson; Tomas U Vasteras SEAANM Shukla; AnshumanAACI VasterasAACO SEAAGP Shukla; Anshuman Vasteras SE - The present invention relates to an AC/DC converter station for interconnection of a DC transmission line and an AC network, the AC/DC converter station including an AC/DC converter and a control system configured to control the AC/DC converter. The AC/DC converter station comprises a capacitor connected in series between the AC/DC converter and the AC network, and a voltage measurement device arranged to measure the voltage across the capacitor. The AC/DC converter further comprises a control system connected to the voltage measurement device and arranged to receive, from the voltage measurement device, a signal indicative of a measured voltage. The control system is arranged to perform the control of the AC/DC converter in dependence of the signal received from the voltage measurement device. The invention further relates to a method of operating an AC/DC converter station. | 2013-01-17 |
| 20130016542 | ELECTRIC POWER CONVERSION DEVICE AND SURGE VOLTAGE SUPPRESSING METHODAANM Nakamura; KazuyaAACI Chiyoda-kuAACO JPAAGP Nakamura; Kazuya Chiyoda-ku JPAANM Terada; KeiAACI Chiyoda-kuAACO JPAAGP Terada; Kei Chiyoda-ku JPAANM Takahashi; KazutakaAACI Chiyoda-kuAACO JPAAGP Takahashi; Kazutaka Chiyoda-ku JPAANM Jimbo; ShigeoAACI Chiyoda-kuAACO JPAAGP Jimbo; Shigeo Chiyoda-ku JP - To provide an electric power conversion device that converts direct current power supplied from a direct-current power supply into alternating current power, the electric power conversion device includes six switching elements constituted by a voltage-driven transistor that uses a wide bandgap semiconductor and a diode, and a drive circuit that controls a voltage for driving the transistor at a time of turning off the switching elements based on a predetermined voltage profile specifying that the transistor is operated in a non-linear region. | 2013-01-17 |
| 20130016543 | DC TO AC CONVERTERAANM KU; Chen-WeiAACI TAOYUAN HSIENAACO TWAAGP KU; Chen-Wei TAOYUAN HSIEN TWAANM LEE; Lei-MingAACI TAOYUAN HSIENAACO TWAAGP LEE; Lei-Ming TAOYUAN HSIEN TW - A DC to AC converter includes a first switch, a second switch, a first half bridge inverter, and a second half bridge inverter. The first switch includes a first terminal and a second terminal. The second switch includes a first terminal and a second terminal. A portion between the first terminal of the first switch and the first terminal of the second switch is operable to receive a direct current power source. The first half bridge inverter includes a first terminal, a second terminal, and an output terminal. The second half bridge inverter includes a first terminal, a second terminal, and an output terminal. A portion between the output terminal of the first half bridge inverter and the output terminal of the second half bridge inverter is operable to output an alternative current. | 2013-01-17 |
| 20130016544 | Method and Device for Controlling a Configurable Power Supply - An apparatus, device, and system for generating an amount of output power in response to a direct current (DC) power input includes a configurable power supply, which may be electrically coupled to the DC power input. The configurable power supply is selectively configurable between multiple circuit topologies to generate various DC power outputs and/or and AC power output. The system may also include one or more DC power electronic accessories, such as DC-to-DC power converters, and/or one or more AC power electronic accessories such as DC-to-AC power converters. The power electronic accessories are couplable to the configurable power supply to receive the corresponding DC or AC power output of the configurable power supply. | 2013-01-17 |
| 20130016545 | AC-TO-DC CONVERSION APPARATUS AND RELATED CONTROL MANNER THEREOFAANM Xu; MingAACI NanjingAACO CNAAGP Xu; Ming Nanjing CNAANM Chen; Qiao-LiangAACI NanjingAACO CNAAGP Chen; Qiao-Liang Nanjing CN - An AC-to-DC conversion apparatus is provided, and which includes a first switch-element, an output capacitor and a bridgeless power-factor-correction (PFC) circuit. The bridgeless PFC circuit is coupled to an AC input, and includes a first inductor, a second inductor and a bridge circuit constructed by second to fifth switch-elements. The first switch-element is connected between bridgeless PFC circuit and the output capacitor. Under such circuit configuration and suitable control manner, the common-mode interference in the provided AC-to-DC conversion apparatus is lowered and thus reducing the power loss. | 2013-01-17 |
| 20130016546 | ELECTRICAL SYSTEM ARCHITECTURE AND ELECTRICAL POWER GENERATION SYSTEMAANM MOUNTAIN; Stephen J.AACI DerbyAACO GBAAGP MOUNTAIN; Stephen J. Derby GB - An electrical system architecture, for example for an aircraft, including a generator driven by an engine of the aircraft to generate electrical energy, which is arranged for extracting the said electrical energy as an AC signal for supply to a system bus. The electrical system architecture also includes an active rectifier coupled to the system bus, that is adapted to rectify the AC signal to a DC signal for supply to a load in the system, and for controlling extraction of the said electrical energy by the generator. An electrical power generation system, including a generator, including a stator and a rotor, for converting mechanical power into alternating current electrical power by electromagnetic induction, and an active rectifier for converting the alternating current output of the generator into direct current electrical power is provided. | 2013-01-17 |
| 20130016547 | Simplified Multilevel DC Converter Circuit StructureAANM Liao; Yi-HungAACI Erlun TownshipAACO TWAAGP Liao; Yi-Hung Erlun Township TWAANM Lai; Ching-MingAACI Taichung CityAACO TWAAGP Lai; Ching-Ming Taichung City TW - A simplified multilevel DC converter circuit structure comprises a dual input DC power supply, a power control module and an AC side low-pass filter, wherein each of the dual input DC power supply supplies half of the rated DC voltage to the power control module, and the power control module is composed of six power switches, and different switching combinations of each power switch are controlled to convert a DC voltage to an output of an AC voltage, and two of the power switches of the power control module perform a low-frequency switching twice every cycle of the output voltage, and the withstand voltage is equal to the input voltage, and the remaining power switches perform the switching by a high frequency, and the withstand voltage is only half of the input voltage, such that a multilevel voltage can be outputted, and a low harmonic AC waveform can be outputted from the AC side low-pass filter. | 2013-01-17 |
| 20130016548 | SEMICONDUCTOR DEVICEAANM SEKI; ShinseiAACI WakoAACO JPAAGP SEKI; Shinsei Wako JP - A semiconductor device includes at least one arm series circuit, a conductive first thermal buffer member, and a conductive second thermal buffer member. The arm series circuit includes an upper arm, a lower arm, a positive-electrode terminal, a negative-electrode terminal, and an output terminal. The first thermal buffer member has a linear expansion coefficient greater than a linear expansion coefficient of the first switching device and smaller than a linear expansion coefficient of one of the positive-electrode terminal and the output terminal. The second thermal buffer member has a linear expansion coefficient greater than a linear expansion coefficient of the second switching device and smaller than a linear expansion coefficient of one of the negative-electrode terminal and the output terminal. | 2013-01-17 |
| 20130016549 | METHOD FOR CONTROLLING AN ELECTRICAL CONVERTER - A method is provided for predicting pulse width modulated switching sequences for a multi-phase multi-level converter. With a first predicted switching sequence, due to multi-phase redundancies, equivalent switching sequences are determined. From the equivalent switching sequences, one switching sequence optimal with respect to a predefined optimization goal is selected. The selected switching sequence is used to switch the converter. | 2013-01-17 |
| 20130016550 | INVERTERAANM Ku; Chen-WeiAACI Taoyuan HsienAACO TWAAGP Ku; Chen-Wei Taoyuan Hsien TWAANM Lee; Lei-MingAACI Taoyuan HsienAACO TWAAGP Lee; Lei-Ming Taoyuan Hsien TWAANM Huang; HoAACI Taoyuan HsienAACO TWAAGP Huang; Ho Taoyuan Hsien TW - An inverter including a switch circuit for converting a DC power to output an AC voltage between a first output terminal and a second output terminal is provided. The switch circuit includes a first switch branch having a first switch element, a second switch element, and a third switch element; a second switch branch having a fourth switch element, a fifth switch element, and a sixth switch element; a first freewheeling unit connected to the first switch element, the second switch element, and the second output terminal for providing a freewheeling path between the second output terminal and the first switch element and the second switch element; and a second freewheeling unit connected to the fourth switch element and the fifth switch element and the first output terminal for providing a freewheeling path between the first output terminal and the fourth switch element and the fifth switch element. | 2013-01-17 |
| 20130016551 | MAGNETIC RANDOM ACCESS MEMORY CELL WITH IMPROVED DISPERSION OF THE SWITCHING FIELDAANM Lombard; LucienAACI GrenobleAACO FRAAGP Lombard; Lucien Grenoble FRAANM Prejbeanu; Ioan LucianAACI Seyssinet ParisetAACO FRAAGP Prejbeanu; Ioan Lucian Seyssinet Pariset FR - The present disclosure concerns a magnetic random access memory MRAM cell comprising a tunnel magnetic junction formed from a first ferromagnetic layer, a second ferromagnetic layer having a second magnetization that can be oriented relative to an anisotropy axis of the second ferromagnetic layer at a predetermined high temperature threshold, and a tunnel barrier; a first current line extending along a first direction and in communication with the magnetic tunnel junction; the first current line being configured to provide an magnetic field for orienting the second magnetization when carrying a field current; wherein the MRAM cell is configured with respect to the first current line such that when providing the magnetic field, at least a component of the magnetic field is substantially perpendicular to said anisotropy axis. The MRAM cell has an improved switching efficiency, lower power consumption and improved dispersion of the switching field compared to conventional MRAM cells. | 2013-01-17 |
| 20130016552 | SEMICONDUCTOR MEMORY DEVICE FEATURING SELECTIVE DATA STORAGE IN A STACKED MEMORY CELL STRUCTURE - A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a plane; a second memory cell including a non-volatile second variable resistance element that stores data by varying a resistance value and a selection diode that selects the second variable resistance element; and a second memory layer provided with more than one such second memory cell arranged in a plane; wherein more than one such second memory layer is stacked over the first memory layer. | 2013-01-17 |
| 20130016553 | MRAM Sensing with Magnetically Annealed Reference CellAANM Rao; Hari M.AACI San DiegoAAST CAAACO USAAGP Rao; Hari M. San Diego CA USAANM Zhu; XiaochunAACI San DiegoAAST CAAACO USAAGP Zhu; Xiaochun San Diego CA US - Systems and method for reading/sensing data stored in magnetoresistive random access memory (MRAM) cells using magnetically annealed reference cells. A MRAM includes a reference circuit comprising at least one magnetic storage cell, wherein each magnetic storage cell in the MRAM is programmed to the same state. The reference circuit includes a load element coupled to the magnetic storage cell, wherein the load element is configured to establish a reference voltage during a read operation. | 2013-01-17 |
| 20130016554 | METHOD AND APPARATUS FOR INCREASING THE RELIABILITY OF AN ACCESS TRANSITOR COUPLED TO A MAGNETIC TUNNEL JUNCTION (MTJ) - A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor. | 2013-01-17 |
| 20130016555 | SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DRIVING THE SAMEAANM KIM; Myoung SubAACI Ichon-siAACO KRAAGP KIM; Myoung Sub Ichon-si KRAANM Kim; Soo GilAACI Ichon-siAACO KRAAGP Kim; Soo Gil Ichon-si KRAANM Park; Nam KyunAACI Ichon-siAACO KRAAGP Park; Nam Kyun Ichon-si KRAANM Kim; Sung CheoulAACI Ichon-siAACO KRAAGP Kim; Sung Cheoul Ichon-si KRAANM Do; Gap SokAACI Ichon-siAACO KRAAGP Do; Gap Sok Ichon-si KRAANM Sim; Joon SeopAACI Ichon-siAACO KRAAGP Sim; Joon Seop Ichon-si KRAANM Lee; Hyun JeongAACI Ichon-siAACO KRAAGP Lee; Hyun Jeong Ichon-si KR - A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode. | 2013-01-17 |
| 20130016556 | PLANAR PHASE- CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS - A method for operating a phase change memory that includes initializing a memory cell that includes: a first conductive electrode having a length greater than its width and an axis aligned with the length; a second conductive electrode having an edge oriented at an angle to the axis of the first conductive electrode; an insulator providing a separation distance between an end of the first conductive electrode and the edge of the second conductive electrode; and a phase change material covering a substantial portion of the first conductive electrode and at least a portion of the second conductive electrode. The initializing the memory cell includes creating a first amorphous material region in the phase change material. An active crystalline material region is created inside the first amorphous material region. Information is stored in the memory cell by creating a second amorphous material region inside the active crystalline material region. | 2013-01-17 |
| 20130016557 | SEMICONDUCTOR MEMORY DEVICE HAVING A THREE-DIMENSIONAL STRUCTURE - A three-dimensional memory device includes a stack of semiconductor layers. Phase change memory (PCM) cell arrays are formed on each layer. Each PCM cell includes a variable resistor as storage element, the resistance of which varies. On one layer, formed is peripheral circuitry which includes row and column decoders, sense amplifiers and global column selectors to control operation of the memory. Local bit lines and worldliness are connected to the memory cells. The global column selectors select global bitlines to be connected to local bit lines. The row decoder selects wordlines. Applied current flows through the memory cell connected to the selected local bitline and wordline. In write operation, set current or reset current is applied and the variable resistor of the selected PCM cell stores “data”. In read operation, read current is applied and voltage developed across the variable resistor is compared to a reference voltage to provide as read data. | 2013-01-17 |
| 20130016558 | METHOD OF STORING DATA IN NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING NONVOLATILE MEMORY DEVICEAANM Ahn; Jung-RoAACI Suwon-siAACO KRAAGP Ahn; Jung-Ro Suwon-si KRAANM Lee; Bong-YongAACI Suwon-siAACO KRAAGP Lee; Bong-Yong Suwon-si KRAANM Lee; Hae-BumAACI Suwon-siAACO KRAAGP Lee; Hae-Bum Suwon-si KRAANM Kim; Eui-DoAACI Ansan-siAACO KRAAGP Kim; Eui-Do Ansan-si KRAANM Jang; Houng-KukAACI Hwaseong-siAACO KRAAGP Jang; Houng-Kuk Hwaseong-si KRAANM Shin; Kyung-JunAACI Hwaseong-siAACO KRAAGP Shin; Kyung-Jun Hwaseong-si KRAANM Yoon; Tae-HyunAACI SeoulAACO KRAAGP Yoon; Tae-Hyun Seoul KR - In a method of storing data in a nonvolatile memory device, a program operation is performed on target memory cells among a plurality of memory cells based on a program voltage. A verification operation is performed on the target memory cells based on a verification voltage to determine whether all of the target memory cells are completely programmed. The verification voltage is changed depending on the program operation. | 2013-01-17 |
| 20130016559 | NAND FLASH MEMORY SYSTEM AND METHOD PROVIDING REDUCED POWER CONSUMPTIONAANM SONG; JONG-UKAACI SEOULAACO KRAAGP SONG; JONG-UK SEOUL KRAANM JANG; SOON-BOKAACI SEOULAACO KRAAGP JANG; SOON-BOK SEOUL KRAANM KIM; YOUNG-WOOKAACI GUNPO-SIAACO KRAAGP KIM; YOUNG-WOOK GUNPO-SI KRAANM KIM; HYUN-JINAACI SUWON-SIAACO KRAAGP KIM; HYUN-JIN SUWON-SI KR - A NAND flash memory device comprises a NAND flash memory comprising a first pad and a plurality of second pads. The first pad comprises a first receiver configured to receive a first signal. The second pads comprise a plurality of respective second receivers configured to receive a plurality of respective second signals. The second receivers are selectively powered, i.e., turned on or off, according to a logic level of the first signal. | 2013-01-17 |
| 20130016560 | SEMICONDUCTOR MEMORY DEVICESAANM YANO; MasaruAACI TokyoAACO JPAAGP YANO; Masaru Tokyo JPAANM CHIANG; Lu-PingAACI Hsinchu CityAACO TWAAGP CHIANG; Lu-Ping Hsinchu City TW - A semiconductor memory device includes a memory array, a row selection circuit and a bit line selection circuit. The memory array is composed of a plurality of cell units, wherein each cell unit has memory cells connected in series. The row selection circuit selects the memory cells in a row direction of the cell units, and the bit line selection circuit selects a bit line from an even bit line and an odd bit line coupled to the cell units. The bit line selection circuit includes a first selection part including selection transistors for selectively coupling the even or odd bit line to a sensor circuit and a second selection part including bias transistors for selectively coupling the even or odd bit line to a voltage source providing biases, wherein the bias transistors and the memory cells are formed in a common well. | 2013-01-17 |
| 20130016561 | ERASE SYSTEM AND METHOD OF NONVOLATILE MEMORY DEVICEAANM NAM; Sang-WanAACI Hwaseong-siAACO KRAAGP NAM; Sang-Wan Hwaseong-si KR - An erase system and method of a nonvolatile memory device includes supplying an erase voltage to a plurality of memory cells of a nonvolatile memory, performing a read operation with a read voltage to word lines of the plurality of memory cells, and performing an erase verification operation with an erase verification voltage to at least one of the word lines of the plurality of memory cells, the erase verification voltage lower than the read voltage. | 2013-01-17 |
| 20130016562 | METHOD AND SYSTEM FOR ADJUSTING READ VOLTAGE IN FLASH MEMORY DEVICEAANM MUN; Kui-YonAACI Hwaseong-SiAACO KRAAGP MUN; Kui-Yon Hwaseong-Si KR - A method is provided for adjusting a read voltage in a flash memory device. The method includes storing first program count information when first pages of flash memory cells are programmed, the first program count information indicating a number of bits having a first logic value from among bits of data programmed in the first pages of the flash memory cells, and obtaining first read count information by counting a number of bits having the first logic value from among bits of data read from the first pages of the flash memory cells, while reading data from the flash memory cells using read voltages. The read voltages are adjusted based on the difference between the first read count information and the first program count information. | 2013-01-17 |
| 20130016563 | MEMORY CIRCUITAANM OSANAI; JunAACI Chiba-shiAACO JPAAGP OSANAI; Jun Chiba-shi JPAANM Hirose; YoshitsuguAACI Chiba-shiAACO JPAAGP Hirose; Yoshitsugu Chiba-shi JPAANM Tsumura; KazuhiroAACI Chiba-shiAACO JPAAGP Tsumura; Kazuhiro Chiba-shi JPAANM Inoue; AyakeAACI Chiba-shiAACO JPAAGP Inoue; Ayake Chiba-shi JP - Provided is a memory circuit in which erroneous writing is less likely to occur at the time of power-on. A memory circuit ( | 2013-01-17 |
| 20130016564 | ERASE TECHNIQUES AND CIRCUITS THEREFOR FOR NON-VOLATILE MEMORY DEVICESAANM Ferragina; VincenzoAACI San Genesio ed Uniti (PV)AACO ITAAGP Ferragina; Vincenzo San Genesio ed Uniti (PV) ITAANM Surico; StefanoAACI Bussero (MI)AACO ITAAGP Surico; Stefano Bussero (MI) ITAANM Moioli; GiuseppeAACI Albino (BG)AACO ITAAGP Moioli; Giuseppe Albino (BG) ITAANM Bartoli; SimoneAACI Mandello del Lario (LC)AACO ITAAGP Bartoli; Simone Mandello del Lario (LC) IT - Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage. | 2013-01-17 |
| 20130016565 | NONVOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME AND ELECTRONIC DEVICE INCLUDING THE SAMEAANM Park; Jae-WooAACI Suwon-siAACO KRAAGP Park; Jae-Woo Suwon-si KRAANM Im; Jung-NoAACI Gunpo-siAACO KRAAGP Im; Jung-No Gunpo-si KR - A nonvolatile memory device and a method of operating the same are provided. The method includes performing a plurality of program operations on a plurality of memory cells each to be programmed to one of a plurality of program states, performing a program-verify operation on programmed memory cells associated with each of the plurality of program states, the program-verify operation comprises, selecting one of the plurality of offsets based on a noise level of a common source line associated with a programmed memory cell, using the selected offset to select one of a first verify voltage and a second verify voltage higher than the first verify voltage, and verifying a program state of the programmed memory cell using the first verify voltage and the second verify voltage. | 2013-01-17 |
| 20130016566 | DETECTING THE COMPLETION OF PROGRAMMING FOR NON-VOLATILE STORAGE - A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when all non-volatile storage elements have reached their target level or when the number of non-volatile storage elements that have not reached their target level is less than a number or memory cells that can be corrected using an error correction process during a read operation (or other operation). The number of non-volatile storage elements that have not reached their target level can be estimated by counting the number of non-volatile storage elements that have not reached a condition that is different (e.g., lower) than the target level. | 2013-01-17 |
| 20130016567 | NON-VOLTOLE MEMORY CELL AND METHODS FOR PROGRAMMING, ERASING AND READING THEREOFAANM CHANG; Chia-ChuanAACI Miaoli CountyAACO TWAAGP CHANG; Chia-Chuan Miaoli County TWAANM Chen; Wei-SungAACI Hsinchu CountyAACO TWAAGP Chen; Wei-Sung Hsinchu County TWAANM Wu; Chung-HoAACI Hsinchu CityAACO TWAAGP Wu; Chung-Ho Hsinchu City TW - A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a substrate having a first conductive type. A first transistor, a second transistor and a select transistor having a second conductive type are disposed in the substrate, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. A source region of the first transistor is coupled to a bit line. A drain region of the second transistor and a gate of the select transistor are coupled to a select gate line. A drain region of the first transistor is coupled to a source region of the select transistor. A drain region of the select transistor is coupled to a select line. A bit is stored in the first and second gates by controlling the bit line and the select gate line. A bit stored in the first and second gates is erased by controlling the bit line and the select gate line. | 2013-01-17 |
| 20130016568 | NON-VOLTOLE MEMORY CELL AND METHODS FOR PROGRAMMING, ERASING AND READING THEREOFAANM CHANG; Chia-ChuanAACI Miaoli CountyAACO TWAAGP CHANG; Chia-Chuan Miaoli County TWAANM Chen; Wei-SungAACI Hsinchu CountyAACO TWAAGP Chen; Wei-Sung Hsinchu County TWAANM Wu; Chung-HoAACI Hsinchu CityAACO TWAAGP Wu; Chung-Ho Hsinchu City TW - A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a well region having a first conductive type. A first transistor and a second transistor having a second conductive type are disposed on the well region, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. The first transistor and the second transistor share a drain region, coupling to a bit line. A first source region of the first transistor and a second region of the second transistor are coupled to a first select line and a second line, respectively. A bit is stored in the first and second gates by controlling the first select line and the second line. A bit stored in the first and second gates is erased by controlling the first select line or the second line. | 2013-01-17 |
| 20130016569 | MEMORY DEVICE HAVING IMPROVED PROGRAMMING OPERATION - Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation. | 2013-01-17 |
| 20130016570 | N-Channel Erasable Programmable Non-Volatile Memory - In an embodiment of the invention, a method of fabricating a floating-gate NMOSFET (n-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves as the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation. | 2013-01-17 |
| 20130016571 | CIRCUITS, DEVICES, SYSTEMS, AND METHODS OF OPERATION FOR CAPTURING DATA SIGNALS - Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus. The data capture circuit receives data relative to a write strobe signal and captures a first digit of the data responsive to a first edge of the write strobe signal and at least a second digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each digit in substantially the same manner as the data capture circuit, and generates a latch control signal indicative of when each digit is latched. The latch control signal is provided to a write control circuit that determines which digit was latched first relative to a timing, and generates a select control signal to drive captured digits onto the bus in the order the digits were received. | 2013-01-17 |
| 20130016572 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array block including a plurality of memory cells each including a data holding circuit configured to store data using a first and a second circuit elements and a transistor configured to connect the data holding circuit and a bit line together, sense amplifiers connected to bit lines directly or via switches, and a dummy memory cell array including a plurality of dummy memory cells each having the same circuit configuration as that of the memory cell with respect to the element size and the layout configuration. The plurality of dummy memory cells each include at least one inverter circuit configuration, and are connected together by the inverter circuits being connected together in series. An output signal of the inverter circuit of one in the final stage of the dummy memory cells is an activation signal for the sense amplifiers. | 2013-01-17 |
| 20130016573 | MEMORY DEVICE WITH TRIMMABLE POWER GATING CAPABILITIESAANM Goel; AnkurAACI KarnalAACO INAAGP Goel; Ankur Karnal INAANM Konudula; Venkateswara ReddyAACI BanagaloreAACO INAAGP Konudula; Venkateswara Reddy Banagalore INAANM Gowda; Sathisha NanjundeAACI HassanAACO INAAGP Gowda; Sathisha Nanjunde Hassan IN - A memory device includes at least one memory cell including a storage element electrically connected with a source potential line. A drive strength of the storage element is controlled as a function of a voltage level on the source potential line. The memory device further includes a clamp circuit electrically connected between the source potential line and a voltage source. The clamp circuit is operative to regulate the voltage level on the source potential line relative to the voltage source. A control circuit of the memory device is connected with the source potential line. The control circuit is operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device. A coarseness by which the voltage level on the source potential line is adjusted is selectively controlled as a function of at least a first control signal. | 2013-01-17 |
| 20130016574 | SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED REFRESH CHARACTERISTICS - A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period. | 2013-01-17 |
| 20130016575 | Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage - In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use. | 2013-01-17 |
| 20130016576 | TIME DIVISION MULTIPLEXING SENSE AMPLIFIERAANM O'CONNELL; Cormac MichaelAACI KanataAACO CAAAGP O'CONNELL; Cormac Michael Kanata CA - A circuit comprises a plurality of memory cells, a word line, a plurality of pairs of bit lines, a pre-charge and equalization device, a column select device, and a sense amplifier. The word line is configured to control the plurality of memory cells. Each pair of bit lines of the plurality of pairs of bit lines corresponds to a memory cell of the plurality of memory cells and is coupled to a pair of switches. The sense amplifier is coupled to the plurality of pairs of bit lines, the pre-charge and equalization device, and the column select device. | 2013-01-17 |
| 20130016577 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEMAANM NAGADOMI; YasushiAACI Yokohama-shiAACO JPAAGP NAGADOMI; Yasushi Yokohama-shi JP - A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations. | 2013-01-17 |
| 20130016578 | POWER SUPPLY SYSTEM FOR MEMORIESAANM WU; KANGAACI Shenzhen CityAACO CNAAGP WU; KANG Shenzhen City CNAANM TIAN; BOAACI Shenzhen CityAACO CNAAGP TIAN; BO Shenzhen City CN - A power supply system for memory modules includes a control unit and a voltage regulator. The control unit includes a basic input/output system (BIOS) and a control chip connected to the BIOS. The BIOS controls the control chip to output a control signal according to the number of the memory modules mounted in memory slots. The voltage regulator is connected to the control chip through first and second general purpose input/output (GPIO) buses. The voltage regulator receives the control signal from the control chip through the first and second GPIO buses and regulates power supply modes, to output different phase voltages to the memory modules mounted in the memory slots. | 2013-01-17 |
| 20130016579 | SEMICONDUCTOR DEVICE - A semiconductor device capable of stabilizing power supply by suppressing power consumption as much as possible. The semiconductor device of the invention includes a central processing unit having a plurality of units and a control circuit, and an antenna. The control circuit includes a means for outputting, based on a power supply signal including data on power supply from an antenna (through an antenna) or a load signal obtained by an event signal supplied from each of the units, one or more of a first control signal for stopping power supply to one or more of the units, a second control signal for varying a power supply potential supplied to one or more of the units, and a third control signal for stopping supplying a clock signal to one or more of the units. | 2013-01-17 |
| 20130016580 | MIXING/EXTRUDING APPARATUS AND START-UP METHOD FOR MIXING/EXTRUDING APPARATUSAANM HOTANI; SHINAACI Takasago-shiAACO JPAAGP HOTANI; SHIN Takasago-shi JPAANM NAGAOKA; TATSUTOAACI Takasago-shiAACO JPAAGP NAGAOKA; TATSUTO Takasago-shi JPAANM HATANAKA; TAKESHIAACI Takasago-shiAACO JPAAGP HATANAKA; TAKESHI Takasago-shi JP - A mixing/extruding apparatus having a mixer/extruder provided with a diverter, an electric motor for driving this mixer/extruder, and a power supply device for supplying a drive power to this electric motor, and the power supply device includes a start-up power supply portion for supplying a drive power with which the electric motor is rotated at low speed with a smaller output than an output generated upon the normal operation to the electric motor, an operation power supply portion for supplying a drive power with which the electric motor is rotated at high speed with the output generated upon the normal operation to the electric motor, and a power supply switching device for switching the drive power from the start-up power supply portion to be supplied to the electric motor to the drive power from the operation power supply portion. | 2013-01-17 |
| 20130016581 | Mixing Device Having a Wear-Resistant LiningAANM Doerr; MartinAACI WalldurnAACO DEAAGP Doerr; Martin Walldurn DEAANM Worner; WolfgangAACI Hopfingen-WaldstettenAACO DEAAGP Worner; Wolfgang Hopfingen-Waldstetten DEAANM Gerl; StefanAACI WerbachAACO DEAAGP Gerl; Stefan Werbach DEAANM Schmitt; ClemensAACI Walldurn-AltheimAACO DEAAGP Schmitt; Clemens Walldurn-Altheim DEAANM Wagner; PeterAACI HardheimAACO DEAAGP Wagner; Peter Hardheim DE - The present invention relates to a mixing device, comprising a vessel for receiving material for mixing, which can be rotated abut a vessel axis and has a discharge opening disposed in the base thereof, a mixing tool disposed in the interior of the vessel, and a closure lid for closing the discharge opening, where the vessel base and/or the closure lid are provided with a wear-resistant lining on the side facing the interior of the vessel. In order to provide a mixing device having a wear-resistant lining which is less prone to wear, and in the event of wear can be replaced more easily and above all more cost-effectively, according to the invention the wear-resistant lining consists of a main lining part and a wear element, wherein the wear element is disposed closer to the vessel axis than the main lining part. | 2013-01-17 |
| 20130016582 | SYSTEM FOR EXPLORATION OF SUBTERRANEAN STRUCTURESAANM Fallet; TrulsAACI OsloAACO NOAAGP Fallet; Truls Oslo NOAANM Woods; ErlingAACI HafrsfjordAACO NOAAGP Woods; Erling Hafrsfjord NO - A system for communication through subterranean structures underneath a surface comprises at least one exploration tool adapted to penetrate into the underground, at least one transmitter, at least one receiver, and signal transfer means for transmitting signals between the exploration tool and a recording unit arranged overground, where at least one of the transmitter or receiver is integrated in the exploration tool. The exploration tool is a device which is able to penetrate into the underground in order to bring equipment into the underground independent of any existing or new wells. | 2013-01-17 |
| 20130016583 | Correcting Aliasing of Pulsed Wave Doppler of Diagnostic Ultrasound - Pulsed wave (PW) Doppler has the same emitted and reflected pulse frequency because it emits the next ultrasound pulse after receiving the previously reflected one. But, the forward blood flow will interact with the emitted ultrasound pulse and shorten its time of flight (TOF), which creates a positive TOF shift between the calculated TOF and detected TOF. If the velocity of forward flow is too fast and causes the TOF shift more than half of the calculated TOF, the reflected ultrasound pulses are considered as from the previously emitted pulses with longer TOF, which will show negative TOF shift and be misinterpreted as aliasing. This aliasing TOF shift can be completely rectified to its correct registration no matter how fast the forward flow velocity will be. So, the advantages of TOF shift theory can better quantitatively explain the spectral characteristics of PW Doppler, and more accurately calculate the flow velocity. | 2013-01-17 |
| 20130016584 | METHODS AND APPARATUS FOR OBTAINING SENSOR MOTION AND POSITION DATA FROM UNDERWATER ACOUSTIC SIGNALSAANM Zhou; JiangyingAACI DurhamAAST NCAACO USAAGP Zhou; Jiangying Durham NC USAANM Zachery; KarenAACI RaLeighAAST NCAACO USAAGP Zachery; Karen RaLeigh NC USAANM Qian; MingAACI CaryAAST NCAACO USAAGP Qian; Ming Cary NC USAANM Bogdanov; AlexanderAACI Simi ValleyAAST CAAACO USAAGP Bogdanov; Alexander Simi Valley CA US - Technologies are provided to recover motion, position, or navigation data of underwater sensors using bathymetry data. A method includes iteratively fitting data obtained by an underwater sensor from interactions between acoustic signals and an underwater floor, and deriving at least one of motion, position, or navigation data of the underwater sensor from the fitting. A standalone sonar can use the methods, systems, apparatuses, and computer programs to realize the derivation of motion, position, or navigation data without a position or motion sensor. | 2013-01-17 |
| 20130016585 | VARIABLE POWER FISH FINDER - A device having a digital controller, a power amplifier, a sonar transducer, and a sonar receiver communicatively coupled to the digital controller. The digital controller provides a power control signal to the power amplifier, which in turn drives the sonar transducer at a level determined in real time by the digital controller to prevent excessive noise from being detected by the sonar receiver. | 2013-01-17 |
| 20130016586 | FISH FINDER WITH SIMPLIFIED CONTROLS - A fish finder having a sonar transducer, a sonar receiver, a display unit having a single user control or no user controls. The fish finder has a digital controller within the display unit that has a predetermined set of operational parameters programmed therein. Upon activation of the control, the digital controller operates the sonar transducer and sonar receiver according to the predetermined operational parameters. | 2013-01-17 |
| 20130016587 | ULTRASONIC TRANSDUCER UNIT AND ULTRASONIC PROBEAANM Lee; Seung-MokAACI OsakaAACO JPAAGP Lee; Seung-Mok Osaka JP - In an ultrasonic transducer unit comprising a plurality of ultrasonic transducers, each of the ultrasonic transducers is provided with a recess formed in one face of an insulating substrate, and a substrate-side electrode is buried in a bottom of the recess, and a vibrating membrane is formed so as to cover the recess. | 2013-01-17 |
| 20130016588 | SYSTEM FOR INTERCHANGEABLE MOUNTING OPTIONS FOR A SONAR TRANSDUCERAANM O'Dell; Kyle D.AACI Fort GibsonAAST OKAACO USAAGP O'Dell; Kyle D. Fort Gibson OK US - Systems and apparatuses for interchangeable mounting options for a transducer housing are provided herein. Such a system may provide for easy change of mounting to a watercraft, such as between transom mounting, portable mounting, trolling motor mounting, and thru-hull mounting. A system for interchangeable mounting options of a sonar transducer to a watercraft may comprise at least one transducer, a transducer housing configured to house the at least one transducer, and a mount adapter. The transducer housing may comprise at least one upper engagement surface configured to adjacently engage the mount adapter to facilitate mounting. The at least one upper engagement surface may be configured to releasably engage the mount adapter to allow the mount adapter to be detached and removed without damaging or altering the transducer housing. | 2013-01-17 |
| 20130016589 | RADIO-CONTROLLED TIMEPIECEAANM Takada; AkinariAACI TokyoAACO JPAAGP Takada; Akinari Tokyo JPAANM Ike; TakujiAACI TokyoAACO JPAAGP Ike; Takuji Tokyo JP - A radio-controlled timepiece includes an oscillator circuit of which an oscillation condition can be varied by an oscillation condition adjustment circuit that adjusts an oscillation frequency, a frequency divider circuit that divides the oscillation frequency and generates a time measurement reference timing signal, a frequency adjustment circuit that adjusts the period of time measurement reference timing signal, a local oscillator circuit that uses the oscillation frequency as a reference frequency and outputs a local oscillation frequency, and a control circuit. The control circuit, when the radio-controlled timepiece is performing reception operations, causes the oscillation condition adjustment circuit to operate whereby the oscillation frequency is adjust to an optimal frequency for the local oscillator circuit and the variation setting value of the frequency adjustment circuit is set such that time measurement reference timing signal has a fixed period for normal operations and for reception operations. | 2013-01-17 |
| 20130016590 | TIMEPIECE MOVEMENT COMPRISING A MODULE FITTED WITH A WHEEL SET MESHING WITH ANOTHER WHEEL SET PIVOTING IN A BASE ON WHICH THE MODULE IS MOUNTEDAANM Moulin; JulienAACI VollegesAACO CHAAGP Moulin; Julien Volleges CHAANM Villar; IvanAACI BienneAACO CHAAGP Villar; Ivan Bienne CHAANM Kaelin; LaurentAACI SonvilierAACO CHAAGP Kaelin; Laurent Sonvilier CHAANM Wyssbrod; BaptistAACI NidauAACO CHAAGP Wyssbrod; Baptist Nidau CH - Timepiece movement including a module fitted with a first wheel set meshing with a second wheel set, which pivots on a base on which the module is mounted. The movement includes a means of positioning the module formed by a cam, at least most of the periphery of which forms an Archimedes' spiral. The cam is arranged so as to allow the distance of centres between the first and second wheel sets to be adjusted, when the cam is rotated on itself about the centre of the Archimedes' spiral. The cam is preferably calibrated. The invention also concerns a method of adjusting the distance of centres between the two wheel sets using said cam to optimise the gearing efficiency of the two wheel sets. | 2013-01-17 |
| 20130016591 | THERMALLY-ASSISTED MAGNETIC RECORDING MEDIUM AND MAGNETIC RECORDING/REPRODUCING DEVICE USING THE SAMEAANM TOMIKAWA; SatoshiAACI TokyoAACO JPAAGP TOMIKAWA; Satoshi Tokyo JPAANM MIZUNO; TomohitoAACI TokyoAACO JPAAGP MIZUNO; Tomohito Tokyo JP - A thermally-assisted magnetic recording (TAMR) medium of the present invention includes: a magnetization direction arrangement layer on a substrate; and a magnetic recording layer on the magnetization direction arrangement layer, wherein the magnetization direction arrangement layer is made of at least one selected from a group consisting of Co, Zr, CoZr, CoTaZr, CoFeTaZrCr, CoNbZr, CoNiZr, FeCoZrBCu, NiFe, FeCo, FeAlN, (FeCo)N, FeAlSi, and FeTaC so that a spreading of the heating spot applied from the magnetic head for thermally-assisted recording to the film surface of the magnetic recording medium is suppressed, and that an SN is improved by arranging the magnetization direction of the perpendicularly written recording magnetization to become identical to a perpendicular direction, and realizing the higher recording density. | 2013-01-17 |
| 20130016592 | THERMALLY-ASSISTED MAGNETIC RECORDING HEAD, HEAD GIMBAL ASSEMBLY AND MAGNETIC RECORDING DEVICEAANM TOMIKAWA; SatoshiAACI TokyoAACO JPAAGP TOMIKAWA; Satoshi Tokyo JPAANM Mizuno; TomohitoAACI TokyoAACO JPAAGP Mizuno; Tomohito Tokyo JPAANM Kurihara; KatsukiAACI TokyoAACO JPAAGP Kurihara; Katsuki Tokyo JP - A thermally-assisted magnetic recording head, includes: a pole that generates a writing magnetic field from an end surface that forms a portion of an air bearing surface opposing a magnetic recording medium; a waveguide through which light for exciting a surface plasmon propagates; a plasmon generator that couples to the light in a surface plasmon mode and generates near-field light from a near-field light generating portion on a near-field light generating end surface that forms the portion of the air bearing surface; and magnetic field focusing parts that are able to focus the writing magnetic field generated from the pole and that are disposed on both sides of the pole in a track width direction from a perspective of the air bearing surface side. | 2013-01-17 |
| 20130016593 | SYSTEM AND METHOD FOR INITIALIZATION OF MEDIA ASSET MODULES FOR IMPROVED EXECUTION SEQUENCE ON A PLAYBACK ENVIRONMENTAANM Prestenback; KyleAACI BurbankAAST CAAACO USAAGP Prestenback; Kyle Burbank CA USAANM Robert; ArnaudAACI Simi ValleyAAST CAAACO USAAGP Robert; Arnaud Simi Valley CA US - There is provided a system and method for initialization of media asset modules for an improved execution sequence on a playback environment. The system includes a player application configured to segment media assets associated with a primary media content into a plurality of asset modules, assemble the plurality of asset modules into a media file, identify a first subset of asset modules from the plurality of asset modules for loading in a first loading process, determine a loading sequence for the first subset of asset modules, and load the first subset of asset modules according to the loading sequence before beginning playback of the primary media content. The player application may be further configured to identify, determine another loading sequence for, and load additional asset modules after playback of the primary media content has begun. | 2013-01-17 |
| 20130016594 | OPTICAL DISK APPARATUSAANM Kondo; KenjiAACI OsakaAACO JPAAGP Kondo; Kenji Osaka JPAANM Fujiune; KenjiAACI OsakaAACO JPAAGP Fujiune; Kenji Osaka JPAANM Yamamoto; TakeharuAACI OsakaAACO JPAAGP Yamamoto; Takeharu Osaka JP - Provided is an optical disk apparatus capable achieving stable focus control or tracking control. A first detector receives reflected light from an object lens optical system, a second detector receives reflected light from a prescribed information layer, a positional deviation determination unit determines positional deviation between a focal point of a light beam and a point where information on the prescribed information layer is recorded or reproduced, on the basis of a signal from the second detector, a stray light determination unit determines a surface stray light component which is reflected light from the surface of an optical disk and is included in the signal from the positional deviation determination unit, on the basis of the signal from the first detector, and a stray light correction unit corrects the signal output from the positional deviation determination unit on the basis of the surface stray light component thus determined. | 2013-01-17 |
| 20130016595 | METHOD OF DRIVING OPTICAL DISC AND OPTICAL DISC DRIVE USING THE METHODAANM Yi; Ho-seokAACI Suwon-siAACO KRAAGP Yi; Ho-seok Suwon-si KRAANM Han; Yong-hoAACI Hwaseong-siAACO KRAAGP Han; Yong-ho Hwaseong-si KR - A method of driving an optical disc and an optical disc drive using the method is provided. The method includes rotating an optical disc by a spindle motor, transferring an optical pickup positioned to correspond to the optical disc by driving a sled motor, and decreasing a current supplied to the spindle motor while driving the sled motor. | 2013-01-17 |
| 20130016596 | OPTICAL STORAGE MEDIUM WITH OPTICALLY DETECTABLE MARKS - Optically detectable marks readable by a wide range of optical systems are included on an optical storage medium. Among other uses, the marks may be used to determine the type of the optical storage medium in an optical device capable of reading multiple types of optical storage media. | 2013-01-17 |
| 20130016597 | OPTICAL PICKUP APPARATUSAANM Fukumoto; SatoruAACI OsakaAACO JPAAGP Fukumoto; Satoru Osaka JPAANM Murakami; ShinzohAACI OsakaAACO JPAAGP Murakami; Shinzoh Osaka JP - An optical pickup apparatus is provided. Segmented regions included in a focus diffraction region includes focus segmented regions corresponding in number with different light emitted by a light source. Different focus segmented regions are arranged adjacent to each other alternately in a direction perpendicular to a parallel dividing line. Segmented regions included in a tracking diffraction region includes tracking segmented regions corresponding in number with different light emitted by the light source. Different tracking segmented regions are arranged adjacent to each other alternately in a direction perpendicular to the parallel dividing line. | 2013-01-17 |
| 20130016598 | OPTICAL INFORMATION RECORDING/REPRODUCING APPARATUS AND OBJECTIVE OPTICAL SYSTEM FOR THE SAMEAANM YAMAGATA; NaokiAACI TokyoAACO JPAAGP YAMAGATA; Naoki Tokyo JPAANM INOUE; SatoshiAACI SaitamaAACO JPAAGP INOUE; Satoshi Saitama JPAANM TAKEUCHI; ShuichiAACI SaitamaAACO JPAAGP TAKEUCHI; Shuichi Saitama JP - An objective optical system for an optical information recording/reproducing apparatus, at least one surface of the objective optical system being configured to be a phase shift surface having a phase shift structure, wherein: the phase shift surface has a first area contributing to converging first, second and third light beams onto recording surfaces of first, second and third optical discs, respectively; in the first area, the phase shift surface has at least two types of phase shift structures including a first phase shift structure having first steps and a second phase shift structure having second steps; the phase shift surface has a plurality of combinations of annular zones which satisfy a condition: | 2013-01-17 |
| 20130016599 | OPTICAL PICKUP DEVICE AND OPTICAL DISC APPARATUS - Optical pickup device including: semiconductor laser diode emitting optical flux; objective lens converging flux emitted from the diode and radiating flux to an optical disc; diffraction grating branching an optical flux reflected from the disc; and a photodetector receiving flux branched by the grating and has a plurality of light receiving parts, wherein: the grating has areas A, B and C; among diffracted beams diffracted by a track of the optical disc, only a 0-th order diffracted beam becomes incident upon area A, and 0-th and ±1-st order diffracted beams become incident upon area B; the photodetector detects a reproduction signal from optical fluxes diffracted in areas A, B and C; the plurality of light receiving parts which detect the +1-st order diffracted beam or the −1-st diffracted beam diffracted in area A are aligned in a direction substantially perpendicular or parallel to a track direction of the disc. | 2013-01-17 |
| 20130016600 | NETWORK APPARATUS AND METHOD OF RETRANSMITTING FRAME USING THE SAMEAANM HWANG; Sung HoAACI SuwonAACO KRAAGP HWANG; Sung Ho Suwon KRAANM Park; Joun SupAACI SuwonAACO KRAAGP Park; Joun Sup Suwon KRAANM Kim; Ki HongAACI SuwonAACO KRAAGP Kim; Ki Hong Suwon KRAANM Park; Chul GyunAACI YonginAACO KRAAGP Park; Chul Gyun Yongin KRAANM Song; Tae WonAACI SeoulAACO KRAAGP Song; Tae Won Seoul KRAANM Pack; Sang HeonAACI SeoulAACO KRAAGP Pack; Sang Heon Seoul KR - There is provided a network apparatus capable of effectively retransmitting a frame in a frame aggregation environment, and a method of retransmitting a frame using the same. The network apparatus includes: a transmitting node broadcasting a plurality of data frames in a frame aggregation environment; a receiving node receiving the plurality of broadcast data frames and broadcasting a reception result; and at least one relay node receiving and storing at least a portion of the plurality of broadcast data frames and transmitting, together with the transmitting node, a data frame for which retransmission is required to the receiving node according to a calculated transmission success rate when the reception result from the receiving node is a retransmission request. | 2013-01-17 |
| 20130016601 | APPARATUS AND METHOD FOR MAINTAINING A CIRCUIT-SWITCHED VOICE CALL IN A MULTI-RAB WIRELESS COMMUNICATION SYSTEM IN AN AREA OF WEAK COVERAGE - An apparatus and a method are provided for improving user experience in a multi-radio access bearer (multi-RAB) wireless communication system. After a user equipment establishes a circuit-switched communication link and a packet-switched communication link with a core network, it may receive an indication of an error associated with the packet-switched communication link. Here, if the value of a timer such as the RAB re-establishment timer T314 has a predetermined value (e.g., 0), the user equipment may release the packet-switched communication link, and maintain the circuit-switched communication link. The packet-switched communication link may then be re-established. In this fashion, errors that may occur on the data call need not interrupt a voice call. | 2013-01-17 |
| 20130016602 | SIMPLIFIED SIGNALING FOR SMALL DATA TRANSMISSIONS - A signaling procedure for establishing and terminating connections for small data transmissions (SDTs) by wireless devices. A wireless device sends an access request message to a serving wireless access node on a random access channel (RACH). The access request message includes an indication that the access is for a SDT. The access request message includes the amount of data that will be transmitted as part of the SDT. The wireless access node sends an assignment message to immediately assign radio resources to the wireless device without further signaling needed for the SDT to begin. When the wireless device begins the SDT, the first data block is coded and transmitted according to a first predetermined coding scheme. If there are any subsequent data blocks, the wireless device includes an information element in the header of the first data block to indicate the coding scheme for the subsequent data blocks. | 2013-01-17 |
| 20130016603 | MULTIPLEXING SCHEMES FOR OFDMA - Methods and systems are provided for allocating resources including VoIP (voice over Internet Protocol) and Non-VoIP resources. In some embodiments, multiplexing schemes are provided for use with OFDMA (orthogonal frequency division multiplexing access) systems, for example for use in transmitting VoIP traffic. In some embodiments, various HARQ (Hybrid Automatic request) techniques are provided for use with OFDMA systems. In various embodiments, there are provided methods and systems for dealing with issues such as Handling non-full rate vocoder frames, VoIP packet jitter handling, VoIP capacity increasing schemes, persistent and non-persistent assignment of resources in OFDMA systems. | 2013-01-17 |
| 20130016604 | METHOD AND APPARATUS FOR EFFICIENTLY TRANSMITTING CONTROL INFORMATION TO SUPPORT UPLINK MULTIPLE ANTENNA TRANSMISSION - The present invention relates to a method for transmitting control information regarding uplink multiple antenna transmission may comprise the steps of: transmitting DCI for scheduling the uplink transmission of a plurality of data blocks through a PDCCH; receiving the plurality of data blocks scheduled by the DCI; transmitting information which indicates positive acknowledgement or negative acknowledgement to each of the plurality of received data blocks through the PHICH; and receiving retransmission for the negative acknowledged data blocks. When the number of the negative-acknowledged data blocks is not equal to the number data blocks indicated in the PDCCH, a pre-coding matrix, which is for the number of transmission layers equivalent to that of layers corresponding to the negative-acknowledged data blocks, may be used for retransmission. | 2013-01-17 |
