| 03rd week of 2013 patent applcation highlights part 16 |
| Patent application number | Title | Published |
|---|
| 20130015805 | ENERGY STORAGE ELEMENT LINK AND MONITOR - The invention provides an energy storage system having storage elements linked for collective charging and discharging. Monitoring circuitry is provided for monitoring each of the storage elements independently. Preferably, the system includes control circuitry configured for controlling the linking of individual storage elements in order to enhance system performance. In preferred embodiments, the system also includes storage elements in an arrangement whereby they may be selectably linked and delinked, in series, parallel, or in one or more series/parallel combination. | 2013-01-17 |
| 20130015806 | Tamper-Resistant Network-Attached Energy System with Access Control - Described herein are a system and method to provide energy to consumers using a prepaid usage model so as to protect the ability to recoup start-up and recurrent costs while simultaneously offering lower-income individuals the ability to access the energy on-demand. The system and method allow verification with an account server of a user's prepaid usage balance so an energy provider need not extend credit to the user or bill a user after energy usage. The system is portable and versatile in that it can be adapted to different energy sources including renewable energy sources such as wind, water, and/or solar sources. Anti-tampering features reduce the likelihood that the energy system will be disassembled with the components appropriated for repurposing. | 2013-01-17 |
| 20130015807 | System and Method for Using Capacitors in Wireless Networks - A battery-free wireless network is provided with one or more series or parallel capacitive networks. One or more solar panels are used to charge the capacitive networks and one or more charging circuits are used to control the charging of the capacitive networks. One or more DC-DC converters maybe used to provide a voltage to a wireless router, switch or other network device, the timer/clock circuitry, and a user interface. In those instances when it is desired that the timer/clock circuitry remain powered at all times, the timer/clock circuitry is preferentially preserved at the expense of the network device such that if, for any reason, the capacitive network is drained after running the network device, there will still be sufficient power stored in the capacitive network to maintain the timer/clock circuitry. | 2013-01-17 |
| 20130015808 | DEVICE AND METHOD FOR CHARGING A MASTER DEVICE USING A DETACHABLE DEVICEAANM LEE; HyangbokAACI SeoulAACO KRAAGP LEE; Hyangbok Seoul KR - A charging control method of a master device receiving an operating power from an auxiliary battery device or an internal battery, the auxiliary battery device including a battery having a first power supply and a first power supply output port for outputting the first power supply, is provided. The method includes converting a second power supply to the first power supply upon detecting the second power supply at an input port of the master device in order to provide the converted first power supply as an operating power of the master device and/or a charging power of the internal battery, and detecting a connection with the auxiliary battery device upon detecting the first power supply at the input port in order to provide the first power supply as the operating power of the master device and/or the charging power of the internal battery without voltage drop. | 2013-01-17 |
| 20130015809 | DEVICE AND METHOD FOR CONTROLLED EXCHANGE OF ENERGY BETWEEN AN ELECTRICAL POWER NETWORK AND A LOADAANM Frey; ThomasAACI EbersbergAACO DEAAGP Frey; Thomas Ebersberg DEAANM Stulle; Markus A.AACI MunchenAACO DEAAGP Stulle; Markus A. Munchen DE - A device for controlling the exchange of energy between an electrical power network and a load includes a stationary charging station for establishing an energy connection between the electrical power network and a supply point. The charging station has an LS controller for sending and receiving control signals via a signal transmission path, and includes a SIM station installed on the load side having a SIM controller. The SIM controller sends a SIM identifier of the SIM station to the LS controller via a signal transmission path at time intervals, wherein the LS controller adds an amount of energy exchanged between the electrical power network and the load to an energy amount counter associated with the SIM identifier. The amount of energy exchanged between the electrical power network and the load via the energy connection in a time interval is below a specified measurement resolution of the energy amount counter. | 2013-01-17 |
| 20130015810 | Battery Charging Apparatus with a Common Control Loop for a Low Drop-Out Voltage Regulator and a Boost RegulatorAANM Guo; GuoyongAACI Santa ClaraAAST CAAACO USAAGP Guo; Guoyong Santa Clara CA USAANM Nie; DanAACI ChengduAACO CNAAGP Nie; Dan Chengdu CN - A flexible dual mode battery charger that charges a battery in two different modes, depending on the difference between the adapter voltage and the battery voltage, with a smooth transition between these two modes and the charging current remains relatively constant during the transition is provided in this application. At a lower battery level, the dual mode battery charger charges the battery as a LDO charger and when battery voltage is very close to the adapter voltage, the charger migrates its operating mode from the LDO mode to the boost mode and charges the battery as a boost charger. This flexible battery charger uses one common control circuit for controlling the operations of the LDO charger and the boost charger. The switching operation from one operation mode to other operation mode is smooth. | 2013-01-17 |
| 20130015811 | WIRELESS MOBILE COMMUNICATION DEVICE UTILIZING ANTENNA FOR POWER CHARGING AND WIRELESS CHARGING SYSTEM HAVING THE SAMEAANM TANG; CHAI-LUNAACI Miaoli CountyAACO TWAAGP TANG; CHAI-LUN Miaoli County TWAANM CHANG; YU-PINAACI Taoyuan CountyAACO TWAAGP CHANG; YU-PIN Taoyuan County TW - A wireless charging mobile communication device includes a wireless communication module, an electricity storage module, a converting module, an antenna module and a switching module. The antenna module receives and transmits wireless signal or electromagnetically induces a current. The switching module is electrically coupled to the antenna module, the wireless communication module, and the converting module. The switching module is for connecting the antenna module with the wireless communication module or connecting the antenna module with the converting module. The converting module is electrically coupled to the electricity storage module and converts the electromagnetically induced current for facilitating a charging of the electricity storage module. The converting module, the antenna module, and the switching module are integrated as an antenna device. | 2013-01-17 |
| 20130015812 | ELECTRICAL CHARGING SYSTEM HAVING ENERGY COUPLING ARRANGEMENT FOR WIRELESS ENERGY TRANSMISSION THEREBETWEEN - An electrical charging system (ECS) to electrically charge a battery includes a power transmitter, an energy coupling arrangement, at least one electrical signal shaping device (ESSD) including a controller, and an alignment means. The arrangement includes a first transducer disposed external to the vehicle and a second transducer attached with the vehicle. The alignment means communicates with the vehicle to ensure repeatable vehicle positioning so that the second transducer is positioned relative to the first transducer so that the second transducer receives the energy produced by the power transmitter wirelessly transmitted from the first transducer. The energy received by the second transducer is electrically shaped by the ESSD and further electrically transmitted through the ESSD as controlled by the controller to electrically charge the ESD. Methods to operate and electrically transmit energy through the ECS to electrically charge the EDS are also presented. | 2013-01-17 |
| 20130015813 | WIRELESS POWER RECEIVERAANM KIM; Joon-IlAACI SeoulAACO KRAAGP KIM; Joon-Il Seoul KRAANM Park; Sung-BumAACI Suwon-siAACO KRAAGP Park; Sung-Bum Suwon-si KRAANM Park; Se-HoAACI Suwon-siAACO KRAAGP Park; Se-Ho Suwon-si KRAANM Lee; Young-MinAACI Yongin-siAACO KRAAGP Lee; Young-Min Yongin-si KRAANM Lee; Woo-RamAACI Hwaseong-siAACO KRAAGP Lee; Woo-Ram Hwaseong-si KR - A wireless power receiver is provided for wirelessly receiving driving power from a wireless power transmitter. The wireless power receiver includes a power reception unit for wirelessly receiving the driving power from the wireless power transmitter. The wireless power receiver also includes a rectifier for rectifying the driving power output from the power reception unit into an Alternating Current (AC) power type. The wireless power receiver additionally includes a load unit for storing the rectified driving power output from the rectifier. The wireless power receiver further includes a controller for detecting an amount of the rectified driving power stored in the load unit to control output from the rectifier to the load unit. The wireless power receiver also includes an impedance adjuster for adjusting an impedance in the power reception unit according to the amount of the rectified driving power stored in the load unit. | 2013-01-17 |
| 20130015814 | Charge Disruption Monitoring and Notification SystemAANM Kelty; Kurt RussellAACI Palo AltoAAST CAAACO USAAGP Kelty; Kurt Russell Palo Alto CA USAANM Kohn; Scott IraAACI Redwood CityAAST CAAACO USAAGP Kohn; Scott Ira Redwood City CA US - A system and method for notifying a designated party when an electric vehicle charging operation is unexpectedly disrupted is provided. The system monitors the connection between the electric vehicle and the external battery pack charging source, issues a command to a notification system to send a notification message to the designated party when an interruption is detected, and then issues the notification message in accordance with a set of notification instructions. The notification instructions may include one or more criteria for determining whether the disruption is authorized, thus not requiring the transmittal of the notification message. Criteria for accepting the change in battery pack charging status as authorized includes user/device proximity to the vehicle, achievement of a target battery pack SOC, and location of the vehicle within a safe zone. | 2013-01-17 |
| 20130015815 | System for Identifying an Electric Vehicle Connected to Electric Vehicle Service Equipment - A system for identifying an electric vehicle connected to electric vehicle service equipment (EVSE) and which involves RF communication exploits the OBDM of the electric vehicle as well as the auto-CAM system. Power is applied from the EVSE to supply electric power and the flow of current to the battery charger is detected. The VIN and a power-on signal is then transmitted by RF to the EVSE transceiver. Power is removed from the EVSE to the electric vehicle. A VIN and a power-off signal is transmitted to the EVSE and processed to confirm the identity of the connected electric vehicle. Power is then re-applied to the EVSE to charge the battery power supply. | 2013-01-17 |
| 20130015816 | Valet EVSE System - A valet EVSE system employs a plurality of outlet stations which are configured with an electrical outlet and brackets for receiving a portable EVSE unit. The portable EVSE unit is configured to removably mount to the brackets and draw power from the electrical outlet. In one embodiment a given station is adapted to receive and supply power to two portable EVSE units. A housing is provided with a pivoted cover for securing the plug of the EVSE unit with the outlet disposed in the housing. | 2013-01-17 |
| 20130015817 | CHARGE AND DISCHARGE BALANCING CIRCUIT FOR STORAGE BATTERY SETAANM WANG; LianAACI TaipeiAACO TWAAGP WANG; Lian Taipei TWAANM HSIEH; Tar LiAACI Yangmei CityAACO TWAAGP HSIEH; Tar Li Yangmei City TW - A charge and discharge balancing circuit for a storage battery set, the set comprising n storage batteries connected in series, the circuit comprising: a switch set constituted of n switches, each switch having a first and a second switching nodes and a common node, the second switching node of a previous switch and the first switching node of a next switch being electrically connected, and the first switching node and the second switching node of each switch being connected in parallel to both terminals of the storage battery in order; an electricity storage component set constituted of n−1 electricity storage components connected in series, both terminals of each electricity storage component being connected in parallel to the common nodes of two switches in order; and a pulse generator for controlling the switching of the common node of each switch between the first and the second switching node at a frequency. | 2013-01-17 |
| 20130015818 | CIRCUIT ASSEMBLYAANM Schaefer; TimAACI HarztorAACO DEAAGP Schaefer; Tim Harztor DE - The invention relates to a circuit assembly ( | 2013-01-17 |
| 20130015819 | POWER STORAGE UNIT, CORRECTION METHOD FOR CAPACITY VALUES OF STORAGE BATTERIES, AND POWER STORAGE SYSTEMAANM Nakashima; TakeshiAACI Moriguchi CityAACO JPAAGP Nakashima; Takeshi Moriguchi City JPAANM Ikebe; HayatoAACI Moriguchi CityAACO JPAAGP Ikebe; Hayato Moriguchi City JP - A power storage unit is provided which is able to facilitate recalibration and which is able to supply power even while recalibration is being performed. A method for correcting the capacity values of storage batteries, and a power storage system are also provided. | 2013-01-17 |
| 20130015820 | SYSTEM AND METHOD FOR BALANCING ELECTRICAL ENERGY STORAGE DEVICES VIA DIFFERENTIAL POWER BUS AND CAPACITIVE LOAD SWITCHED-MODE POWER SUPPLYAANM Kim; Jang DaeAACI San JoseAAST CAAACO USAAGP Kim; Jang Dae San Jose CA US - System and method are provided for transferring electrical energy among multiple electrical energy storage devices via a differential power bus and a capacitive load switched-mode power supply. The switched-mode power supply transfers the electrical energy between the load capacitor and the differential power bus to which the electrical energy storage devices (e.g., rechargeable batteries and/or capacitors connected in parallel or series or combinations of both) are electrically connected via bus switches. As a result, electrical energy is efficiently transferred and distributed among the electrical energy storage devices. | 2013-01-17 |
| 20130015821 | SYSTEM AND METHOD FOR BALANCING ELECTRICAL ENERGY STORAGE DEVICES VIA DIFFERENTIAL POWER BUS AND CAPACITIVE LOAD SWITCHED-MODE POWER SUPPLY - System and method are provided for transferring electrical energy among multiple electrical energy storage devices via multiple differential power buses and capacitive load switched-mode power supplies. The switched-mode power supplies transfer the electrical energy between the load capacitors and the differential power buses to which the electrical energy storage devices (e.g., rechargeable batteries and/or capacitors connected in parallel or series or combinations of both) are electrically connected via bus switches. As a result, electrical energy is efficiently transferred and distributed among the electrical energy storage devices. | 2013-01-17 |
| 20130015822 | Multi-Purpose Power Management Apparatus, Power Path Control Circuit and Control Method ThereforAANM Kung; Nien-HuiAACI Hsinchu CityAACO TWAAGP Kung; Nien-Hui Hsinchu City TW - The present invention discloses a multi-purpose power management apparatus, a power path control circuit, and a control method therefor. The multi-purpose power management apparatus controls power conversion between an input power and an output power and charging operation from the output power to a battery. The multi-purpose power management apparatus includes: a switch circuit including at least one power transistor; a switch control circuit generating a PWM signal to control the power transistor, for controlling the power conversion between the input power and the output power; a charging management circuit for controlling the charging operation from the output power to the battery; and a path selection circuit for determining whether the charging operation is controlled by the charging management circuit. | 2013-01-17 |
| 20130015823 | Charge Rate Modulation of Metal-Air Cells as a Function of Ambient Oxygen Concentration - A method for charging a metal-air battery pack at the maximum possible rate while maintaining an ambient oxygen concentration below a preset concentration is provided, thereby minimizing the risks associated with generating oxygen during the charging cycle. | 2013-01-17 |
| 20130015824 | DETECTING AND SWITCHING BATTERY POLARITY IN A BATTERY CHARGER - Disclosed herein, among other things, are apparatus and methods for detecting and switching battery polarity in a battery charger. In various embodiments, a method includes grounding a first terminal of a battery inserted in a charger and sensing a bipolar voltage from a second terminal of the battery. The bipolar voltage is converted to a reduced unipolar voltage for sensing by an input to a microcontroller. A low resistance analog switch connects the battery to a charging circuit. The switch state of the analog switch is controlled using an output of the microcontroller, to present the proper battery polarity to the charging circuit based on the unipolar voltage. The battery is charged using the charging circuit, in various embodiments. | 2013-01-17 |
| 20130015825 | FLYWHEEL APPARATUSAANM Pullen; KeithAACI LondonAACO GBAAGP Pullen; Keith London GB - The present invention provides a flywheel apparatus for use as an energy storage system, the apparatus comprising: a housing unit having a base; a flywheel assembly mounted within the housing unit, the assembly comprising a flywheel supported by a rotatable axle arranged to enable rotation of the assembly within the housing, the axle defining an axis of rotation; stabilising means located within the housing unit arranged to stabilise rotation of the flywheel assembly about the rotation axis; and levitation means arranged to levitate the flywheel assembly above the base of the housing unit, in order to create a clearance between the flywheel assembly and the base of the housing unit. | 2013-01-17 |
| 20130015826 | Permanent magnet multipole alternator for electrical energy generation systemsAANM Imoli; DanteAACI MontebellunaAACO ITAAGP Imoli; Dante Montebelluna IT - A permanent magnet multipole alternator includes an external rotor mechanically connectable to a source of variable velocity and having permanent magnets, an internal stator having windings housed in slots defined by equidistant teeth terminating in projecting extension pieces, a circuit converting the alternating current generated by the alternator into substantially direct current, and a circuit controlling the rotational speed of the energy source based on load. The conversion circuit has a bridge rectifier circuit, the permanent magnets of the rotor are of approximately trapezoidal shape, the distance between the magnets and the extension pieces of the stator teeth is between 0.8 and 1.8 mm, the ratio between the lengths of the major and minor bases of each magnet is between 1.2 and 6, and the ratio between the length of each extension piece of the stator teeth and the distance between the magnets, is between 0.5 and 2. | 2013-01-17 |
| 20130015827 | POWER MANAGEMENT CIRCUIT AND METHODAANM SHI; JustinAACI Ann ArborAAST MIAACO USAAGP SHI; Justin Ann Arbor MI US - A power management circuit and method are described. In the method, whether a first voltage and/or a voltage source are present is determined. Based on a first result of the determination, the first voltage is converted to a second voltage. A boost converter is used to convert the second voltage to a third voltage, Alternatively, based on a second result of the determination, a buck converter is used to convert the third voltage to the second voltage. | 2013-01-17 |
| 20130015828 | LOW POWER LOW-DROPOUT LINEAR VOLTAGE REGULATORAANM AMIR; EranAACI Givat AdaAACO ILAAGP AMIR; Eran Givat Ada IL - An integrated circuit, including: a low dropout regulator configured to output regulated power to a device that can be in standard mode drawing power from the regulator or in idle mode during which it substantially does not draw power from the regulator; a capacitor in parallel to the regulator's output configured to be charged when the regulator is enabled and to provide power instead of the regulator when the regulator is disabled; a control configured to disable and enable the regulator; wherein the control is configured to disable the regulator when the device is in idle mode and enable the regulator when the device is in standard mode; and wherein during idle mode the control enables the regulator at various times to prevent the charge of the capacitor from decreasing more than a pre-selected amount. | 2013-01-17 |
| 20130015829 | Synchronization of hysteretic power convertersAANM Menegoli; PaoloAACI San JoseAAST CAAACO USAAGP Menegoli; Paolo San Jose CA USAANM Marino; Fabio AlessioAACI San JoseAAST CAAACO USAAGP Marino; Fabio Alessio San Jose CA US - A novel method to synchronize the switching frequency of hysteretic power converters is presented. The method includes the generation of a clock signal and the injection of a periodic disturbance signal operating at the frequency of the generated clock in the main loop of the converter to synchronize the hysteretic power converter to switch at the frequency of the clock. | 2013-01-17 |
| 20130015830 | Switching Power Supply Having Separate AC And DC Current Sensing PathsAANM Zhang; JindongAACI FremontAAST CAAACO USAAGP Zhang; Jindong Fremont CA US - In a current mode controlled switching power supply, current through the inductor is sensed to determine when to turn off or on the switching transistors. The inductor current has a higher frequency AC component and a lower frequency DC component. The AC current feedback path, sensing the ramping ripple current, is separate from the DC current path, sensing the lower frequency average current. Separating the current sensing paths allows the signal to noise ratio of the AC sense signal to be increased and allows the switching noise to be filtered from the DC sense signal. The gain of the DC sense signal is adjusted so that the DC sense signal has the proper proportion to the AC sense signal. The AC sense signal and the DC sense signal are combined by a summing circuit. The composite sense signal is applied to a PWM comparator to control the duty cycle of the switch. | 2013-01-17 |
| 20130015831 | VOLTAGE REGULATION IN CHARGE PUMPSAANM WONG; Yanyi L.AACI BellevueAAST WAAACO USAAGP WONG; Yanyi L. Bellevue WA USAANM Sutandi; AgustinusAACI IssaquahAAST WAAACO USAAGP Sutandi; Agustinus Issaquah WA US - Voltage regulation in charge pumps. A high voltage generation system includes a charge pump having an output voltage node and a regulated input voltage node. The high voltage generation system also includes a voltage regulator. The voltage regulator includes a capacitive attenuator in electrical communication with the output voltage node. The voltage regulator also includes a comparator in electrical communication with the capacitive attenuator and with a reference voltage source. The voltage regulator further includes a buffer in electrical communication between the comparator and the regulated input voltage node. | 2013-01-17 |
| 20130015832 | VOLTAGE REGULATOR AND MEMORY DEVICE INCLUDING THE SAMEAANM YOON; Gil WonAACI Hwaseong-siAACO KRAAGP YOON; Gil Won Hwaseong-si KRAANM JUNG; Dong IlAACI Hwaseong-siAACO KRAAGP JUNG; Dong Il Hwaseong-si KR - A voltage regulator and a memory device including same are provided. The voltage provider includes a resistive circuit configured to output at least one divided voltage; at least one driver circuit configured to be connected to the resistive circuit and to set the at least one divided voltage; and a compensation circuit configured to be connected to the at least one driver circuit, to receive a predetermined voltage, and to apply a power supply voltage to the at least one driver circuit. The at least one driver circuit may set the at least one divided voltage based on the power supply voltage received from the compensation circuit. | 2013-01-17 |
| 20130015833 | AUTOMATIC POWER CONVERTER BYPASSAANM George; Mark StevenAACI WilsonvilleAAST ORAACO USAAGP George; Mark Steven Wilsonville OR USAANM Bernards; Charles LawrenceAACI Lake OswegoAAST ORAACO USAAGP Bernards; Charles Lawrence Lake Oswego OR US - A power converter includes a bypass circuit connected in parallel with a power stage of the power converter. The bypass circuit provides a lower loss current path in parallel with the power stage when an input voltage of the power converter exceeds a predetermined threshold. The power converter may be a boost power converter used in a vehicle to provide power from a main power bus of the vehicle to a subsystem of the vehicle such as an anti-lock brake system. | 2013-01-17 |
| 20130015834 | SYSTEM AND METHOD FOR POWER TRIMMING A BANDGAP CIRCUITAANM GLIBBERY; AdamAACI HantsAACO GBAAGP GLIBBERY; Adam Hants GB - Techniques to perform bandgap circuit trimming that maximize the operating range and minimize the trimming time at which the bandgap will be accurate. A bandgap circuit output voltage may be trimmed by heating the circuit, supplying increasing input power to the bandgap circuit, and adjusting operational parameters of the bandgap circuit to generate a constant bandgap circuit output voltage. When the bandgap circuit output voltage may remain constant, a constant input power may be applied to the bandgap circuit and its output voltage may be adjusted to a predetermined voltage level. | 2013-01-17 |
| 20130015835 | RIPPLE FREE BAND-GAP VOLTAGE GENERATOR IMPLEMENTING A CHOPPING TECHNIQUE AND RELATIVE METHODAANM CORRADI; StefanoAACI SiracusaAACO ITAAGP CORRADI; Stefano Siracusa ITAANM CRISTAUDO; DomenicoAACI Tremestieri EtneoAACO ITAAGP CRISTAUDO; Domenico Tremestieri Etneo ITAANM BATTAGLIA; DanieleAACI San Gregorio di Catania (CT)AACO ITAAGP BATTAGLIA; Daniele San Gregorio di Catania (CT) IT - A band-gap reference voltage generator for generating a stable band-gap reference voltage including a chopped band-gap circuit, a first sample and hold circuit coupled to the chopped band-gap circuit, a second sample and hold circuit coupled to the chopped band-gap circuit, and an output circuit coupled to the first and second sample and hold circuits for generating the stable band-gap reference voltage. | 2013-01-17 |
| 20130015836 | LOW NOISE STEP-DOWN CONVERTER AND LOW NOISE VOLTAGE SUPPLY ASSEMBLYAANM Chang; Chiu-HsienAACI New Taipei CityAACO TWAAGP Chang; Chiu-Hsien New Taipei City TWAANM Wu; Ming-FengAACI New Taipei CityAACO TWAAGP Wu; Ming-Feng New Taipei City TWAANM Cheng; Nai-ShuoAACI New Taipei CityAACO TWAAGP Cheng; Nai-Shuo New Taipei City TWAANM Chen; Yen-TingAACI New Taipei CityAACO TWAAGP Chen; Yen-Ting New Taipei City TW - A low noise step-down converter includes a rectified voltage output, a pulse generator, a rectifying diode, a rectifying inductor, a rectifying capacitor, and an impedance element. The rectified voltage output is provided for outputting a converted voltage. The pulse generator includes a pulse wave output. The pulse generator receives an input voltage and outputs a pulse wave through the pulse wave output. The rectifying diode is reversely coupled to the pulse wave output. One end of the rectifying inductor is connected to the pulse wave output for receiving the pulse wave while the other is connected to the rectified voltage output. One end of the rectifying capacitor is connected to the rectified voltage output, and the other end is electrically grounded. The impedance element at least provides resistance impedance and inductance impedance, wherein the rectifying diode and the impedance element are connected in series and are electrically grounded. | 2013-01-17 |
| 20130015837 | ON-CHIP SIGNAL WAVEFORM MEASUREMENT CIRCUITAANM Jenkins; Keith A.AACI Sleepy HollowAAST NYAACO USAAGP Jenkins; Keith A. Sleepy Hollow NY USAANM Wang; Peter Z.AACI Yorktown HeightsAAST NYAACO USAAGP Wang; Peter Z. Yorktown Heights NY US - Methods and apparatus are provided for on-chip signal waveform measurement. An integrated circuit is provided that comprises an on-chip comparator for comparing a voltage level of a signal to be measured to a voltage level of a reference voltage, at a time determined by at least one edge of an evaluation clock. The reference voltage can be varied to obtain a plurality of voltage points. The evaluation clock can be varied to obtain a plurality of time sampling points. In addition, the reference voltage and the evaluation clock can both be varied to obtain a plurality of voltage-time sampling points constituting a waveform corresponding to the signal to be measured. | 2013-01-17 |
| 20130015838 | DOCUMENT SIZE DETECTING DEVICE AND MULTI-FUNCTION PERIPHERALAANM Liao; Hung-WeiAACI New Taipei CityAACO TWAAGP Liao; Hung-Wei New Taipei City TW - A document size detecting device and multi-function peripheral are provided. The multi-function peripheral includes a body, a tray and a document size detecting device. The tray is disposed on the body, and the document size detecting device is disposed on the tray. The document size detecting device includes a size adjusting unit, a pressing element, a circuit board and a film. The size adjusting unit is disposed on the tray and the pressing element is disposed on the size adjusting unit. The circuit board is disposed on the tray and by the size adjusting unit. The circuit board has first pads and the film disposed on the circuit board has second pads corresponding to the first pads. The pressing element presses on the film, such that the second pad under the pressing element contacts one of the first pads to generate a detecting signal transmitting to the body. | 2013-01-17 |
| 20130015839 | INTEGRATED CURRENT SENSORAANM FRANKE; JoergAACI FreiburgAACO DEAAGP FRANKE; Joerg Freiburg DE - An integrated current sensor is provided, having a semiconductor body arranged on a metal substrate, having a first surface with a passivation layer embodied on the first surface and a magnetic field concentrator embodied in a flat manner under the semiconductor body, a first Hall-effect sensor embodied under the passivation layer in the semiconductor body, a second Hall-effect sensor embodied under the passivation layer in the semiconductor body, wherein a first conductor is provided embodied on the first surface between the first Hall-effect sensor and the second Hall-effect sensor, and the magnetic field concentrator is embodied under the first Hall-effect sensor and under the second Hall-effect sensor and under the first conductor. | 2013-01-17 |
| 20130015840 | Method for Obtaining Field Strength Information - A method includes generating an input voltage for an operational amplifier from a received electromagnetic signal in a receiver unit by an input resistance and generating an output voltage by the operational amplifier by a fixed amplification factor. The input voltage is changed until the output voltage lies within a predefined interval that includes the value of the reference voltage. The input voltage is tapped at a divider node of a voltage divider. The gate voltage of the MOS transistor, operating within a nonlinear range and connected to the divider node, is changed to adjust the output voltage to the reference voltage such that a forward resistance of the transistor is changed nonlinearly. A field strength value received by the receiver unit is determined from a comparison of the value of the present gate voltage with quantities assigned to stored gate voltage values. | 2013-01-17 |
| 20130015841 | CONNECTION SYSTEM FOR SENSOR DEVICEAANM Caprio; MatthewAACI SeattleAAST WAAACO USAAGP Caprio; Matthew Seattle WA USAANM McMorrow; Gerald J.AACI RedmondAAST WAAACO USAAGP McMorrow; Gerald J. Redmond WA USAANM Clay; AndrewAACI EverettAAST WAAACO USAAGP Clay; Andrew Everett WA USAANM Ivanova; Ekaterina FilipovaAACI KirklandAAST WAAACO USAAGP Ivanova; Ekaterina Filipova Kirkland WA USAANM Valenzuela; AntonioAACI EverettAAST WAAACO USAAGP Valenzuela; Antonio Everett WA USAANM Beasley; VanessaAACI ClaytonAAST NCAACO USAAGP Beasley; Vanessa Clayton NC US - A system for connecting remote equipment to a sensor device having a connector coupled to at least two terminals located on different portions of the sensor device. The portions of the sensor device may be an anterior portion and a posterior portion with each having at least one terminal. In turn, the terminals are nested on top of one another and at least one terminal is electrically accessible through a window region of the other portion. Further, the terminals are alignable with each other and with a connector by alignment indicators, which may provide a visual alignment indication for the terminals as well as a mechanical alignment of the connector with the sensor device. | 2013-01-17 |
| 20130015842 | CURRENT DETECTION APPARATUSAANM Kawaguchi; YasunoriAACI Shimada-shiAACO JPAAGP Kawaguchi; Yasunori Shimada-shi JP - A current detection apparatus includes two magnetic detectors that are arranged oppositely on a front surface and a back surface of a board which is located above a current path in order to detect a strength of a magnetic field, an electromagnetic shielding frame member that is mounted on the current path so that the two magnetic detectors and a part of the current path are accommodated inside the electromagnetic shielding frame member, and a control circuit that determines whether a failure which occurs in either of the two magnetic detectors from a difference between magnetic fields detected by the two magnetic detectors, respectively. Sensitivities of the two magnetic detectors are made adjusted so that current values outputted from the two magnetic detectors depending on detected magnetic fields are identical to each other in a normal state. | 2013-01-17 |
| 20130015843 | CURRENT SENSOR WITH CALIBRATION FOR A CURRENT DIVIDER CONFIGURATIONAANM Doogue; Michael C.AACI ManchesterAAST NHAACO USAAGP Doogue; Michael C. Manchester NH USAANM Milano; Shaun D.AACI ConcordAAST NHAACO USAAGP Milano; Shaun D. Concord NH US - An integrated circuit (IC) current sensor that self-calibrates to adjust its signal gain when employed in a current divider configuration is presented. The current sensor includes an integrated current conductor, a magnetic field transducer, a controllable gain stage and a calibration controller. The integrated current conductor is adapted to receive a portion of a calibration current. The calibration current corresponds to a full scale current. The magnetic field transducer, responsive to the calibration current portion, provides a magnetic field signal having a magnitude proportional to a magnetic field generated by the calibration current portion. The controllable gain stage is configured to amplify the magnetic field signal with an adjustable gain to provide an amplified magnetic field signal. The calibration controller is responsive to a calibration command signal to adjust the adjustable gain of the controllable gain stage to a calibrated gain in order to provide the amplified magnetic field signal at a predetermined voltage level that corresponds to a desired current sensor output signal voltage level if the full scale current were received by the integrated current conductor. | 2013-01-17 |
| 20130015844 | HIGH-RESOLUTION NON-CONTACTING MULTI-TURN SENSING SYSTEMS AND METHODS - Disclosed are systems and methods for measuring multi-turn position of a shaft with high resolution and in a non-contact manner. In some embodiments, a multi-turn sensing apparatus can include a rotation counter configured to determine a number of turns made by a shaft, and an angular position sensor configured to measure an angular position of the shaft within a given turn. The number of turns can be determined with an M-bit resolution, and the angular position per turn can be measured with an N-bit resolution. Selected appropriately, the rotation counter can be configured to operate as a relatively low resolution; and yet the multi-turn sensing apparatus can maintain the N-bit per-turn angular resolution throughout the full range. Accordingly, the multi-turn sensing apparatus can have an effective resolution of M+N bits. | 2013-01-17 |
| 20130015845 | ABSOLUTE ANGULAR POSITION SENSOR USING TWO MAGNETORESISTIVE SENSORSAANM Fox; JoshuaAACI FreeportAAST ILAACO USAAGP Fox; Joshua Freeport IL US - In one example, a rotary position sensor is provided. The rotary position sensor comprises an integrated circuit, a first magnetic field angular position sensor, and a second magnetic field angular position sensor. The first magnetic field angular position sensor provides at least a first signal to the integrated circuit and the second magnetic field angular position sensor provides at least a second signal to the integrated circuit. The integrated circuit is configured to provide an output signal indicative of an angular position of a magnetic field, wherein the output signal is based at least on the first signal and the second signal, and wherein the output signal has an angular range of approximately 360 degrees. | 2013-01-17 |
| 20130015846 | MAGNETIC ROTARY ENCODERAANM Mehnert; WalterAACI OttobrunnAACO DEAAGP Mehnert; Walter Ottobrunn DEAANM Theil; ThomasAACI FeldafingAACO DEAAGP Theil; Thomas Feldafing DE - A magnetic rotary encoder for the fine resolution of the rotational angle of a shaft ( | 2013-01-17 |
| 20130015847 | MAGNETIC FIELD SENSOR AND METHOD FOR DETERMINING AND CORRECTING AN OFFSET VOLTAGE OF A MAGNETIC FIELD SENSOR - A magnetic field sensor having a Hall sensor with a first terminal contact and with a second terminal contact and with a third terminal contact and with a fourth terminal contact and with a fifth terminal contact, whereby a first switch with a control input is provided between the first terminal contact and the fifth terminal contact, and the first switch connects or disconnects the first terminal contact to/from the fifth terminal contact, and a control unit is provided and the control unit is connected to the control input of the first switch. | 2013-01-17 |
| 20130015848 | FIELD GENERATOR PATCH WITH DISTORTION CANCELLATIONAANM Govari; AssafAACI HaifaAACO ILAAGP Govari; Assaf Haifa ILAANM Altmann; Andres ClaudioAACI HaifaAACO ILAAGP Altmann; Andres Claudio Haifa ILAANM Ephrath; YaronAACI KarkurAACO ILAAGP Ephrath; Yaron Karkur IL - A magnetic field generator includes a substrate, a main generator coil, at least one field sensor, at least one shim coil, a driver circuit and a correction circuit. The main generator coil, the field sensor, and the shim coil are all disposed on the substrate. The driver circuit is coupled to drive the main generator coil with a driving current at a selected frequency. The correction circuit is coupled to receive a signal at the selected frequency from the at least one field sensor and, in response to deviations in the signal from a predefined baseline, to drive the at least one shim coil with a driving current having an amplitude configured to return the signal to the baseline. | 2013-01-17 |
| 20130015849 | DEVICE FOR DETERMINING THE WEAR OF A CARBON CERAMIC BRAKE DISKAANM BRANDESTINI; MarcoAACI LachenAACO CHAAGP BRANDESTINI; Marco Lachen CHAANM STIERLI; PeterAACI UerikonAACO CHAAGP STIERLI; Peter Uerikon CH - Device for determining wear in a carbon ceramic brake disk. The device includes a coil arrangement having at least one coil structured and arranged to generate a magnetic field in the brake disk and to detect an eddy current in the brake disk, and an arcuate measuring area. | 2013-01-17 |
| 20130015850 | Die-Sized Atomic Magnetometer and Method of Forming the MagnetometerAANM Lindorfer; PhilippAACI San JoseAAST CAAACO USAAGP Lindorfer; Philipp San Jose CA USAANM Hopper; Peter J.AACI San JoseAAST CAAACO USAAGP Hopper; Peter J. San Jose CA USAANM French; WilliamAACI San JoseAAST CAAACO USAAGP French; William San Jose CA USAANM Mawson; PaulAACI Los GatosAAST CAAACO USAAGP Mawson; Paul Los Gatos CA USAANM Hunt; StevenAACI San JoseAAST CAAACO USAAGP Hunt; Steven San Jose CA USAANM Parsa; RoozbehAACI San JoseAAST CAAACO USAAGP Parsa; Roozbeh San Jose CA US - The cost and size of an atomic magnetometer are reduced by attaching together a first die which integrates together a vapor cell, top and side photo detectors, and processing electronics, a second die which integrates together an optics package and a heater for the vapor cell, and a third die which integrates together a VCSEL, a heater for the VCSEL, and control electronics. | 2013-01-17 |
| 20130015851 | Sensor with Concurrent Autosensing of Output Mode and Manual Selection - A switching sensor may automatically configure itself to a sinking or a sourcing mode by monitoring the voltage of its switched output to determine a loading configuration associated with each of these operating modes. The auto detection may occur not only at start up but also during operation of the sensor by monitoring the output voltage or current in coordination with knowledge about the intended state of the output by the sensor. A manual selection of the operating mode and override of the autodetect feature may be provided for cases when multiple sensors are connected in parallel. | 2013-01-17 |
| 20130015852 | MAGNETOMETER - The present invention refers to a magnetometer ( | 2013-01-17 |
| 20130015853 | HALL SENSOR - A Hall sensor is provided having a first Hall element with a first terminal contact and with a second terminal contact and with a third terminal contact, a second Hall element with a fourth terminal contact and with a fifth terminal contact and with a sixth terminal contact, a third Hall element with a seventh terminal contact and with an eighth terminal contact and with a ninth terminal contact, and a fourth Hall element with a tenth terminal contact and with an eleventh terminal contact and with a twelfth terminal contact. The first Hall element and the second Hall element and the third Hall element and the fourth Hall element are connectable in series. | 2013-01-17 |
| 20130015854 | METHOD AND PROCESSOR AND MAGNETIC RESONANCE APPARATUS FOR DESIGNING RF PULSES TO MITIGATE OFF-RESONANCE EFFECTSAANM Adalsteinsson; ElfarAACI BelmonttAAST MAAACO USAAGP Adalsteinsson; Elfar Belmontt MA USAANM Fautz; Hans-PeterAACI ForchheimAACO DEAAGP Fautz; Hans-Peter Forchheim DEAANM Setsompop; KawinAACI CharlestownAAST MAAACO USAAGP Setsompop; Kawin Charlestown MA USAANM Wald; LawrenceAACI CambridgeAAST MAAACO USAAGP Wald; Lawrence Cambridge MA US - In a magnetic resonance apparatus and operating method therefor, and in a processor that is programmed to design RF pulses for operating such a magnetic resonance apparatus, the RF pulses are designed to mitigate off-resonance effects caused by inhomogeneity of the basic (B0) magnetic field in the magnetic resonance apparatus. The RF pulses of a parallel transmit array are designed with different spatial phase distributions, that deviate from a constant phase from pulse-to-pulse, with the absolute value of the difference between respective spatial phase distributions of any two successively radiated RF pulses corresponding to the off-resonance that is caused by B0-inhomogeneity during the time between the radiation of the successive pulses. Additionally, or separately, currents supplied to the shim coils can be taken into account in the design of the RF pulses as an additional degree of freedom, with the shimming of the basic magnetic field produced by the shim currents deviating from shim currents designed to ideally produce a homogenous B0 field. | 2013-01-17 |
| 20130015855 | MAGNETIC RESONANCE IMAGING APPARATUS AND MAGNETIC RESONANCE IMAGING METHOD - According to one embodiment, a magnetic resonance imaging apparatus includes an imaging unit and a strain correction unit. The imaging unit is configured to acquire frames of diffusion weighted image data corresponding to different b-values by diffusion weighted imaging with applying MPG pulses corresponding to the different b-values of which application axes are same. The strain correction unit is configured to calculate a strain correction coefficient for diffusion weighted image data to be a target of a strain correction based on diffusion weighted image data corresponding to a b-value different from a b-value corresponding to the diffusion weighted image data to be the target of the strain correction among the frames of the diffusion weighted image data to generate image data after the strain correction by the strain correction of the diffusion weighted image data to be the target of the strain correction using the calculated strain correction coefficient. | 2013-01-17 |
| 20130015856 | MRI MICROSCOPE ADAPTER - Disclosed embodiments pertain to an inventive method and apparatus that confers the ability to image using Magnetic Resonance Imaging (MRI) to an optical microscope. Through implementation of the disclosed embodiments, it is possible to collect spectroscopic information as well as anatomic information using the objective structure and/or MRI-enabled stage. | 2013-01-17 |
| 20130015857 | MAGNETIC RESONANCE IMAGING OF SINGLE DOMAIN NANOPARTICLES - A method and system are disclosed for gathering information about an object including single domain particles which have a diameter in the range of about 5 to 80 nm. In one aspect, a method includes generating a static magnetic field of less than about 0.1 Tesla on the object and generating an RF energy, pulsed or continuous wave, so as to generate electron paramagnetic resonance of the single domain particles. The method also includes detecting the electron paramagnetic resonance of the single domain particles in the form of an image of the object. The single domain particles may have a predetermined diameter and a predetermined saturation magnetization and the applied magnetic field may be such that the single domain particles reach a magnetization being at least about 10% of the saturation magnetization. The method may be used for detecting tags in an object and for activating tags. | 2013-01-17 |
| 20130015858 | LINEAR RESONATOR OF A HIGH-FREQUENCY ANTENNA FOR A NUCLEAR MAGNETIC RESONANCE IMAGING APPARATUSAANM Ferrand; GuillaumeAACI ParisAACO FRAAGP Ferrand; Guillaume Paris FRAANM Luong; MichelAACI SceauxAACO FRAAGP Luong; Michel Sceaux FRAANM France; AlainAACI BordeauxAACO FRAAGP France; Alain Bordeaux FR - A linear resonator of a high-frequency antenna suitable for emitting a radiofrequency energisation signal and for receiving a radiofrequency relaxation signal, the linear resonator includes a radiating element to emit a radiofrequency energisation signal and receive a radiofrequency relaxation signal. The resonator also includes: a balun circuit including a power-supply line and two coupling lines; a substrate made of a dielectric material, supporting the radiating element which contains the balun circuit; two contact points connecting the balun circuit to the radiating element, the contact points being formed by one of the ends of the coupling lines extending out of the substrate, the distance separating the two contact points being selected so as to ensure the impedance matching of the resonator; and a chip floorplan separating the coupling lines from the radiating element. | 2013-01-17 |
| 20130015859 | TESTING APPARATUS FOR LIGHT EMITTING DIODESAANM Tseng; I-ShihAACI Taoyuan HsienAACO TWAAGP Tseng; I-Shih Taoyuan Hsien TWAANM Chang; Tien-TengAACI Taoyuan HsienAACO TWAAGP Chang; Tien-Teng Taoyuan Hsien TWAANM Lee; JeffAACI Taoyuan HsienAACO TWAAGP Lee; Jeff Taoyuan Hsien TWAANM Cheng; Chih-YuAACI Taoyuan HsienAACO TWAAGP Cheng; Chih-Yu Taoyuan Hsien TWAANM Cheng; Hsu-TingAACI Taoyuan HsienAACO TWAAGP Cheng; Hsu-Ting Taoyuan Hsien TW - A testing apparatus for flip chip LEDs includes a transparent substrate, a spacing member, a flexible transparent carrier, and a vacuum generator. The spacing member is configured on a first surface of the transparent substrate. The flexible transparent carrier is removably assembled to the spacing member so that a closed space is formed by the flexible transparent carrier, the spacing member, and the first surface of the transparent substrate. The vacuum generator is connected to the closed space for pumping air out of the closed space, and then a part of the transparent substrate clings to the first surface to form a testing area for loading the flip chip LED. | 2013-01-17 |
| 20130015860 | Method And System For Determining A Target State of Charge To Charge A Battery In A Vehicle Using External Electric PowerAANM Crombez; Dale ScottAACI LivoniaAAST MIAACO USAAGP Crombez; Dale Scott Livonia MI US - A system and method is provided for determining a target state of charge (SOC) to charge a storage battery in an electric vehicle using electric power from an external power source. Charging the storage battery to the target SOC occurs prior to starting a drive cycle of the vehicle. The target SOC is determined based on a profile of regenerative braking energy expected to be recovered and a profile of energy expected to be used from the battery during a portion of a future drive cycle. | 2013-01-17 |
| 20130015861 | CONVERTER CIRCUIT AND METHOD OF DRIVING THE SAMEAANM CHOE; ANDREW KUNILAACI SeoulAACO KRAAGP CHOE; ANDREW KUNIL Seoul KR - Provided are a converter circuit and a method of driving the same. The converter circuit includes: an input unit receiving a conversion target signal; a detection unit receiving a conversion target signal for each interval from the input unit, sampling the conversion target signal for each interval according to a plurality of timings to calculate an average value for each interval, and outputting a comparison unit input signal by using the average value for each interval; and a comparison unit comparing the comparison unit input signal with a predetermined reference signal to output a comparison result value. | 2013-01-17 |
| 20130015862 | ROTATION ANGLE SENSORAANM Ludwig; RonnyAACI ReutlingenAACO DEAAGP Ludwig; Ronny Reutlingen DE - A rotation angle sensor which has at least one capacitor having capacitor plates and a dielectric designed as a disk. The disk is situated between the capacitor plates, and fills out differently sized surface portions between the capacitor plates, depending on the rotation angle. The rotation angle sensor is designed to determine the rotation angle as a function of a measured value of the capacitance of the at least one capacitor. | 2013-01-17 |
| 20130015863 | COMBINED SEAT HEATER AND CAPACITIVE OCCUPANCY SENSORAANM Lamesch; LaurentAACI LamadelaineAACO LUAAGP Lamesch; Laurent Lamadelaine LUAANM Schoos; AloyseAACI BertrangeAACO LUAAGP Schoos; Aloyse Bertrange LU - A combined seat heater and capacitive occupancy sensor comprises a heating element ( | 2013-01-17 |
| 20130015864 | METHOD AND APPARATUS FOR DETERMINING A FRACTION OF AN ADSORBED MATERIAL CONTAINED IN AN ADSORBER MATERIALAANM Lopatin; SergejAACI LorrachAACO DEAAGP Lopatin; Sergej Lorrach DEAANM Uehlin; ThomasAACI SchopfheimAACO DEAAGP Uehlin; Thomas Schopfheim DE - A method for determining a fraction of an adsorbed material contained in a formed body serving as an adsorber material. For the case in which the adsorber material is present in the form of a formed body, at least two electrodes are arranged, spaced apart from one another, on a surface of the formed body and/or are firmly inserted in the formed body; that, for the case, in which the adsorber material is present in the form of a powder or granulate, a corresponding formed body made of the same material is durably inserted in the powder or granular material. The electrodes are supplied with an alternating electrical current, whereby an electrical characteristic variable is ascertained; and, based on the characteristic variable, degree of saturation of the adsorber material is ascertained. Furthermore, a corresponding apparatus is claimed. | 2013-01-17 |
| 20130015865 | CAPACITANCE-TYPE DETECTING DEVICEAANM Izumi; HiroshiAACI Miyagi-kenAACO JPAAGP Izumi; Hiroshi Miyagi-ken JP - A capacitance-type detecting device according to an embodiment of the invention includes a plurality of detecting electrodes that are provided on a sensor substrate such that capacitance is formed between adjacent electrodes. Capacitance formed in a corner detection region in which the detection sensitivity of the sensor substrate is relatively low is more than that formed in a central detection region in which the detection sensitivity is relatively high. | 2013-01-17 |
| 20130015866 | Capacitive occupant detection system with interference detectionAANM Wendt; ChristophAACI MettendorfAACO DEAAGP Wendt; Christoph Mettendorf DEAANM Khan; DarrenAACI Rochester HillsAAST MIAACO USAAGP Khan; Darren Rochester Hills MI USAANM Puetz; MichaelAACI TrierAACO DEAAGP Puetz; Michael Trier DEAANM Tonteling; MarcAACI LuxembourgAACO LUAAGP Tonteling; Marc Luxembourg LUAANM Favalli; GianlucaAACI HautcharageAACO LUAAGP Favalli; Gianluca Hautcharage LU - A capacitive occupant detection system ( | 2013-01-17 |
| 20130015867 | TOUCH SENSING METHOD AND APPARATUSAANM Aras; SualpAACI DallasAAST TXAACO USAAGP Aras; Sualp Dallas TX USAANM Nihei; TatsuyukiAACI TokyoAACO JPAAGP Nihei; Tatsuyuki Tokyo JPAANM Rahman; AbidurAACI AllenAAST TXAACO USAAGP Rahman; Abidur Allen TX US - A method for measuring for generating a touch capacitance measurement is provided. Gain and offset control signals are generated, where the gain and offset control signals are adjusted to compensate for base capacitance of a touch sensor. The gain control signal is applied to a touch sensor during a first phase of a clock signal, and the offset control signal is applied to an output circuit during a second phase of the clock signal. The output circuit is coupled to the touch sensor during the second phase of the clock signal. The touch capacitance measurement is generated by compensating for the base capacitance with the gain and offset control signals, and a gain is applied to the touch capacitance measurement. | 2013-01-17 |
| 20130015868 | CAPACITANCE SENSING CIRCUITS, METHODS AND SYSTEMS HAVING GROUND INSERTION ELECTRODES - A capacitance sensing system can include a plurality of transmit (TX) electrodes disposed in a first direction; a plurality of first electrodes disposed in a second direction and coupled to the TX electrodes by a mutual capacitance, and coupled to a capacitance sense circuit when at least one TX electrode receives a transmit signal; and a plurality of second electrodes structures, interspersed with the first electrodes and coupled to a ground node at least while the one TX electrode receives the transmit signal. | 2013-01-17 |
| 20130015869 | TEMPERATURE MEASUREMENT OF ACTIVE DEVICE UNDER TEST ON STRIP TESTERAANM Francisco; RonaldoAACI ChandlerAAST AZAACO USAAGP Francisco; Ronaldo Chandler AZ USAANM Wong; Chi LungAACI GilbertAAST AZAACO USAAGP Wong; Chi Lung Gilbert AZ USAANM Messang; TimAACI GilbertAAST AZAACO USAAGP Messang; Tim Gilbert AZ USAANM Aberra; Ezana HaileAACI ChandlerAAST AZAACO USAAGP Aberra; Ezana Haile Chandler AZ US - A plurality of devices under test (DUT) are arranged in a strip tester having a temperature controlled heater block. Each DUT has a respective set of electrical test probes and a thermally conductive test probe for electrically and thermally coupling, respectively, of the strip tester to the DUTs. Temperature measurement of each of the plurality of DUTs is performed by a temperature measuring device. The temperature measuring device can be part of the test board of the strip tester and will be in thermal communications with the DUT through the thermally conductive test probe, or temperature of the DUT can be measurement with an RTD embedded in the thermally conductive test probe, thereby providing faster thermal response time. | 2013-01-17 |
| 20130015870 | TEST SYSTEM WITH CONTACT TEST PROBESAANM Nickel; Joshua G.AACI San JoseAAST CAAACO USAAGP Nickel; Joshua G. San Jose CA USAANM Pascolini; MattiaAACI San MateoAAST CAAACO USAAGP Pascolini; Mattia San Mateo CA USAANM Syed; AdilAACI Santa ClaraAAST CAAACO USAAGP Syed; Adil Santa Clara CA US - Electronic device structures such as structures containing antennas, cables, connectors, welds, electronic device components, conductive housing structures, and other structures can be tested for faults using a test system to perform conducted testing. The test system may include a vector network analyzer or other test unit that generates radio-frequency test signals in a range of frequencies. The radio-frequency test signals may be transmitted to electronic device structures under test using a contact test probe that has at least signal and ground pins. The test probe may receive corresponding radio-frequency signals. The transmitted and received radio-frequency test signals may be analyzed to determine whether the electronic device structures under test contain a fault. | 2013-01-17 |
| 20130015871 | SYSTEMS, DEVICES, AND METHODS FOR TWO-SIDED TESTING OF ELECTRONIC DEVICES - Systems, devices, and methods for two-sided testing of electronic devices. These systems, devices, and methods may include the use of a test fixture that is configured to electrically connect a back side electrical pad of a device under test with an auxiliary pad that faces in a different direction than the back side electrical pad. Additionally or alternatively, these systems, devices, and methods also may include the use of a probe head that is configured to form an electrical connection with both the auxiliary pad and a front side electrical pad of the device under test. The systems, devices, and methods also may include providing a test signal to the device under test, receiving a resultant signal from the device under test, and/or analyzing the resultant signal. | 2013-01-17 |
| 20130015872 | Test Schemes and Apparatus for Passive InterposersAANM Lee; Yun-HanAACI Baoshan TownshipAACO TWAAGP Lee; Yun-Han Baoshan Township TWAANM Wang; Mill-JerAACI Hsin-ChuAACO TWAAGP Wang; Mill-Jer Hsin-Chu TWAANM Chou; Tan-LiAACI Zhubei CityAACO TWAAGP Chou; Tan-Li Zhubei City TW - A probe card includes a plurality of probe pins, and a switch network connected to the plurality of probe pins. The switch network is configured to connect the plurality of probe pins in a first pattern, and reconnect the plurality of probe pins in a second pattern different from the first pattern. | 2013-01-17 |
| 20130015873 | CABLE ASSEMBLY, CONNECTOR AND SEMICONDUCTOR TESTERAANM Suzuki; TeruhitoAACI YamatoAACO JPAAGP Suzuki; Teruhito Yamato JPAANM Sakiyama; ShinAACI TokyoAACO JPAAGP Sakiyama; Shin Tokyo JP - In a cable assembly, when auxiliary ground conductor is provided so as to face the lower surface of supporting insulating member, elastically-deformed piece in an elastically deformed status comes in contact with the tip of ground terminal protruding from the lower surface of supporting insulating member. | 2013-01-17 |
| 20130015874 | MUT FOR TESTING MEMORY MODULESAANM Yang; Yung-ChingAACI Taoyuan CountyAACO TWAAGP Yang; Yung-Ching Taoyuan County TW - An MUT unit for testing memory modules includes a first circuit board; a second circuit board coupled to the first circuit board in a vertical orientation; a socket on a top surface of the first circuit board; and a resilient member electrically connecting the first and second circuit boards at an joint there between, wherein the resilient member comprises a horizontal segment that is welded to a bottom surface of the first circuit board, a vertical segment that is welded to a surface of the second circuit board, and a curved buffer segment connecting the horizontal segment and the vertical segment. | 2013-01-17 |
| 20130015875 | FAILURE DETECTION SYSTEM FOR PHOTOVOLTAIC ARRAYAANM Kumar; ArunAACI Ann ArborAAST MIAACO USAAGP Kumar; Arun Ann Arbor MI US - A process for detecting and terminating a fault in a photovoltaic device is provided that operates in the millisecond or faster timescale. A process includes measuring a current or voltage in each of a plurality of strings relative to a common rail. When the voltage or current from a string is outside a predetermined threshold, a flag is generated indicating the presence of a fault in the string. A control unit will detect the flag and disconnect the faulty string from the system through a switch. The use of continuously rolling averages of baseline currents and voltages as well as a series of measurements averaged to measure the difference of current or voltage at each step provides a process and a fault detection system that does not suffer from false fault detections thereby providing a reliable and efficient system for detecting and terminating faults in photovoltaic devices. | 2013-01-17 |
| 20130015876 | APPARATUS AND METHOD FOR MEASURING DEGRADATION OF CMOS VLSI ELEMENTSAANM LAI; Fang-Shi JordanAACI Chia YiAACO TWAAGP LAI; Fang-Shi Jordan Chia Yi TWAANM LU; Chih-ChengAACI Tainan CityAACO TWAAGP LU; Chih-Cheng Tainan City TWAANM LIN; Yung-FuAACI Hsinchu CityAACO TWAAGP LIN; Yung-Fu Hsinchu City TWAANM HSUEH; Hsu-FengAACI Tainan CityAACO TWAAGP HSUEH; Hsu-Feng Tainan City TWAANM CHANG; Chin-HaoAACI Hsinchu CityAACO TWAAGP CHANG; Chin-Hao Hsinchu City TWAANM WENG; Cheng YenAACI Hsinchu CityAACO TWAAGP WENG; Cheng Yen Hsinchu City TWAANM MHALA; Manoj M.AACI HsinchuAACO TWAAGP MHALA; Manoj M. Hsinchu TW - The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages. | 2013-01-17 |
| 20130015877 | METHOD AND APPARATUS FOR TESTING A SEMICONDUCTOR DEVICEAANM Shao; Jhih JieAACI Toufen TownshipAACO TWAAGP Shao; Jhih Jie Toufen Township TWAANM Huang; Szu-ChiaAACI Hsinchu CityAACO TWAAGP Huang; Szu-Chia Hsinchu City TWAANM Chung; Tang-HsuanAACI Kaohsiung CityAACO TWAAGP Chung; Tang-Hsuan Kaohsiung City TWAANM Tseng; Huan ChiAACI Hsinchu CityAACO TWAAGP Tseng; Huan Chi Hsinchu City TW - The present disclosure provides a method for testing a semiconductor device. The method includes providing a testing unit and an electronic circuit coupled to the testing unit and applying a first electrical signal to the testing unit. The method includes sweeping a second electrical signal across a range of values, the second electrical signal supplying power to the electronic circuit, wherein the sweeping is performed while a value of the first electrical signal remains the same. The method includes measuring a third electrical signal during the sweeping, the measured third electrical signal having a range of values that each correspond to one of the values of the second electrical signal. The method includes adopting an optimum value of the second electrical signal that yields a minimum value of the third electrical signal. The method includes testing the testing unit while the second electrical signal is set to the optimum value. | 2013-01-17 |
| 20130015878 | POWER SYSTEM FAULT ZONE DETECTION - A system, method, and apparatus for power transmission fault zone detection. Each phase of a three-phase current in the power system is monitored, a modal component is determined from the three-phase current, high frequency transients in the modal component are extracted using wavelet packet transformation, and a travelling wave front is detected in the modal component indicating the fault. A wave sign is determined and the signs of two travelling waves are logically combined to determine whether or not the fault is within a protected zone. | 2013-01-17 |
| 20130015879 | SEMICONDUCTOR DEVICEAANM ARAKI; HiroeiAACI TokyoAACO JPAAGP ARAKI; Hiroei Tokyo JP - A device includes an output circuit including a plurality of unit buffers, each of the unit buffers having an adjustable impedance; a controller circuit operable to selectively activate at least one of the unit buffers; and an impedance adjustment part operable to adjust the impedance of each of the unit buffers in response to a change of the number of the unit buffers that are selectively activated by the controller circuit. | 2013-01-17 |
| 20130015880 | SEMICONDUCTOR DEVICE AND METHOD OF ADJUSTING AN IMPEDANCE OF AN OUTPUT BUFFERAANM HARAGUCHI; YoshinoriAACI TokyoAACO JPAAGP HARAGUCHI; Yoshinori Tokyo JP - A semiconductor device has a ZQ circuit ( | 2013-01-17 |
| 20130015881 | INTERLOCK CIRCUIT AND INTERLOCK SYSTEM INCLUDING THE SAME - An interlock circuit includes an input delay unit and an output suppressing unit. The input delay unit delays a plurality of input signals, provides a plurality of delayed input signals, and provides a plurality of exclusive input signals by performing a logical operation on the plurality of delayed input signals. The output suppressing unit provides a plurality of output signals, which are not simultaneously enabled, based on the plurality of exclusive input signals and the plurality of input signals. | 2013-01-17 |
| 20130015882 | Compact and Robust Level Shifter Layout DesignAANM Datta; AnimeshAACI San DiegoAAST CAAACO USAAGP Datta; Animesh San Diego CA USAANM Goodall, III; William JamesAACI CaryAAST NCAACO USAAGP Goodall, III; William James Cary NC US - Method and apparatus for voltage level shifters (VLS) design in bulk CMOS technology. A multi-voltage circuit or VLS that operate with different voltage levels and that provides area and power savings for multi-bit implementation of level shifter design. A two-bit VLS to shift bits from a first voltage level logic to a second voltage level logic. The VLS formed with a first N-well in a substrate. The VLS formed with a second N-well in the substrate, adjacent to a side of the first N-well. The VLS formed with a third N-well in the substrate, adjacent to a side of the first N-well and opposite the second N-well. A first one-bit VLS circuit having a portion formed on the first N-well and a portion formed on the second N-well. A second bit VLS circuit having a portion formed on the first N-well and a portion formed on the third N-well. | 2013-01-17 |
| 20130015883 | CMOS LOGIC INTEGRATED CIRCUITAANM HORI; ChikahiroAACI Kanagawa-kenAACO JPAAGP HORI; Chikahiro Kanagawa-ken JPAANM Takiba; AkiraAACI Kanagawa-kenAACO JPAAGP Takiba; Akira Kanagawa-ken JP - A CMOS logic integrated circuit includes a level shifter and a CMOS logic circuit. The level shifter converts a signal of a first logic level to a signal of a second logic level. The signal of the first logic level changes between a first low potential and a first high potential higher than the first low potential. The signal of the second logic level changes between the first low potential and a second high potential higher than the first high potential. The CMOS logic circuit includes a first N-channel type MOSFET and a second N-channel type MOSFET. The second N-channel type MOSFET is connected in series with the first N-channel type MOSFET. A first signal of the first logic level is input into a gate of the first N-channel type MOSFET. A second signal of the second logic level has an inversion relationship with the first signal. | 2013-01-17 |
| 20130015884 | SWITCHING CIRCUITS, LATCHES AND METHODS - Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching circuit may have a metastable state that is closer to a first voltage corresponding to the first binary level than it is to a second voltage corresponding to the second binary level. In other embodiments, the metastable state may be dynamically adjustable so that it is at one voltage before the circuit switches and at a different voltage after the circuit switches. As a result, the switching circuit may respond relatively quickly to the input signal transitioning from the first binary level to the second binary level. | 2013-01-17 |
| 20130015885 | QUBIT READOUT VIA RESONANT SCATTERING OF JOSEPHSON SOLITONSAANM NAAMAN; OFERAACI Ellicot CityAAST MDAACO USAAGP NAAMAN; OFER Ellicot City MD USAANM Park; Jae I.AACI BoulderAAST COAACO USAAGP Park; Jae I. Boulder CO USAANM Pesetski; Aaron A.AACI GambrillsAAST MDAACO USAAGP Pesetski; Aaron A. Gambrills MD US - Systems and methods are provided for reading an associated state of a qubit. A first soliton is injected along a first Josephson transmission line coupled to the qubit. A velocity of the first soliton is selected according to a physical length of the qubit and a characteristic frequency of the qubit. A second soliton is injected at the selected velocity along a second Josephson transmission line that is not coupled to the qubit. A delay associated with the first soliton is determined relative to the second soliton. | 2013-01-17 |
| 20130015886 | High Voltage, High temperature Semiconductor Driver for Switching Power semiconductor devicesAANM Johnson; Brant TureAACI ConcordAAST MAAACO USAAGP Johnson; Brant Ture Concord MA US - The application discloses a novel way to provide an integrated circuit driver interface between a control device and semiconductor power devices that benefit from the drivers unique ability to provide positive and negative voltages that improve the switching characteristics of the power devices. This invention's unique construction allows it to operate at high voltages and high temperature to the benefit of multiple power conversion applications. | 2013-01-17 |
| 20130015887 | DRIVE CIRCUIT WITH ADJUSTABLE DEAD TIMEAANM Piselli; MarcoAACI PaduaAACO ITAAGP Piselli; Marco Padua ITAANM Massaro; SimoneAACI VeneziaAACO ITAAGP Massaro; Simone Venezia ITAANM Lenz; MichaelAACI ZornedingAACO DEAAGP Lenz; Michael Zorneding DEAANM Puerschel; MarcoAACI MunichAACO DEAAGP Puerschel; Marco Munich DEAANM Graovac; DusanAACI MunichAACO DEAAGP Graovac; Dusan Munich DE - A drive circuit includes a first input terminal configured to receive a first input signal, a first output terminal configured to provide a first drive signal, a second output terminal configured to provide a second drive signal, and a mode selection terminal configured to have a mode selection element connected thereto. The drive circuit is configured to generate the first and second drive signals dependent on the first input signal such that there is a dead time between a time when one of the first and second drive signals assumes an off-level and a time when the other one of the first and second drive signals assumes an on-level, and evaluate at least one electrical parameter of the mode selection element and is configured to adjust a first signal range of the first drive signal and a second signal range of the second drive signal dependent on the evaluated parameter and to adjust the dead time dependent on the evaluated parameter. | 2013-01-17 |
| 20130015888 | SEMICONDUCTOR DEVICE, START-UP CIRCUIT, OPERATING METHOD FOR THE SAMEAANM Chan; Wing-ChorAACI Hsinchu CityAACO TWAAGP Chan; Wing-Chor Hsinchu City TWAANM Hu; Chih-MinAACI Kaohsiung CityAACO TWAAGP Hu; Chih-Min Kaohsiung City TWAANM Chen; Li-FanAACI Hsinchu CityAACO TWAAGP Chen; Li-Fan Hsinchu City TW - A semiconductor device, a start-up circuit, and an operating method for the same are provided. The start-up circuit comprises a semiconductor unit, a first circuit, a second circuit, a voltage input terminal and a voltage output terminal. The first circuit is constituted by one diode or a plurality of diodes electrically connected to each other in series. The second circuit is constituted by one diode or a plurality of diodes electrically connected to each other in series. The semiconductor unit is coupled to a first node between the first circuit and the second circuit. The voltage input terminal is coupled to the semiconductor unit. The voltage output terminal is coupled to a second node between the semiconductor unit and the first circuit. | 2013-01-17 |
| 20130015889 | THRESHOLD VOLTAGE BASED POWER TRANSISTOR OPERATION - A system and method for operating a power transistor. Parasitic impedances naturally present in a circuit board or other interconnect structures exhibit a parasitic impedance effective to generate a parasitic voltage signal in response to operating the power transistor. The parasitic voltage signal is monitored in order to better control the power transistor. In particular, the threshold voltage of the power transistor can be determined and used to more optimally control the power transistor. | 2013-01-17 |
| 20130015890 | METHOD AND SYSTEM FOR CALIBRATING FREQUENCYAANM CHOU; MING-HUNGAACI TAIPEI CITYAACO TWAAGP CHOU; MING-HUNG TAIPEI CITY TWAANM HSIEH; CHING-FENGAACI TAIPEI CITYAACO TWAAGP HSIEH; CHING-FENG TAIPEI CITY TW - A method for calibrating frequency, applicable to calibrating a frequency signal generated by a frequency generating unit of an apparatus at a preset frequency, includes obtaining the cycle number of the clock rate of a frequency signal based on a reference signal and a clock mask synchronous with the frequency signal; obtaining a frequency of the frequency signal based on the cycle number; correcting the frequency according to a plurality of phase shift signals generated based on the reference signal; and minimizing an error of the frequency of the frequency signal by increasing the quantity of the phase shift signals, so as to calibrate the frequency signal generated by the frequency generating unit. | 2013-01-17 |
| 20130015891 | DYNAMIC DIVIDE BY 2 WITH 25% DUTY CYCLE OUTPUT WAVEFORMS - Disclosed are frequency dividers, methods, apparatus, and other implementations, including a frequency divider that includes at least one input line to deliver at least one signal with a first frequency, a divider stage comprising multiple divider active components to produce output signals each with a second frequency equal to substantially half the first frequency, and an input stage electrically coupled to the divider stage to enable operation of the divider stage, the input stage including multiple additional active components. Each of the output signals is electrically coupled to an input of a different corresponding component of the multiple additional active components to electrically actuate the respective different corresponding components such that each of the multiple additional active components is periodically in an ON state while during the same time at least another of the multiple additional active components of the input stage is in an OFF state. | 2013-01-17 |
| 20130015892 | DOUBLE-POINT MODULATOR WITH ACCURATE AND FAST GAIN CALIBRATIONAANM Badets; FranckAACI VoironAACO FRAAGP Badets; Franck Voiron FRAANM Ramet; SergeAACI JarrieAACO FRAAGP Ramet; Serge Jarrie FRAANM Ayraud; MichelAACI VoreppeAACO FRAAGP Ayraud; Michel Voreppe FR - A phase-locked loop double-point modulator may include a frequency divider having a ratio which can be changed by a first modulation signal, and an oscillator, a frequency of which can be changed by a second modulation signal correlated to the first modulation signal. A calibration circuit may be configured, in a calibration mode, to match the gains of the first and second modulation signals based on frequency measurements of the oscillator for two different calibration values of the second modulation signal. The phase-locked double-point modulator may also include an attenuator having a constant ratio greater than 1 and placed in the path of the second modulation signal, and a selector switch configured to be controlled by the calibration circuit to reduce the ratio of the attenuator in the calibration mode. | 2013-01-17 |
| 20130015893 | MULTI-CLOCK REAL-TIME COUNTERAANM Severson; Matthew L.AACI San DiegoAAST CAAACO USAAGP Severson; Matthew L. San Diego CA US - A shared real-time counter is configured to provide an accurate counter output based on a fast clock period when driven by a fast clock signal or by a slow clock signal. Combinational logic circuitry provides glitch free switching between a fast clock signal input to the counter and a slow clock input to the counter. The counter is always on and increases its count by an appropriate rational number of counts representing fast clock cycles for every cycle of the fast clock while in a fast clock mode, and by an appropriate rational number of fast clock periods for every cycle of the slow clock signal while in a slow clock mode | 2013-01-17 |
| 20130015894 | DIFFERENTIAL RING OSCILLATOR-TYPE VOLTAGE CONTROL OSCILLATORAANM KOUYAMA; KunihikoAACI Yokohama-shiAACO JPAAGP KOUYAMA; Kunihiko Yokohama-shi JP - A voltage control oscillator according to the present invention includes: a voltage-current converter circuit that converts an inputted voltage to a current according to the value of the voltage; a current mirror circuit; a ring oscillator including differential inverters connected in multiple stages; an inverting amplifier; and a buffer. The ring oscillator outputs, from each of the differential inverters, a signal amplitude-limited by a “current converted by the voltage-current converter circuit and the current mirror circuit” and a “voltage applied from the inverting amplifier” and the ring oscillator outputs an oscillatory frequency in response to the output signal. | 2013-01-17 |
| 20130015895 | TEMPERATURE COMPENSATION CIRCUITAANM Nguyen; Darin DungAACI PhoenixAAST AZAACO USAAGP Nguyen; Darin Dung Phoenix AZ US - A temperature compensation circuit is disclosed. A temperature compensation circuit may include a temperature coefficient generator configured to generate a first signal and a second signal, wherein the first signal is proportional-to-absolute-temperature (ptat) and the second signal is negatively-proportional-to-absolute-temperature (ntat), a first programmable element configured to multiply at a first programmable ratio an amplitude of a third signal having a negative temperature coefficient from a first temperature to a second temperature, and a second programmable element configured to multiply at a second programmable ratio an amplitude of a fourth signal having a positive temperature coefficient from the second temperature to a third temperature. | 2013-01-17 |
| 20130015896 | PHASE-LOCKED LOOP APPARATUS AND TUNING VOLTAGE PROVIDING CIRCUIT THEREOFAANM Li; Hsiang-ChiAACI Hsinchu CityAACO TWAAGP Li; Hsiang-Chi Hsinchu City TW - A phase-locked loop apparatus (PLL apparatus) and a tuning voltage providing circuit thereof are provided. The PLL apparatus is for receiving an input signal and producing an output signal according to the received input signal. The PLL apparatus includes a voltage-controlled oscillator (VCO), a loop filter and a tuning voltage providing circuit. The VCO receives a control voltage and produces the output signal according to the received control voltage. The loop filter has a resistor-capacitor network and the network receives the control voltage and is coupled to a reference voltage. The tuning voltage providing circuit receives the output signal and the input signal and provides a tuning voltage to the resistor-capacitor network according to the input signal and the output signal. | 2013-01-17 |
| 20130015897 | DUTY RATIO CORRECTION CIRCUITAANM KIM; Young-wookAACI Gunpo-siAACO KRAAGP KIM; Young-wook Gunpo-si KRAANM JANG; Soon-bokAACI SeoulAACO KRAAGP JANG; Soon-bok Seoul KRAANM SONG; Jong-ukAACI SeoulAACO KRAAGP SONG; Jong-uk Seoul KRAANM OH; Hwa-seokAACI Yongin-siAACO KRAAGP OH; Hwa-seok Yongin-si KRAANM KIM; Sung-haAACI SeoulAACO KRAAGP KIM; Sung-ha Seoul KR - A duty ratio correction circuit for correcting a duty ratio of a clock signal. The duty ratio correction circuit includes an asymmetry buffer that receives a clock signal and adjusts a duty ratio of the clock signal in response to control signals; a clock generating circuit that i s connected to the asymmetry buffer and detects the duty ratio of the clock signal; and a controller that generates the control signals according to the duty ratio of the clock signal. An operation of the controller is recorded as a program on a computer-readable recording medium. | 2013-01-17 |
| 20130015898 | FREQUENCY-DOUBLING DELAY LOCKED LOOP - A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period. | 2013-01-17 |
| 20130015899 | DELAY LINES, AMPLIFIER SYSTEMS, TRANSCONDUCTANCE COMPENSATING SYSTEMS AND METHODS OF COMPENSATING - Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may include an input transistor receiving a signal being delayed by the delay line. The delay line may include a compensating circuit configured to compensate for a change in a transconductance of the input transistor resulting from various factors. One such compensating circuit may be configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of a transistor in the compensating circuit. The bias signal may be used by each of the delay stages to maintain the gain of the respective delay stage substantially constant, such as a gain of substantially unity, despite changes in a transconductance of the respective input transistor in each of the delay stages. | 2013-01-17 |
| 20130015900 | COUNTERMEASURE METHOD AND DEVICE FOR PROTECTING DATA CIRCULATING IN AN ELECTRONIC MICROCIRCUIT - The disclosure relates to a countermeasure method in an electronic microcircuit, comprising successive process phases executed by a circuit of the microcircuit, and adjusting a power supply voltage between power supply and ground terminals of the circuit, as a function of a random value generated for the process phase, at each process phase executed by the circuit. | 2013-01-17 |
| 20130015901 | MIXER CIRCUIT AND VARIATION SUPPRESSING METHODAANM Kitsunezuka; MasakiAACI TokyoAACO JPAAGP Kitsunezuka; Masaki Tokyo JP - In a mixer circuit that solves the problem of the extreme increase in circuit complexity that accompanies compensating for amplitude errors and phase errors, a voltage current conversion unit ( | 2013-01-17 |
| 20130015902 | RESISTOR-SHARING SWITCHING CIRCUITAANM Kim; Yu SinAACI Gyeonggi-doAACO KRAAGP Kim; Yu Sin Gyeonggi-do KRAANM Park; Sung HwanAACI Gyeonggi-doAACO KRAAGP Park; Sung Hwan Gyeonggi-do KR - Disclosed herein is a resistor-sharing switching circuit including: a first switching device and a second switching device; and a resistor whose first end is connected to a control signal input end to which a control signal for controlling bodies of the first switching device and the second switching device is applied and whose second end is connected to the bodies of the first switching device and the second switching device. | 2013-01-17 |
| 20130015903 | RESISTOR-SHARING SWITCHING CIRCUITAANM Kim; Yu SinAACI Gyeonggi-doAACO KRAAGP Kim; Yu Sin Gyeonggi-do KRAANM Park; Sung HwanAACI SeoulAACO KRAAGP Park; Sung Hwan Seoul KR - Disclosed herein is a resistor-sharing switching circuit, including: a first switching element turning on/off between a first input and output terminal and a second input and output terminal; a second switching element turning on/off between the first input and output terminal and a third input and output terminal; a signal transmission unit connected to both a control terminal of the first switching element and a control terminal of the second switching element; and a resistor having one end connected to the signal transmission unit and the other end connected to a control signal input terminal. | 2013-01-17 |
| 20130015904 | POWER GATING CONTROL MODULE, INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM, ELECTRONIC DEVICE, AND METHOD THEREFORAANM Priel; MichaelAACI HertzeliaAACO ILAAGP Priel; Michael Hertzelia ILAANM Rozen; AntonAACI GederaAACO ILAAGP Rozen; Anton Gedera ILAANM Shoshany; YossiAACI Gan YavneAACO ILAAGP Shoshany; Yossi Gan Yavne IL - An integrated circuit device comprising at least one signal processing module and a power gating control module arranged to control gating of at least one power supply to at least a part of the at least one signal processing module. The power gating control module is arranged to receive at least one operating parameter; configure at least one power gating setting of the power gating control module based at least partly on the at least one received operating parameter; and apply power gating for at least part of the at least one signal processing module in accordance with the at least one configured power gating setting. | 2013-01-17 |
