03rd week of 2009 patent applcation highlights part 42 |
Patent application number | Title | Published |
20090017541 | Porous Sheet-Form Material For Cell Culture, And Bioreactor And Culturing Method Utilizing Same - The present invention provides a bioreactor having a system that can grow cells, tissue, etc. while maintaining or improving their function, and finally recover the cells as they are with good efficiency. The bioreactor has a porous sheet-form material disposed in its main body, the porous sheet-form material being formed from a nonwoven fabric, etc. having high cell affinity in order to retain cells. This porous sheet-form material has a thermosensitive polymer and a cell-adhesive substance incorporated thereinto, and the porous sheet-form material is not only cell-adhesive but also allows cells and tissue to be detached from the porous sheet-form material as they are by, for example, cooling from 37° C. to 25° C. Furthermore, in order to efficiently ensure the bioactivity or the survival of the cells, it is arranged so that circulation of a culture medium in a culturing space of the bioreactor is of a radial flow type. | 2009-01-15 |
20090017542 | High-efficiency wild-type-free AAV helper functions - The present invention provides methods and compositions for producing high titer, wild-type-free preparations of recombinant AAV (“rAAV”) virions. The compositions of the present invention include novel nucleic acids encoding AAV helper functions and AAV helper function vectors. The present invention also includes host cells transfected by the claimed nucleic acids, methods of using the claimed vectors, and rAAV virions produced by such methods. | 2009-01-15 |
20090017543 | Viral Vectors - The present invention relates to an integration defective retroviral vector particle for gene therapy comprising a viral genome, wherein said vector particle is capable of infecting a mammalian target cell. | 2009-01-15 |
20090017544 | AUTOMATIC ANALYZER AND ANALYSIS METHOD USING THE SAME - Disclosed herein is an automatic analyzer which determines a vessel blank value of the automatic analyzer based on a criterion associated with the sensitivity of an analysis item to determine whether or not a vessel is usable. An automatic analyzer includes: an operation unit for calculating an absolute value of a difference between a vessel blank value immediately before measurement of the analysis item and a vessel blank value under periodical measurement to determine whether or not a vessel is usable for measurement based on a plurality of criteria set for each analysis item; and a function of issuing an alarm if the vessel blank value is not judged to be within a criterion. | 2009-01-15 |
20090017545 | Method of Determining Metal by Colorimetry and Determination Reagent - The present invention is a method for calorimetrically determining a metal in a sample using a chelating coloring agent, characterized by coexistence of a masking agent for iron, copper or nickel. Also, the present invention is a reagent for calorimetrically determining a metal in a sample using a chelating coloring agent, characterized by inclusion of a masking agent for iron, copper and/or nickel. Further, the present invention is a masking agent for iron, copper and/or nickel and a method for reducing positive errors due to iron, copper or nickel contained in a sample. | 2009-01-15 |
20090017546 | FLUORESCENT ISOTOPE TAGS AND THEIR METHOD OF USE - The present invention provides novel reactive fluorescent compounds that incorporate stable isotopic (deuterium, 13-carbon, 15-nitrogen, 18-oxygen) substitutions. The invention includes the use of these compounds, in combination with non-isotopically substituted analogs, for the purification, identification and relative quantification of proteins, peptides, saccharides, metabolites, and other biologically important compounds by combining liquid chromatography (LC) and mass spectrometry (MS). Fluorescent labeling of target compounds in this manner provides orders-of-magnitude sensitivity enhancement over traditional stable isotope labels, and also affords the possibility of simultaneous multiplexed analysis due to the multiwavelength nature of different fluorophores. | 2009-01-15 |
20090017547 | SYSTEMS AND METHODS FOR DNA COMPUTING USING METHYLATION - The present disclosure is directed to new methods and systems performing flexible and reversible modification of DNA in order to establish the logical value of true or false for a set of clauses. It combines both the biological meaning and experimental procedure with the logical implementation of the basic Boolean operators: OR, AND, and NOT. A feature of methylation logic is the use of the reversibility of DNA methylation of cytosine and adenine. Logic variables can be negated by reversing the DNA methylation status. Four implementation scenarios are described: three of them use methyl-sensitive restriction enzymes and the fourth uses methyl-binding proteins. Encoding can use either single or double stranded DNA. In addition, the disclosure allows for solving a multi-variable SAT problems by implementing a logic circuit. | 2009-01-15 |
20090017548 | Method for Determining the Effectiveness of Stabilized Chlorine Dioxide in a Mouth Rinse - A method for determining the available treatment dosage of stabilized chlorine dioxide in the prevention and the treatment of plaque accumulation, volatile sulfur compound production, gingivitis and periodontitis, and for differentiating the treatment dosage from other chlorine-containing compounds that may not have such beneficial effects is disclosed. When in solution as stabilized chlorine dioxide, the presence of other ions such as chlorate and chloride may not only obscure results as to the concentration of stabilized ClO | 2009-01-15 |
20090017549 | Apparatus and Method for Determining The Concentration of Iodine-Containing Organic Compounds in an Aqueous Solution - A method for determining the amount of a known iodine-containing organic compound in an aqueous solution. The method comprises electrochemically reducing the known iodine-containing organic compound in an aqueous medium to release iodide anions, chemically oxidizing the iodide anions to produce molecular iodine, and measuring the amount of molecular iodine. The known iodine-containing organic compound is preferably an aryl iodide, such as Iothalamate. Other preferred iodine-containing organic compounds include various glomerular filtration rate (GFR) marker compounds in plasma or urine samples, as useful in the measurement of GFR for an animal. The electrochemical reduction of the known iodine-containing organic compound is preferably performed in an electrochemical cell including a working electrode separated from a counter electrode by a cation exchange membrane. The working electrode most preferably includes bismuth and the counter electrode most preferably includes platinum. | 2009-01-15 |
20090017550 | Method For Determining A Carbon Source Of A Product - This invention is directed to a method for determining a source of carbon feed used in manufacturing product produced from the carbon feed. The invention further provides a method for tracking products, particularly MTO products, derived from a particular carbon feed. In general, the method involves a variety of steps that include one or more of determining, comparing, inventorying, and tracking the | 2009-01-15 |
20090017551 | Method and device for the detection of hydrogen - The present invention relates to a device and a method for the detection of hydrogen in a gas volume by means of an exothermal catalytic recombination of hydrogen and oxygen present in the gas volume into water. The amount of energy that is released during such an exothermal catalytic recombination is measured in the form of a temperature difference and is compared with a stored limit value. When a corresponding limit value is exceeded an appropriate signal is output. | 2009-01-15 |
20090017552 | FLUORESCEIN BASED SENSORS FOR TRACKING NITRIC OXIDE IN LIVE CELLS - The present invention is directed, in part, to coordination complexes for detecting analytes, and methods of making and using the same. | 2009-01-15 |
20090017553 | Immunoassay-based microsensing using optical sensors - A biosensor device, system, and method for detecting biological material. The sensor includes a substrate including sample regions having attachable thereon an immobilized first species associated with the biological material and includes at least one optical sensor associated with the sample regions and configured to detect induced radiation from a second species selectively attached to the first species at the sample regions. The induced radiation provides an indication that the biological material is on the substrate. The system includes a processor in communication with the optical sensor and is configured to monitor the induced radiation from the second species. The method immobilizes a first species of the biological material on the at least one sample region, attaches a second species of the biological material to the first species, induces radiation from the second species, and detects the radiation with at least one optical sensor associated with the at least one sample region. | 2009-01-15 |
20090017554 | DETECTION AND MIXING IN A CONDUIT IN INTEGRATED BIOANALYSIS SYSTEMS - Apparatuses and methods in which detection is integrated with various liquid processing and environmental control functions to create integrated bioanalysis systems are disclosed. Though the various integrated bioanalysis systems are useful for any number of analysis formats, they are adaptable to high-throughput processing of samples. | 2009-01-15 |
20090017555 | DELTA-9-TETRAHYDROCANNABINOL DETECTION METHOD - The invention provides competitive immunoassay techniques for high sensitivity detection of delta-9-tetrahydro-cannabinol ( | 2009-01-15 |
20090017556 | METHODS AND COMPLEXES INVOLVING IMMUNOGLOBULIN MOLECULE - A device that includes a proteinaceous factor is disclosed. The proteinaceous factor is encoded by the nucleotide sequence of any one of SEQ ID NO.: 1, a degenerate variant of SEQ ID NO.: 1, and a complement of SEQ ID NO.: 1. The proteinaceous factor may be a recombinant. In addition, the device may include any one of (i) Immunoglobulin G (IgG) bound non-specifically to the proteinaceous factor, (ii) at least one diagnostic label bound to the proteinaceous factor, (iii) Immunoglobulin G bound non-specifically to the proteinaceous factor and at least one diagnostic label bound to the proteinaceous factor, and (iv) at least one base supporting the proteinaceous factor. | 2009-01-15 |
20090017557 | FVII Specific Antibodies and Use Thereof - The present invention relates to novel antibodies against FVII, use for determining amount of correctly folded and intact FVII in a sample, as well as for purification and process optimization. | 2009-01-15 |
20090017558 | APOLIPOPROTEIN E STABLE FOLDING INTERMEDIATE AND METHODS OF USE THEREOF - The present invention provides isolated apolipoprotein E (apoE) stable folding intermediates. The invention further provides methods for identifying compounds that alter the structure or level or activity of an apoE stable folding intermediate, as well as methods of inhibiting the formation or activity of stable folding intermediates of apoE. The invention further provides methods for reducing the level and/or activity of an apoE stable folding intermediate, and methods for treating disorders relating to apoE4 in a subject. | 2009-01-15 |
20090017559 | Methods for diagnosing renal disorders - The present invention relates to methods for diagnosing the presence and progress of pathologies characterized by an accumulation of the extracellular matrix components by measuring the level of Connective Tissue Growth Factor (CTGF) in a sample. The method of the present invention is directed to diagnosing kidney fibrosis and associated renal disorders, in particular, complications associated with diabetes, hyperglycemia, and hypertension. | 2009-01-15 |
20090017560 | CARDIOVASCULAR AUTOIMMUNE DISEASE PANEL AND METHODS OF USING SAME - Provided herein among other things are diagnostic tests, methods of use, and kits for the assessment and management of cardiovascular autoimmune disease and risk of cardiovascular autoimmune disease. Assay methods of the invention can be employed among other things to identify cardiovascular autoimmune disease, or risk thereof, in subjects who have cardiovascular disease, an autoimmune disease, or who are related to an individual with an autoimmune disease. The method can be employed for testing of a subject that exhibits symptoms of cardiovascular disease, as well as of a subject that is apparently healthy and does not yet exhibit symptoms of cardiovascular disease, but may with time. In one embodiment, the invention also provides a method of determining whether a subject having, or at risk for, a cardiovascular disease is a candidate for immunosuppressive therapy or immunoabsorption therapy. The invention also provides kits and kit components that are useful for performing the methods of the invention. | 2009-01-15 |
20090017561 | Labelled silica nanoparticles for immunochromatographic reagent, immunochromatographic reagent, immunochromatographic test strip using the same, and immunochromatographic fluorescence-detecting system or radiation-detecting system - Labelled silica nanoparticles for immunochromatographic reagent, comprising silica nanoparticles containing a labelled substance. | 2009-01-15 |
20090017562 | RAMAN-ACTIVE REAGENTS - Raman Active Reagents (ERLs) are developed which use a nanoparticle substrate substantially covered with a mixed monolayer derived from a Raman active reporter molecule and an analyte binding molecule that both bind to the surface of the nanoparticle and thereby avoid the necessity for separate synthesis of a bifunctional linker molecule in making the ERL. | 2009-01-15 |
20090017563 | PLASMA TREATMENT AND REPAIR PROCESSES FOR REDUCING SIDEWALL DAMAGE IN LOW-K DIELECTRICS - A method of forming an interconnect structure for an integrated circuit, including the steps of providing a substrate and forming a dielectric stack on the substrate including an etch-stop layer, a low-k dielectric layer, and a hardmask layer. The method further includes the steps of patterning a photoresist masking layer on the dielectric stack to define a plurality of feature defining regions and plasma processing the substrate in a plasma-based reactor, The processing step includes etching a plurality of features into the hardmask layer and at least a portion of the low-k dielectric layer and performing a plasma treatment process in situ in the plasma-based reactor, where the plasma treatment process includes flowing at least one hydrocarbon into the reactor and generating a plasma, where a mass flow rate of the hydrocarbon is at least 0.1 sccm. The method also includes forming a metal conductor in the plurality of features. | 2009-01-15 |
20090017564 | METHOD TO DETECT AND PREDICT METAL SILICIDE DEFECTS IN A MICROELECTRONIC DEVICE DURING THE MANUFACTURE OF AN INTEGRATED CIRCUIT - The present invention provides a method detecting metal silicide defects in a microelectronic device. The method comprises positioning ( | 2009-01-15 |
20090017565 | MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet. | 2009-01-15 |
20090017566 | Substrate Removal During LED Formation - A light emitting diode (LED) is fabricated using an underfill layer that is deposited on either the LED or the submount prior to mounting the LED to a submount. The deposition of the underfill layer prior to mounting the LED to the submount provides for a more uniform and void free support, and increases underfill material options to permit improved thermal characteristics. The underfill layer may be used as support for the thin and brittle LED layers during the removal of the growth substrate prior to mounting the LED to the submount. Additionally, the underfill layer may be patterned to and/or polished back so that only the contact areas of the LED and/or submount are exposed. The patterns in the underfill may also be used as a guide to assist in the singulating of the devices. | 2009-01-15 |
20090017567 | Method for manufacturing semiconductor device - An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated. | 2009-01-15 |
20090017568 | Semiconductor device, electronic device and method for manufacturing semiconductor device - A semiconductor device of the present invention is manufactured by the following steps: forming a single-crystal semiconductor layer over a substrate having an insulating surface; irradiating a region of the single-crystal semiconductor layer with laser light; forming a circuit of a pixel portion using a region of the single-crystal semiconductor layer which is not irradiated with the laser light; and forming a driver circuit for driving the circuit of the pixel portion using the region of the single-crystal semiconductor layer which is irradiated with the laser light. Thus, a semiconductor device using a single-crystal semiconductor layer which is suitable for a peripheral driver circuit region and a single-crystal semiconductor layer which is suitable for a pixel region can be provided. | 2009-01-15 |
20090017569 | METHOD FOR FABRICATING LIQUID CRYSTAL DISPLAY DEVICE - A method for fabricating a liquid crystal display device is disclosed. The method includes forming a first conductive layer on an insulating substrate, forming a first insulating layer, a second conductive layer, and a third conductive layer on the first conductive layer, patterning the second conductive layer and the third conductive layer, such that the third conductive layer is located on a partial region of the second conductive layer and a partial region of the third conductive layer adjacent to the first conductive layer is removed, forming a second insulating layer on the patterned third conductive layer, forming a first contact hole to expose the first conductive layer by patterning the first and second insulating layers, and a second contact hole to expose the third conductive layer by patterning the second insulating layer, and forming a fourth conductive layer to connect the first and third conductive layers with each other by way of the first and second contact holes. | 2009-01-15 |
20090017570 | SEMICONDUCTOR LASER DEVICE AND METHOD FOR FABRICATING THE SAME - In a semiconductor laser device, a plurality of light-emitting elements emitting light with different wavelengths are integrated on a substrate. Each of the light-emitting elements includes, on the substrate, an active layer and cladding layers respectively provided on top and bottom of the active layer. One of the cladding layers provided on top of the active layer is an upper cladding layer having a mesa ridge portion. An etching stopper layer for forming the ridge portion is interposed between the ridge portion and the other portion of the upper cladding layer. The thickness of the etching stopper layer varies among the light-emitting elements. | 2009-01-15 |
20090017571 | SENSING DEVICES FROM MOLECULAR ELECTRONIC DEVICES - The present invention generally relates to the fabrication of molecular electronics devices from molecular wires and Single Wall Nanotubes (SWNT). In one embodiment, the cutting of a SWNT is achieved by opening a window of small width by lithography patterning of a protective layer on top of the SWNT, followed by applying an oxygen plasma to the exposed SWNT portion. In another embodiment, the gap of a cut SWNT is reconnected by one or more difunctional molecules having appropriate lengths reacting to the functional groups on the cut SWNT ends to form covalent bonds. In another embodiment, the gap of a cut SWNT gap is filled with a self-assembled monolayer from derivatives of novel contorted hexabenzocoranenes. In yet another embodiment, a device based on molecular wire reconnecting a cut SWNT is used as a sensor to detect a biological binding event. | 2009-01-15 |
20090017572 | NANOELECTROMECHANICAL TRANSISTORS AND METHODS OF FORMING SAME - Nanoelectromechanical transistors (NEMTs) and methods of forming the same are disclosed. In one embodiment, an NEMT may include a substrate including a gate, a source region and a drain region; an electromechanically deflectable nanotube member; and a channel member electrically insulatively coupled to the nanotube member so as to be aligned with the source region and the drain region, wherein the electromechanical deflection of the nanotube member is controllable, in response to an electrical potential applied to the gate and the nanotube member, between an off state and an on state, the on state placing the channel member in electrical connection with the source region and the drain region to form a current path. | 2009-01-15 |
20090017573 | Image sensor with improved dynamic range and method of formation - Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor structure comprises at least one semiconductor channel region, at least one gate for controlling the channel region, and first and second leads respectively coupled to a source region on one side of the at least one channel region and a drain region on an opposite side of the at least one channel region. The transistor structure has at least two threshold voltages associated with the at least one channel region, and an I-V characteristic of the transistor structure is determined at least in part by the threshold voltages. | 2009-01-15 |
20090017574 | THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, DISPLAY APPARATUS HAVING THE SAME AND METHOD OF MANUFACTURING THE DISPLAY APPARATUS - A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor. | 2009-01-15 |
20090017575 | Methods Of Forming Openings - Some embodiments include methods of forming openings in which a metal-containing structure is formed over a region of a semiconductor substrate. A patterned metal-containing material is formed over the metal-containing structure, with the metal-containing material having a gap extending therethrough. An entirety of the metal-containing structure is removed through the gap to leave an opening over the region of the semiconductor substrate. The region of the semiconductor substrate may comprise CMOS sensors, and one or both of filter material and microlens material may be formed within the opening. | 2009-01-15 |
20090017576 | Semiconductor Processing Methods - Some embodiments include methods of forming semiconductor constructions in which a semiconductor material sidewall is along an opening, a protective organic material is over at least one semiconductor material surface, and the semiconductor material sidewall and protective organic material are both exposed to an etch utilizing at least one fluorine-containing composition. The etch is selective for the semiconductor material relative to the organic material, and reduces sharpness of at least one projection along the semiconductor material sidewall. In some embodiments, the opening is a through wafer opening, and subsequent processing forms one or more materials within such through wafer opening to form a through wafer interconnect. In some embodiments, the opening extends to a sensor array, and the protective organic material is comprised by a microlens system over the sensor array. Subsequent processing may form a macrolens structure across the opening. | 2009-01-15 |
20090017577 | Methods of Forming Phase Change Memory Devices Having Bottom Electrodes - Phase change memory devices can have bottom patterns on a substrate. Line-shaped or L-shaped bottom electrodes can be formed in contact with respective bottom patterns on a substrate and to have top surfaces defined by dimensions in x and y axes directions on the substrate. The dimension along the x-axis of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process used to fabricate the phase change memory device. Phase change patterns can be formed in contact with the top surface of the bottom electrodes to have a greater width than each of the dimensions in the x and y axes directions of the top surface of the bottom electrodes and top electrodes can be formed on the phase change patterns, wherein the line shape or the L shape represents a sectional line shape or a sectional L shape of the bottom electrodes in the x-axis direction. | 2009-01-15 |
20090017578 | Application of RFID labels - Disclosed is a method for producing an RFID label with the aid of a printing process. The aim of the invention is make it easy to apply the parts required onto the label while completing the label in a simple manner. Said aim is achieved by applying at least one portion of the antenna and the resonant circuit required for the function to the printing material by means of sheet-fed offset printing or directly or indirectly with the aid of a relief printing plate. The resonant circuits or chips are applied individually or to a packaging that is to be created or filled in the same alignment once several copies of the labels have been produced on one sheet and have been separated therefrom. | 2009-01-15 |
20090017579 | METHOD OF MANUFACTURING MICRO ELECTRO MECHANICAL SYSTEMS DEVICE - Provided is a MEMS device which is robust to the misalignment and does not require the double-side wafer processing in the manufacture of a MEMS device such as an angular velocity sensor, an acceleration sensor, a combined sensor or a micromirror. After preparing a substrate having a space therein, holes are formed in a device layer at positions where fixed components such as a fixing portion, a terminal portion and a base that are fixed to a supporting substrate are to be formed, and the holes are filled with a fixing material so that the fixing material reaches the supporting substrate, thereby fixing the device layer around the holes to the supporting substrate. | 2009-01-15 |
20090017580 | SYSTEMS AND METHODS FOR VERTICALLY INTEGRATING SEMICONDUCTOR DEVICES - Systems and methods for vertically integrating semiconductor devices are described. In one embodiment, a method comprises providing an interposer, aligning and bonding a plurality of die to a first surface of the interposer, aligning and bonding a backplate to the plurality of die, and reducing at least one portion of the interposer to create a reconstituted wafer. In another embodiment, an apparatus comprises an interposer operable to receive at least one donor semiconductor device disposed on a first surface of the interposer and aligned therewith, and at least one host semiconductor device disposed on a second surface of the interposer and aligned therewith; where the interposer allows the at least one donor and host semiconductor devices to become vertically integrated. | 2009-01-15 |
20090017581 | Method for manufacturing a semiconductor device - A single-crystal semiconductor layer is provided in a large area over a large-sized glass substrate, whereby a large-scale SOI substrate is obtained. A single-crystal semiconductor substrate provided with an embrittlement layer and a dummy substrate are bonded to each other, and the single-crystal semiconductor substrate is separated at the embrittlement layer as a boundary by heat treatment to form a piece of single-crystal semiconductor over the dummy substrate. The dummy substrate is divided to form a piece of single-crystal semiconductor. The piece of single-crystal semiconductor is bonded to a supporting substrate, and the piece of single-crystal semiconductor is separated from the dummy substrate. Then, a plurality of pieces of single-crystal semiconductor are arranged and transferred to the large-sized glass substrate. | 2009-01-15 |
20090017582 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - This invention includes a method for manufacturing a semiconductor device by which implementation of a finer pitch for a semiconductor chip can be handled, and the creation of voids inside an under-filling resin can be reduced in order to realize highly reliable flip-chip mounting. It involves a step in which multiple electrodes arranged two-dimensionally on one side of a semiconductor chip are connected to corresponding conductive regions on a substrate; a step in which an under-filling resin is injected between the one surface of the semiconductor chip and the substrate; and a step in which the under-filling resin is melted at a temperature higher than its glass transition temperature while under a prescribed pressure and cured. | 2009-01-15 |
20090017583 | DOUBLE ENCAPSULATED SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A double encapsulated semiconductor package and manufacturing methods of forming the same are provided. Embodiments of the semiconductor package include a complex chip having normal and random pads formed on its active surface, the complex chip being attached to a first surface of a wiring substrate. First and second windows are formed in the wiring substrate to respectively expose the normal and random pads, and to allow bonding wires to be connected to the normal and random pads with the wiring substrate. A first resin encapsulation portion is formed by a molding method in the first window and a second resin encapsulation portion is formed by a potting method in the second window. | 2009-01-15 |
20090017584 | PROCESS FOR FINFET SPACER FORMATION - A process for finFET spacer formation generally includes depositing, in order, a conformnal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure; tilt implanting dopant ions into portions of the capping layer about the gate structure; selectively removing undoped capping material about the source and drain regions; selectively removing exposed portions of the spacer material; selectively removing exposed portions of the capping material; anisotropically removing a portion of the spacer material so as to expose a top surface of the gate material and isolate the spacer material to sidewalls of the gate structure; and removing the oxide liner from the fin to form the spacer on the finFET structure. | 2009-01-15 |
20090017585 | Self Aligned Gate JFET Structure and Method - A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielectric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed. | 2009-01-15 |
20090017586 | CHANNEL STRESS MODIFICATION BY CAPPED METAL-SEMICONDUCTOR LAYER VOLUME CHANGE - A method for fabricating a field effect device, such as a field effect transistor, uses a first metal-semiconductor layer, such as a first metal-silicide layer, adjacent a channel in the field effect device. The first metal-semiconductor layer has a first volume. The first metal-semiconductor layer is capped with a capping layer and processed to form a second metal-semiconductor layer that has a second volume different than the first volume. Due to the presence of the capping layer, the difference in volume between the second volume and the first volume introduces a stress into the channel of the field effect device. | 2009-01-15 |
20090017587 | Disposable organic spacers - A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode ( | 2009-01-15 |
20090017588 | SYSTEMS AND METHODS THAT SELECTIVELY MODIFY LINER INDUCED STRESS - The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided ( | 2009-01-15 |
20090017589 | TRI-GATE INTEGRATION WITH EMBEDDED FLOATING BODY MEMORY CELL USING A HIGH-K DUAL METAL GATE - Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality of transistors including dual-gate memory cells, PMOS transistors, and NMOS transistors. An insulative layer is formed overlying the silicon body of the memory cell. A layer of a high-k dielectric and at least a metal layer cover the silicon bodies and their overlying layers. Next, gain regions of the transistors are filled with polysilicon. Thus, a gate is formed on the top surface and both sidewalls of a tri-gate transistor. Thereafter, the high-k dielectric and the metal layer overlying the insulative layer of the memory cell are removed to expose the insulative layer. Thus, two electrically-isolated gates of the memory cell are formed. | 2009-01-15 |
20090017590 | METHOD FOR FABRICATING SONOS A MEMORY - A method for fabricating a SONOS memory is disclosed. First, a semiconductor substrate is provided and a SONOS memory cell is formed on said semiconductor substrate. A passivation layer is deposited on the SONOS memory cell and a contact pad is formed on the passivation layer. Subsequently, an ultraviolet treatment is performed and an annealing process is conducted thereafter. | 2009-01-15 |
20090017591 | Local Oxidation of Silicon Planarization for Polysilicon Layers Under Thin Film Structures - In accordance with the teachings described herein, a method for fabricating a patterned polysilicon layer having a planar surface may include the steps of: depositing a polysilicon film above a substrate material; depositing an oxide-resistant mask over the polysilicon film; patterning and etching the oxide-resistant mask to form a patterned mask layer over the polysilicon film, such that the polysilicon film includes masked and unmasked portions; etching the unmasked portions of the polysilicon film for a first amount of time; oxidizing the etched polysilicon film for a second amount of time to form an oxide layer that defines the patterned polysilicon layer; and removing the patterned mask layer; wherein the first and second amounts of time are selected such that the oxide layer and the patterned polysilicon layer have about the same thickness and form a planar surface. | 2009-01-15 |
20090017592 | Siloxane polymer composition, method of forming a pattern using the same, and method of manufacturing a semiconductor using the same - A siloxane polymer composition includes an organic solvent in an amount of about 93 percent by weight to about 98 percent by weight, based on a total weight of the siloxane polymer composition, and a siloxane complex in an amount of about 2 percent by weight to about 7 percent by weight, based on the total weight of the siloxane polymer composition, the siloxane complex including a siloxane polymer with an introduced carboxylic acid and being represented by Formula 1 below, | 2009-01-15 |
20090017593 | METHOD FOR SHALLOW TRENCH ISOLATION - Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described. | 2009-01-15 |
20090017594 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - There is provided a non-volatile semiconductor memory device exhibiting excellent electrical characteristics and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having two trenches, an isolation oxide film provided in the trench, a floating gate electrode, an ONO film, and a control gate electrode. The isolation oxide film has an upper surface with a region having a curvature protruding downward. The floating gate electrode has a flat upper surface and extends from a main surface of the semiconductor substrate between the two trenches to the two isolation oxide films. The ONO film extends from the upper surface of the floating gate electrode to a side surface of the floating gate electrode. The control gate electrode is provided on the ONO film to extend from the upper surface of the floating gate electrode to the side surface of the floating gate electrode. | 2009-01-15 |
20090017595 | RELIABLE GAP-FILLING PROCESS AND APPARATUS FOR PERFORMING THE PROCESS IN THE MANUFACTURING OF SEMICONDUCTOR DEVICES - A reliable gap-filling process is performed in the manufacturing of a semiconductor device. An apparatus for performing the gap-filling process includes a chamber in which a wafer chuck is disposed, a plasma generator for generating plasma used to etch the wafer, an end-point detection unit for detecting the point at which the etching of the wafer is to be terminated, and a controller connected to the end-point detection unit. The end-point detection unit monitors the structure being etched at a region outside the opening that is to be filled, and generates in real time data representative of the layer that is being etched. As soon as an underlying layer is exposed and begins to be etched, an end-point detection signal is generated and the etching process is terminated. In the case in which the layer being etched is an oxide layer, a uniform etching is achieved despite any irregularity that exists in the thickness to which the oxide layer is formed. | 2009-01-15 |
20090017596 | Methods Of Forming Oxides, Methods Of Forming Semiconductor Constructions, And Methods Of Forming Isolation Regions - Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing composition. The conversion may utilize one or more oxygen-containing species (such as ozone) and a temperature of less than or equal to 300° C. In some embodiments, the spin-on material is formed within an opening in a semiconductor material to form a trenched isolation region. Other dielectric materials may be formed within the opening in addition to the silicon dioxide-containing composition formed from the spin-on material. Such other dielectric materials may include silicon dioxide formed by chemical vapor deposition and/or silicon dioxide formed by high-density plasma chemical vapor deposition. | 2009-01-15 |
20090017597 | METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION - A method for manufacturing semiconductor shallow trench isolation is performed as follows. First, a semiconductor substrate including at least one shallow trench is provided, and the shallow trench is filled with Spin-On-Dielectric (SOD) material, e.g., polysilazane, to form a SOD material layer. Then, the SOD material layer is subjected to a planarization process. Oxygen ions are implanted into the SOD material layer to a predetermined depth, and a high temperature process is performed afterwards to transform the portion of the SOD material layer having oxygen ions into a silicon oxide layer. The oxygen ions can be implanted by plasma doping, immersion doping or ion implantation. | 2009-01-15 |
20090017598 | Method of manufacturing semiconductor device - To provide a method of manufacturing a semiconductor device in which the space between semiconductor films transferred at plural locations is narrowed. A first bonding substrate having first projections is attached to a base substrate. Then, the first bonding substrate is separated at the first projections so that first semiconductor films are formed over the base substrate. Next, a second bonding substrate having second projections is attached to the base substrate so that the second projections are placed in regions different from regions where the first semiconductor films are formed. Subsequently, the second bonding substrate is separated at the second projections so that second semiconductor films are formed over the base substrate. In the second bonding substrate, the width of each second projection in a direction (a depth direction) perpendicular to the second bonding substrate is larger than the film thickness of each first semiconductor film formed first. | 2009-01-15 |
20090017599 | Method for manufacturing semiconductor device - An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated. | 2009-01-15 |
20090017600 | WAFER DIVIDING METHOD USING LASER BEAM WITH AN ANNULAR SPOT - In a wafer dividing method of dividing a wafer into individual devices, the wafer being sectioned by streets to form the devices each made of a laminated body in which an insulating film and a function film are laminated on a front surface of a semiconductor substrate, the method includes a laser processing groove forming step for forming a laser processing groove on the laminated body so as to reach the semiconductor substrate by applying a laser beam formed with an annular spot to the laminated body side of the wafer along the street, the annular spot having an outer diameter larger than a width of a cutting blade and smaller than a width of the street; and a cutting step for allowing a cutting blade to cut the semiconductor substrate of the semiconductor wafer along the laser processing groove formed at the street. | 2009-01-15 |
20090017601 | CRYSTALLINE FILM DEVICES, APPARATUSES FOR AND METHODS OF FABRICATION - Methods of depositing thin film materials having crystalline content are provided. The methods use plasma enhanced chemical vapor deposition. According to one embodiment of the present invention, microcrystalline silicon films are obtained. According to a second embodiment of the present invention, crystalline films of zinc oxide are obtained. According to a third embodiment of the present invention, crystalline films of iron oxide are obtained. | 2009-01-15 |
20090017602 | METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE FOR MICROELECTRONICS AND OPTOELECTRONICS - The method includes the following steps:
| 2009-01-15 |
20090017603 | METHOD OF FORMING EPITAXIAL LAYER - A method of forming an epitaxial layer on a silicon substrate includes (a) providing a silicon substrate; (b) performing a wet-cleaning process onto the silicon substrate; (c) performing a first plasma cleaning process onto the wet-cleaned silicon substrate by providing a chlorine (Cl | 2009-01-15 |
20090017604 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device comprises providing a substrate. Under an atmosphere containing a fluoride nitride compound, a plasma treatment process is performed to simultaneously fluorinate and nitrify a surface of the substrate. Thereafter, a dielectric layer is formed on the substrate. | 2009-01-15 |
20090017605 | METHODS FOR DOPING NANOSTRUCTURED MATERIALS AND NANOSTRUCTURED THIN FILMS - A method for introducing one or more impurities into nano-structured materials. The method includes providing a nanostructured material having a feature size of about 100 nm and less. The method includes subjecting a surface region of the nanostructured material to one or more impurities to form a first region having a first impurity concentration within a vicinity of the surface region. In a specific embodiment, the method includes applying a driving force to one or more portions of at least the nanostructured material to cause the first region to form a second region having a second impurity concentration. | 2009-01-15 |
20090017606 | Method for Producing a Semiconductor Component Having Regions Which are Doped to Different Extents - A method for producing a semiconductor component, in particular a solar cell, having regions which are doped to different extents. A layer is formed which inhibits the diffusion of a dopant and can be penetrated by a dopant, on at least one part of the surface of a semiconductor component material. The diffusion-inhibiting layer is at least partially removed in at least one high-doping region. A dopant source is formed on the diffusion-inhibiting layer and in the at least one high-doping region. Then the dopant is diffused from the dopant source into the semiconductor component material. The semiconductor component is suitable for use in integrated circuits, electronic circuits, solar cell modules, and to produce solar cells having a selective emitter structure. | 2009-01-15 |
20090017607 | GATE CD TRIMMING BEYOND PHOTOLITHOGRAPHY - A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a conductive material, such as polysilicon, is formed over the gate dielectric layer. The gate layer is patterned to form a gate electrode having a first horizontal dimension. One or more growth-stripping operations are performed to reduce a critical dimension of the gate electrode to a second horizontal dimension, where the second horizontal dimension is less than the first horizontal dimension. | 2009-01-15 |
20090017608 | SEMICONDUCTOR DEVICE FABRICATING METHOD - A method for fabricating a semiconductor device is provided which has first and second regions, transistors of different conductivity types being formed on parts of a substrate corresponding to the first and second regions. The method includes the steps of: (a) forming a first insulating film to cover the parts of the substrate corresponding to the first and second regions; (b) forming a first thin film on the first insulating film, the first thin film having a relatively higher etching rate than the first insulating film in plasma etching using a halogen gas; and (c) removing a part of the first thin film corresponding to the first region by the plasma etching using a mask covering the second region and modifying a part of the first insulating film corresponding to the first region. | 2009-01-15 |
20090017609 | RECTANGULAR CONTACT USED AS A LOW VOLTAGE FUSE ELEMENT - A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contact is made long enough so that it makes contact at each end with a metal layer, but design rule spacing is still maintained between the connections with the metal layer. The overlapping areas between the rectangular contact and the metal layers are asymmetrical. Alternatively, these overlapping areas are smaller than the design rule overlap requirements. In a second embodiment, a fuse element is constructed with a plurality of rectangular-shaped contacts. As a result, a current value that is significantly lower than conventional fuse current values, can be used to melt such a contact or blow the fuse. | 2009-01-15 |
20090017610 | Junction structure of terminal pad and solder, semiconductor device having the junction structure, and method of manufacturing the semiconductor device - The present invention provides a semiconductor device which comprises a terminal pad ( | 2009-01-15 |
20090017611 | Semiconductor device and method for fabricating the same - In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect. | 2009-01-15 |
20090017612 | METHODS FOR FABRICATING ARRAY SUBSTRATES - Methods for fabricating array substrates are provided. A method for fabricating an array substrate includes forming a first metal layer over a substrate and then patterned by a first photolithography to forming a gate line, a gate electrode connecting the gate line, and a pad over the substrate. An insulating layer, a semiconductor layer, and an ohmic contact layer are formed over the substrate to cover the gate line, the gate electrode and the pad. The ohmic contact layer, the semiconductor layer, and portions of the insulating layer are patterned by a second photolithography to forming a semiconductor structure over the substrate and a via hole in the insulating layer over the pad to exposing a part of the pad. | 2009-01-15 |
20090017613 | METHOD OF MANUFACTURING INTERCONNECT SUBSTRATE AND SEMICONDUCTOR DEVICE - An interconnect substrate includes an interconnect, an insulating layer, a non-photosensitive resin layer, a photosensitive resin layer, a first electrode pad, and a second electrode pad. The non-photosensitive resin layer is constructed with a non-photosensitive insulating material. Also, the non-photosensitive resin layer has a first opening. The photosensitive resin layer is constructed with a photosensitive insulating material. Also, the photosensitive resin layer has a second opening. The opening area of the second opening is larger than that of the first opening. The first electrode pad is disposed on the first surface side of the insulating layer. The first electrode pad is exposed to the first opening. The second electrode pad is disposed on the second surface side of the insulating layer. The second electrode pad is exposed to the second opening. | 2009-01-15 |
20090017614 | SEMICONDUCTOR DEVICE - In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film. | 2009-01-15 |
20090017615 | Method of removing an insulation layer and method of forming a metal wire - A method of removing an insulation layer pattern covering metal wires includes providing an insulation layer pattern on a substrate, the insulation layer pattern having openings exposing the substrate, forming metal wires in the openings by depositing a barrier layer on inner surfaces of the openings, such that a lower portion of the barrier layer is thinner that an upper portion of the barrier layer, and depositing a metal layer to fill the openings, and performing an etching process with an etching vapor to remove the insulation layer pattern from the substrate to expose the metal wires. | 2009-01-15 |
20090017616 | METHOD FOR FORMING CONDUCTIVE STRUCTURES - A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed layer on the conductive hardmask layer and the sidewalls and bottom of the trench; filling the trench with a fill material; removing the liner/seed layer from the top surface of the conductive hardmask layer; removing the fill material from the trench; electroplating a metal layer onto exposed surfaces of the conductive hardmask layer and liner/seed layer; and removing the metal layer and the conductive hardmask layer from the dielectric hardmask layer so the metal layer and edges of the liner/seed layer are coplanar with the top surface of the dielectric hardmask layer. | 2009-01-15 |
20090017617 | METHOD FOR FORMATION OF HIGH QUALITY BACK CONTACT WITH SCREEN-PRINTED LOCAL BACK SURFACE FIELD - A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius. | 2009-01-15 |
20090017618 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device that includes heating a wafer on which an Al—Cu sputtering thin film is formed before patterning the Al—Cu sputtering thin film. The heating is performed at a temperature no less than a solid solution temperature of copper or at a temperature between 300° C. and 600° C. The process temperature in heating the process wafer is not higher than the flow temperature of aluminum or is the temperature at which a reflow process can be performed. | 2009-01-15 |
20090017619 | METHOD FOR MANUFACTURING METAL SILICIDE LAYER IN A SEMICONDUCTOR DEVICE - A metal suicide layer is fabricated in a semiconductor device. A first metal layer is deposited on a silicon substrate formed with an S interlayer dielectric having a contact hole through PVD. A second metal layer is deposited on the first metal layer through any one of CVD and ALD. Annealing is performed on the silicon substrate which is formed with the first and second metal layers to form the metal silicide. The portions of the second metal layer and the first metal layer which have not reacted during annealing are removed. | 2009-01-15 |
20090017620 | Method of manufacturing semiconductor device for dual damascene wiring - A method of manufacturing a semiconductor device includes forming a via hole in an interlayer dielectric film, forming a wiring trench in said interlayer dielectric film for connecting to the via hole, and forming a dual damascene wiring trench in the interlayer dielectric film for forming a dual damascene wiring which is connected to a conductive film. In forming the via hole, the via hole is formed in a bow shape and, in forming the wiring trench, the wiring trench is formed by etching to a position where a diameter of the via hole becomes substantially a maximum to provide a via having a forward taper shape under the wiring trench. | 2009-01-15 |
20090017621 | Manufacturing method for semiconductor device and manufacturing device of semiconductor device - The semiconductor manufacturing method includes the step (ST. | 2009-01-15 |
20090017622 | CHEMICAL TREATMENT METHOD - A chemical treatment apparatus and a method for performing a chemical treatment of a wafer, etc., by supplying a chemical via a cell. The apparatus includes a cylindrical inner cell and a cylindrical outer cell with open ends disposed at an outer circumference of the inner cell. The outer cell is axially movable to vary the width of a slit formed between a bottom end of the outer cell and a top surface of the substrate-holding means by the axial movement, thereby adjusting the discharge rate of the chemical and varying the pressure of the chemical. | 2009-01-15 |
20090017623 | WAFER PROCESSING METHOD - A wafer processing method having a step of reducing the thickness of a wafer in only a device forming area where semiconductor chips are formed by grinding and etching the back side of the wafer to thereby form a recess on the back side of the wafer. At the same time, an annular projection is formed around the recess to thereby ensure the rigidity of the wafer. Accordingly, handling in shifting the wafer from the back side recess forming step to a subsequent step of forming a back side rewiring layer can be performed safely and easily. | 2009-01-15 |
20090017624 | Nodule Defect Reduction in Electroless Plating - An electroless plating method and the apparatus for performing the same are provided. The method includes providing a plating solution; contacting a front surface of the wafer with the plating solution; and incurring a plating reaction substantially simultaneously on an entirety of the front surface of the wafer. The step of incurring a plating reaction substantially simultaneously includes lift-dispense electroless plating and face-down immersion. | 2009-01-15 |
20090017625 | Methods For Removing Gate Sidewall Spacers In CMOS Semiconductor Fabrication Processes - Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows. | 2009-01-15 |
20090017626 | SEMICONDUCTOR WET ETCHANT AND METHOD OF FORMING INTERCONNECTION STRUCTURE USING THE SAME - A semiconductor wet etchant includes deionized water, a fluorine-based compound, an oxidizer and an inorganic salt. A concentration of the fluorine-based compound is 0.25 to 10.0 wt % based on a total weight of the etchant, a concentration of the oxidizer is 0.45 to 3.6 wt % based on a total weight of the etchant, and a concentration of the inorganic salt is 1.0 to 5.0 wt % based on a total weight of the etchant. The inorganic salt comprises at least one of an ammonium ion (NH | 2009-01-15 |
20090017627 | Methods of Modifying Oxide Spacers - Methods for reducing line roughness of spacers and other features utilizing a non-plasma and non-wet etch fluoride processing technology are provided. Embodiments of the methods can be used for spacer or line reduction and/or smoothing the surfaces along the edges of such features through the reaction and subsequent removal of material. | 2009-01-15 |
20090017628 | SPACER LITHOGRAPHY - Ultrafine dimensions are accurately and efficiently formed in a target layer using a spacer lithographic technique comprising forming a first mask pattern, forming a cross-linkable layer over the first mask pattern, forming a cross-linked spacer between the first mask pattern and cross-linkable layer, removing the cross-linkable layer, cross-linked spacer from the upper surface of the first mask pattern and the first mask pattern to form a second mask pattern comprising remaining portions of the cross-linked spacer, and etching using the second mask pattern to form an ultrafine pattern in the underlying target layer. Embodiments include forming the first mask pattern from a photoresist material capable of generating an acid, depositing a cross-linkable material comprising a material capable of undergoing a cross-linking reaction in the presence of an acid, and removing portions of the non-cross-linked layer and cross-linked spacer from the upper surface of the first mask pattern before removing the remaining portions of the first mask pattern and remaining noncross-linked layer. | 2009-01-15 |
20090017629 | METHOD OF FORMING CONTACT STRUCTURE WITH CONTACT SPACER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method of forming a contact structure with a contact spacer and a method of fabricating a semiconductor device using the same. In the method of forming a contact structure, an interlayer dielectric layer is formed on a semiconductor substrate. The interlayer dielectric layer is patterned, thereby forming a contact hole for exposing a predetermined region of the semiconductor substrate. A contact spacer is formed on a sidewall of the contact hole using a deposition method having an inclined deposition direction with respect to a main surface of the semiconductor substrate. The deposition direction may be set between the main surface and a normal with respect to the main surface. Further, there is provided a method of fabricating a semiconductor device using the method of forming the contact structure. | 2009-01-15 |
20090017630 | Methods For Forming Contacts For Dual Stress Liner CMOS Semiconductor Devices - Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL. | 2009-01-15 |
20090017631 | SELF-ALIGNED PILLAR PATTERNING USING MULTIPLE SPACER MASKS - A method for fabricating a semiconductor mask is described. The image of a series of lines from a first spacer mask is first provided to a mask layer to form a patterned mask layer. The image of a series of lines from a second spacer mask is then provided to the patterned mask layer to form a pillar mask comprised of a series of pillars. The image of the series of lines from the second spacer mask is non-parallel with the series of lines from the first spacer mask. | 2009-01-15 |
20090017632 | METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES USING RIE PROCESS - A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a source radio frequency and anisotropic etch performance is induced by a second bias radio frequency. | 2009-01-15 |
20090017633 | ALTERNATIVE METHOD FOR ADVANCED CMOS LOGIC GATE ETCH APPLICATIONS - Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer. | 2009-01-15 |
20090017634 | USE OF A PLASMA SOURCE TO FORM A LAYER DURING THE FORMATION OF A SEMICONDUCTOR DEVICE - A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface. | 2009-01-15 |
20090017635 | APPARATUS AND METHOD FOR PROCESSING A SUBSTRATE EDGE REGION - The present invention comprises an apparatus and method for etching at a substrate edge region. In one embodiment, the apparatus comprises a chamber having a process volume, a substrate support arranged inside the process volume and having a substrate support surface, a plasma generator coupled to the chamber and configured to supply an etching agent in a plasma phase to a peripheral region of the substrate support surface, and a gas delivery assembly coupled to a gas source for generating a radial gas flow over the substrate support surface from an approximately central region of the substrate support surface toward the peripheral region of the substrate support surface. | 2009-01-15 |
20090017636 | TITANIUM NITRIDE-STRIPPING LIQUID, AND METHOD FOR STRIPPING TITANIUM NITRIDE COATING FILM - A titanium nitride-stripping liquid for stripping a titanium nitride coating film, the titanium nitride-stripping liquid being capable of stripping a titanium nitride coating film even in a semiconductor multilayer laminate having particularly a layer that includes tungsten or a tungsten alloy, without corrosion of this layer is provided, and furthermore, a titanium nitride-stripping liquid which can strip a titanium nitride coating film without affecting an insulating layer is provided. A titanium nitride-stripping liquid including hydrofluoric acid, hydrogen peroxide and water, and further including an inorganic acid other than hydrofluoric acid. According to the present invention, since the titanium nitride-stripping liquid includes an inorganic acid other than hydrofluoric acid, a titanium nitride coating film can be stripped even in the case in which a semiconductor multilayer laminate has a layer that includes tungsten or a tungsten alloy, without corrosion of the layer by the titanium nitride-stripping liquid. | 2009-01-15 |
20090017637 | METHOD AND APPARATUS FOR BATCH PROCESSING IN A VERTICAL REACTOR - The present invention generally provides an apparatus and method for the processing a plurality of substrates in a batch processing chamber. One embodiment of the present invention provides a method for processing a plurality of substrates comprising positioning the plurality of substrates in an inner volume of a batch processing chamber, wherein the plurality of substrates are arranged in a substantially parallel manner, and at least a portion of the plurality of substrates are positioned with a device side facing downward, and flowing one or more processing gases cross the plurality of substrates. | 2009-01-15 |
20090017638 | Substrate processing apparatus and method for manufacturing semiconductor device - It is intended to provide a substrate processing apparatus and a semiconductor device manufacturing method capable of suppressing formation of a film inside a nozzle and extending a replacement or maintenance cycle of the nozzle, thereby realizing improvement in operation rate of the apparatus. A substrate processing apparatus comprising: a reaction container for performing a processing for generating a film containing a plurality of elements on a substrate; a heater for heating an inside of the reaction container; at least one nozzle that is provided inside the reaction container in such a fashion that at least a part thereof is opposed to the heater for supplying a first gas containing at least one of the plurality of elements forming the film and capable of depositing a film by itself into the reaction container; and a circulation pipe that is provided in such a fashion as to cover at least the part of the nozzle opposed to the heater for supplying a second gas containing at least one of the plurality of elements forming the film and not capable of depositing a film by itself into the reaction container after circulating the second gas thereinside. | 2009-01-15 |
20090017639 | NOVEL SILICON PRECURSORS TO MAKE ULTRA LOW-K FILMS OF K<2.2 WITH HIGH MECHANICAL PROPERTIES BY PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION - A method for depositing a low dielectric constant film on a substrate is provided. The low dielectric constant film is deposited by a process comprising reacting one or more organosilicon compounds and a porogen and then post-treating the film to create pores in the film. The one or more organosilicon compounds include compounds that have the general structure Si—C | 2009-01-15 |
20090017640 | BORON DERIVED MATERIALS DEPOSITION METHOD - Methods of forming boron-containing films are provided. The methods include introducing a boron-containing precursor into a chamber and depositing a network comprising boron-boron bonds on a substrate by thermal decomposition or a plasma process. The network may be post-treated to remove hydrogen from the network and increase the stress of the resulting boron-containing film. The boron-containing films have a stress between about −10 GPa and 10 GPa and may be used as boron source layers or as strain-inducing layers. | 2009-01-15 |