03rd week of 2009 patent applcation highlights part 27 |
Patent application number | Title | Published |
20090016041 | ADAPTER AND CONSUMER ELECTRONIC DEVICE FUNCTIONAL UNIT - A functional unit of a consumer electronic device and an adapter. performing a first primary function and mountable to an appliance host performing a second primary function. The adapter includes a main body, a first support component capable of supporting the consumer electronic device, a second support component capable of removably coupling the functional unit to the host, and a third support component capable of alternatively supporting the functional unit on a horizontal surface when the adapter main body is removed from the host. The adapter provides an electromagnetic service to the consumer electronic device selected from a power service and a data service supplied by the adapter. | 2009-01-15 |
20090016042 | Idle control system and method of mounting - An idle control system for a vehicle is provided. | 2009-01-15 |
20090016043 | Cable management arrangement for a telecommunications cabinet - A telecommunications system including a frame to which telecommunications equipment is mounted. The frame defines a patch panel region and an active equipment region. Patch cords are interconnected between the patch panel region and the active equipment region. The system further includes a slack storage panel that stores patch cord slack. The slack storage panel defines a single cable routing pathway. The patch cords are routed through the slack storage panel such that no portion of the length of each patch cord overlaps itself. In systems including both copper and fiber cables, the copper cables are routed separately from the fiber cables. | 2009-01-15 |
20090016044 | INTEGRATED DC CIRCUIT FOR A CEILING FAN COMBINED WITH A LAMP - An integrated DC circuit for a ceiling fan combined with a lamp is composed of a control circuit connected with a motor and a lamp, and a rectifying-filtering circuit connected with the control circuit. The rectifying-filtering circuit can alter an exterior AC power into a DC power for the motor and the lamp to use. As the motor and the lamp use the same DC power, electric leakage can be minimized to upgrade security and only a simplified structure with less material is needed, posing a reduction of cost. | 2009-01-15 |
20090016045 | Surgical headlamp - A surgical headlamp containing lamp housings, each containing multiple LED light sources is featured wherein the LEDs cooperate together to produce a light engine. The lamp housings may be adjusted so that light beams emitted by each LED be selectively converged through a focusing lens at a spot a predetermined distance in front of the lamp housings. Each lamp housing typically contains in addition to the LEDs, one or more focusing lenses to gather and direct the light generated by the LEDs forward to an illuminated work area. Batteries, preferably rechargeable, are mounted in a waist pack external to the headband, and are used to poser the LEDs. A cooling system for cooling the heat generated by the LED's is provided which utilizes a swirling effect of fluid adjacent a heat sink to transfer the heat to the swirling fluid. | 2009-01-15 |
20090016046 | LIGHT SYSTEM AND METHOD FOR CREATING A LOCALIZED LIGHT - The invention relates to the creation of a localized light, particularly to a light system ( | 2009-01-15 |
20090016047 | Compositions and methods for the treatment and prevention of ocular conditions - Methods and devices are described that use one or more thermally responsive current-controlling elements to regulate current flow to an electrical component, particularly a light source such as an LED. Examples of such thermally responsive current-controlling elements include thermistors, inductors, and capacitors. for treating conditions or disorders which can be alleviated by reducing food intake are disclosed which comprise administration of an effective amount of a purine analog, alone or in conjunction with other compounds or compositions that affect satiety. The methods are useful for treating conditions or disorders wherein appetite reduction would be beneficial, including obesity and binge-eating disorder. Pharmaceutical compositions for use in the methods of the invention are also disclosed. | 2009-01-15 |
20090016048 | TORCH LAMP SYSTEMS, FLAME LAMP ASSEMBLIES, AND LAMPS WITH SWIRLING FLAMES - Torch lamp systems and flame lamp assemblies for producing swirling flames are disclosed herein. In one embodiment, a flame lamp assembly for providing a flame having a continuous spiral movement can include a plurality of spaced apart panels and a frame for supporting the panels to form a chamber for housing the flame. The frame can support the panels such that adjacent panels are spaced apart at panel junctions to create a plurality of air intake slots. The plurality of air intake slots can be in communication with the chamber to allow air to flow from an external environment into the chamber at an angle to provide vortical air flow within the chamber. The assembly can also include a burner assembly configured to receive fuel from a fuel source and to provide a fuel flow from a fuel release point to the chamber for ignition to provide the flame. | 2009-01-15 |
20090016049 | Modular utility light - A modularly constructed hand held, utility light is described and taught having a sealed electrical module and a separately attached hand-hold module. The hand-hold module includes two half shells that when assembled and attached to the electric module completes the utility tight. | 2009-01-15 |
20090016050 | BATTERY CARTRIDGE FOR FLASHLIGHT - A battery cartridge has a casing adapted to releasably hold at least one battery, externally accessible contacts on the casing, and internal circuitry in the casing between the contacts and poles of the battery. A switch is mounted in the casing and connected to the circuitry between one of the poles and the respective contacts for controlling current flow therebetween. | 2009-01-15 |
20090016051 | LIGHT EMITTING DEVICE DIFFUSERS FOR GENERAL APPLICATION LIGHTING - An LED diffuser may provide a more deterministic distribution of light from multiple discrete sources without relying on statistical scattering, and therefore, may reduce the type of efficiency losses associated with conventional diffusers as noted above. For example, an LED diffuser may have a smooth external surface that can be both aesthetically pleasing and easily cleanable. In still other embodiments according to the invention, an LED diffuser can include a single multilayer film. Further, an LED diffuser can include a plurality of multi-layer films that can provide additive diffusion properties. An LED diffuser can also be provided as a component of an LED light fixture. | 2009-01-15 |
20090016052 | Apparatus and Method of Using LED Light Sources to Generate a Unitized Beam - An apparatus includes: a plurality of light emitting diodes (LED) of similar or differing wavelengths; a reflector for collecting energy from two or more LEDs into an approximately composite beam; and a housing for distributing this energy into a common aperture. A heat sink and electronic control for the individual LEDs is included. The LEDs have different color outputs and are selectively controlled to determine the color of light from the apparatus. In one embodiment there are at least two LEDs, at least two reflector cavities, a common combining cavity or zone, a mounting each of the LEDs within the reflector cavities and a housing. The LEDs are mounted on the heat sink and selectively driven to modulate the intensity of selected ones of the LEDs according the nature of the frequency bands in the driving signal, e.g. mixed color outputs according to the control of a musical signal. | 2009-01-15 |
20090016053 | Backlight Module Structure and Backlight Module Incorporating Same - A backlight module structure and a backlight module incorporating the structure are provided. The backlight module includes a back plate and at least one light source device. The back plate includes a base and a plurality of projections which are substantially parallel to each other. The projections are disposed on the base and spaced apart from each other to define at least one slot and be placed at a specific height (the first height) relative to the base. The light source device is adapted to fit into the slot. The light source device includes a substrate and a plurality of light sources which are disposed on the substrate and are placed at another specific height (the second height) relative to the base. The first height is substantially equal to or higher than the second height. | 2009-01-15 |
20090016054 | LED night light with projection feature - The current invention for LED night light for night time or dark area use including plug-in wall outlet night light or direct current operated night light with projection features to project the image, message, data, logo, time on ceiling, walls, floor, desired surface. The said LED night light incorporated with optics means may selected from group combination from optics-lens, convex lens, concave lens, openings, cut-outs, film, grating means, hologram means (same as inventor's U.S. Pat. No. 5,667,736) to create the preferred image on the desired location to let viewer to see. | 2009-01-15 |
20090016055 | HIGH-POWER LIGHT EMITTING DIODE (LED) STREET LAMP AND BODY FRAME THEREOF - A high-power light emitting diode (LED) street lamp includes a body frame, a plurality of light emitting diode (LED) modules, and a base unit convexly positioned on the body frame along the light emission direction of the high-power light emitting diode (LED) street lamp. The light emitting diode (LED) modules have a plurality of light emitting diodes (LEDs), and at least one circuit board. The light emitting diodes (LEDs) are electrically connected to the at lease one circuit board to be served as the light emitting diode (LED) modules. The base unit has a plurality of supporting surfaces which support the light emitting diode (LED) modules. The supporting surfaces are symmetrically positioned on a normal direction of an end surface of the base unit, and the light emitting diode (LED) modules are positioned on the adjacent supporting surfaces, respectively. The supporting surfaces further comprise a plurality of first supporting surfaces adjacent to the normal direction of the end surface of the base unit, a plurality of second supporting surfaces adjacent to the first supporting surfaces, and a plurality of third supporting surfaces adjacent to the second supporting surfaces. An angle formed by the first supporting surfaces and the normal direction of the end surface of the base unit is in a range between 76 degrees to 86 degrees. An angle formed by the second supporting surfaces and the normal direction of the end surface of the base unit is in a range between 49 degrees to 59 degrees. An angle formed by the third supporting surfaces and the normal direction of the end surface of the base unit is in a range between 37 degrees to 47 degrees. | 2009-01-15 |
20090016056 | ELECTRONIC DEVICE - Herein disclosed is an electronic device which can have, without deteriorating the effect of notification by light, an extended area to have electronic parts mounted thereon at the portion of the main body | 2009-01-15 |
20090016057 | Incoupling structure for lighting applications - Light incoupling structures for lighting applications, such as lightguides. The incoupling structures include an optically substantially transparent medium for transporting light emitted by a light source and an optical element including at least one hole in the medium for coupling light together with optional further optical elements. A lighting element includes a light source with related integrated optics. | 2009-01-15 |
20090016058 | RING LAMP FOR ILLUMINATING A DELIMITED VOLUME AND THE USE THEREOF - A ring lamp includes a light source having a first hollow cylinder with a lighting device disposed therein. The light source has an emitting surface with a light-emitting direction oriented toward an axis of the hollow cylinder. The lamp also includes a light directing device configured to direct light emission. The light directing device includes a lens system having a lens formed as a second hollow cylinder and configured to focus light into a radial plane which is orthogonal to the axis. The lens system has a ring-shaped aperture diaphragm disposed centrally in an optical path of the light emission behind the lens. The emitting surface of the light source and the lens system have a same length, are coaxial and axially aligned with each other. A radial surface which is defined by an inner radius of the lens system and the length of the lens system spans a delimited volume. | 2009-01-15 |
20090016059 | ILLUMINATION APPARATUS - The illumination apparatus comprises a light source unit which has a LED for emitting illumination light, and a condenser lens for collecting the illumination light, and a main body of the illuminator of the apparatus which holds the light source unit and guides the illumination light. The light source unit comprises a heat dissipation plate which holds LED, and emits the heat emitted from LED | 2009-01-15 |
20090016060 | LIGHTING APPARATUS AND DISPLAY APPARATUS THEREWITH - A lighting apparatus of the present invention is composed of: LED arrays (LL | 2009-01-15 |
20090016061 | ILLUMINATION SYSTEM - An illumination system including a coherent light source, a light integrator and a first actuator is provided. The coherent light source is capable of providing an illumination beam. The light integrator is disposed on a transmission path of the illumination beam, and the first actuator is connected to the light integrator. The light integrator has a light entering end and a light exit end opposite to the light entering end, and the light entering end faces the coherent light source. The first actuator is capable of driving the light integrator to move and/or rotate, so as to change a position at the light entering end entered by the illumination beam. | 2009-01-15 |
20090016062 | LED LAMP - An LED lamp includes a heat dissipation apparatus, an LED module, a bulb and a reflector. The heat dissipation apparatus includes a first heat sink, a second heat sink and a heat conductor positioned between the first heat sink and the second heat sink. The LED module includes a plurality of LEDs mounted on the heat conductor. The bulb is seated on the first heat sink and the reflector is seated on the second heat sink. The reflector and the bulb together form a housing for receiving the LED module and the heat conductor therein. Heat pipes are used to thermally connect the heat conductor and the first and second heat sinks. | 2009-01-15 |
20090016063 | Built-in Heat Diffusion Lamp Body for LED Lamp - A built in beat diffusion lamp body for LED lamp was invented. The purpose of the invention is to solve the difficulties of poor heat conduction and diffusion caused by the small heat diffusion surface of the material of a conventional LED lamp. The lamp body is made of a set of heat diffusion vanes encircling the heat diffusion complex. The vanes and heat diffusion complex are made from Aluminum alloy in a single process of extrusion moulding. The transverse section of the heat diffusion body is volute shaped. The bottom of the heat diffusion complex is fixed to an aluminum board or an aluminum circuit: board by interference fit. The heat generated by the LED elements can be absorbed and diffused by the board, the heat diffusion complex and the surrounding diffusion element. The outward appearance of the heat diffusion lamp body may be shaped into cup, ladder, or cylinder likeness to satisfy the application requirement. The advantages of current invention are: efficient heat absorption, conduction, and diffusion, low cost for manufacturing, and aesthetic appearance. | 2009-01-15 |
20090016064 | HIGH-PRESSURE MERCURY VAPOR DISCHARGE LAMP AND METHOD OF MANUFACTURING A HIGH-PRESSURE MERCURY VAPOR DISCHARGE LAMP - A high-pressure mercury vapor discharge lamp ( | 2009-01-15 |
20090016065 | Reflector for a Lighting Device and Illumination System of a Projection Apparatus - A reflector for the lighting device and an illumination system of the projection apparatus are provided. The reflector comprises a first reflecting structure and a second reflecting structure disposed on the portion of the first reflecting structure. The reflecting surfaces of the first and second reflecting structures are formed with a distance therebetween. After the first portion of the light is reflected from the first reflecting surface and the second portion of the light is reflected from the second reflecting surface, the second portion of the light is adapted to remove the centrally dimmed area at the opening of the lighting device. Thus, the luminance performance can be improved. | 2009-01-15 |
20090016066 | Package Structure for a High-Luminance Light Source - A package structure for a high-luminance light source comprises a circuit board, at least one light source and a resin coating covering the light source. A light refractive layer is formed on a surface of the circuit board and is located correspondingly to the light source, and the light refractive layer is provided for refracting the ineffective light of the light source, so as to turn the ineffective light into effective light, so that the light emitted at different angles from the light source are fully utilized to improve the luminescent efficiency of the light source. | 2009-01-15 |
20090016067 | OPTICAL PLATE AND BACKLIGHT MODULE USING THE SAME - An exemplary optical plate includes at least one transparent plate unit. The transparent plate unit includes a first surface, a second surface, a plurality of enclosing V-shaped protrusions, a diffusion layer and a lamp-receiving portion. The second surface is opposite to the first surface. The enclosing V-shaped protrusions are formed at the first surface. The diffusion layer is formed at the second surface. The lamp-receiving portion is defined in one of the first surface and the second surface. A backlight module using the optical plate is also provided. | 2009-01-15 |
20090016068 | OPTICAL PLATE AND BACKLIGHT MODULE USING THE SAME - An exemplary optical plate ( | 2009-01-15 |
20090016069 | Broad beam light - A high efficiency, broad beam lighting device | 2009-01-15 |
20090016070 | LIGHTING DEVICE - The present invention relates to a lighting device including at least a light source (LS) for emitting light rays and means for guiding said light rays on a projection plane (PP). The guiding means are formed by a lens (OD) presenting a cylindrical portion (CYL) extending along an axis (AX) perpendicular to said projection plane and at least a convex shaped surface (CSH) extending at an extremity of said cylindrical portion. The convex shaped surface is adapted to direct a portion of the light rays emitted from said light source towards said projection plane. The invention enables to project the light towards a projection plane quasi parallel to the beam direction without using any guiding means on the projection plane itself. This solution is consequently relatively compact. | 2009-01-15 |
20090016071 | TAIL LIGHT BRACKET ASSEMBLY - A bracket for controlling the gap between a light housing and bumper on a vehicle, the bracket is provided that includes a first generally flat surface defined by a first bracket leg, a series of second surfaces defined by the first bracket leg and raised above the first surface. The bracket also provides one or more first dual engagement clips supported on the first surface of the first bracket leg to clip a vehicle bumper to the bracket and one or more hooks each supported on a second surface of the first bracket leg allowing engagement of the light housing and bracket. The bracket allows a small uniform gap to be provided between the light housing and bumper and allows the light housing to be removed without removal of the bumper. | 2009-01-15 |
20090016072 | LED LAMP WITH A HEAT DISSIPATION DEVICE - An LED lamp includes a heat sink ( | 2009-01-15 |
20090016073 | Automatic Lighting System with Adaptive Alignment Function - An automatic lighting system for a vehicle includes a detection device, an illumination source and a control. The illumination source is directed generally forwardly with respect to a direction of travel of the vehicle, and has an adjustable principal axis of illumination. The detection device may be operable to determine a gaze direction of a driver or driving instructor of a vehicle or may detect a sign or other object of interest, such as a deer or pedestrian or the like, generally forwardly and sidewardly of the vehicle. The control is operable to adjust the principal axis of illumination of the illumination source in response to an output of the detection device so as to provide enhanced illumination at areas sideward and forward of the vehicle. | 2009-01-15 |
20090016074 | Semiconductor light engine using glass light pipes - A light engine for use in systems such as automotive lighting systems employs two or more semiconductor light sources, such as LEDs. Light emitted from the light sources is captured by light pipes which are mounted such that the light capturing surface of the light pipes are properly positioned, with respect to the semiconductor light sources. The light pipes transfer substantially all of the light captured from the semiconductor light sources to light emitting surfaces of the light pipes which can be appropriately located adjacent the output optics of the lighting system. The light engine can be easily assembled as the light pipes are in modules including a carrier member that can be mounted to a positioning member which also includes apertures to position the light capture surfaces of the light pipes at a known position with respect to the semiconductor light sources. | 2009-01-15 |
20090016075 | SEMICONDUCTOR LIGHTING IN CONSOLE SYSTEM FOR ILLUMINATING BIOLOGICAL TISSUES - The present disclosure is directed to illumination techniques that include the use of one or more sets of Light Emitting Diodes or LEDs as light sources in a console/module system. The LED light sources can be utilized to produce a light beams with a specified/combination of intensity and spectrum. Of course, embodiments according to the present disclosure are not limited to one intensity/spectrum but multiple combinations of intensity and spectrum can be implemented. Such systems/methods can be implemented with various optical elements including filter, lenses, mirrors, and/or optical fibers. The system is controlled by voice activation, touch screen, footswitch or wireless communication. The LEDs might also be pulsed as a driving system. The optical fiber cable is tethered to the control. | 2009-01-15 |
20090016076 | DISPLAY APPARATUS - The invention relates to a display apparatus with a display unit, having means for background lighting at the back of the display apparatus. According to the invention, the means for background lighting comprise two illumination units being provided at the right-hand and left-hand of the display apparatus, said illumination units being formed as substantially vertically positioned, longitudinal light guides comprising means for coupling out light, each of the light guides being provided on at least one of its ends with a light source. The light sources preferably comprise coloured LEDs. | 2009-01-15 |
20090016077 | Light Guiding Member and Linear Light Source Apparatus Using Same - A light guide member of the present invention is made of a light transmitting material. The light guide includes a light emitting surface | 2009-01-15 |
20090016078 | LIGHT VALVE TO ENHANCE DISPLAY BRIGHTNESS - A display system ( | 2009-01-15 |
20090016079 | Planar lighting apparatus - A planar lighting apparatus is provided in which thinning is promoted while higher and more uniform brightness is achieved by maintaining an LED on a light-incoming face of a light guide plate easily and stably. A planar lighting apparatus | 2009-01-15 |
20090016080 | Planar Lighting Apparatus - Higher brightness of a planar lighting apparatus is promoted by improving close contact between a light-emitting face of an LED and a side end face of a light guide plate. | 2009-01-15 |
20090016081 | BACKLIGHT WEDGE WITH ADJACENT REFLECTIVE SURFACES - A backlight includes a visible light transmissive body having a light guide portion and a light input portion. The visible light transmissive body primarily propagates light by TIR and includes a light input surface and a light output surface. The light guide portion has a light reflection surface and a light emission surface. The light input portion has opposing side surfaces that are not parallel. A light source is disposed adjacent to the light input surface and emits light into the light input portion. A specularly reflective layer is disposed adjacent to but not in intimate contact with the opposing side surfaces and reflects more than 80% of visible light incident on the specularly reflective layer. | 2009-01-15 |
20090016082 | Systems and Methods for Frequency Control of a Voltage Converter - Various embodiments of the present invention provide voltage converters and methods for using such. As one example, a voltage converter is disclosed that includes a transformer, an operational detector, and a controllable oscillator. The transformer includes a first winding and a second winding, and the operational detector provides an electrical output corresponding to an operational characteristic of the transformer. The controllable oscillator provides a clock output with a frequency corresponding to the electrical output. This clock output at least in part controls application of a voltage input to the first winding. | 2009-01-15 |
20090016083 | SECONDARY SIDE SYNCHRONOUS RECTIFIER FOR RESONANT CONVERTER - A resonant converter including a primary side switching stage having high- and low-side switches series connected at a switching node and controlled by a primary side controller; a transformer having a primary coil and a secondary coil, the secondary coil having at least one pair of portions series connected at a node, a resonant tank formed by series connecting the primary coil to the switching node with a first inductor and a first capacitor; at least one pair of first and second secondary side switches connected to the at least one pair of portions, respectively, the first and second secondary side switches of each pair being used for synchronous rectification; and a secondary side controller to control and drive the first and second secondary side switches of each pair by sensing voltage across each secondary side switch and determining a turn ON and turn OFF transition for the first and second secondary side switches in close proximity to a point in time when there is zero current through the secondary side switch to achieve synchronous rectification. | 2009-01-15 |
20090016084 | ARRANGEMENT PROVIDED WITH A VOLTAGE CONVERTER FOR SUPPLYING VOLTAGE TO AN ELECTRICAL LOAD AND ASSOCIATED METHOD - An apparatus includes a voltage converter for supplying voltage to an electrical load. The voltage converter is electrically connected at an output to a terminal of a series circuit. The voltage converter includes mechanisms for connecting the electrical load and a current sink. The voltage supplied by the voltage converter is dependent on an input voltage and on a present multiplication factor. The apparatus also includes a first comparator, a second comparator, and selection logic. | 2009-01-15 |
20090016085 | Method and Apparatus for a Charge Pump DC-to-DC Converter Having Parallel Operating Modes - According to one or more aspects of DC-to-DC voltage conversion as taught herein, a DC-to-DC converter selectively operates in a first mode wherein an included linear pass output circuit supplies the output power from the DC-to-DC converter, in a second mode wherein an included charge pump output circuit supplies the output power, and in a third mode wherein the linear pass and charge pump output circuits operate in parallel to supply the output power. With this third mode, also referred to as a “dual” mode, wherein the linear pass and charge pump output circuits operate in parallel, the DC-to-DC converter keeps the more efficient output circuit on after it has begun switching to operation with the less efficient output circuit. Such switchover may be performed dynamically in response to changing operating conditions. Detected operating conditions may include input voltages, output voltages, and output load conditions. | 2009-01-15 |
20090016086 | Secondary side constant voltage and constant current controller - A low-cost integrated circuit is used as a secondary side constant voltage and constant current controller. The integrated circuit has four terminals and two amplifier circuits. A first amplifier circuit is used to sense a voltage on a FB terminal and in response to cause a first current to flow through an OPTO terminal. A second amplifier circuit is used to sense a voltage between a SENSE terminal and a SOURCE terminal and in response to cause a second current to flow through the same OPTO terminal. The FB terminal is used for output voltage feedback and is also used to supply power onto the integrated circuit. The SOURCE terminal is used for output current feedback and is also used as power supply return for the integrated circuit. The cost of the integrated circuit is reduced by having only four terminals. | 2009-01-15 |
20090016087 | Switching power source - An error voltage Verr, as amplified by an amplifier, and an input voltage Vin, are multiplied together by a multiplier to generate a first threshold value signal Vth | 2009-01-15 |
20090016088 | SEMICONDUCTOR ASSEMBLY - A semiconductor assembly is disclosed. One embodiment provides a first semiconductor and a second semiconductor, each having a first main connection and a second main connection arranged on opposite sides, and a carrier having a patterned metallization with a first section spaced apart from a second section. The first semiconductor is electrically connected to the first section by its second main connection, and the second semiconductor electrically connected to the second section by its second main connection. The first semiconductor chip first main connection and the second semiconductor chip first main connection are electrically connected to one another and for the connection of an external load or of an external supply voltage. | 2009-01-15 |
20090016089 | Electromechanical power transfer system with even phase number dynamoelectric machine and three level inverter - An electromechanical power transfer system that converts direct current (DC) electrical power to variable mechanical power, comprises: a source of DC that has a neutral ground, a positive potential output with a level of electrical potential that is positive relative to the neutral ground and a negative potential output with a level of electrical potential that is negative relative to the neutral ground; a multiphase alternating current (AC) dynamoelectric machine with an even number of phases; and a neutral point clamped (NPC) inverter system that receives electrical power from the positive and negative potential outputs the DC source to generate multiphase AC power for the dynamoelectric machine with the same number of even phases that exhibits no common mode potential/noise. | 2009-01-15 |
20090016090 | Synchronous Rectifier and Controller for Inductive Coupling - A synchronous rectifier is arranged to rectify inductively coupled power using FETs (field effect transistors) to minimize the voltage drop of the rectifier, which minimizes power loss. Power loss is an important consideration in applications where fairly significant power is coupled to a device (such as a battery charger or other energy storage device) for a fairly short time (such as less than one hour) at a fairly low voltage (such as around 2.5 to 4.5 volts). Body diodes of the FETs can be used to supply power for bootstrapping and control logic for controlling the FETs. | 2009-01-15 |
20090016091 | Circuit and system for ultrasonic power regulation - A circuit for power regulation of ultrasonic generators comprising a half bridge or full bridge circuit and a regulator circuit that controls or regulates the output power of the bridge circuit by, among other things, subtracting bridge voltage from the +VDC power supply. A full range of bridge circuit output powers are efficiently produced by varying the duty cycle of the drive signal to the switching device in the regulator circuit. | 2009-01-15 |
20090016092 | SEMICONDUCTOR MEMORY DEVICE AND LOCAL INPUT/OUTPUT DIVISION METHOD - A semiconductor memory device includes: a memory cell array that is arrayed on a plurality of mats; an even number of redundancy Y-switch (YS) signal lines that are provided in three mat units and arranged in the bit line direction on the mat that is positioned in the middle among the three mats disposed continuously in the word line direction; a local input/output (LIO) line that is connected to a sense amplifier portion of the three mats, extends in the word line direction, and is divided in two in a redundancy area that is a part of the even number of redundancy Y switch signal lines; and a plurality of bit line selecting Y switch signal lines that connect bit line output of the memory cell array on the three mats to the local input/output line; wherein 8-bit data prefetch is performed from the three mats by selecting the plurality of bit line selecting Y switch signal lines and turning them ON simultaneously so as to connect the selected bit line output to each local input/output line divided in two. | 2009-01-15 |
20090016093 | MEMORY SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT - A ferroelectric memory provided in a memory system stores in advance set data for data write time to memory cells. The set data include two types of data that differ between in a power-on state and in a power-off instruction time. When power is turned on, the set data that are stored in the ferroelectric memory are stored and retained in a latch circuit by a control circuit. Based on the set data retained in the latch circuit, data writing is performed in the ferroelectric memory respectively in the power-on state and in the power-off instruction time. Thus, operations of the ferroelectric memory can be controlled with desired operation timings according to operating conditions for each memory system. Excessive stress application to the ferroelectric memory during the power-on state is prevented and endurance deterioration is suppressed, while data retention characteristics after power-off are improved. | 2009-01-15 |
20090016094 | Selection device for Re-Writable memory - A memory cell including a memory element and a non-ohmic device (NOD) that are electrically in series with each other is disclosed. The NOD comprises a semiconductor based selection device operative to electrically isolate the memory element from a range of voltages applied across the memory cell that are not read voltages operative read stored data from the memory element or write voltages operative to write data to the memory element. The selection device may comprise a pair of diodes that are electrically in series with each other and disposed in a back-to-back configuration. The memory cell may be fabricated over a substrate (e.g., a silicon wafer) that includes active circuitry. The selection device and the semiconductor materials (e.g., poly-silicon) that form the selection device are fabricated above the substrate and are integrated with other thin film layers of material that form the memory cell. | 2009-01-15 |
20090016095 | NON-VOLATILE SRAM MEMORY CELL EQUIPPED WITH MOBILE GATE TRANSISTORS AND PIEZOELECTRIC OPERATION - The present application relates to a non-volatile random-access memory cell equipped with a suspended mobile gate and with piezoelectric means for operating the gate. | 2009-01-15 |
20090016096 | Integrated Circuits; Method for Manufacturing an Integrated Circuit; Method for Decreasing the Influence of Magnetic Fields; Memory Module - Embodiments of the invention relate generally to integrated circuits, to a method for manufacturing an integrated circuit, to a method for decreasing the influence of magnetic fields, and to a memory module. In an embodiment of the invention, an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction may include a free layer with a magnetization orientation that is selected by the application of a write current through the magnetic tunnel junction, and a retention layer that retains the selectable magnetization orientation of the free layer at temperatures below a retention temperature. | 2009-01-15 |
20090016097 | MAGNETOELECTRIC DEVICE AND METHOD FOR WRITING NON-VOLATILE INFORMATION INTO SAID MAGNETOELECTRIC DEVICE - This invention relates to a device comprising at least a first ferromagnetic layer ( | 2009-01-15 |
20090016098 | MAGNETORESISTIVE DEVICE - A method of operating a magnetoresistive device is described. The device comprises a ferromagnetic region configured to exhibit magnetic anisotropy and to allow magnetisation thereof to be switched between at least first and second orientations and a gate capacitively coupled to the ferromagnetic region. The method comprises applying an electric field pulse to the ferromagnetic region so as to cause orientation of magnetic anisotropy to change for switching magnetisation between the first and second orientations. | 2009-01-15 |
20090016099 | Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices - In a memory device and in a method of programming the same, a memory device comprises: a plurality of memory cells, each memory cell comprising a resistance-changeable material that has an initial resistance that is determined in response to an applied programming current in a programming operation; and a modification circuit that modifies the resistance of the memory cell following a programming operation of the memory cell to vary the resistance of the memory cell from the initial resistance to a second resistance by applying a saturation current in a saturation operation. Each memory cell is connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation, that is used to apply the saturation current to the corresponding memory cell in the saturation operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a subsequent read operation. | 2009-01-15 |
20090016100 | Multi-level phase change memory device and related methods - Provided are a phase change memory device and a reading method thereof. An example embodiment of a phase change memory device may include main cells programmed to have any one of a plurality of resistance states respectively corresponding to multi-bit data, reference cells programmed to have at least two respectively different resistance states among the resistance states each time the main cells are programmed, and a reference voltage generation circuit sensing the reference cells to generate reference voltages for identifying each of the resistance states. | 2009-01-15 |
20090016101 | Reading Technique for Memory Cell With Electrically Floating Body Transistor - A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region. | 2009-01-15 |
20090016102 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH STORES MULTI-VALUE INFORMATION - To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information. | 2009-01-15 |
20090016103 | MSB-BASED ERROR CORRECTION FOR FLASH MEMORY SYSTEM - A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result. | 2009-01-15 |
20090016104 | Nonvolatile semiconductor memory device and programming method thereof - A programming method of a multi-bit flash memory device includes programming multi-bit data into selected memory cells through pluralities of programming loops. In each programming loop, an increment of a programming voltage applied to the selected memory cells is varied in accordance with a result of program-verification for each data state of the multi-bit data and reading-verification for a data state is skipped when the program-verification indicates that data state has passed. | 2009-01-15 |
20090016105 | NONVOLATILE MEMORY UTILIZING MIS MEMORY TRANSISTORS CAPABLE OF MULTIPLE STORE OPERATIONS - A nonvolatile semiconductor memory device includes a latch configured to store data, a plurality of word lines, a driver configured to activate one of the plurality of word lines, and a plurality of nonvolatile memory cells coupled to the respective word lines, each of the nonvolatile memory cells coupled to the latch so as to exchange stored data with the latch upon activation of a corresponding one of the word lines, each of the nonvolatile memory cells including two MIS transistors and configured to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors, wherein the driver includes at least one nonvolatile memory cell storing count data responsive to a number of times storing of data has been performed with respect to the plurality of nonvolatile memory cells, and is configured to activate one of the word lines indicated by the count data. | 2009-01-15 |
20090016106 | SUB VOLT FLASH MEMORY SYSTEM - Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system. | 2009-01-15 |
20090016107 | Methods of operating nonvolatile memory devices - Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell. | 2009-01-15 |
20090016108 | NONVOLATILE SEMICONDUCTOR MEMORY - A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage. | 2009-01-15 |
20090016109 | Semiconductor device and its control method - A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the sectors includes a pull-up transistor that is driven by a corresponding one of the decoders via a corresponding one of global word lines connecting the sectors and drives one of the local word lines, and the pull-up transistor is kept OFF by the control signal. | 2009-01-15 |
20090016110 | METHODS OF READING DATA FROM NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A method of reading data in a non-volatile memory device includes applying a bit line read voltage to a bit line and a selected cell read voltage to a word line, both of which are electrically connected to a selected cell located in a selected string. A first read voltage is applied to word lines electrically connected to first non-selected cells separated from the selected cell in the selected string, and a second read voltage is applied to word lines electrically connected to second non-selected cells adjacent to the selected cell in the selected string. The second read voltage is lower than the first read voltage. A pass voltage is applied to turn on a string select transistor and a ground select transistor, respectively, in the selected string. An electrical signal output from the selected string is compared with a standard signal to read data stored in the selected cell. | 2009-01-15 |
20090016111 | Flash memory device and program recovery method thereof - A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to non-selected word lines, the second voltage being lower than the first voltage, lowering the first voltage of the selected word line to a third voltage after programming the memory cells connected to the selected word line, the third voltage being lower than the first voltage, and recovering a fourth voltage of the selected word line and the non-selected word lines, the fourth voltage being lower than the second and third voltages. | 2009-01-15 |
20090016112 | Method of Programming a Flash Memory Device - A non-volatile memory device includes an array of flash memory cells therein and a voltage generator. The voltage generator is configured to generate a program voltage (Vpgm), a pass voltage (Vpass), a blocking voltage (Vblock) and a decoupling voltage (Vdcp) during a flash memory programming operation. The blocking voltage is generated at a level that inhibits inadvertent programming of an unselected memory cell(s). This voltage level of the blocking voltage is set so that Vdcp2009-01-15 | |
20090016113 | NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE - Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate. | 2009-01-15 |
20090016114 | CIRCUIT AND METHOD OF GENERATING HIGH VOLTAGE FOR PROGRAMMING OPERATION OF FLASH MEMORY DEVICE - Provided is a high voltage generator for a flash memory device including a voltage pumping unit configured to generate a high voltage in response to a pumping clock signal, a transistor having a gate coupled to the high voltage and a source coupled to a program voltage, a voltage distributor coupled to the drain of the transistor, the voltage distributor configured to generate a distributor voltage, and a pumping clock controller configured to compare the distributor voltage to a reference voltage and to generate the pumping clock signal when the high voltage is less than a voltage substantially equal to the program voltage plus the threshold voltage of the transistor. | 2009-01-15 |
20090016115 | TESTING NON-VOLATILE MEMORY DEVICES FOR CHARGE LEAKAGE - A method of and apparatus for testing a floating gate non-volatile memory semiconductor device comprising an array of cells including floating gates for storing data in the form of electrical charge. The method includes applying a test pattern of said electrical charge to the floating gates, exposing the device to energy to accelerate leakage of the electrical charges out of the cells, and subsequently comparing the remaining electrical charges in the cells to the test pattern. The energy is applied in the form of electromagnetic radiation of a wavelength such as to excite the charges in the floating gates to an energy level sufficient for accelerating charge loss from the floating gates of defective cells relative to charge loss from non-defective cells. The wavelength is preferably in the range of 440 to 560 nm. | 2009-01-15 |
20090016116 | Method of Programming and Erasing a Non-Volatile Memory Array - A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory cells that can be processed simultaneously is determined, based on the selected voltage and characteristics of the memory cells and the circuit. The array is divided into processing groups, each group having a number of cells less than or equal to the maximum determined number. Finally, the voltage is applied to the cells. | 2009-01-15 |
20090016117 | HIGH-SPEED VERIFIABLE SEMICONDUCTOR MEMORY DEVICE - A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing. | 2009-01-15 |
20090016118 | NON-VOLATILE DRAM WITH FLOATING GATE AND METHOD OF OPERATION - A non-volatile capacitor-less 1T DRAM has a semiconductor substrate of a first conducting type with a surface. A first region of a second conductivity type is in the substrate on the surface. A second region of the second conductivity type is in the substrate on the surface, spaced apart from the first region. A body region of the first conductivity type is in the substrate between the first region and the second region. The body region is bound by the surface, one or more insulating regions and the first and second regions. The DRAM further has a floating gate insulated from the surface and is positioned between the first region and the second region. A control gate is capacitively coupled to the floating gate. | 2009-01-15 |
20090016119 | Memory device performing write leveling operation - A memory device includes a multiplexing unit, a pipe latch unit, and an output driver. The multiplexing unit outputs data input from global input/output lines in a normal mode and outputs write leveling data in a writing leveling mode being entered in response to a write leveling signal. The pipe latch unit latches the data outputted from the multiplexing unit and outputting the latched data. The output driver outputs the latched data outputted from the pipe latch unit. | 2009-01-15 |
20090016120 | Synchronous semiconductor device and data processing system including the same - A synchronous semiconductor device includes: input buffers; a latch-signal generating circuit that generates a latch signal based on a clock signal; latch circuits that latch an address signal in response to the latch signal; delay circuits that supply the latch circuits with the address signal in synchronism with the latch signal; NOR gate circuits that inactivate the address signal in response to a chip select signal becoming inactive, the NOR gate circuits being arranged between the input buffers and the delay circuits. According to the present invention, without stopping an operation of the input buffers or an internal clock signal, consumed power generated between the input buffers and the latch circuits can be effectively reduced. | 2009-01-15 |
20090016121 | SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF - When a predetermined code is set to a mode register, a switching signal generating circuit is activated, and a switching signal TCLKE becomes at a high level. When the switching signal TCLKE becomes at a high level, input data supplied from a data input and output terminal DQ is used as an internal clock ICLK. Accordingly, during a test in a wafer state, a clock signal can be received from the data input and output terminal DQ, even when a clock terminal, an address terminal, and a command terminal are connected in common to plural semiconductor memory devices. Therefore, a code for artificially performing a fine adjustment of a reference voltage can be individually supplied for each chip. | 2009-01-15 |
20090016122 | DUAL WORD LINE OR FLOATING BIT LINE LOW POWER SRAM - Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge level during operations in which a logic one is read from the anti-parallel storage circuit. | 2009-01-15 |
20090016123 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main I/O equalizer performing precharge of the common signal line pair, and a control circuit determining whether the precharge operation is continued irrespective of a signal level of a mask signal input from an outside. | 2009-01-15 |
20090016124 | Semiconductor memory device having on-die-termination device and operation method thereof - A semiconductor memory device is capable of stably securing an on-die-termination (ODT) latency in spite of PVT variations and various operating speeds. The semiconductor memory device includes a plurality of termination resistors connected to an output pad in series and parallel, a drive controller, a delay path, and a delay control signal generator. The drive controller activates/inactivates the plurality of termination resistors in response to a driving control signal. The delay path delays a termination command by a delay time corresponding to an on-die-termination (ODT) latency to output the driving control signal, wherein the termination command is converted into a delay locked loop (DLL) clock domain signal. The delay control signal generator controls a conversion point of the termination command into the DLL clock domain signal. | 2009-01-15 |
20090016125 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device can determine whether control for supplying termination resistances is normally performed or not by applying a test signal. The device includes a termination resistance driving controller configured to receive a plurality of termination resistance setting signals in synchronization with an external clock and a delay locked loop (DLL) clock to output a plurality of pre-driving signals and a plurality of termination resistance driving signals for a predetermined time. A data pre-driver is configured to output data in synchronization with the external clock. A test driving detector is configured to drive output nodes to a predetermined voltage level in response to a test signal and the plurality of pre-driving signals. A data output buffer is configured to apply termination resistances corresponding to the plurality of termination resistance driving signals to input/output pads, and output the data from the output nodes to the input/output pads. | 2009-01-15 |
20090016126 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed. | 2009-01-15 |
20090016127 | DUTY DETECTION CIRCUIT, DLL CIRCUIT USING THE SAME, SEMICONDUCTOR MEMORY CIRCUIT, AND DATA PROCESSING SYSTEM - A duty detection circuit includes discharge transistors, charge transistors, detection lines, and a comparator circuit that detects a potential difference of these detection lines, and also includes a gate circuit that controls the discharge transistors and the charge transistors in response to the internal clock signal of an even cycle. As a result, the detection lines are charged and discharged in response to the internal clock signal of the even cycle. Consequently, the duty detection circuit can be applied to a multi-phase DLL circuit, and a potential difference appearing in the detection line can be sufficiently secured. | 2009-01-15 |
20090016128 | Semiconductor integrated circuits and non-volatile memory devices including semiconductor integrated circuits - A semiconductor integrated circuit may include: a mode register and a clock delay control circuit. The mode register may store latency information corresponding to a plurality of frequencies. The clock delay control circuit may generate a delay clock signal using an external clock signal and the latency information. The delay clock signal may be used to control a timing margin of output data read during synchronous burst read operations of a non-volatile memory. A non-volatile memory device may include the semiconductor integrated circuit and a data output unit. The data output unit may use the delay clock signal to control the timing margin of the output data read during synchronous burst read operations. A memory system may include the semiconductor integrated circuit. A computing system may the semiconductor integrated circuit, as well as one or more of a memory controller, bus, modem, microprocessor, user interface, and battery. | 2009-01-15 |
20090016129 | DESIGN STRUCTURE FOR INCREASING FUSE PROGRAMMING YIELD - A design structure which enables e-fuse memory repair. The design structure uses a compressed bit string to generate another bit string based on a select value. The select value provides instructions to an encoding logic element, which generates a second bit string. For example, the select value may instruct the encoding logic to create a duplicate copy of each bit in the compressed bit string to generate a 2n-bit string. Once the fuses are programmed using the second bit string, the fuse values are read out as a third string, which is decoded by a decoding logic element according to the select value, thereby improving memory repair. | 2009-01-15 |
20090016130 | MEMORY DEVICE AND METHOD OF TESTING A MEMORY DEVICE - In a method of testing a memory device, an output path of the memory device and an input path of the memory device are coupled to each other. A signal is transmitted, controlled by a test pattern, via the output path of the memory device. The signal is received via the input path of the memory device and evaluated. | 2009-01-15 |
20090016131 | BIT LINE SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A bit line sense amplifier circuit for use in a semiconductor memory device, and a control method thereof, in which the bit line sense amplifier circuit is controlled to maintain a precharge state thereof until a sense amplifier enable signal to enable the sense amplifier circuit is applied, thereby preventing the bit line sense amplifier circuit of the semiconductor memory device from floating, and preventing or substantially reducing a coupling effect, thereby providing a precise data sensing and amplification operation. | 2009-01-15 |
20090016132 | Semiconductor memory devices, memory systems and computing systems including the same - A semiconductor memory device includes a reference current generating circuit configured to generate a bias signal in response to a precharge signal during a precharge operation. Each of a plurality of sense amplifier circuits is connected to a corresponding one of a plurality of bit lines. Each sense amplifier is configured to precharge a corresponding bit line in response to the bias signal. The reference current generating circuit is configured to maintain the bias signal at a level higher than a voltage of the bit lines, but lower than a supply voltage during a sensing operation. | 2009-01-15 |
20090016133 | SEMICONDUCTOR MEMORY AND SYSTEM - A first precharge circuit couples a bit line pair to a precharge voltage line in a standby period, and separates at least an access side of the bit line pair from the precharge voltage line in accordance with operation start of a word line driving circuit. A sense amplifier amplifies a voltage difference of a node pair after the operation start of the word line driving circuit. A switch circuit is provided between the bit line pair and the node pair. The switch circuit has coupled the access side of the bit line pair to an access side of the node pair at an instant of the operation start of the word line driving circuit, and has separated a non-access side of the bit line pair from a non-access side of the node pair at an instant of operation start of the sense amplifier. | 2009-01-15 |
20090016134 | SEMICONDUCTOR MEMORY DEVICE - This disclosure concerns a semiconductor memory comprising memory cells; word lines connected to gates of the cells; n bit lines connected to the memory cells; sense amplifiers connected to the bit lines; refresh cells provided to correspond to the word lines, respectively, and provided to correspond to k bit lines, where k is a natural number smaller than n, one of the refresh cells storing therein refresh data indicating whether to perform a refresh operation on k memory cells out of the plural memory cells connected to a corresponding word line out of the plural word lines and connected to the k bit lines, respectively; a refresh sense amplifier reading the refresh data; and a refresh selection part provided to correspond to the refresh sense amplifier, and selecting whether to perform the refresh operation on the k memory cells according to the refresh data read by the refresh sense amplifier. | 2009-01-15 |
20090016135 | OSCILLATING DEVICE, METHOD OF ADJUSTING THE SAME AND MEMORY - An oscillating device including: an oscillator generating an oscillation signal according to an enable signal; a counter counting an oscillation number of the oscillation signal and being able to reset at the oscillation number indicated by a first signal; and a comparator comparing the counted oscillation number and a reference number, is provided. | 2009-01-15 |
20090016136 | OSCILLATION DEVICE, METHOD OF OSCILLATION, AND MEMORY DEVICE - An oscillation device includes a first setting unit that outputs an oscillation period designation signal, a calculating unit that performs an arithmetic operation on the oscillation period designation signal, and an oscillating unit that generates an oscillation signal having a period based on the oscillation period designation signal subjected to the arithmetic operation. | 2009-01-15 |
20090016137 | Memory Controller with Programmable Regression Model for Power Control - A memory controller uses a throttling mechanism which estimates a throttling delay for achieving a target power consumption, and periodically blocks all memory commands for a number of clock cycles corresponding to the throttling delay. Idle memory ranks of the memory device are powered down while the memory commands are blocked. A regression model bases the throttling delay on a plurality of operating factors and a plurality of regression coefficients for the operating factors. In the illustrative implementation the operating factors include power consumption, a current number of bank conflicts, a current number of read commands, and a current number of write commands. Different sets of regression coefficients can be programmably stored for use with different system configurations. | 2009-01-15 |
20090016138 | MEMORY CELLS WITH POWER SWITCH CIRCUIT FOR IMPROVED LOW VOLTAGE OPERATION - Static random access memory (SRAM) cells and methods of operation are provided which may be used to provide improved writeability and stability to support low voltage operation of memory devices. For example, in one implementation, by temporarily interrupting the connection between portions of an SRAM cell and a power source such as a reference voltage or current source, the writeability of SRAM cells can be improved. Additional read port implementations are also provided to facilitate low voltage operation. In another implementation, a power switch circuit responsive to a word line and logic signals may be used to provide such interruptions. | 2009-01-15 |
20090016139 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line. | 2009-01-15 |
20090016140 | DYNAMIC VOLTAGE ADJUSTMENT FOR MEMORY - A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit. | 2009-01-15 |