| 02nd week of 2010 patent applcation highlights part 57 |
| Patent application number | Title | Published |
|---|
| 20100011155 | Data processor with flash memory, and method for accessing flash memory - A data processor includes a flash memory that stores a plurality of types of data therein, a random access memory that stores record data information therein, and a controller that can access the flash memory and the RAM. The record data information indicates a head address in the flash memory and a data length corresponding to latest data of each of the plurality of types of data. The controller reads, from the flash memory, the latest data of a type of a reading target among the plurality of types of data, with reference to the record data information. | 2010-01-14 |
| 20100011156 | MEMORY DEVICE AND MANAGEMENT METHOD OF MEMORY DEVICE - A memory device includes a plurality of blocks, and the plurality of blocks may include a plurality of pages. The memory device may translate an external physical address into internal physical address using a non-volatile address translation memory. The memory device may access one page of a plurality of pages using the internal physical address. | 2010-01-14 |
| 20100011157 | DEVICE AND METHOD FOR BACKING UP DATA ON NON- VOLATILE MEMORY MEDIA, OF THE NAND FLASH TYPE, DESIGNED FOR ONBOARD COMPUTERS - The present invention relates to a device making it possible to manage a flash memory component designed for onboard computers notably in the aviation field. In particular, the invention makes it possible to use NAND flash memory media in fields such as aviation, by virtue of its judicious organisation and management of the flash memory components. On the one hand it makes it possible to optimise and on the other hand to control the lifetime of the flash memories. | 2010-01-14 |
| 20100011158 | MEMORY CONTROLLER, MEMORY SYSTEM, AND CONTROL METHOD FOR MEMORY SYSTEM - A memory controller for performing processing for writing data in an interleaved manner and in units of pages in a semiconductor memory section made up of chip | 2010-01-14 |
| 20100011159 | COMBINED MOBILE DEVICE AND SOLID STATE DISK WITH A SHARED MEMORY ARCHITECTURE - A mobile device includes a system-on-chip (SOC) that includes a mobile device control module, a solid state disk (SSD) control module, and a random access memory (RAM) control module. The mobile device control module executes application programs for the mobile device. The solid-state disk (SSD) control module controls SSD operations. The RAM control module communicates with the mobile device control module and the SSD control module and stores both SSD-related data and mobile device-related data in a single RAM. | 2010-01-14 |
| 20100011160 | Method and system for providing security to processors - There are various methods of securing programs and data on a processor. The external address enable pin of the processor is sampled upon a power-on or reset to the processor, to determine whether or not accesses to external memory are allowed. Other changes to the external address enable pin are thereafter ignored. In addition, if it is determined that an internal memory access is occurring, the contents of such an access can be masked to prevent unauthorized viewing of the memory contents via an external memory bus. In addition, a programmable security bit may be set to disable the dumping of flash memory contents, allowing only the erasing of the flash memory. | 2010-01-14 |
| 20100011161 | Memory emulation using resistivity sensitive memory - Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as HDD, DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another. | 2010-01-14 |
| 20100011162 | METHOD AND SYSTEM FOR PERFORMING RAID LEVEL MIGRATION - A RAID level migration system and method are provided that enable RAID level migration to be performed without the use of a hardware RAID controller with NVRAM for storing the migration parameters. Eliminating the need for a hardware controller having NVRAM significantly reduces the costs associated with performing RAID level migration. The system and method are capable of migrating from any arbitrary RAID level to any other arbitrary RAID level. | 2010-01-14 |
| 20100011163 | PORTABLE DEVICE FOR MANAGING MEMORY CARDS - A portable device includes n (n≧2) electrical sockets, each of which is configured to accommodate and to electrically engage a removable external memory card; an input device for selecting accommodated and electrically engaged external memory cards for data reading; and an output device for outputting information that is derived from or related to data read from such selected electrically engaged external memory cards. The information may pertain to digital content of the selected external memory card, to the identity of the selected external memory card, or to the storage capacity of the selected external memory card. | 2010-01-14 |
| 20100011164 | MEMORY SYSTEMS AND METHODS OF INITIALLIZING THE SAME - A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative card address (RCA) prior to initialization of the memory system. The host processor is configured to sequentially access each memory card using the default RCA, and to change the default RCA to a unique RCA upon each sequential access. | 2010-01-14 |
| 20100011165 | CACHE MANAGEMENT SYSTEMS AND METHODS - A multi mode cache system that uses a direct mapped cache scheme for some addresses and an associative cache scheme for other addresses. | 2010-01-14 |
| 20100011166 | Data Cache Virtual Hint Way Prediction, and Applications Thereof - A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed. | 2010-01-14 |
| 20100011167 | Heterogeneous processors sharing a common cache - A multi-core processor providing heterogeneous processor cores and a shared cache is presented. | 2010-01-14 |
| 20100011168 | METHOD AND APPARATUS FOR CACHE FLUSH CONTROL AND WRITE RE-ORDERING IN A DATA STORAGE SYSTEM - Methods and apparatus for cache flush control and write re-ordering in a data storage system are provided. A cache flush control method includes cache flushing information stored in a cache memory to a first storage apparatus of a plurality of storage apparatuses included in a data storage system when a cache flush condition is generated, and performing a write command in a second storage apparatus of the plurality of storage apparatuses which has a write speed lower than the first storage apparatus according to information stored in the first storage apparatus processed with the cache flush. | 2010-01-14 |
| 20100011169 | CACHE MEMORY - Disclosed is a cache memory, design structure, and corresponding method for improving cache performance comprising one or more cache lines of equal size, each cache line adapted to store a cache block of data from a main memory in response to an access request from a processor; and a predict buffer, of size equal to the size of the cache lines, configured to store a next block of data from said main memory in response to a predict-fetch signal generated using at least one previous access request. | 2010-01-14 |
| 20100011170 | CACHE MEMORY DEVICE - A cache memory device includes an address generation unit, a data memory, a tag memory, and a hit judging unit. The address generation unit generates a prefetch index address included in a prefetch address based on an input address supplied from a higher-level device. The tag memory stores a plurality of tag addresses corresponding to a plurality of line data stored in the data memory. Further, the tag memory comprises a memory component that is configured to receive the prefetch index address and an input index address included in the input address in parallel and to output a first tag address in accordance with the input index address and a second tag address in accordance with the prefetch index address in parallel. The hit judging unit performs cache hit judgment of the input address and the prefetch address based on the first tag address and the second tag address. | 2010-01-14 |
| 20100011171 | CACHE CONSISTENCY IN A MULTIPROCESSOR SYSTEM WITH SHARED MEMORY - A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state. | 2010-01-14 |
| 20100011172 | MICROCONTROLLER SYSTEMS HAVING SEPARATE ADDRESS AND DATA BUSES - A microcontroller system includes at least one processor and at least one storage unit for storing data received from or to be sent to the processor. At least two read clients are provided in the processor for retrieving data from the storage unit, and at least one write client is provided in the processor for writing data in the storage unit. The system further includes a memory device provided in the storage unit for storing data, and an arbitration device provided in the storage unit for enabling access to the memory device by the read and the write client. The read clients each have a dedicated read address line connected to the arbitration device for sending a read address of read data to be retrieved from the memory device, and a shared read data bus connected to the memory device for receiving the read data from the read address. | 2010-01-14 |
| 20100011173 | Downgrade Memory Apparatus, and Method for Accessing a Downgrade Memory - A method for accessing a downgrade memory and a downgrade memory apparatus are provided. The downgrade memory apparatus comprises at least one management unit and a controller. The management unit comprises a plurality of blocks, each block having a plurality of pages, and each page having a plurality of sectors, the downgrade memory having a plurality of non-accessible sectors. The controller is configured to parse a write command corresponding to a special block, to select at least one accessible sector according to a status information of the special block and to program the write command to the special block, wherein the status information indicates at least one non-accessible sector in the special block. Thereby the method and the apparatus of downgrade memory may as well omit the non-accessible sectors as enhance the usage memory capacity in accordance with the status information. | 2010-01-14 |
| 20100011174 | MIXED DATA RATES IN MEMORY DEVICES AND SYSTEMS - Mixed data rates in a memory system is disclosed. The system includes at least one semiconductor memory device and another device defining a ring topology. The semiconductor memory device includes input circuitry for receiving a clock signal having a frequency at least substantially equal to a frequency x. A first set of circuit elements are each clocked by a same or respective first internal signal having a frequency at least substantially equal to the frequency x. A second set of circuit elements are each clocked by a same or a respective second internal signal having a frequency at least substantially double that of the frequency x. | 2010-01-14 |
| 20100011175 | SEMICONDUCTOR INTEGRATED CIRCUIT AND ACCESS CONTROLLING METHOD OF SEMICONDUCTOR MEMORY - An area detection unit detects a main rectangular area to which an access start address indicated by one-dimensional access information is included among main rectangular areas corresponding to two-dimensional access information. An address conversion unit divides the detected main rectangular area into sub rectangular areas, detects a sub rectangular area to which the access start address indicated by the one-dimensional access information is included, and converts the one-dimensional access information into first two-dimensional access information based on a relative position of the sub rectangular area being detected. A memory controller receives the first and second two-dimensional access information, and converts the two-dimensional access information into an access address. Accordingly, a modification of a memory controller accessing a semiconductor memory by receiving the two-dimensional access information becomes unnecessary. As a result, existing design properties can be effectively utilized, and a development period of a system can be reduced. | 2010-01-14 |
| 20100011176 | Performance of binary bulk IO operations on virtual disks by interleaving - A method and system are provided for executing a binary bulk input/output (IO) operation on a first virtual disk and a second virtual using interleaving. The performance improvement due to the method is expected to increase as more information about the configuration of the virtual disks and their implementation are taken into account. Aspects of a binary bulk IO operation, which distinguish it from a unary bulk IO operation, are collection of information regarding both virtual disks and consideration of performance factors on both virtual disks, individually and jointly. Performance factors considered may include contention among tasks implementing the parallel process, load on the storage system(s) from other processes, performance characteristics of components of the storage system(s), and the virtualization relationships (e.g., mirroring, striping, and concatenation) among physical and virtual storage devices within the virtual configuration. | 2010-01-14 |
| 20100011177 | METHOD FOR MIGRATION OF SYNCHRONOUS REMOTE COPY SERVICE TO A VIRTUALIZATION APPLIANCE - A method, system, computer program product, and computer program storage device for receiving and processing I/O requests from a host device and providing data consistency in both a primary site and a secondary site, while migrating a SRC (Synchronous Peer to Peer Remote Copy) from a backend storage subsystem to a storage virtualization appliance. While transferring SRC from the backend storage subsystem to the storage virtualization appliance, all new I/O requests are saved in both a primary cache memory and a secondary cache memory, allowing a time window during which the SRC at the backend storage subsystem can be stopped and the secondary storage device is made as a readable and writable medium. The primary cache memory and secondary cache memory operates separately on each I/O request in write-through, read-write or no-flush mode. | 2010-01-14 |
| 20100011178 | SYSTEMS AND METHODS FOR PERFORMING BACKUP OPERATIONS OF VIRTUAL MACHINE FILES - Backup systems and methods are disclosed for a virtual computing environment. Certain examples include a system having a backup management server that communicates with a host server having at least one virtual machine. The management server coordinates with the host server to perform backup copies of entire virtual machine disks from outside the guest operating system of the virtual machine. In certain examples, such backup systems further utilize a volume shadow copy service executing on the host server to quiesce virtual machine applications to put data in a consistent state to be backed up. The backup system then utilizes hypervisor snapshot capabilities of the host server to record intended changes to the virtual machine disk files while such files are being copied (e.g., backed up) by the host server. Such recorded changes can be later committed to the virtual machine disk files once the backup operation has completed. | 2010-01-14 |
| 20100011179 | REMOTE COPY SYSTEM AND METHOD - A remote copy system includes a first storage device performing data transmission/reception with a host computer, a second storage device receiving data from the first storage device, and a third storage device receiving data from the second storage device. The first storage device includes a logical volume, the second storage device includes a logical volume being a virtual volume, and the third storage device includes a logical volume. The first storage system changes the state of a first pair of the logical volumes based on the state of a second pair of the logical volumes. With such a remote copy system and a method for use therein, any data backup failure can be prevented. | 2010-01-14 |
| 20100011180 | INFORMATION PROCESSING APPARTAUS, CONTENT CONTROL METHOD, AND STORAGE MEDIUM - According to one embodiment, a storage medium configured to be connectable to apparatuses for processing an encrypted content, the medium stores a content key of the encrypted content, and a copy control list includes information indicating one of the apparatuses which is a copying destination of the encrypted content. | 2010-01-14 |
| 20100011181 | Methods for synchronizing storage system data - In accordance with one example, a method for comparing data units is disclosed comprising generating a first digest representing a first data unit stored in a first memory. A first encoded value is generated based, at least in part, on the first digest and a predetermined value. A second digest representing a second data unit stored in a second memory different from the first memory, is generated. A second encoded value is derived based, at least in part, on the second digest and the predetermined value. It is determined whether the first data unit and the second data unit are the same based, at least in part, on the first digest, the first predetermined value, the first encoded value, and the second digest, by first processor. If the second data unit is not the same as the first data unit, the first data unit is stored in the second memory. | 2010-01-14 |
| 20100011182 | Techniques For Scheduling Requests For Accessing Storage Devices Using Sliding Windows - A system includes a storage device and a scheduler. The scheduler determines if deadlines of requests for accessing the storage device fall within first and second sliding windows. The scheduler issues requests that are in the first sliding window in a first order of execution and requests that are in the second sliding window in a second order of execution. | 2010-01-14 |
| 20100011183 | METHOD AND DEVICE FOR ESTABLISHING AN INITIAL STATE FOR A COMPUTER SYSTEM HAVING AT LEAST TWO EXECUTION UNITS BY MARKING REGISTERS - A method for establishing an initial state in a computer system having at least two execution units, a switchover between a performance mode and a compare mode being performed, and during the switchover from the performance mode to the compare mode, an initial state for the compare mode being generated, wherein memories or memory areas that are potentially to be adapted for the initial state are provided with an identifier that indicates whether or not the data and/or instructions in these memories or memory areas must be modified for the initial state. | 2010-01-14 |
| 20100011184 | MANAGEMENT METHOD AND A MANAGEMENT SYSTEM FOR VOLUME - It is made possible to update information registered in a database of iSNS, SLP and the like in response to a configurational change in a storage device, and for a host computer to discover a disk volume. In response to changes in contents of operation to alter a storage configuration such as in creating or deleting a volume or LUN, contents of the alteration are reflected in the database of iSNS or SLP. Also, in response to a change in setting of LUN masking, a discovery domain of iSNS or attribute values of SLP are updated so that the host computer can discover the disk volume. Also, objects and services are reregistered periodically according to a registration period of iSNS or lifetime of SLP to prevent registered contents from expiring. | 2010-01-14 |
| 20100011185 | STORAGE SYSTEM AND METHOD FOR STORAGE CAPACITY CHANGE OF HOST-DEVICE-SPECIFIED DEVICE - A controller in a storage system receives a capacity change command specifying a device, and changes, to a volume capacity value indicating a storage capacity following the capacity change command, a volume capacity value of a virtual volume associated with the device specified in management information, which includes the volume capacity value indicating a storage capacity of the virtual volume. As such, without increasing or decreasing the number of logical volumes associated with a device provided by a host device, the device can be changed in storage capacity. | 2010-01-14 |
| 20100011186 | SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE - A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system. | 2010-01-14 |
| 20100011187 | Performance enhancement of address translation using translation tables covering large address spaces - An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators. | 2010-01-14 |
| 20100011188 | MICROPROCESSOR THAT PERFORMS SPECULATIVE TABLEWALKS - A microprocessor performs a speculative page tablewalk. The microprocessor includes a tablewalk engine that determines whether at least one of a predetermined set of conditions exists with respect to characteristics of the page of memory whose physical address specified by a memory access instruction is missing in the TLB, performs operations of the tablewalk in an out-of-order manner with respect to the execution of unretired program instructions older than the memory access instruction while none of the predetermined set of conditions exists, and waits to perform the operations of the tablewalk until the microprocessor has retired all program instructions older than the memory access instruction when at least one of the predetermined set of conditions exists. The predetermined set of conditions may include the tablewalk needing to load information from a strongly-ordered page, update page mapping information, or access a global page. | 2010-01-14 |
| 20100011189 | INFORMATION PROCESSING DEVICE AND METHOD FOR DESIGNING AN INFORMATION PROCESSING DEVICE - An information processing device includes a plurality of processor cores each including a plurality of transistors, and at least one substrate bias circuit that supplies each of the plurality of transistors with a substrate bias voltage that is determined based on the number of the processor cores. | 2010-01-14 |
| 20100011190 | DECODING MULTITHREADED INSTRUCTIONS - A microprocessor capable of decoding a plurality of instructions associated with a plurality of threads is disclosed. The microprocessor may comprise a first array comprising a first plurality of microcode operations associated with an instruction from within the plurality, the first array capable of delivering a first predetermined number of microcode operations from the first plurality of microcode operations. The microprocessor may further comprise a second array comprising a second plurality of microcode operations, the second array capable of providing one or more of the second plurality of microcode operations in the event that the instruction decodes into more than the first predetermined number of microcode operations. The microprocessor may further comprise an arbiter coupled between the first and second arrays, where the arbiter may determine which thread from the plurality of threads accesses the second array. | 2010-01-14 |
| 20100011191 | DATA PROCESSING DEVICE WITH INSTRUCTION TRANSLATOR AND MEMORY INTERFACE DEVICE TO TRANSLATE NON-NATIVE INSTRUCTIONS INTO NATIVE INSTRUCTIONS FOR PROCESSOR - A data processing device includes a processor core, and a memory interface portion arranged between the processor core and an external memory mapped into a predetermined external memory space. The memory interface portion includes a fetch circuit for receiving an address value for access to the external memory space from the processor core, and fetching the data at the address in the external memory, a translator for translating the normative instruction fetched from the external memory into the native instruction, and a select circuit for selectively applying the data read from the external memory space and the instruction prepared by translating the instruction read from the external memory space by the translator to the processor core depending on whether the address value for the access to the external memory space is in a predetermined region or not. | 2010-01-14 |
| 20100011192 | SIMPLIFYING COMPLEX DATA STREAM PROBLEMS INVOLVING FEATURE EXTRACTION FROM NOISY DATA - Methods, systems and computer program products for simplifying complex data stream problems involving feature extraction from noisy data. Exemplary embodiments include a method for processing a data stream, including applying multiple operators to the data stream, wherein an operation by each of the multiple operators includes retrieving the next chunk for each of set of input parameters, performing digital processing operations on a respective next chunk, producing sets of output parameters and adding data to one or more internal data stores, each internal data store acting as a data stream source. | 2010-01-14 |
| 20100011193 | Selective Hardware Lock Disabling - Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire the LAO, a unit to cause the ROB to selectively disable the lock, and a unit to snoop a buffer. The apparatus may, based on the snooping, selectively abort a transaction associated with the CS. | 2010-01-14 |
| 20100011194 | STATE AS A FIRST-CLASS CITIZEN OF AN IMPERATIVE LANGUAGE - A state component saves a present state of a program or model. This state component can be invoked by the program or model itself, thereby making state a first-class citizen. As the state of the program evolves from the saved state, the saved state remains for reflection and recall, for example, for testing, verification, transaction processing, etc. Using a state reference token, the saved state of the program or model can be accessed by the program or model. For example, the program or model by utilizing a state component, can return itself to the saved state. After returning to the saved state, a second execution path can be introduced without requiring re-execution of the actions leading to the saved state. In another example, the state space of an executing model is saved in order to generate inputs required to exercise a program or model. | 2010-01-14 |
| 20100011195 | PROCESSOR - A processor includes a plurality of executing sections configured to simultaneously execute instructions for a plurality of threads, an instruction issuing section configured to issue instructions to the plurality of executing sections, and an instruction sync monitoring section configured to, when an instruction-synchronizing instruction is issued to one or more of the plurality of executing sections from the instruction issuing section, monitor completion of execution of the instruction-synchronizing instruction for each of the executing sections, to which the instruction-synchronizing instruction has been issued, thus detecting completion of execution of preceding instructions for the thread to which the instruction-synchronizing instruction belongs. After issuing the instruction-synchronizing instruction, the instruction issuing section stops issuance of succeeding instructions for the thread to which the instruction-synchronizing instruction belongs, until the completion of execution of the preceding instructions for the thread to which the instruction-synchronizing instruction belongs is detected by the instruction sync monitoring section. | 2010-01-14 |
| 20100011196 | Method and program network for exception handling - A method and a program network for exception handling are described. At least one error program element including an input and an output and an item of exception information stored for exception handling in the form of a data structure are defined in a graphical programming language. | 2010-01-14 |
| 20100011197 | ENHANCED UEFI FRAMEWORK LAYER - A unified extensible firmware interface (UEFI) includes providing by a manufacturer, a basic input/output system (BIOS) personality module to initialize an information handling system (IHS) and receiving from an outside vendor, a BIOS initialization module to initialize the IHS. The UEFI also includes integrating operations of the personality module and the initialization module by translating communication between the personality module and the initialization module. | 2010-01-14 |
| 20100011198 | MICROPROCESSOR WITH MULTIPLE OPERATING MODES DYNAMICALLY CONFIGURABLE BY A DEVICE DRIVER BASED ON CURRENTLY RUNNING APPLICATIONS - A computing system includes a microprocessor that receives values for configuring operating modes thereof. A device driver monitors which software applications currently running on the microprocessor are in a predetermined list and responsively dynamically writes the values to the microprocessor to configure its operating modes. Examples of the operating modes the device driver may configure relate to the following: data prefetching; branch prediction; instruction cache eviction; instruction execution suspension; sizes of cache memories, reorder buffer, store/load/fill queues; hashing algorithms related to data forwarding and branch target address cache indexing; number of instruction translation, formatting, and issuing per clock cycle; load delay mechanism; speculative page tablewalks; instruction merging; out-of-order execution extent; caching of non-temporal hinted data; and serial or parallel access of an L2 cache and processor bus in response to an instruction cache miss. | 2010-01-14 |
| 20100011199 | Method and device of bootloader-to-go - A method comprising two steps is provided for a simplified on-site bootloading process. Step 1: having a computer or similar device preload initialization instructions and executable codes to an intermediate device. Step 2: having that said device transfer such initialization instructions and executable codes to the operating device. The intermediate device named “bootloader-to-go” is provided in this invention. The said bootloader-to-go device provides the uncomplicated transferring of the initialization instructions and executable codes to the operating device without complex configuration steps. The said bootloader-to-go device is handheld, operated by a single operating switch and is equipped with versatile I/O bus connections compatible to operating devices with various I/O types. There is no need of a hosting computer or similar device on site, the bootloading speed is not controlled by a hosting computer, and therefore the bootloading time is predictable and can be repeated. | 2010-01-14 |
| 20100011200 | METHOD AND SYSTEM FOR DEFENDING SECURITY APPLICATION IN A USER'S COMPUTER - Protecting the integrity and the effectiveness of a security agent that is installed in a user's device while the user's device operates online or offline. The security agent may be used for enforcing a security policy required by an organization or network to which the user's computer belongs. One aspect of exemplary embodiments of the present invention is to associate the content of one or more storage devices of the user's computer with the security agent and with a boot-loader program used by the user's computer. | 2010-01-14 |
| 20100011201 | COMPUTER SYSTEM AND CONTROL METHOD THEREOF - A control method of a computer system, including setting whether to enable a connection with at least one peripheral device in an operating system of the computer system to transmit and receive data; and enabling or disabling the connection with the at least one peripheral device based on the setting when the computer system is booted. | 2010-01-14 |
| 20100011202 | MULTI-STAGE BOOT PIN SAMPLING - In accordance with embodiments, a method for configuring an electronic device during a power-on sequence includes sampling a boot pin state multiple times. The method also includes storing a value corresponding to each sampled boot pin state, wherein the stored values comprise one of four different states for a single boot pin. | 2010-01-14 |
| 20100011203 | CONTROL PROTOCOL FOR IMAGE ENUMERATION AND TRANSFER - A control protocol is used to deploy and install an operating system image on a client. The data structure of the control protocol includes an operation code corresponding to an operation associated with the deployment and installation of the operating system image on the client. When a server receives a request packet from the client, the server parses the request packet and sends the parsed request packet to a provider. The provider then executes the operation associated with the operation code and generates a return value. The return value is sent to the server. The server then composes a reply packet including the return value and transmits the reply packet to the client. | 2010-01-14 |
| 20100011204 | Method and System for Image Management in a Computing System - A method and system for migrating data to a build-to-order computing system is provided. The method comprises storing an image at a remote site. The image comprises data stored on a computing system. An order is received to provide a second computing system to a customer. Access to the image is provided to the second computing system such that the second computing system can store the image. | 2010-01-14 |
| 20100011205 | SECURE DATA EXCHANGE TECHNIQUE - Techniques utilizing common encryption approaches for data from multiple parties enable those parties to discover information that is held in common by the parties without disclosing to any party information that is not held in common by the parties. Encrypted information for each party can be compared to determine which encrypted values match, and those encrypted values can be returned to any of the parties such that a party can determine which corresponding data the parties have in common, without having access to any other data of any other parties. | 2010-01-14 |
| 20100011206 | EMBEDDED APPARATUS, REMOTE-PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT - A processing unit performs a predetermined process by a remote operation from a client device. A monitoring unit monitors a first port for an unencrypted communication with the processing unit and a second port for an encrypted communication with the processing unit, denies a connection request via the first port, and accepts a connection request via the second port. When a connection request encrypted with either one of the first port and the second port specified as a forwarding destination port is received, an encrypted communication unit decrypts the connection request and transfers decrypted connection request to the monitoring unit via the forwarding destination port. | 2010-01-14 |
| 20100011207 | Service Oriented Architecture Device - A system for Service Oriented Architecture (SOA) communication includes a plurality of SOA nodes having a standardized hardware configuration, wherein the standardized hardware configuration includes an operating engine, an encryption module accessed by the operating engine, which provides security for message traffic, a compression module to compress and decompress the message traffic, a routing module accessed by the operating engine, to determine the routing of message types, incoming traffic routed to appropriate service clients, outbound traffic routed to appropriate SOA devices, a security module that authenticates and authorizes message traffic, and one or more network interfaces, and one or more networks over which the SOA nodes communicate with one another. | 2010-01-14 |
| 20100011208 | CRYPTOGRAPHIC CONTROL AND MAINTENANCE OF ORGANIZATIONAL STRUCTURE AND FUNCTIONS - Methods, systems and devices for cryptographic control and maintenance of organizational structure and functions are provided. A method for control and maintenance of an operational organizational structure, the method includes associating entities with cryptographic capabilities; organizing entities within the organizational structure as roles; and maintaining roles within the organizational structure. The system may involve at least a Public Key Infrastructure operation. Elements in said organizational structure may be assigned to roles and/or groups within said organizational structure. | 2010-01-14 |
| 20100011209 | SECURE EXECUTION OF A COMPUTER PROGRAM - Hijacking of an application is prevented by securing execution of a computer program on a computing system. Prior to execution of the computer program, the computer program is analyzed to identify permitted targets of all indirect transfers. An application-specific policy based on the permitted targets is created. When the program is executed on the computing system, the application-specific policy is enforced such that the program is prohibited from executing indirect transfer instructions that do not target one of the permitted targets. | 2010-01-14 |
| 20100011210 | Method And Apparatus For Remotely Provisioning Software-Based Security Coprocessors - A virtual security coprocessor is created in a first processing system. The virtual security coprocessor is then transferred to a second processing system, for use by the second processing system. For instance, the second processing system may use the virtual security coprocessor to provide attestation for the second processing system. In an alternative embodiment, a virtual security coprocessor from a first processing system is received at a second processing system. After receiving the virtual security coprocessor from the first processing system, the second processing system uses the virtual security coprocessor. Other embodiments are described and claimed. | 2010-01-14 |
| 20100011211 | Radio Frequency Identification (RFID) Based Authentication System and Methodology - Disclosed are embodiments of a radio frequency identification (RFID) authentication system and an associated authentication methodology. The embodiments incorporate an identification device (e.g., an identification badge, a key fob, etc.) with an embedded RFID tag. The embedded RFID tag is associated with a specific user and stores a private key generated as part of a public key-private key encryption scheme. The private key is read by an RFID reader and used to decode public key encrypted data stored within or accessible by a computer system (e.g., a desktop computer system, a laptop computer system, a personal digital assistant (PDA), a digital fax machine, wireless telephone, etc.). Thus, the embodiments provide a portable way to use public key-private key encryption scheme data anywhere using RFID technology. | 2010-01-14 |
| 20100011212 | RADIO FREQUENCY IDENTIFICATION (RFID) BASED AUTHENTICATION METHODOLOGY USING STANDARD AND PRIVATE FREQUENCY RFID TAGS - Disclosed is a self-contained hardware-based authentication system that incorporates different authentication protocols for access to soft and/or hard assets with different security levels. The system embodiments include the use of a RFID device that comprises dual RFID tags operating under different frequencies. Specifically, one RFID tag operates on a public frequency and, when activated, transmits an identifier encrypted using a public key. The other RFID tag operates on a private frequency and, when activated, transmits a private key that can be used to decrypt the encrypted identifier. Upon receipt by a processor (e.g., a local processor or security server) of a request for access to a specific asset, a security level for the specific asset is determined. Then, depending upon the particular security level (e.g. low, medium or high) different authentication protocols are instituted using the RFID device. Also disclosed are embodiments of an associated authentication methodology. | 2010-01-14 |
| 20100011213 | INFORMATION PROCESSING DEVICE, COMPUTER PROGRAM, AND INFORMATION PROCESSING SYSTEM - An information processing device includes: a receiving unit that receives a first random number from another information processing device; a generating unit that generates a second random number; a time-variant-key generating unit that generates a time variant key for encryption according to the second random number; an encrypting unit that encrypts the first random number with the time variant key; and a transmitting unit that transmits the first random number encrypted by the time variant key and the second random number to the other information processing device. | 2010-01-14 |
| 20100011214 | METHOD AND APPARATUS FOR SECURE TRUSTED TIME TECHNIQUES - A method and apparatus to establish a trustworthy local time based on trusted computing methods are described. The concepts are scaling because they may be graded by the frequency and accuracy with which a reliable external time source is available for correction and/or reset, and how trustworthy this external source is in a commercial scenario. The techniques also take into account that the number of different paths and number of hops between the device and the trusted external time source may vary. A local clock related value which is protected by a TPM securely bound to an external clock. A system of Accuracy Statements (AS) is added to introduce time references to the audit data provided by other maybe cheaper sources than the time source providing the initial time. | 2010-01-14 |
| 20100011215 | Securing dynamic authorization messages - To fortify trust in a roaming environment, a token is introduced in transactions between an authoritative entity (e.g., a Home AAA in RADIUS) and a service providing entity (e.g., a NAS in RADIUS). A Token-Information is sent from the authoritative entity to the service providing entity during the initial authentication. Subsequent transactions include a token computed from the Token-Information. The service providing entity discards messages that it receives that do not contain the correct token. The Token-Information is transported in an encrypted fashion. The token provides secure transactions when messages between the authoritative entity and the service providing entity are routed through proxy servers. | 2010-01-14 |
| 20100011216 | Method of providing secure tamper-proof acquired data from process instruments - Field devices used to measure process parameters can also function as a data historian by storing process data and associated time stamps. In response to a request for stored process data, the field device uses a cipher and a secret method to generate an encrypted validation string that is provided along with unencrypted information including the process data and time stamps. A validation service that maintains a secure database of field devices and their associated ciphers and secret methods can validate the unencrypted information by using the validation string. | 2010-01-14 |
| 20100011217 | WATERMARK SIGNAL GENERATING APPARATUS - An apparatus | 2010-01-14 |
| 20100011218 | SYSTEM AND METHOD FOR SECURE AUTHENTICATION OF A "SMART" BATTERY BY A HOST - Systems and methods for providing a battery module | 2010-01-14 |
| 20100011219 | Secure Use of User Secrets on a Computing Platform - A computing platform ( | 2010-01-14 |
| 20100011220 | AUTHENTICATION AND KEY AGREEMENT METHOD, AUTHENTICATION METHOD, SYSTEM AND DEVICE - An AKA method, and authentication method and related devices are disclosed so that a user card not supporting storing of a SQN can resist replay attacks during an AKA procedure. In an AKA method, a second device generates a fourth sequence number for a user according to system time of the second device if the second device determines that the fourth sequence number for the user is not stored in the second device and synchronizing a third sequence number of the user that is stored by a first device with the fourth sequence number by interacting with the first device. The second device and the first device may perform an anti-replay protection in authentication using the synchronized third sequence number and the fourth sequence numbers. In the AKA method, a terminal can generate a SQN based on the system time and a random number which makes the SQN value more random. Even if an attacker knows the time value or even controls the system time of the terminal, the attacker is unable to predict the SQN generated by the terminal so that a replay attack is improbable. The security is thus enhanced. | 2010-01-14 |
| 20100011221 | Secured storage device with two-stage symmetric-key algorithm - A secured storage device uses a user key set by user to encrypt a primary key that is for encryption or decryption of user data, to produce a first encrypted data. In the secured storage device, neither the primary key nor the user key is stored, but the first encrypted data, and a secondary key and a second encrypted data produced from the secondary key encrypted with the user key for verifying the password inputted by user are stored. Therefore, even though a storage medium in the secured storage device is detached and read, the primary key and the user key cannot be obtained by a third party for reading out any encrypted user data from the secured storage device. | 2010-01-14 |
| 20100011222 | Interfacing with a system that includes a passcode authenticator - Protecting the security of an entity by using passcodes is disclosed. A passcode device generates a passcode. In an embodiment, the passcode is generated in response to receipt of user information. The passcode is received by another system, which authenticates the passcode by at least generating a passcode from a passcode generator, and comparing the generated passcode with the received passcode. The passcode is temporary. At a later use a different passcode is generated from a different passcode generator. | 2010-01-14 |
| 20100011223 | METHOD FOR MAKING SMART CARDS CAPABLE OF OPERATING WITH AND WITHOUT CONTACT - The invention concerns a method for making smart cards capable of operating with or without contact called mixed cards and contactless smart cards. In order to avoid the risk of deteriorating the antenna the method consists in producing an antenna comprising at least two turns, on a support sheet, said antenna having its turns located outside the connecting pads, and in providing an insulating bridge so as to connect each of the antenna ends to a connection pad respectively. | 2010-01-14 |
| 20100011224 | SYSTEM AND METHOD FOR PRODUCING AND CHECKING VALIDATION CERTIFICATES - A system, method, and computer program product for computing a digest value of a document, one or more schemas, and a validation report. The validation report indicates a validation status of the document based on the schema or schemas. The digest value is encrypted to produce a digital signature of the document, the schema or schemas, and the validation report. | 2010-01-14 |
| 20100011225 | INFORMATION TERMINAL, SECURITY DEVICE, DATA PROTECTION METHOD, AND DATA PROTECTION PROGRAM - An information terminal that decrypts sealed data without returning program data after update to the state before update. The information terminal includes update certificate storage unit | 2010-01-14 |
| 20100011226 | DATA MANAGEMENT METHOD, DATA MANAGEMENT SYSTEM, AND DATA STORAGE SYSTEM - Encrypted data and an encryption key used for the encrypted data are separately stored and managed. A first storage device stores an encrypted data block, predetermined information and first management information. The predetermined information includes key data for decrypting the encrypted data block and includes a requirement for using the encrypted data block. The first management information is used to manage the encrypted data block and includes a first storage address at which the predetermined information is stored. A host device transfers the predetermined information from the first storage device to a second storage device, causes second management information including a second storage address, at which the transferred predetermined information is stored and which is included in the second storage device to be stored in the second storage device. | 2010-01-14 |
| 20100011227 | SYSTEM AND METHOD FOR MEASUREMENT-BASED POWER AND ENERGY ACCOUNTING FOR VIRTUAL MACHINES - A method for measurement-based power and energy accounting for virtual machines distributed among at least one hosting device is disclosed. The method comprising determining an energy for the hosting device during a first time interval and a second time interval, partitioning a difference in the determined energy among virtual machines within a plurality of regions of the hosting device, determining a level of activity of each of the resources in each virtual machine within a corresponding one of the regions, determining an energy of each resource in each corresponding virtual machine wherein energy associated with resources shared among an plurality of virtual machines are allocated to a corresponding one of the virtual machines based on a number of requests made to the shared resource by the corresponding virtual machine, determining a total energy for each of the virtual machines in corresponding regions based on a level of activity of the virtual machine and the energy associated with the corresponding shared resources, and determining a power for each of the virtual machines by dividing the determined total energy by a length of the time interval. | 2010-01-14 |
| 20100011228 | Power supply - A power supply allows an electronic product to access the Internet, characterized in that a casing of the power supply is provided with a network connection port, the casing of the power supply is provided therein with a power line communication module, the power line communication module is coupled to the network connection port, the power line communication module receives an original package data and transmits the original package data to the electronic product via the network connection port. | 2010-01-14 |
| 20100011229 | METHODS OF POWERING UP A DISK DRIVE STORAGE ENCLOSURE AND STORAGE ENCLOSURES - A method of powering up a disk drive storage enclosure is disclosed, the storage enclosure having at least one power supply and at least one module having a keyed readable interface corresponding to its power rating. The method includes: receiving a power-on signal; determining the power supplying capability of the storage enclosure; determining the power requirement of the storage enclosure including reading the keyed readable interface to determine the power rating of the at least one keyed module; determining the power mode attainable by the system in accordance with the power supplying capability and the power requirement, the modes including at least power on and power off; and, powering up or not powering up the storage enclosure in accordance with the power mode. | 2010-01-14 |
| 20100011230 | LINK AGGREGATION WITH DYNAMIC BANDWIDTH MANAGEMENT TO REDUCE POWER CONSUMPTION - Embodiments of the present invention provide configurations and techniques for determining, by link aggregation logic, whether a load of network traffic communicated across a team of aggregated links allows inactivation of one or more aggregated links of the team, wherein the team of aggregated links is coupled with a plurality of network interface cards (NICs). On determining that the load of network traffic communicated across the team of aggregated links allows inactivation of the one or more aggregated links of the team, the link aggregation logic is configured to power off or place into a power save mode one or more NICs of the plurality of NICs corresponding to the one or more aggregated links. Other embodiments may be described and/or claimed. | 2010-01-14 |
| 20100011231 | ACCESS POINT ROTATION FOR SHARING POWER LOAD - Aspects of the disclosure provide a method for sharing power load in a network. The method includes identifying a first device to serve as an AP of the network in a next time interval, providing network information from a second device that presently serves as the AP to the first device. When the first device starts to serve as the AP of the network, the second device can be configured to enter into a power save state in order to reduce power consumption by the second device in the next time interval. | 2010-01-14 |
| 20100011232 | DIGITAL COMPONENT POWER SAVINGS IN A HOST DEVICE AND METHOD - A control arrangement, for example, in a digital component that forms part of a system, draws an input current for its operation and is configured for monitoring an interface for any one of a group of commands and, upon detecting an issued one of the group of commands, operates the component for executing the issued command in an operational mode, and during an idle time on the interface, the control arrangement exclusively monitors the interface for any one of the group of commands such that the input current is limited to a leakage current. The component may draw less than 1 milliamp of current during the idle mode. | 2010-01-14 |
| 20100011233 | ADAPTIVE POWER CONTROL - A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted. | 2010-01-14 |
| 20100011234 | APPARATUS, SYSTEM, AND METHOD FOR REDUCING IDLE POWER IN A POWER SUPPLY - An apparatus, system, and method is provided for reducing idle power in a power supply. The apparatus includes a connection module to determine whether a load is connected to the output terminal of the power supply. Also included is an idle module that turns off the power supply for an idle interval when the connection module determines that a load is not connected to the output. A monitor module turns on the power supply for a monitor interval when the idle interval ends. During the monitor interval, the connection module determines whether the load has been connected to the output terminal of the power supply. An activation module turns on the power supply if the connection module determines, during the monitor interval, that the load has been connected to the power supply. If the load has not been connected, another idle interval is initiated. | 2010-01-14 |
| 20100011235 | METHOD AND APPARATUS FOR POWER MANAGEMENT - An electronic device includes a processor configured to run a plurality of applications, a power supply coupled to the processor, and a database coupled to the processor The database is configured to store information identifying each of the plurality of applications as being in either a first set of applications or a second set of applications. The processor monitors the power level of the power supply and is configured to disable the first set of applications when the power level reaches a predetermined power level. | 2010-01-14 |
| 20100011236 | METHOD AND SYSTEM FOR ENHANCING COMPUTER PERIPHERAL SAFETY - A method and system for enhancing computer peripheral safety is provided. In accordance with various aspects of the present invention, the exemplary method and system are configured to monitor and/or isolate alternating current (A.C.) supplies with and/or from any peripheral subsystems or devices. An exemplary method and system comprises an A.C. supply, a host computer system, and a peripheral subsystem or device connected to the host computer system, such as an ultrasound imaging and/or therapy peripheral, and an isolation subsystem configured for monitoring and/or isolating the A.C. supply from the peripheral subsystem or device. In accordance with an exemplary embodiment, an isolation subsystem comprises application software and associated modules and functions that when executed continuously monitors and/or polls the host computer's hardware and/or operating system for the presence of an isolated source, such as a battery, or an unisolated power source, such as through a battery charger and/or other connection path to the A.C. main supply. In accordance with other exemplary embodiments, an isolation subsystem can comprises a wireless or other safe/isolated electrical link for connecting a patient contact device, and/or a verification link or other verification mechanisms configured between an isolation transformer and host computer to monitor or observe usage to power the host computer and peripheral subsystem. | 2010-01-14 |
| 20100011237 | Controlling real time during embedded system development - Disclosed herein are representative embodiments of methods, systems, and apparatus that can used to control real-time events (e.g., the real-time clock) during the design, simulation, or verification of an embedded system. In one exemplary embodiment disclosed herein, for example, a real-time clock signal is generated and tasks defined by an embedded software application are triggered with the real-time clock signal. In this embodiment, the embedded software application is executed by an embedded processor with a real-time operating system (“RTOS”), and the real-time clock signal is controllable independent of a processor clock signal driving the embedded processor in a manner that allows the real-time clock to have a different time base than the processor clock. | 2010-01-14 |
| 20100011238 | INFORMATION PROCESSING SYSTEM AND DATA RECOVERY METHOD - When data of HDD of computer is backed up to a a data center and a failure occurs in the HDD, the computer notifies failure information to the data center, and the data center stores the backed up data in a storage medium substituting HDD for subsequent delivery. Further, the computer executes processing, using a VNC server, from failure occurrence until recovery. | 2010-01-14 |
| 20100011239 | STORAGE SYSTEM AND DATA RESTORATION METHOD THEREOF - This storage system includes a first storage sub system having a first logical volume where a first data area is dynamically allocated to each prescribed area, and which stores data transmitted from a host computer in the first data area, and a second storage sub system having a second data area for backing up the first logical volume; wherein the first storage sub system includes: a first management unit for managing the status of the first data area allocated to each of the areas of the first logical volume; a transfer unit for transferring the data stored in the first data area allocated to each of the areas of the first logical volume to the second storage sub system; and a restoration unit for restoring the first logical volume based on the status of the first data area managed by the first management unit and/or the data transferred from the second storage sub system. | 2010-01-14 |
| 20100011240 | DEVICE AND METHOD FOR SYNCHRONIZING THE STATES OF A PLURALITY OF SEQUENTIAL PROCESSING UNITS - A device for providing a plurality of clock signals from a common clock signal. The device includes an input for receiving the common clock signal, a first clock signal path for providing a first output clock signal on the basis of the common clock signal and a second clock signal path for providing a second output clock signal. The second clock signal path includes a clock processing device for changing a phase of the common clock signal to provide the second clock signal. | 2010-01-14 |
| 20100011241 | Information processing apparatus and domain dynamic reconfiguration processing method - An information processing apparatus includes a domain configured by plural system boards, and a pair of service processors, wherein when one of the pair of service processors fails during the execution of domain dynamic reconfiguration processing for the domain, the other of the pair of service processors takes over and executes the domain dynamic reconfiguration processing under execution. | 2010-01-14 |
| 20100011242 | Failover method and system for a computer system having clustering configuration - A failover method for a computer system having a clustering configuration, in which among a plurality of computers having the clustering configuration, any one of computers, when detecting a malfunction of a system including a certain computer, transmits a detection of the system malfunction to computers configuring the other systems, and the any one of computers, when detecting the malfunction of the system including the certain computer and receiving malfunction notifications of the system including the certain computer from the computers configuring the other systems, issues a reset request to the certain computer. | 2010-01-14 |
| 20100011243 | Methods, systems and media for software self-healing - Methods, systems, and media for enabling a software application to recover from a fault condition, and for protecting a software application from a fault condition, are provided. In some embodiments, methods include detecting a fault condition during execution of the software application, restoring execution of the software application to a previous point of execution, the previous point of execution occurring during execution of a first subroutine in the software application, and forcing the first subroutine to forego further execution and return to a caller of the first subroutine. | 2010-01-14 |
| 20100011244 | METHOD OF ROUTING DATA IN A NETWORK COMPRISING NODES ORGANIZED INTO CLUSTERS - A method relates to routing data in a network, between source nodes and destination nodes pertaining respectively to distinct source groups and destination groups. The network includes intermediate groups forming at least two potential data transmission paths through which the data can be transmitted. The method includes a determination step, for each group of nodes of the network, including feedback by the nodes of the information group for determination of a quality level, representing quality of the data transmission through this group, and a step of selecting at least one transmission path from among the potential paths, for the transmission of data between the source nodes and destination nodes through the selected transmission path. The selection is made based on the quality levels of the intermediate groups of the network. | 2010-01-14 |
| 20100011245 | FAULT TOLERANT ROUTING IN A NON-HOT-STANDBY CONFIGURATION OF A NETWORK ROUTING SYSTEM - Methods and systems for facilitating fault tolerance in a non-hot-standby configuration of a network routing system are provided. According to one embodiment, a method is provided for replacing an active processing engine with a non-hot-standby processing engine. Multiple processing engines within a network routing system are configured. The processing engines include an active processing engine having one or more software contexts, representative of a set of objects implementing a virtual router, for example, and a non-hot-standby processing engine having no pre-created software contexts corresponding to the one or more software contexts. Responsive to determining a fault associated with the active processing engine, the active processing engine is dynamically replaced with the non-hot-standby processing engine by creating replacement software contexts within the non-hot-standby processing engine corresponding to the one or more software contexts. | 2010-01-14 |
| 20100011246 | DIAGNOSTIC/REMOTE MONITORING BY EMAIL - A network device for use in a communication system having a technical support center operated by a technical support staff, the technical support center being in communication with the network device through a packet switching network. The network device includes one or more hardware subsystems, one or more software subsystems and means for monitoring the status of the hardware and software subsystems so that when a problem occurs with respect to one or more of the hardware and software subsystems of the network device, the network device for transmitting a first message to the technical support center to notify the technical support center of the problem, wherein the technical support staff is able to diagnose the problem without interruption to the operation of the network device. | 2010-01-14 |
| 20100011247 | METHOD AND APPARATUS FOR PARALLEL ECC ERROR LOCATION - An invention is provided for parallel ECC error location in a memory. The invention includes partitioning a set of field elements into w partitions. Then, for each of the w partitions of field elements, i) providing a set of r different field elements of the partition to r parallel search element. Next, in operation ii), each parallel search element computes a sum that is based on a set of coefficients of an error locator polynomial and the field element provided to the particular parallel search element. The set of field elements is advanced r field elements in GF(2 | 2010-01-14 |
| 20100011248 | LIGHT WEIGHT AND HIGH THROUGHPUT TEST CASE GENERATION METHODOLOGY FOR TESTING CACHE/TLB INTERVENTION AND DIAGNOSTICS - A test case manager selects a first test case and a second test case from a plurality of test cases. The test case manager provides the first test case to a first processor and provides the second test case to a second processor. As such, the first processor executes the first test case and the second processor executes the second test case. After the execution, the test case manager loads the first test case onto the second processor and loads the second test case onto the first processor. In turn, the first processor executes the second test case and the second processor executes the first test case. | 2010-01-14 |
| 20100011249 | DEVICE FOR TESTING A FUNCTION OF A DISPLAY PORT, AND SYSTEM AND METHOD FOR TESTING THE SAME - A device is disclosed for testing the function of a display port. The device includes a display port transmitting part, a field programmable gate array, and a memory. The display port transmitting part transmits connecting signals to a display port timing controller mounted on a display panel. The field programmable gate array applies a test signal to the display port timing controller, and controls the connecting signals applied from the display port transmitting part to the display port timing controller. The memory has software that determines acceptance or rejection of the display port function based on data output from the display port timing controller in response to the connecting signals or the test signal. | 2010-01-14 |
| 20100011250 | MICROCONTROLLER INFORMATION EXTRACTION SYSTEM AND METHOD - A system for debugging a device under test may include a processor register with a program count and a debug program register that receives the program count upon execution of an instruction by a processor. In one implementation, a microcontroller under test by a debugger is accessed using a serial interface, such as a JTAG interface. The interface can communicate directly with a debug register to retrieve program count values, both when the microcontroller is halted and when it is executing instructions. The polling interval to retrieve the program count values may be adjusted by a user of the debugger based on considerations such as bandwidth and accuracy. The microcontroller may transmit the program count value to the debug register from a processing register that is not accessible to the debugger. | 2010-01-14 |
| 20100011251 | Medical Equipment Monitoring Method and System - A system and method to facilitate device monitoring and servicing is provided. In one embodiment, a system may include a medical device having at least one component, and monitoring circuitry configured to measure operational data of the component. The system can also include a data processing system configured to analyze the operational data and to output a report based on such analysis. The analysis, in turn, may include applying a transform to the operational data and comparing one or more actual coefficient and threshold coefficient characteristics. | 2010-01-14 |
| 20100011252 | FORMAT TRANSFORMATION OF TEST DATA - A device for processing test data, the device having a data input interface adapted for receiving primary test data indicative of a test carried out for testing a device under test, the primary test data being provided in a primary format, a processing unit adapted for generating secondary test data in a secondary format by transforming, by carrying out a coordinate transformation, the primary test data from the primary format into the secondary format, and a data output interface adapted for providing the secondary test data in the secondary format for storing the secondary test data in a plurality of storage units. | 2010-01-14 |
| 20100011253 | Circuit Arrangement for monitoring errors during signal transmission - A circuit arrangement, having a circuit and a computer unit is provided, in which the circuit and the computer unit are connected to one another via multiple lines for transmitting a number of signals which are embodied as information signals. The circuit has a multiplexer for combining signals, the multiplexer being connected to the computer unit via an additional line. | 2010-01-14 |
| 20100011254 | RISK INDICES FOR ENHANCED THROUGHPUT IN COMPUTING SYSTEMS - Embodiments of a system that adjusts a checkpointing frequency in a distributed computing system that executes multiple jobs are described. During operation, the system receives signals associated with the operation of the computing nodes. Then, the system determines risk metrics for the computing nodes using a pattern-recognition technique to identify anomalous signals in the received signals. Next, the system adjusts a checkpointing frequency of a given checkpoint for a given computing node based on a comparison of a risk metric associated with the given computing node and a threshold, thereby implementing holistic fault tolerance, in which prediction and prevention of potential faults occurs across the distributed computing system. | 2010-01-14 |
