| 02nd week of 2010 patent applcation highlights part 19 |
| Patent application number | Title | Published |
|---|
| 20100007355 | METHOD FOR TESTING RADIO FREQUENCY (RF) RECEIVER TO PROVIDE POWER CORRECTION DATA - A method for testing a radio frequency (RF) receiver as a device under test (DUT) with one or more test instruments to provide a plurality of relative power correction factors, a plurality of received signal strength indication (RSSI) calibration factors, or both. | 2010-01-14 |
| 20100007356 | ELECTROMAGNETIC SHIELDING DEFECT MONITORING SYSTEM AND METHOD FOR USING THE SAME - An embodiment disclosed herein is directed to a method of monitoring an electromagnetic shield effectiveness comprising transmitting a first electromagnetic field toward a first surface of an electromagnetic shield, detecting a second electromagnetic field transmitted from a second surface of the electromagnetic shield, generating a first signal corresponding to the second electromagnetic field and determining whether a defect exists at the electromagnetic shield by comparing the first signal to a predetermined threshold. | 2010-01-14 |
| 20100007357 | Electrical Impedance Tomography Method and Device - Electrical impedance tomography method comprising: an electrical measurement step during which pre-determined electrical conditions are imposed on the surface of a medium to be imaged, while generating a mechanical disturbance at predefined points of the medium by locally modifying the impedance of the medium and an electrical parameter is measured at several points on the surface of the medium; and a calculation step during which the electrical impedance is determined at several points in the internal volume of the medium, taking into account the measurements carried out during the disturbance, as a function of a law for modification of the electrical impedance by this disturbance. | 2010-01-14 |
| 20100007358 | Sensor for high voltage environment - Sensor for measuring electrical parameters in a high voltage environment comprising a high voltage side ( | 2010-01-14 |
| 20100007359 | PASSIVE CAPACITIVELY-COUPLED ELECTROSTATIC (CCE) PROBE ARRANGEMENT FOR DETECTING IN-SITU ARCING EVENTS IN A PLASMA PROCESSING CHAMBER - An arrangement for detecting in-situ arcing events within a processing chamber of a plasma processing system during substrate processing is provided. The arrangement includes a probe arrangement, which is disposed on a surface of the processing chamber and is configured to measure at least one plasma processing parameter. The probe arrangement includes a plasma-facing sensor and a measuring capacitor, wherein the plasma-facing sensor is coupled to a first plate of the measuring capacitor. The probe arrangement also includes a detection arrangement that is coupled to a second plate of the measuring capacitor, wherein the detection arrangement is configured for converting an induced current flowing through the measuring capacitor into a set of digital signals, which is processed to detect the in-situ arcing events. | 2010-01-14 |
| 20100007360 | FLUID SENSOR DEVICE - The invention provides a fluid sensor device ( | 2010-01-14 |
| 20100007361 | POWER SUPPLY DEVICE AND SEQUENCER SYSTEM - A smoothing unit includes a first and a second smoothing capacitors, a first and a second discharge resistors connected in parallel to both ends of the first and the second smoothing capacitors, respectively. During a normal operation, both the first and the second smoothing capacitors are connected electrically to a live line. On the other hand, during a degradation diagnosis, the first and the second smoothing capacitors are alternately connected electrically to the live line at a predetermined timing, and a smoothing capacitor not electrically connected to the live line is subjected to the degradation diagnosis. | 2010-01-14 |
| 20100007362 | RF-BIASED CAPACITIVELY-COUPLED ELECTROSTATIC (RFB-CCE) PROBE ARRANGEMENT FOR CHARACTERIZING A FILM IN A PLASMA PROCESSING CHAMBER - A method for characterizing deposited film on a substrate within a processing chamber during processing is provided. The method includes determining voltage-current characteristic for a probe head when measuring capacitor is set at a first capacitance value. The method also includes applying RF train to the probe head when measuring capacitor is set at a capacitance value greater than first capacitance value. The method further includes providing an initial resistance value and an initial capacitance value for the deposited film. The method yet also includes employing initial resistance value, initial capacitance value, and voltage-current characteristic to generate simulated voltage-time curve. The method yet further includes determining measured voltage-time curve, which represents potential drop across the deposited film for one RF train. The method more over includes comparing the two curves. If the difference is less than predefined threshold, employ initial resistance value and initial capacitance for characterizing the deposited film. | 2010-01-14 |
| 20100007363 | SYSTEM AND METHOD FOR DETERMINING IN-LINE INTERFACIAL OXIDE CONTACT RESISTANCE - The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to advanced process control methodologies for measuring in-line contact resistance in relation to oxide formations. The present invention, in one or more implementations, include an in-line method of determining contact resistance across a semiconductor wafer and determining the contact resistance value and the number of monolayers of the wafer. | 2010-01-14 |
| 20100007364 | Hot Testing of Semiconductor Devices - A testing apparatus for testing of integrated circuit devices at elevated temperatures comprises hot belt | 2010-01-14 |
| 20100007365 | SOCKET FOR DOUBLE ENDED PROBE, DOUBLE ENDED PROBE, AND PROBE UNIT - A socket for a double ended probe with a first probe and a second probe includes a hollow pipe member housing the first probe and the second probe, the first probe and the second probe are arranged in an axial direction of the socket, and the socket includes an abutment holding the first probe and the second probe at predetermined positions on an inner side of the hollow pipe member. | 2010-01-14 |
| 20100007366 | TEST EQUIPMENT AND SEMICONDUCTOR DEVICE - An interface circuit is connected to an ATE via a test control bus BUS | 2010-01-14 |
| 20100007367 | Packaged Die Heater - A heater for heating packaged die for burn-in and heat testing is described. The heater may be a ceramic-type heater with a metal filament. The heater may be incorporated into the integrated circuit package as an additional ceramic layer of the package, or may be an external heater placed in contact with the package to heat the die. Many different types of integrated circuit packages may be accommodated. The method provides increased energy efficiency for heating the die while reducing temperature stresses on testing equipment. The method allows the use of multiple heaters to heat die to different temperatures. Faulty die may be heated to weaken die attach material to facilitate removal of the die. The heater filament or a separate temperature thermistor located in the package may be used to accurately measure die temperature. | 2010-01-14 |
| 20100007368 | Semiconductor integrated circuit and method of testing the same - Provided is a semiconductor integrated circuit including: a first path that includes a first logic circuit; a second path that includes a second logic circuit; and a subsequent-stage circuit that is connected to an output of the first path and is connected to an output of the second path, in which the second path further includes a first internal path that is selected as a propagation path during a normal operation period; and a second internal path that is selected as a propagation path during a test operation period and includes a delay circuit having a delay amount larger than a delay amount of the first internal path. | 2010-01-14 |
| 20100007369 | DISPLAY SUBSTRATE AND APPARATUS AND METHOD FOR TESTING DISPLAY PANEL HAVING THE SAME - A display substrate includes a gate pad part, a source pad part, a first static dissipative part, and a first test part. A gate pad part is formed on one terminal of each of a plurality of gate lines and transfers signals to the gate lines. A source pad part is formed on one terminal of each of a plurality of source lines and transfers signals to the source lines. A first static dissipative part disperses static charge that flows into the source pad part. A first test part receives a first test signal, makes electrical contact with the first static dissipative part, and transfers the first test signal to the source lines through the first static dissipative part. A display apparatus including the display substrate transmits first test signals that are uniformly applied to source lines through a first test part, so defects are easily detected through a gross test. | 2010-01-14 |
| 20100007370 | APPARATUS, SYSTEM, AND METHOD FOR ERROR DETECTION IN A STAND ALONE POWER SUPPLY - An apparatus for error checking in a power supply includes a power module that determines that the power supply is in a self-test condition. The self-test condition involves the power supply being connected to an input power source while it is disconnected from the electronic load that it normally services. A load module connects an internal test load to the power supply when the power supply is in self-test condition, and an error checking module performs error check operations on the power supply while it is connected to the test load. The apparatus also includes a notify module that actuates an indicator when the error checking module determines that there are one or more faults in the power supply. The apparatus may also include a log module for storing error messages and reports in non-volatile memory. | 2010-01-14 |
| 20100007371 | TESTABLE TRISTATE BUS KEEPER - A method of testing a tristate element by applying a given value to the tristate, applying an opposite value to a keeper element connected at an output of the tristate, capturing a first value at a downstream position of the tristate, evaluating a second value at the output of the tristate using the first value, comparing the second value to the opposite value, and producing a failure code for the tristate when the second value is not equal to the opposite value. Then, applying the opposite value to the tristate, applying the given value to the keeper element, capturing the first value, evaluating the second value using the first value, comparing the second value to the given value, and producing a failure code for the tristate when the second value is not equal to the given value. A passing code for the tristate is produced when a failure code has not been produced. | 2010-01-14 |
| 20100007372 | SEMICONDUCTOR DEVICE - A semiconductor, which includes a first phase detecting unit configured to detect a phase of a second clock on the basis of a phase of a first clock, and generate a first detection signal corresponding to a result of the detection, a second phase detecting unit configured to detect a phase of a delayed clock, which is generated by delaying the second clock by a predetermined time, on the basis of the phase of the first clock, and generate a second detection signal corresponding to a result of the detection, and a logic level determining unit configured to determine a logic level of a feedback output signal according to the first detection signal, the second detection signal and the feedback output signal. | 2010-01-14 |
| 20100007373 | IMPEDANCE MATCHING LOGIC - An impedance matching logic generates code values that define pull-up and pull-down transistors to be enabled with output buffers. The output buffers store the code values using a two-stage latch configuration, such that updated code values are always stored within the output buffer, even if the output buffer is driving an output signal when the updated code values are received. The impedance matching logic uses previously determined code values to shorten the time required to calculate updated code values. The impedance matching logic may be operated in response to a clock signal having a frequency lower than the frequency of the output clock signal used to control the output buffers. The impedance matching logic may adjust the code values by certain percentages using a multiplication function, thereby allowing for design fine tuning (e.g., due to layout mismatch). | 2010-01-14 |
| 20100007374 | ON-DIE THEVENIN TERMINATION FOR HIGH SPEED I/O INTERFACE - The method, system, and apparatus of on-die Thevenin termination for high speed I/O interface are disclosed. In one embodiment, a system of terminating a transmission line of a chip includes a pull-up circuit located within the chip comprising a voltage source and a positive switch device coupled with the transmission line of the chip, a pull-down circuit located within the chip comprising a ground and a negative switch device coupled with the transmission line of the chip, a resistor located within the chip coupled with the voltage source, the positive switch device, the ground, the negative switch device, and a pad coupled with the resistor to terminate the transmission line of the chip. The system may include resistors coupled in parallel with each other. The system may include an impedance module to determine a load impedance value as seen from the pad that matches a source impedance value. | 2010-01-14 |
| 20100007375 | TERMINATION RESISTANCE CIRCUIT - A termination resistance circuit includes a control signal generator for generating a control signal whose logical value changes when a calibration code has a predetermined value, a plurality of parallel resistors which are respectively turned on/off in response to the calibration code, and a resistance value changing unit for changing the total resistance value of the termination resistance circuit in response to the control signal. | 2010-01-14 |
| 20100007376 | STORAGE ELEMENTS FOR A CONFIGURABLE IC AND METHOD AND APPARATUS FOR ACCESSING DATA STORED IN THE STORAGE ELEMENTS - Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry for outputting data stored in the storage elements. The output circuitry includes a first set of interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits. | 2010-01-14 |
| 20100007377 | METHOD AND SYSTEM FOR A SERIAL PERIPHERAL INTERFACE - An integrated circuit device includes a serial peripheral interface adapted for receiving a first command supporting an address of a first configuration, wherein the serial peripheral interface supports an address of a second configuration upon receipt of a second command, the second configuration being different from the first configuration. In a specific embodiment, the first and the second configurations are different in address length. In another embodiment, a second address cooperated with the second command has a first part and a second part, the second part comprising a plurality of byte addresses, each of the byte addresses being associated with a corresponding byte of data. In another embodiment, integrated circuit device also includes a mode logic circuit for controlling operations of the first command and the second command. Various other embodiments are also described. | 2010-01-14 |
| 20100007378 | PROGRAMMABLE GATE ARRAY, SWITCH BOX AND LOGIC UNIT FOR SUCH AN ARRAY - A switch box ( | 2010-01-14 |
| 20100007379 | PROGRAMMABLE LOGIC DEVICES WITH FUNCTION-SPECIFIC BLOCKS - A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB. If the FSB is a multiplier, additional features include facilitating accumulation of successive multiplier outputs (using either addition or subtraction and with sign extension if desired) and/or arithmetically combining the outputs of multiple multipliers. | 2010-01-14 |
| 20100007380 | LEVEL SHIFTER AND LEVEL SHIFTING METHOD THEREOF - A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage. The second switch device is coupled to the first switch device for outputting a first operational voltage as the output voltage according to the first voltage. The first control switch is coupled to the first switch device for receiving the first voltage. The third switch device is coupled between the first control switch and the first operational voltage and controlled by the output voltage. The second level-switching device is coupled to the first level-switching device for receiving the input voltage and accordingly outputting a second operational voltage as the output voltage. | 2010-01-14 |
| 20100007381 | DRIVE SIGNAL OUTPUT CIRCUIT AND MULTI-CHIP PACKAGE - Input signals from a signal input terminal are input to a logic circuit, and a control signal corresponding to states of the input signals is output. The control signal is supplied to an output circuit, a plurality of transistors are controlled, and a drive signal is output corresponding to states of the transistors. In the logic circuit, the logic is switched according to the polarity of the setting signal which is input to a logic setting terminal, and a control signal corresponding to the input signal is changed. | 2010-01-14 |
| 20100007382 | Inverter circuit and balanced input inverter circuit - A balanced input inverter circuit includes a first P-type MOS transistor including a gate terminal connected to an input, a source terminal connected to a first power source potential, and a drain terminal connected to an output, a first N-type MOS transistor including a gate terminal connected to the input, a drain terminal connected to the output, and a source terminal connected to a second power source potential, a first inverter circuit including an input terminal connected to an inverted input, and an output terminal connected to a back gate terminal of the first N-type MOS transistor, a first diode connected between the first power source potential and a first power source terminal of the first inverter circuit, a second inverter circuit including an input terminal connected to the inverted input, and an output terminal connected to a back gate terminal of the first P-type MOS transistor, and a second diode connected between the second power source potential and a second power source terminal of the second inverter circuit. | 2010-01-14 |
| 20100007383 | METHOD AND APPARATUS FOR GENERATING A PHASE DEPENDENT CONTROL SIGNAL - A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The control signal may be used to adjust the delay value of a voltage-controlled delay circuit in order to adjust the phase relationship between the first and second clock signals to have a predetermined phase relationship. | 2010-01-14 |
| 20100007384 | COMBINATION AC/DC PEAK DETECTOR AND SIGNAL TYPE DISCRIMINATOR - A device and method for current detecting and discriminating is disclosed. The device includes a differential receiver configured to receive a current input, a positive-side Schmitt trigger in communication with the input stage, wherein the positive-side Schmitt trigger is configured to receive an output provided by the input stage, and wherein the positive-side Schmitt trigger is configured to create a positive-side Schmitt trigger output representative of the current input, and a negative-side Schmitt trigger in communication with the input stage, wherein the negative-side Schmitt trigger is configured to receive the output provided by the input stage, and wherein the negative-side Schmitt trigger is configured to create a negative-side Schmitt trigger output representative of the current input. | 2010-01-14 |
| 20100007385 | SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS - First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half. | 2010-01-14 |
| 20100007386 | Semiconductor device, display panel, and electronic apparatus - A single-channel thin-film transistor buffer includes a first output stage including first and second thin-film transistors connected in series, a seventh thin-film transistor having one main electrode connected to a control electrode of the first thin-film transistor (first control line), the other main electrode connected to a power source of the second thin-film transistor, and a control electrode connected to a second control line, an eighth thin-film transistor having one main electrode connected to a control electrode of the second thin-film transistor (second control line), the other main electrode connected to the power source of the second thin-film transistor, and a control electrode connected to the first control line, and an eleventh thin-film transistor having a control electrode connected to an output terminal of a second output stage connected in parallel with the first output stage and one main electrode connected to the first control line. | 2010-01-14 |
| 20100007387 | TRIANGULAR WAVE GENERATING CIRCUIT HAVING SYNCHRONIZATION WITH EXTERNAL CLOCK - A triangular wave generating circuit includes: an integrating unit including a capacitor, the integrating unit having an output for providing a triangular wave signal; first and second constant current sources for charging and discharging the capacitor; a switch unit for coupling the first and second current sources to the integrating unit to charge and discharge the capacitor in response to an internal clock signal; a high/low level limiter including first and second comparing units for comparing the output of the integrating unit with upper and lower triangular wave peak limit reference voltages, respectively, and providing output signals indicating when the output of the integrating unit coincides with the peak limit reference voltages; a clock generator for providing the internal clock signal in response to the comparing unit output signals; and means for varying a peak-to-peak swing of the triangular wave signal over time to synchronize the internal clock signal with an externally supplied clock pulse. | 2010-01-14 |
| 20100007388 | METHOD AND ARRANGEMENT RELATING POWER SUPPLY IN AN ELECTRICAL DEVICE - The present invention relates to an arrangement and method for eliminating power failures due to harmful motion. The device includes electrical components that use electrical power, a power source that connects to the electrical components, a motion sensor, and a processing unit. The motion sensor may sense a motion of the device substantially corresponding to free-fall condition, the processing unit may receive a signal from the motion sensor based on the first predetermined motion profile, and the processing unit may generate a signal supplied to at least some of the electrical components to cause a shut down operational mode. | 2010-01-14 |
| 20100007389 | MULTIPLE FREQUENCY SYNCHRONIZED PHASE CLOCK GENERATOR - Generation of multiple clocks having a synchronized phase relationship may reduce the size, complexity, power consumption, jitter and cost of circuitry while improving its functionality, performance, reliability and fault coverage. A multiple frequency clock generator may comprise an independent digital control oscillator (DCO) for generating a first clock and dependent DCOs for generating additional clocks that align at a common multiple frequency with the first clock with or without adjustment thereof. The independent and dependent DCOs may generate the first and additional clocks from a delay lock loop (DLL) by selecting a sequence of tap select signals. Tap select signals may be adjusted to maintain a desired phase and/or frequency of the first and additional clocks. Dependent DCOs may generate sequences of tap select signals based on the sequence of tap select signals generated by the independent DCO to incorporate adjustments, e.g., PLL error corrections. | 2010-01-14 |
| 20100007390 | Clock generating circuit, power converting system, and related method with spread spectrum for EMI reduction - A clock signal generating circuit includes a main delay circuit and a variable delay circuit. The main delay circuit receives a feedback clock signal, and outputs an output clock signal after a first delay when receiving the feedback clock signal. The variable delay circuit receives the output clock signal, and updates the feedback clock signal after a second delay when receiving the output clock signal. The second delay is periodically varied and is shorter than the first delay. | 2010-01-14 |
| 20100007391 | METHOD FOR USING DIGITAL PLL IN A VOLTAGE REGULATOR - A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop. | 2010-01-14 |
| 20100007392 | CRYSTAL AUTO-CALIBRATION METHOD AND APPARATUS - A system for automatically calibrating a crystal of a communication device and a method thereof are described. The system comprises a timing generator for generating a timing signal, a timing adjustment device coupled with the timing generator and for adjusting the timing of the timing signal responsive to receipt of an adjustment signal, and a calibration device coupled with the timing adjustment device and arranged to transmit the adjustment signal responsive to a comparison between the timing signal and a reference signal. | 2010-01-14 |
| 20100007393 | Method and Apparatus for Achieving 50% Duty Cycle on the Output VCO of a Phased Locked Loop - Described herein are methods and apparatuses for achieving a desired duty cycle on an output of a PLL. According to one embodiment, a method is described, including generating a single ended clock signal from a differential common mode clock signal using a limiting differential amplifier, wherein the single ended clock signal has a duty cycle, generating a differential bias current signal in response to the duty cycle of the single ended clock signal, and correcting the duty cycle of the single ended clock signal to a desired duty cycle by applying the differential bias current signal to the limiting differential amplifier. According to another embodiment, a CML-to-CMOS converter circuit is described, including a limiting differential amplifier for generating a single ended clock signal from a differential common mode clock signal, wherein the single ended clock signal has a duty cycle, a low-pass filter for generating a measurement of the duty cycle of the single ended clock signal, and a second differential amplifier for (i) comparing the measurement with a reference voltage and (ii) generating a differential bias current signal in response to the comparison. | 2010-01-14 |
| 20100007394 | METHOD AND APPARATUS OF PROVIDING A BIASED CURRENT LIMIT FOR LIMITING MAXIMUM OUTPUT POWER OF POWER CONVERTERS - A biased current-limit circuit for limiting a maximum output power of a power converter includes an oscillator for generating a pulse signal. A waveform generator generates a waveform signal in response to a switching signal and a second-sampling signal. A sample-hold circuit is used to sample the waveform signal to generate a hold signal in response to a first-sampling signal. The sample-hold circuit further samples the hold signal to generate a current-limit threshold in response to the second-sampling signal. A current comparator is utilized to compare a current-sensing signal with the current-limit threshold to limit a maximum on-time of the switching signal. | 2010-01-14 |
| 20100007395 | PULSE GENERATOR - At an occasion of a level transition when a second periodic voltage becomes equal to a main reference voltage a first periodic voltage generating circuit starts a first monotonically changing time-period in which a voltage value of a first periodic voltage increases monotonically from 0, which is an initial value, towards a voltage value of the main reference voltage. At an occasion of a level transition of a first main switching signal when the first periodic voltage becomes equal to the main reference voltage, a second periodic voltage generating circuit starts a second monotonically changing time-period in which a voltage value of the second periodic voltage increases monotonically from 0, which is an initial value, towards a voltage value of the main reference voltage. | 2010-01-14 |
| 20100007396 | COMPOUND LOGIC FLIP-FLOP HAVING A PLURALITY OF INPUT STAGES - A compound logic flip-flop. The flip-flop includes a plurality of input stages, wherein each of the input stages is coupled to receive at least one input signal and a clock signal. Each of the plurality of input (i.e. ‘master’) stages is configured to perform a corresponding input logic function during a first phase of a clock cycle and to store a result of the corresponding input logic function. The flip-flop further includes an output (i.e. ‘slave’) stage coupled to receive the clock signal and the results of the input logic functions from each of the plurality of input stages. The output stage is configured, during a second phase of the clock cycle, to logically combine the results of the input logic functions by performing an output logic function and provide an output signal based on a result of the output logic function. | 2010-01-14 |
| 20100007397 | Delay line circuit for generating a fixed delay - A delay line circuit is provided. The delay line circuit includes a reference voltage generating circuit that generates a reference voltage, the reference voltage having a positive temperature coefficient. The delay line circuit also includes a voltage regulating circuit that generates a regulated voltage in response to the generated reference voltage as an input, and a delay chain circuit coupled to the voltage regulator to receive the regulated voltage, the delay chain circuit outputting a delay signal. In an embodiment consistent with the present invention, the reference voltage generating circuit includes a bandgap reference voltage circuit. In another embodiment consistent with the present invention, the reference voltage generating circuit includes a proportional to absolute temperature (PTAT) circuit. | 2010-01-14 |
| 20100007398 | Linear monotonic delay chain circuit - A method and circuit for generating an adjustable delay signal is presented, wherein the delay can be linear and monotonic with high resolution delay steps. The circuit utilizes one or more serially coupled delay cells and a load cell. Each delay cell comprises an inverter, a nor-multiplexer, and a programmable capacitor, wherein a first control signal is used to control the operation of the nor-multiplexer and a second control signal is used to control capacitance of the programmable capacitor. Values of the first and the second control signals are selected based on any desired range of total delay time and any desired delay time for a specific application of the circuit. | 2010-01-14 |
| 20100007399 | PRE-DRIVER FOR BRIDGE CIRCUIT - A pre-driver for driving a high-side transistor of a bridge driver is connected to a bridge driver including first and second drive transistors connected in series between a high voltage power supply and ground. A reference circuit generates a reference voltage that varies depending on the output voltage of the bridge driver. In response to the reference voltage, the regulator circuit generates an internal power supply voltage that is substantially higher than the output voltage by a constant value. A buffer circuit generates a drive voltage for driving the first drive transistor based on the internal power supply voltage and the output voltage. | 2010-01-14 |
| 20100007400 | POWER SUPPLY CIRCUIT FOR PULSE WIDTH MODULATION CONTROLLER - A power supply circuit for a pulse width modulation controller includes a first resistor and an electric switch having first, second, and third terminals. The first terminal is capable of receiving a control signal of a computer. The second terminal is connected to a stand-by power supply of the computer. The third terminal is connected to the pulse width modulation controller via the first resistor. | 2010-01-14 |
| 20100007401 | SWITCH CONTROL CIRCUIT - A switch control circuit for controlling a bridge circuit comprising: an upper and a lower transistor, connected to a positive and a negative voltage, respectively, and comprising a flywheel diode connected in parallel with each transistor. An LC-circuit filters the voltage from the junction of the transistors. A drive circuit controls each transistor in order to switch off the corresponding switch element when a reference current has been obtained in the inductor and for switching on the corresponding switch element when the current in the inductor is essentially zero. A first timer circuit is arranged for preventing the on-switch of the switch element until a minimum time period has passed. | 2010-01-14 |
| 20100007402 | Weatherproof switch for indoor and outdoor information clusters and function switches - A weatherproof switch for use with an information/instrument cluster including a button having a body located adjacent to the information/instrument cluster, the body having a first end and a second end; a magnet substantially disposed within the second end of the body; a sensor located a distance from the magnet to produce a magnetic field of a first strength; and a circuit connecting the sensor to a function of the information/instrument cluster for controlling the function when the first end of the button is operated to increase and decrease the distance between the magnet and the sensor such as to produce magnetic field of a second strength. | 2010-01-14 |
| 20100007403 | SYSTEM AND METHOD OF MEASURING TEMPERATURE IN A POWER CONTROLLER - An improved system and method measuring a temperature in a power controller is provided. The system includes a circuit board, a solid state switching device, a heat sink, and a temperature sensor. The solid state switching device may be mounted on the circuit board and controls the switching of power to an industrial load. The heat sink is mounted on the solid state switching device such that a first portion of the heat sink is thermal communication with the solid state switching device and a second portion of the heat sink is in thermal communication with an exposed portion of a trace on the circuit board. The temperature sensor may be in thermal communication with the trace. As such, the temperature sensor may be in thermal communication with the solid state switching device through the trace of the circuit board. | 2010-01-14 |
| 20100007404 | Temperature sensor circuit and method for controlling the same - A temperature sensor circuit comprises a first reference voltage generator configured to generate a first signal that linearly varies with temperature and a first reference voltage signal that maintains a certain level irrespective of temperature, a second reference voltage generator configured to generate a second reference voltage signal by using the first reference voltage signal, and a controller configured to compare the first signal with the second reference voltage signal and control a voltage level of the first signal according to a comparison result. | 2010-01-14 |
| 20100007405 | NON-CONTACT TOUCH SWITCH - A non-contact touch switch allows a control circuit to do an accurate change-over start to AC switch power supply by using a human body advanced medium induction manner and comprises an outer cover, correspondingly installed at an outlet of a switch power cord; a microcomputer control circuit, installed on an inner side of the outer cover; a medium transferring interface, installed on the outer cover and having an interconnection with the microcomputer control circuit; a start switch, one end thereof being connected with the microcomputer control circuit and another end thereof being disposed with a control contact connected with an AC switch power cord so as to control an electrification time of an electric facility connected therewith afterwards; and a power interceptor, connected between the microcomputer control circuit and the control contact of the start switch, capable of directly intercepting a power supply from a general public power through the switch power cord to act as a power supply of a normal operation of an internal circuit after being rectified and stabilized. whereby, a volume of a combined switch is allowed to reduce substantially, no additional attached battery is required and the control function can then be brought into full play, a normal work can be maintained once the public power is connected. | 2010-01-14 |
| 20100007406 | Electrical fuse devices and methods of operating the same - Provided are an electrical fuse device and a method of operating the same. The electrical fuse device may include a fuse, and a driving element connected to the fuse and including a resistance change layer having a resistance that changes according to an applied voltage. The resistance change layer may have a metal-insulator transition (MIT) characteristic. As the driving element is turned on, a programming current may be applied to the fuse connected to the driving element. | 2010-01-14 |
| 20100007407 | CIRCUIT FOR GENERATING A NEGATIVE VOLTAGE SUPPLY SIGNAL, AND ASSOCIATED POWER SUPPLY DEVICE AND PORTABLE ELECTRONIC APPARATUS - A circuit for generating a negative voltage supply signal is disclosed. The circuit has a first capacitive element coupled to receive a switched input signal which switches at least between a first state with a positive first voltage and a second state with a second voltage, different from the first voltage. A second capacitive element is coupled to provide the negative voltage supply signal. Control circuitry is coupled to the first capacitive element and the second capacitive element. The control circuitry is arranged, in the first state of the switched input signal, to enable charging of the first capacitive element by the switched input signal, and, in the second state of the switched input signal, to enable charging of the second capacitive element by the first capacitive element to generate the negative voltage supply signal. | 2010-01-14 |
| 20100007408 | INTERNAL VOLTAGE GENERATING CIRCUIT - An output terminal of a first boost circuit is connected to a second boost circuit. After the second boost circuit is started up, a boost clock frequency of the second boost circuit is reduced. A time required to start up the second boost circuit is reduced, and in addition, a current supply capability of the first boost circuit is increased after the second boost circuit is started up. When the second boost circuit is driven, output voltages of the first and second boost circuits are stably supplied without instantaneously changing the output voltage of the first boost circuit. | 2010-01-14 |
| 20100007409 | Method and Related Device for an Adjustable Leading Edge Blanking Device in a Power Supply Device - A method for an adjustable leading edge blanking device in a power supply device includes generating a detection signal according to a leading edge and a trailing edge of a spike signal, generating a blanking signal according to the detection signal, for blanking the spike signal between the leading edge and the trailing edge, and controlling output states of the power supply device according to the blanking signal. | 2010-01-14 |
| 20100007410 | Switch method for switching class amplifiers - In accordance with one the present disclosure, systems and methods are disclosed that include transmitting a binary signal from a signal source into a switch where the switch is in series between the signal source and a first circuit element. In addition, the switch is operating substantially in a switched mode and creates a switched output signal and the switch is controlled by the binary signal. Also disclosed in this method is detecting a negative voltage in a signal from a second circuit element. In this method the first circuit element is in series between the second circuit element and the switch, and upon detecting the negative voltage from the second circuit element the first circuit element creates high impedance in the first circuit element. | 2010-01-14 |
| 20100007411 | PREMIUM POWER AMPLIFIER - The present invention discloses a premium power amplifier applied in an antenna module, and the premium power amplifier includes a first transmission unit, having two symmetrical and identical first arc-shaped circuits, two secondary power amplifiers connected in parallel with each other, and a second transmission unit having two symmetrical and identical second arc-shaped circuits, in which those components above are installed between a power amplifier and an output terminal of the antenna. So that the output power of the antenna can be improved greatly, and the effective transmission distance can be extended. | 2010-01-14 |
| 20100007412 | PULSED LOAD MODULATION AMPLIFIER AND METHOD - Improved power amplifiers and related methods using a pulsed load modulation technique that controls the load modulation characteristics in a digital pulsed fashion. | 2010-01-14 |
| 20100007413 | ECG ELECTRODE CONTACT QUALITY MEASUREMENT SYSTEM - A system and method are provided for generating output signals indicative of contact quality of a plurality of electrodes coupled to a patient. A signal generator coupled to a reference electrode injects an alternating signal into the patient. A plurality of differential amplifiers, each coupled to a respective one of the plurality of electrodes to detect an input signal from the patient, are operable to output a respective output signal in response to a respective input signal. The output signal generated by the respective differential amplifier is indicative of contact quality for the respective electrode. | 2010-01-14 |
| 20100007414 | Gain Control for Linear Radio Freqency Power Amplifiers - A bias control circuit is provided comprising an input port for receiving a signal indicative of an amplitude of a supply voltage provided to a multi stage power amplifier circuit. Electronic circuitry, electrically coupled to the input port, generates a bias control signal in dependence upon the signal indicative of a supply voltage for provision to a first stage power amplifier of the multi stage power amplifier circuit. The bias control signal is generated such that a gain change of the multi stage power amplifier circuit due to a supply voltage change is substantially compensated. | 2010-01-14 |
| 20100007415 | SIGNAL NONLINEAR DISTORATION MAGNITUDE DETECTION METHOD AND DEVICE - The present invention relates to a method for detecting signal nonlinear distortion magnitude, used for extracting and detecting the nonlinear distortion output by a radio frequency power amplifier, characterized in respectively extracting input signal and output signal, and performing square after matching the amplitudes and frequencies of the input signal and output signal respectively, obtaining respective low frequency components of the squared input signal and output signal, therefore, the carrier component of the signals can be filtered, and the low frequency components can characterize the distorted signal feature as well as facilitate handling. The present invention performs square after matching the input signal and output signal, extracts the low frequency component, and then the relativity with the frequency and bandwidth of the signal is low, therefore, the difficulty in detecting the distortion can be reduced greatly. In addition, the square is equivalent to amplify the distortion, which is favorable to improve the detection sensitivity of output distortion. | 2010-01-14 |
| 20100007416 | WIDEBAND DIFFERENTIAL AMPLIFIER INCLUDING SINGLE-ENDED AMPLIFIERS COUPLED TO A FOUR-PORT TRANSFORMER - A differential amplifier is formed from a first single-ended amplifier circuit, a second single-ended amplifier circuit, and a four-port transformer circuit coupled to the first and second single-ended amplifier circuits to form the differential amplifier. | 2010-01-14 |
| 20100007417 | Differential amplifier with symmetric circuit topology - A differential amplifier circuit is provided with a first input stage including a transistor pair of a first conductivity type, of which transistor pair receives differential input signals; a first output stage connected to the first input stage; a second input stage including a transistor pair of a second conductivity type different from the first conductivity type, of which transistor pair receives the differential input signals; a second output stage connected to the second input stage; and an output terminal. The second output stage is structured with a circuit topology in which transistors of the first conductivity type in the first output stage are replaced with transistors of the second conductivity type, transistors of the second conductivity type in the first output stage are replaced with transistors of the first conductivity type, ground terminals in the first output stage are replaced with power supply terminals, and power supply terminals in the first output stage are replaced with ground terminals. The output terminal is commonly connected to outputs of the first and second output stages. | 2010-01-14 |
| 20100007418 | INPUT SYSTEM FOR A VARIABLE GAIN AMPLIFIER HAVING CLASS-AB TRANSCONDUCTANCE STAGES - A variable gain amplifier includes an attenuator having a plurality of pairs of tap points, and a plurality of pairs of gm cells, wherein each pair of gm cells is coupled to a corresponding pair of the tap points, and each pair of gm cells is constructed and arranged to operate as a multi-tanh cell. | 2010-01-14 |
| 20100007419 | Instrumentation Input Systems - An input stage for an instrumentation system may include a resistor coupled between an input terminal and a summing node, and an amplifier arranged to maintain the voltage at the summing node. In anther embodiment, an instrumentation input system may include an input stage to receive a signal to be measured, and a variable gain amplifier having an input coupled to an output of the input stage, wherein the variable gain amplifier comprises two or more gain stages. A variable gain amplifier may include an attenuator having an input and a series of tap points and a series of low-inertia switches to steer outputs from the attenuator to an output terminal. | 2010-01-14 |
| 20100007420 | Operational amplifier - An operational amplifier includes an input stage amplifier that receives an input signal, an output stage amplifier that amplifies a signal output from the input stage amplifier and outputs the signal, a capacitor that is connected between an input node and an output node of the output stage amplifier, and a charge and discharge control circuit that controls a charge and discharge current of the capacitor. | 2010-01-14 |
| 20100007421 | ATTENUATOR WITH BIAS CONTROL CIRCUIT - An attenuator includes one or more series attenuation branches including one or more series field effect transistors (FETs) each having a gate; one or more shunt attenuation branches including one or more shunt FETs each having a gate; and a bias control FET. The bias control FET receives at its gate a first bias control signal and in response thereto produces at one of its drain and source terminals a second bias control signal. Either the first bias control signal is coupled to the gates of one or more series FETs, and the second bias control signal is coupled to the gates of the one or more shunt FETs; or the first bias control signal is coupled to the gates of the one or more shunt FETs, and the second bias control signal is coupled to the gates of the one or more series FETs. | 2010-01-14 |
| 20100007422 | AMPLIFIER CIRCUIT - There is provided an amplifier circuit includes: an amplifying transistor; a first transistor having a DC current amplification factor generally equal to the DC current amplification factor of the amplifying transistor and constituting a current mirror circuit in conjunction with the amplifying transistor; and a current source circuit being operable to supply a current to the first transistor and including a second transistor having opposite conductivity type to the conductivity type of the first transistor. The second transistor is operated in a saturation region at a power supply voltage lower than an operating voltage range so that the DC current amplification factor of the amplifying transistor can be detected. | 2010-01-14 |
| 20100007423 | INTEGRATED POWER AMPLIFIER - Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies. | 2010-01-14 |
| 20100007424 | METHOD OF ACHIEVING HIGH SELECTIVITY IN RECEIVER RF FRONT-ENDS - According to some embodiments, an apparatus may comprise an amplifier, wherein the amplifier comprises: an output stage formed of a positive output terminal providing a positive output voltage and a negative output terminal providing a negative output voltage; a load tank coupled in parallel with the output stage and configured to filter signals received at the amplifier; and a negative resistance block coupled in parallel with the output stage and the load tank. | 2010-01-14 |
| 20100007425 | PLL FREQUENCY SYNTHESIZER - A frequency synthesizer includes a voltage-controlled oscillator, a frequency range tuning circuit which detects a frequency control code that sets a voltage-controlled frequency range of the voltage-controlled oscillator corresponding to the frequency division ratio which is variably-set, and a frequency control code memory which stores the frequency control code detected by the frequency range tuning circuit corresponding to the frequency division ratio. In an initialization interval, the frequency range tuning circuit detects the frequency control code corresponding to the frequency division ratio which is variably-set, and the frequency control code memory stores the frequency control code which is detected. In a normal operation interval, in response to the frequency selection signal, the frequency control code, which is stored in the frequency control code memory and corresponds to the frequency division ratio which is variably-set, is output to the voltage-controlled oscillator. | 2010-01-14 |
| 20100007426 | NONLINEAR PULSE OSCILLATOR METHODS AND APPARATUS - Methods and apparatus for implementing stable self-starting and self-sustaining high-speed electrical nonlinear pulse (e.g., soliton, cnoidal wave, or quasi-soliton) oscillators. Chip-scale nonlinear pulse oscillator devices may be fabricated using III-V semiconductor materials (e.g., GaAs) to attain soliton pulse widths on the order of a few picoseconds or less (e.g., 1 to 2 picoseconds, corresponding to frequencies of approximately 300 GHz or greater). In one example, a nonlinear pulse oscillator is implemented as a closed loop structure that comprises a nonlinear transmission line and a distributed nonlinear amplifier arrangement configured to provide a self-adjusting gain as a function of an average voltage of the oscillator signal. In another example, a nonlinear oscillator employing a lumped nonlinear amplifier and a nonlinear transmission line in a closed loop arrangement may be used in combination with a two-port nonlinear transmission line that provides additional pulse compression for pulses circulating in the oscillator. | 2010-01-14 |
| 20100007427 | SWITCHING CAPACITOR GENERATION CIRCUIT - A switching capacitor generation circuit which reduces the on-resistance and parasitic capacitance of a switch element and improves the operation properties of the switch element. The switching capacitor generation circuit, which has first and second output terminals, includes a first capacitor coupled to the first output terminal, a second capacitor coupled to the second output terminal, and a single switch element coupled between the first and the second capacitors. | 2010-01-14 |
| 20100007428 | OSCILLATION CIRCUIT - This oscillation circuit includes a triangular wave generation circuit that generates a triangular wave signal corresponding to an outputted clock signal, a comparison circuit that generates a clock signal corresponding to a comparison of the triangular wave signal with a first reference voltage and a second reference voltage, a current adjusting circuit that adjusts the value of adjusted current according to the power supply voltage for the comparison circuit, and a reference voltage generation circuit that generates the first reference voltage and the second reference voltage having a voltage differential that corresponds to the value of the adjusted current. The current adjusting circuit increases the adjusted current when the power supply voltage for the comparison circuit rises, and reduces the adjusted current when the power supply voltage drops. The reference voltage generation circuit increases the voltage differential between the first reference voltage and the second reference voltage when the adjusted current increases, and reduces the voltage differential when the adjusted current decreases. | 2010-01-14 |
| 20100007429 | PRINTED CIRCUIT BOARD - A printed circuit board includes a plurality of differential pairs arranged thereon side-by-side. Each differential pair includes two transmission lines. Each transmission line includes a plurality of sections of equal length. Every two adjacent sections in each transmission line meet at an angle, and all angles are equal. The length of each section is determined by dividing the distance between two corresponding angles of the two transmission lines of each differential pair by the cosine of half of the angle. | 2010-01-14 |
| 20100007430 | BALANCED-UNBALANCED CONVERSION CIRCUIT - A balanced-unbalanced conversion circuit includes a first coupling line, an unbalanced terminal connected to the first coupling line, a ground terminal connected to the unbalanced terminal through the first coupling line, a second coupling line electromagnetically coupled to the first coupling line, a first balanced terminal connected to the second coupling line, a second balanced terminal connected to the first balanced terminal through the second coupling line, and a band-reject filter serially connected to the first coupling line to remove predetermined-band signals of high frequency signals transmitted through the first coupling line. | 2010-01-14 |
| 20100007431 | SIGNAL TRANSMISSION STRUCTURE - A signal transmission structure includes two power planes, a signal line and a first pillar. The power planes spaced by an interval space provide a first voltage and a second voltage respectively. The signal line, disposed on first surfaces of the power planes, is disposed across the interval space. The first pillar is disposed within the interval space and is aside the signal line, in which the first pillar is apart from the power planes and the signal line. | 2010-01-14 |
| 20100007432 | Orthomode junction assembly with associated filters for use in an antenna feed system - A reverse orthomode junction assembly with associated filters for use in an antenna feed system for transmitting a first electromagnetic signal at a first frequency range lower than the second frequency range of a receive second electromagnetic signal. The assembly includes an orthomode junction with an antenna port for connecting to an antenna, an opposed generally coaxial first signal port to transmit the first signal, and a generally perpendicular second signal port, located there between, to receive the second signal. A first signal channel having on-axis second signal reject filters connects to the first port; and a second signal channel having cross-axis first signal reject filters connects to the second port. The use of a magic-tee as a combiner for the receive signal provides tracking capability to the antenna feed system. | 2010-01-14 |
| 20100007433 | Power Splitter/Combiner - The present invention is directed to a system that includes a front-end interface device having a first front-end interface port, a second front-end interface port and a third front-end interface port. The front-end interface device is configured to split a first signal directed into the first front-end interface port into a second signal provided at the second front-end interface port and a third signal provided at the third front-end interface port. The first signal has a first bandwidth, the second signal has a second bandwidth and the third signal has a third bandwidth. The second bandwidth is substantially disposed in a relatively high frequency portion of the first bandwidth and the third bandwidth is substantially disposed in a relatively low frequency portion of the first bandwidth. An N-way high-band device includes a first high-band device port coupled to the second front-end interface port and N second high band ports. N is an integer greater than or equal to two (2). The N-way high-band device is configured to split the second signal into N-high band signals and direct the N-high band signals out of corresponding ones of the N-second high band ports. An N-way low-band device includes a first low-band device port coupled to the third front-end interface port and N-second low band ports. The N-way low-band device is configured to split the third signal into N-low band signals and direct the N-low band signals out of corresponding ones of the N-second low band ports. N back-end interface devices are coupled to the N-way high-band device and the N-way low-band device. Each back-end interface device of the N back-end interface devices includes a first back-end interface port coupled to a corresponding one of the N second high band ports, a second back-end interface port coupled to a corresponding one of the N second low band ports, and a third back-end interface port. Each back-end interface is configured to combine one of the N-high band signals and one of the N-low band signals to form a fourth signal directed out of the third back-end interface port such that N-fourth signals are directed out of the N back-end interface devices. The fourth signal has a fourth bandwidth. The fourth signal is a version of the first signal such that the fourth bandwidth and the first bandwidth are substantially identical. | 2010-01-14 |
| 20100007434 | Branching filter package - A branching filter package has a SAW filter chip housing area which houses a piezo electric base, on which a transmitting SAW filter and a receiving SAW filter having a different frequency passing band with each other, are formed, and an impedance matching circuit and a branching circuit for the transmitting SAW filter and the receiving SAW filter. | 2010-01-14 |
| 20100007435 | Duplexer - To provide a duplexer which is small in size and excellent in separation characteristic of transmission/reception signals. An antenna port is disposed on a center of a rearward side in a disposition area of a duplexer, a high band side filter and a low band side filter are respectively disposed on a left side and a right side of the antenna port, a parallel arm at a last stage in the low band side filter, a parallel arm at a last stage in the high band side filter, a first signal port and a second signal port seen from the antenna port are positioned on a forward side of the antenna port, a ground side of a parallel arm on a front stage side of the parallel arm at the last stage in the low band side filter and a ground side of a parallel arm on a front stage side of the parallel arm at the last stage in the high band side filter are mutually connected via a conductive path formed on a piezoelectric substrate at a rearward side of the antenna port, and the parallel arms connected by the conductive path are positioned on the rearward side of the parallel arms at the last stages. Accordingly, a separation characteristic at a high band side is improved. | 2010-01-14 |
| 20100007436 | TWO-DIMENSIONAL LEFT-HANDED METAMATERIAL - The present invention provides a two-dimensional left-handed metamaterial that functions as a two-dimensional electromagnetic wave propagation medium in which the equivalent permittivity and permeability of the medium are both negative, exhibits superior low-loss, broadband characteristics as a left-handed material, and has a simple constitution, enabling low-cost manufacture. | 2010-01-14 |
| 20100007437 | LC COMPOSITE COMPONENT - An LC composite component capable of reducing an overall size while keeping a Q-value of a resonator at a high level and increasing coupling flexibility of resonators includes two capacitor electrodes and two input/output terminal electrodes extending therefrom provided on a first dielectric layer. A ground electrode and another capacitor electrode are provided on second and sixth dielectric layers, respectively. Two substantially linear line electrodes are provided on a third dielectric layer. Two substantially U-shaped line electrodes are provided on a fourth dielectric layer. Two substantially crank-shaped line electrodes are provided on a fifth dielectric layer. Six via electrodes arranged to connect ends of respective line electrodes are provided on the third, fourth, and fifth dielectric layers. These via electrodes and line electrodes constitute electrodes of a double helix structure. | 2010-01-14 |
| 20100007438 | BAND PASS FILTER - A band pass filter includes an original circuit. An interaction of at least two of components of the original circuit produces at least a mutual capacitor or at least a mutual inductor, which constitutes a resonance circuit with the original circuit to produce at least a transmission zero for increasing the attenuation rate of the stop band. | 2010-01-14 |
| 20100007439 | TRANSFORMER - A transformer is provided with four capacitors and four inductors. The first capacitor is electrically connected between a first port and ground in series. The first inductor is electrically connected to the first port in series. The second capacitor is electrically connected between the first inductor and ground in series. The second inductor is electrically connected between the first inductor and the second capacitor in series. The third capacitor is electrically connected between a second port and ground in series. The third inductor is electrically connected to the second port in series. The fourth capacitor is electrically connected between a third port and ground in series. The fourth inductor is electrically connected between the third inductor and the third port in series. | 2010-01-14 |
| 20100007440 | POWER SUPPLY CIRCUIT FOR MOTHERBOARD - A power supply circuit includes a first resistor and a first capacitor. One end of the first resistor is connected to a system power. The other end of the first resistor is connected to the anode of the first capacitor. The cathode of the first capacitor is connected to a digital analog converter A (DACA) VDD pin of a north bridge on a motherboard. The system power provides a stable power signal for the DACA VDD of the north bridge via the first resistor and the first capacitor. Thereby the display no longer ripples when the resolution of the display is adjusted to a certain value. | 2010-01-14 |
| 20100007441 | Coaxial connector having a dielectric material for impedance matching - A coaxial connector includes a first inner conductor and a second inner conductor. A capacitor connects between the first inner conductor and the second inner conductor. An outer conductor extends along and surrounds the first and second inner conductors and the capacitor. A first dielectric material is filled in a gap between the outer conductor and the first and second inner conductors. A support member supports the first and second inner conductors with respect to the outer conductor. A second dielectric material for impedance matching is provided between the capacitor and the outer conductor. | 2010-01-14 |
| 20100007442 | TUNING ELEMENT AND TUNABLE RESONATOR - A resonator is provided with a tuning element based on piezoelectricity. The piezoelectric basic element includes at least one piezoelectric layer and a metal layer. Such a basic element is first coated with a thin insulating layer and then with a good conductor. The thickness of the conductive coating is greater than the skin depth of a field corresponding to the operating frequency of the structure in the conductor. The tuning element formed in this manner is fastened on, e.g., some inner surface of the resonator cavity and acts to change the natural frequency of the resonator by electric control. When using the tuning element, no mechanical arrangement is required for moving the tuning element. Furthermore, the tuning element does not cause considerable dielectric losses nor intermodulation when being in a radiofrequency electromagnetic field, because the field cannot significantly penetrate through said conductive coating into the piezoelectric material. | 2010-01-14 |
| 20100007443 | Nano electromechanical integrated-circuit filter - A nano electromechanical integrated circuit filter and method of making. The filter comprises a silicon substrate; a sacrificial layer; a device layer including at least one resonator, wherein the resonator includes sub-micron excitable elements and wherein the at least one resonator possess a fundamental mode frequency as well as a collective mode frequency and wherein the collective mode frequency of the at least one resonator is determined by the fundamental frequency of the sub-micron elements. | 2010-01-14 |
| 20100007444 | GHz Surface Acoustic Resonators in RF-CMOS - An improved SAW resonator fabricated using RF-CMOS technology is disclosed. The SAW resonator is capable of a resonant frequency of from about 1 GHz to about 3.12 GHz. Several different embodiments namely both single and double port resonators implemented in standard CMOS (0.6 μm) and RF-CMOS (0.18 μm) technologies are presented. | 2010-01-14 |
| 20100007445 | TRANSMISSION LINE RESONATOR, HIGH-FREQUENCY FILTER USING THE SAME, HIGH-FREQUENCY MODULE, AND RADIO DEVICE - A transmission line type resonator having a low-loss characteristic. In order to realize the low-loss characteristic, the transmission line type resonator in the present invention includes a laminate body formed of a plurality of dielectric sheets, a transmission line of complex right hand left hand system disposed between the plurality of dielectric sheets, and an external connection terminal disposed at the end face of the transmission line type resonator and connected with the transmission line of complex right hand left hand system. | 2010-01-14 |
| 20100007446 | FILTER DEVICE AND METHOD FOR MANUFACTURING THE SAME - A filter device having a frame made of plated steel sheet generates a smaller insertion loss and is excellent in productivity. Resonant elements are shaped into a cylindrical form by bending the steel sheet, whose both sides are plated, before they are placed in a filter housing. A gap formed on a lateral face of the resonant element is brazed with solder, and an outer plated face of the resonant element is brazed with solder to an inner plated face of the frame. | 2010-01-14 |
| 20100007447 | MISWIRING CIRCUIT COUPLED TO AN ELECTRICAL FAULT INTERRUPTER - The disclosure relates to an electrical fault interrupter comprising at least one electrical fault sensor which is configured to detect an electrical fault condition, at least one miswiring circuit configured to detect the improper connection to the electrical fault sensor, and at least one circuit interrupter which is configured to open at least one circuit in the presence of an electrical fault or a miswiring condition. In at least one embodiment, one end of the miswiring circuit is coupled to a ground line. | 2010-01-14 |
| 20100007448 | MEMS relay with a flux path that is decoupled from an electrical path through the switch and a suspension structure that is independent of the core structure and a method of forming the same - A micro-electromechanical (MEMS) relay decouples a flux path from magnetic actuation from the electrical path through the switch to eliminate signal degradations that result from fluctuations in the current around the core and, thereby the flux. In addition, the MEMS relay has a suspension structure that is independent of the core. | 2010-01-14 |
| 20100007449 | MAGNETICALLY COUPLED DEVICE - Provided is a magnetically coupled device, a method of assembling the magnetically coupled system, and a method whereby positioning a first arrangement and a second arrangement prevents a magnetic field generated from within a first plurality of magnets and a second plurality of magnets from affecting a magnetically sensitive component. | 2010-01-14 |
| 20100007450 | Tone Wheel - A tone wheel constituting a rotation detection magnetic encoder in combination with a magnetic sensor fixed onto a stationary side member, the tone wheel comprising a metal reinforcing ring fitted in a rotary side member and a circular multipolar magnet fixed to the metal reinforcing ring. the circular multipolar magnet is made of a plastic magnet of a circular resin molded product which contains a magnetic powder therein and is magnetized with a number of S and N poles alternatively along its circumference; the circular multipolar magnet is fixed to a surface of the metal reinforcing ring opposed to the magnetic sensor with an adhesive; and a restraint portion is provided at a part of the portion wherein the circular multipolar magnet is fixed to the metal reinforcing ring, thereby fixation of the circular multipolar magnet to the metal reinforcing ring is reinforced and depart of the circular multipolar magnet from the metal reinforcing ring is prevented. | 2010-01-14 |
| 20100007451 | SURFACE MOUNT MAGNETIC COMPONENT ASSEMBLY - A surface mount magnetic component assembly including a magnetic core having a side with a stepped external surface, a coil within the magnetic core, and terminal clips for making electrical connections to the ends of the coil. The ends of the coil extend through the stepped external surface, the terminal clips attach to the stepped external surface, and the external surface is mounted to a circuit board to complete electrical connection with improved reliability. Smaller component sizes with improved manufacturability and consistency result. | 2010-01-14 |
| 20100007452 | HIGH VOLTAGE TRANSFORMER WITH A SHIELD RING. A SHIELD RING AND A METHOD OF MANUFACTURE SAME - A high voltage transformer including a transformer housing. Internal components and provided in the transformer housing. The internal components are submerged in transformer oil and are provided with insulation for insulating a high voltage winding end. The insulation includes a shield ring arranged above the winding end and a pressboard structure formed in a zigzag pattern arranged around the winding end. The shield ring includes a core covered with a conducting layer and a continuous solid insulation layer outside the conducting layer. The insulation layer includes integrated solid insulation sections of which at least some among themselves having varying thickness. Also a shield ring and a method of manufacture the shield ring. | 2010-01-14 |
| 20100007453 | SURFACE MOUNT MAGNETIC COMPONENTS AND METHODS OF MANUFACTURING THE SAME - Magnetic component assemblies including moldable magnetic materials including surface mount termination features, as well as manufacturing methods therefor, are disclosed that are advantageously utilized in providing surface mount magnetic components such as inductors and transformers. | 2010-01-14 |
| 20100007454 | APPARATUS, SYSTEM, AND METHOD FOR AN INTEGRATED WINDING STRUCTURE FOR A MAGNETIC CORE - An apparatus, system, and method are disclosed for combining multiple windings on a magnetic core. An integrated winding structure has a winding base and multiple winding extensions. The multiple winding extensions and the winding base are formed from a single sheet of electrically conductive material. Each of the multiple winding extensions has a base portion that extends from the winding base, a wrapping portion that extends from the base portion, and a connection portion that extends from the wrapping portion. The connection portions and the winding base each have electrical connection surfaces. Each of the multiple winding extensions forms one or more windings on the magnetic core. | 2010-01-14 |
