02nd week of 2010 patent applcation highlights part 15 |
Patent application number | Title | Published |
20100006958 | Tilting Actuator with Close-Gap Electrodes - An electromechanical tilting device including a first and a second electrode structures, shaped, positioned and oriented to define at least partially interdigitated electrodes, and a suspension defining a tilt-containing motion path for the second structure with respect to the first structure. The motion path is selected to cause changes in overlapping regions and overlapping regions' gaps of the interdigitated electrodes. The device is configured such that an increase in one or more voltage bias applied to interdigitated driving electrodes makes a decrease in a total area of overlapping regions of the driving electrodes electrically energetically favorable. | 2010-01-14 |
20100006959 | PACKAGE OF MEMS DEVICE AND METHOD FOR FABRICATING THE SAME - A package of a micro-electro-mechanical systems (MEMS) device includes a cap wafer, a plurality of bonding bumps formed over the cap wafer, a plurality of array pads arrayed on an outer side of the bonding bumps, and an MEMS device wafer bonded to an upper portion of the cap wafer in a manner to expose the array pads. | 2010-01-14 |
20100006960 | Novel magnetic tunnel junction (MTJ) to reduce spin transfer magnetizaton switching current - A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to <1×10 | 2010-01-14 |
20100006961 | Recessed Germanium (Ge) Diode - A photodiode is formed in a recessed germanium (Ge) region in a silicon (Si) substrate. The Ge region may be fabricated by etching a hole through a passivation layer on the Si substrate and into the Si substrate and then growing Ge in the hole by a selective epitaxial process. The Ge appears to grow better selectively in the hole than on a Si or oxide surface. The Ge may grow up some or all of the passivation sidewall of the hole to conformally fill the hole and produce a recessed Ge region that is approximately flush with the surface of the substrate, without characteristic slanted sides of a mesa. The hole may be etched deep enough so the photodiode is thick enough to obtain good coupling efficiencies to vertical, free-space light entering the photodiode. | 2010-01-14 |
20100006962 | Method of manufacturing a porous structure - Disclosed is a method for fabrication of a porous structure that can prevent release of a protective layer from a semiconductor substrate even if a liquid chemical is used during an anodic oxidation process. The method includes forming an oxide layer on an upper face of the semiconductor substrate. The semiconductor substrate has a diffusion layer in its upper face. The method also includes forming a plurality of contact holes at desired positions of the oxide layer. The method also includes forming a wire in each of the contact holes, and forming an opening between wires to expose a surface of the diffusion layer. The method also includes forming a drain on a peripheral circumference of the opening and depositing a protective film over an entire upper part of the substrate. The protective film fills the drain. The method also includes removing most of the protective film from the opening while leaving behind a part of the protective film on the peripheral circumference of the opening and exposing a certain portion of the diffusion layer. The method also includes applying an anodic oxidation process to the exposed diffusion layer using the remaining protective film as a protective layer. | 2010-01-14 |
20100006963 | WAFER LEVEL PROCESSING FOR BACKSIDE ILLUMINATED SENSORS - A backside illuminated image sensor comprises a sensor layer having a plurality of photosensitive elements of a pixel array, an oxide layer adjacent a backside surface of the sensor layer, and at least one dielectric layer adjacent a frontside surface of the sensor layer. A color filter array is formed on a backside surface of the oxide layer, and a transparent cover is attached to the backside surface of the oxide layer overlying the color filter array. Redistribution metal conductors are in electrical contact with respective bond pad conductors through respective openings in the dielectric layer. A redistribution passivation layer is formed over the redistribution metal conductors, and contact metallizations are in electrical contact with respective ones of the respective redistribution metal conductors through respective openings in the redistribution passivation layer. The image sensor may be implemented in a digital camera or other type of digital imaging device. | 2010-01-14 |
20100006964 | BACKSIDE ILLUMINATED IMAGE SENSOR HAVING BIASED CONDUCTIVE LAYER FOR INCREASED QUANTUM EFFICIENCY - A backside illuminated image sensor includes a sensor layer comprising a plurality of photosensitive elements of the pixel array, a circuit layer comprising circuitry associated with the pixel array, a conductive layer formed on a backside surface of the sensor layer, and one or more conductive contacts configured to couple the conductive layer to a bias source in the circuit layer. The biased conductive layer produces an electric field across the photosensitive elements of the pixel array that facilitates charge carrier collection and reduces crosstalk between adjacent photosensitive elements, thereby providing improved quantum efficiency in the image sensor. The image sensor may be implemented in a digital camera or other type of digital imaging device. | 2010-01-14 |
20100006965 | ELECTRONIC DEVICE PACKAGE WITH ELECTROMAGNETIC COMPATIBILITY (EMC) COATING THEREON - Electronic device packages with electromagnetic compatibility (EMC) coating thereon are presented. An electronic device package includes a chip scale package having a CMOS image sensor (CIS) array chip and a set of lenses configured with an aperture. An encapsulation is molded overlying the chip scale package. A shield is atop the encapsulation. A frame fixes the set of lenses to the encapsulation. An electromagnetic compatibility (EMC) coating is formed on the encapsulation to prevent electromagnetic interference. | 2010-01-14 |
20100006966 | Method for making lens modules and lens module made thereby - A method for making lens modules includes the steps of: a) providing a wafer including an array of sensor chips; b) mounting a plurality of lens assemblies on the sensor chips, respectively, thereby defining a plurality of intersecting spacing grooves among the lens assemblies; c) forming substrate layer by filling in the spacing grooves with a resin material; and d) cutting the wafer and the substrate layer along intersecting cutting lines each extending along one of the spacing grooves and each intervening the lens assemblies, the substrate layer being divided into a plurality of barrels respectively surrounding the lens assemblies. A lens module made by the method is also disclosed. | 2010-01-14 |
20100006967 | SEMICONDUCTOR PHOTODETECTOR - A semiconductor photodetector comprises: a semiconductor substrate; a first multilayer reflective layer on a first surface of the semiconductor substrate and including semiconductor layers; a first optically-resonant layer on the first multilayer reflective layer; a second multilayer reflective layer on the first optically-resonant layer and including semiconductor layers; a light absorbing layer on the second multilayer reflective layer; a reflective film on the light absorbing layer; and an antireflective film on a second surface of the semiconductor substrate. The first optically-resonant layer has a larger thickness than the semiconductor layers of the first and second multilayer reflective layers. The combined optical thickness of the layers between the second multilayer reflective layer and the reflective film is not equal to the optical thickness of the first optically-resonant layer. | 2010-01-14 |
20100006968 | Image sensors and methods of manufacturing the same - Provided are image sensors and a methods of manufacturing image sensors. The image sensors may include a substrate, a pixel array region, and a peripheral circuit region. The substrate includes a first region and a second region. The pixel array region may be formed on the first region. The peripheral circuit region may be formed on the second region. The first region may be located higher than the second region. According to the image sensor and the method of manufacturing the same, the vertical height of the pixel array region is decreased as compared to the prior art, and thus the aspect ratio at the pixel array region is minimized. As a result, condensing efficiency the image sensor may be improved. | 2010-01-14 |
20100006969 | Image sensor, substrate for the same, image sensing device including the image sensor, and associated methods - A method of fabricating a CMOS image sensor includes forming a substrate structure that includes a first substrate, a second substrate, and an index matching layer containing nitrogen and an oxide layer between the first and second substrates, and, forming at least one light-sensing device in the second substrate, and after forming the substrate structure, forming a metal interconnection structure on a first surface of the second substrate, the first surface facing away from the first substrate, such that the at least one light sensing device is between the metal interconnection structure and the index matching layer and the oxide layer, the metal interconnection structure being electrically connected to the at least one light-sensing device. | 2010-01-14 |
20100006970 | BACKSIDE ILLUMINATED IMAGE SENSOR WITH REDUCED DARK CURRENT - A backside illuminated image sensor comprises a sensor layer implementing a plurality of photosensitive elements of a pixel array, and an oxide layer adjacent a backside surface of the sensor layer. The sensor layer comprises a seed layer and an epitaxial layer formed over the seed layer, with the seed layer having a cross-sectional doping profile in which a designated dopant is substantially confined to a pixel array area of the sensor layer. The doping profile advantageously reduces dark current generated at an interface between the sensor layer and the oxide layer. The image sensor may be implemented in a digital camera or other type of digital imaging device. | 2010-01-14 |
20100006971 | IMAGE PICKUP DEVICE AND CAMERA - An object is to provide a solid state image pickup device and a camera which do not worsen a sensor performance in terms of an optical property, a saturated charge amount and the like. A solid state image sensor including a pixel region having a plurality of pixels includes at least a photodiode and an amplifying portion amplifying photocharges outputted from the photodiode in the pixel region, and further includes a well electrode for taking well potential of a well region in which the amplifying portion is arranged. Between the well electrode and the photodiode, no element isolation regions by an insulation film are arranged. Moreover, on the surface of a first semiconductor region in which the photodiode stores the charges, a second semiconductor layer of a conductivity type reverse to that of the first semiconductor region is arranged. | 2010-01-14 |
20100006972 | WAFER SCALE MEMBRANE FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE FABRICATION - An fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO | 2010-01-14 |
20100006973 | STI Structure At SOI/Bulk Transition For HOT Device - A semiconductor device with STIs separating HOT regions is described. Processes for eliminating voids due to misalignments in boundary region STIs are described. | 2010-01-14 |
20100006974 | STORAGE NITRIDE ENCAPSULATION FOR NON-PLANAR SONOS NAND FLASH CHARGE RETENTION - The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings. | 2010-01-14 |
20100006975 | METHOD OF ELIMINATING MICRO-TRENCHES DURING SPACER ETCH - A method of forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a substrate region. The method also includes forming a pad oxide layer overlying the substrate region. The method additionally includes forming a stop layer overlying the pad oxide layer. Furthermore, the method includes patterning the stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a height. Also, the method includes depositing alternating layers of oxide and silicon nitride to at least fill the trench, the oxide being deposited by an HDP-CVD process. The method additionally includes performing a planarization process to remove a portion of the silicon nitride and oxide layers. In addition, the method includes removing the pad oxide and stop layers. | 2010-01-14 |
20100006976 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention provides a semiconductor device having a capacitor with reduced deterioration of dielectric constant and reduced leakage between upper and lower electrodes and a manufacturing method of such a semiconductor device. A capacity structure is configured by sequentially stacking a lower electrode, a capacitive insulation film, and an upper electrode on wiring or a contact plug. The capacity structure is of a thin-film capacitor structure having, at the interface between the lower electrode and the capacitive insulation film, a thin metal film having insulating properties and exhibiting a high dielectric constant. | 2010-01-14 |
20100006977 | INDUCTOR AND FILTER - An inductor includes a first air-bridge section and a second air-bridge section. The first air-bridge unit extends in a floating location over a substrate between a plurality of support locations on the substrate. The second air-bridge unit extends in a floating location over the first air-bridge unit between a plurality of support locations on the first air-bridge unit. This arrangement enables the first and second air-bridge sections to be connected in parallel, thus branching a flowing current. Thus, the conductor loss in each of the first and second air-bridge sections is reduced. | 2010-01-14 |
20100006978 | CIRCUIT BOARD AND SEMICONDUCTOR DEVICE - A semiconductor device, includes: a semiconductor substrate; a multilayered interconnect structure formed on the semiconductor substrate; a terminal for flip-chip packaging arranged on the surface of the multilayered interconnect structure; and a spiral inductor formed to enclose the terminal for flip-chip packaging, in a plan view, which is not electrically connected with the spiral inductor. The spiral inductor may be provided for peaking by which the gain reduction caused in a high frequency is compensated. | 2010-01-14 |
20100006979 | METHOD OF MANUFACTURING A TRENCH CAPACITOR FOR HIGH VOLTAGE PROCESSES - The present invention provides embodiments of a capacitor and a method of forming the capacitor. The capacitor includes one or more trenches formed in a semiconductor layer above a substrate. The trench includes dielectric material deposited on the trench walls and a conductive fill material formed within the trench and above the dielectric material. The capacitor also includes one or more first doped regions formed adjacent the trench(es) in the semiconductor layer. The first doped region is doped with a first type of dopant. The capacitor further includes one or more second doped regions formed adjacent the first doped region(s) in the semiconductor layer. The second doped regions are doped with a second type of dopant that is opposite to the first type of dopant. | 2010-01-14 |
20100006980 | SEMICONDUCTOR DEVICE - A problem of an increased manufacturing cost is caused in conventional semiconductor devices. A semiconductor device | 2010-01-14 |
20100006981 | CAPACITANCE ARRANGEMENT AND METHOD RELATING THERETO - A capacitance arrangement comprising at least one parallel-plate capacitor comprising a first electrode means, a dielectric layer and a second electrode means partly overlapping each other. A misalignment limit is given. Said first electrode means comprises a first and a second electrode arranged symmetrically with respect to a longitudinal axis, said first and second electrodes have a respective first edge, which face each other, are linear and parallel such that a gap is defined there between. Said second electrode means comprises a third electrode with a first section and a second section disposed on opposite sides of said gap interconnected by means of an intermediate section, which is delimited by a function depending on a first parameter and a second parameter. One of said two parameters is adapted to be selected hence allowing calculation of the other parameter to determine the shape and size of the second electrode means. | 2010-01-14 |
20100006982 | METHOD OF PRODUCING SEMICONDUCTOR WAFER - There is provided a method of producing a semiconductor wafer which is high in the beveling accuracy and the yield for large-size wafers having a diameter of not less than 450 mm, comprising a slicing step for cutting out a disc-shaped wafer having a diameter of not less than 450 mm from a single crystal ingot, a step for lapping a surface of the wafer to conduct planarization, a step for beveling an edge portion of the wafer, a step for grinding the surface of the wafer and a step for mirror-polishing the surface of the wafer, wherein the planarizing step performs the lapping with free abrasive grains of #1000 to #1500. | 2010-01-14 |
20100006983 | PROCESS FOR PRODUCING SUBLITHOGRAPHIC STRUCTURES - A layer structure and process for providing sublithographic structures are provided. A first auxiliary layer is formed over a surface of a carrier layer. A lithographically patterned second auxiliary layer structure is formed on a surface of the first auxiliary layer. The first auxiliary layer is anisotropically etched using the patterned second auxiliary layer structure as mask to form an anisotropically patterned first auxiliary layer structure. The anisotropically patterned first auxiliary layer structure is isotropically etched back using the patterned second auxiliary layer structure to remove subsections below the second auxiliary layer structure and to form an isotropically patterned first auxiliary layer structure. A mask layer is formed over the carrier layer including the subsections beneath the second auxiliary layer structure and is anisotropically etched down to the carrier layer to form the sublithographic structures. The first and second auxiliary layer structures are removed to uncover the sublithographic structures | 2010-01-14 |
20100006984 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; a layered body formed on the substrate and including a multilayer interconnection structure, the layered body including multiple interlayer insulating films stacked in layers, the interlayer insulating films being lower in dielectric constant than a SiO | 2010-01-14 |
20100006985 | FORMATION OF SOI BY OXIDATION OF SILICON WITH ENGINEERED POROSITY GRADIENT - A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type doped silicon-containing layer may be epitaxially grown onto a major surface of the p-type highly-doped epitaxial layer to cover the highly p-type doped epitaxial layer. The overlying non-highly p-type doped epitaxial layer can have a dopant concentration substantially lower than the dopant concentration of the highly p-type doped epitaxial layer. The substrate can then be processed to form a buried oxide layer selectively by oxidizing at least portions of the highly p-type doped epitaxial layer covered by the non-highly p-type doped epitaxial layer, the buried oxide layer separating the overlying monocrystalline semiconductor layer from the underlying semiconductor region. Such processing can be performed while simultaneously annealing the non-highly p-type doped epitaxial layer. | 2010-01-14 |
20100006986 | Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions - A restricted layout region is defined to include a diffusion level layout that includes a plurality of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout of the restricted layout region. The plurality of diffusion region layout shapes include a p-type diffusion region layout shape and an n-type diffusion region layout shape separated by a central inactive region. A gate electrode level layout is defined include a number of rectangular-shaped layout features placed to extend in only a first parallel direction, and defined along at least four different lines of extent in the first parallel direction. The restricted layout region corresponds to an entire gate electrode level of a cell layout. | 2010-01-14 |
20100006987 | INTEGRATED CIRCUIT PACKAGE WITH EMI SHIELD - An integrated circuit (IC) device ( | 2010-01-14 |
20100006988 | Integrated Conformal Shielding Method and Process Using Redistributed Chip Packaging - An integrated conformal electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules ( | 2010-01-14 |
20100006989 | METHOD OF FORMING A SHIELDED SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a semiconductor device is formed to include a plurality of conductor layers that interconnect electrical signals between semiconductor elements of the semiconductor device. A metal shield layer is formed overlying a portion of the plurality of conductor layers. A signal re-distribution layer is formed overlying the metal shield layer. | 2010-01-14 |
20100006990 | INTERCONNECT STRUCTURE FOR HIGH FREQUENCY SIGNAL TRANSMISSIONS - A higher aspect ratio for upper level metal interconnects is described for use in higher frequency circuits. Because the skin effect reduces the effective cross-sectional area of conductors at higher frequencies, various approaches are described to reduce the effective RC delay in interconnects. | 2010-01-14 |
20100006991 | PACKAGING INTEGRATED CIRCUITS FOR HIGH STRESS ENVIRONMENTS - One aspect of the invention pertains to a semiconductor package suitable for use in high stress environments, such as ones involving high pressures, temperatures and/or corrosive substances. In this aspect, a die and leadframe are fully encapsulated in a first plastic casing. The first plastic casing is fully encapsulated in turn with a second plastic casing. The two casings have different compositions. The first plastic casing, for example, may be made of a thermoset plastic material and the second plastic casing may be made of a thermoplastic material. The first plastic casing may have recesses, indentations and/or slots suitable for securing it to the second plastic casing. In some embodiments, a corrosion resistant coating is added to the second plastic casing. Methods for forming semiconductor packages suitable for use in high stress environments are also described. | 2010-01-14 |
20100006992 | Fine-pitch routing in a lead frame based system-in-package (SIP) device - In an example embodiment, there is a package substrate ( | 2010-01-14 |
20100006993 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CHIP ON LEAD - An integrated circuit package system includes: providing a lead having a lead connection surface for connectivity to a next level system; attaching an integrated circuit over the lead having the lead connection surface substantially within a region below a perimeter of the integrated circuit without a die paddle, a substrate conductor, or a redistribution layer; and attaching a die connector to the integrated circuit and the lead. | 2010-01-14 |
20100006994 | Embedded Semiconductor Die Package and Method of Making the Same Using Metal Frame Carrier - An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each having a lead frame interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the lead frame interconnect structure and encapsulant. The package interconnect structure and lead frame interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the lead frame interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the lead frame interconnect structure. | 2010-01-14 |
20100006995 | RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device comprises a semiconductor chip including a silicon substrate, a die pad to which the semiconductor chip is secured through a first solder layer, a resin-encapsulating layer encapsulating the semiconductor chip, and lead terminals electrically connected to the semiconductor chip and including inner lead portion covered with the resin-encapsulating layer. The lead terminals are made of copper or a copper alloy. The die pad is made of 42 alloy or a cover alloy and has a thickness (about 0.125 mm) less than the thickness (about 0.15 mm) of the lead terminals. | 2010-01-14 |
20100006996 | CARRIER FOR BONDING A SEMICONDUCTOR SHIP ONTO AND A METHOD OF CONTRACTING A SEMICONDUCTOR CHIP TO A CARRIER - A carrier ( | 2010-01-14 |
20100006997 | Chip-Stacked Package Structure with Leadframe Having Multi-Piece Bus Bar - The present invention provides a chip-stacked package structure with leadframe having multi-piece bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips stacked together and provided on the die pad, the plurality of chips and the plurality of inner leads arranged in rows facing each other being electrically connected with each other; and an encapsulant provided to cover the chip-stacked structure and the leadframe; wherein the leadframe comprises at least a bus bar provided between the plurality of inner leads arranged in rows facing each other and the die pad, the bus bar being formed by multiple pieces. | 2010-01-14 |
20100006998 | LIQUID RESIN COMPOSITION, SEMICONDUCTOR WAFER HAVING ADHESIVE LAYER, SEMICONDUCTOR ELEMENT HAVING ADHESIVE LAYER, SEMICONDUCTOR PACKAGE, PROCESS FOR MANUFACTURING SEMICONDUCTOR ELEMENT AND PROCESS FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A liquid resin composition of the present invention is a liquid resin composition for bonding a semiconductor element on a support, exhibiting a tackiness of 0.05 N or less after heating at 120° C. for 10 min and a tackiness of 1 N or more at 80° C. A semiconductor wafer having an adhesive layer of the present invention is a semiconductor wafer having an adhesive layer in which the adhesive layer is formed from the above liquid resin composition. A process for manufacturing a semiconductor element of the present invention has the application step of applying an adhesive as a liquid resin composition containing a thermosetting resin and a solvent to one side of a wafer; the evaporation step of evaporating said solvent while substantially maintaining a molecular weight of said liquid resin composition to form an adhesive layer; the bonding step of bonding a dicing sheet on one side of said wafer; and the cutting step of cutting said wafer into pieces. | 2010-01-14 |
20100006999 | SUBSTRATE BONDING METHOD AND ELECTRONIC COMPONENT THEREOF - A substrate bonding method has a film forming step of forming an insulating film for bonding in such a manner that an SiO | 2010-01-14 |
20100007000 | PACKAGE STACKING SYSTEM WITH MOLD CONTAMINATION PREVENTION - A package stacking system includes: providing a package substrate; mounting an integrated circuit over the package substrate; forming a step-down interposer over the integrated circuit; and molding a stack package body, having a step profile, on the package substrate and the step-down interposer. | 2010-01-14 |
20100007001 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other. | 2010-01-14 |
20100007002 | MULTI-LAYER SEMICONDUCTOR PACKAGE - A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through vertical connectors. The top side of the interposer substrate is substantially exposed and comprises input/output (I/O) terminals for the mounting of additional electronic components. The base and interposer substrates can be configured with I/O terminals such that components mounted on the substrates can be electrically coupled through the vertical connectors. The base substrate also can be electrically coupled to an additional electronic component, such as a printed circuit board. Electrical connections can be “wrapped around” from the base substrate to the top of the interposer substrate. The vertical connectors can be positioned along multiple sides of the package. | 2010-01-14 |
20100007003 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a GaAs chip; and a resin sealing the GaAs chip. The GaAs chip includes: a p-type GaAs layer; an n-type GaAs layer on the p-type GaAs layer; a metal electrode located on the n-type GaAs layer along an edge of the GaAs chip and to which a positive voltage is applied; a device region located in a central portion of the GaAs chip; a semi-insulating region located between the metal electrode and the device region and extending in the p-type GaAs layer and the n-type GaAs layer; and a connecting portion disposed outside the semi-insulating region and electrically connecting the p-type GaAs layer to the metal electrode. | 2010-01-14 |
20100007004 | WAFER AND SEMICONDUCTOR PACKAGE - A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad. | 2010-01-14 |
20100007005 | Semiconductor device - A semiconductor device suppresses a magnetic field caused by a current loop formed by a signal wiring and a return path wiring, to reduce transmission loss of a high-speed signal. The semiconductor device includes a signal current path connected from a signal pad to a first external terminal via a first bonding wire and an interposer, and a current return path connected from a second external terminal provided adjacent to the first external terminal to a second pad provided adjacent to the signal pad via the interposer essentially on the same plane. The signal current path and the current return path are positioned so that they intersect with each other, thereby reversing the direction of a loop through which the current flows, and as a result, magnetic fields caused by the current loop formed by the signal current path and the current return path cancel each other. | 2010-01-14 |
20100007006 | Integrated Semiconductor Outline Package - A transistor outline package is provided for a semiconductor integrated device suitable for use in a control module of an automobile for connection between a printed circuit board and a bus bar of such a module. The package includes a package housing, having a first end suitable for mounting to a PCB and which has a width. The package is also formed with a leadframe which includes a heat sink and ground plane blade suitable for connection to a bus bar, a plurality of connector leads suitable for connection to a PCB and at least one source tab lead suitable for connection to a module connector of such a control module. The plurality of connection leads and the source tab lead extend from the first end of the package housing side by side in the direction along and within the width of the first end of the package housing. | 2010-01-14 |
20100007007 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a semiconductor chip having a first surface, and a second surface that is opposite to the first surface and allows a semiconductor device to be formed thereon; bonding pads disposed on the second surface of the semiconductor chip; and a metal ion barrier layer disposed on the first surface of the semiconductor chip, and preventing metal ions from penetrating into the semiconductor chip through the first surface of the semiconductor chip. Accordingly, the semiconductor package can obtain a superior semiconductor device by minimizing moisture absorption and effectively blocking the penetration of metal ions. | 2010-01-14 |
20100007008 | BGA PACKAGE - A BGA package has an LSI package, a plurality of terminal pads arranged in a grid pattern on the rear surface of the LSI package, and solder balls for soldering the LSI package to a printed wiring board via the terminal pads. A plurality of the terminals pads located at each of the four corners of the outermost periphery of the LSI package form a group of first terminal pads, and each group of terminal pads is formed integrally as a reinforcing pad having a greater size than that of the other terminal pads. | 2010-01-14 |
20100007009 | SEMICONDUCTOR PACKAGE AND METHOD FOR PROCESSING AND BONDING A WIRE - A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion. | 2010-01-14 |
20100007010 | SEMICONDUCTOR PACKAGE, METHOD FOR ENHANCING THE BOND OF A BONDING WIRE, AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE - A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire. | 2010-01-14 |
20100007011 | SEMICONDUCTOR PACKAGE AND METHOD FOR PACKAGING A SEMICONDUCTOR PACKAGE - A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad. | 2010-01-14 |
20100007012 | ELECTRONIC SYSTEM MODULES - This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server or supercomputer embodiment is also described. | 2010-01-14 |
20100007013 | Semiconductor device - A semiconductor device, comprising: a semiconductor element | 2010-01-14 |
20100007014 | SEMICONDUCTOR DEVICE - According to an aspect of the invention, a semiconductor device includes: a semiconductor substrate; a memory chip disposed on the semiconductor substrate, the memory chip including: a first face that is not opposed to the semiconductor substrate; and a plurality of first pads disposed on the first face so that the first pads are aligned along a virtual line passing at a central portion on the first face; a controller chip disposed on the first face not to cover the first pads, the controller chip including: a second face that is not opposed to the first face; and a plurality of second pads disposed on the second face so that the second pads are aligned along at least one side of the second face; and a plurality of metal wires electrically connecting the first pads and the second pads. | 2010-01-14 |
20100007015 | INTEGRATED CIRCUIT DEVICE WITH IMPROVED UNDERFILL COVERAGE - An integrated circuit device ( | 2010-01-14 |
20100007016 | DEVICE WITH CONTACT ELEMENTS - A device with contact elements. One embodiment provides an electrical device including a structure defining a main face. The structure includes an array of cavities and an array of overhang regions, each overhang region defining an opening to one of the cavities. The electrical device further includes an array of contact elements, each contact element only partially filling one of the cavities and protruding from the structure over the main face. | 2010-01-14 |
20100007017 | INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD FOR THE SAME - The present invention discloses an inter-connecting structure for a semiconductor package and a method for the same. The inter-connecting structure for the semiconductor package comprises a substrate formed to support a die thereon; core paste formed on the substrate and adjacent to the die; and a stiffener formed in an upper portion of the core paste, wherein the hardness of the stiffener is larger than the hardness of the core paste. | 2010-01-14 |
20100007018 | PROCESS FOR COATING A BUMPED SEMICONDUCTOR WAFER - A process is described that enables the active side of a bumped wafer to be coated with a front side protection (FSP) material or wafer level underfill (WLUF) without contaminating the solder bumps with the coating material and/or filler. In this process a repellent material is applied to a top portion of the solder bumps on the active side of the wafer, the front side of the wafer is then coated with the coating material, the coating material is hardened, and optionally the repellent material is removed from the solder bumps. | 2010-01-14 |
20100007019 | Semiconductor Device and Method of Forming Composite Bump-on-Lead Interconnection - A semiconductor device has a semiconductor die mounted to a substrate with a plurality of composite interconnects formed between interconnect sites on the substrate and bump pads on the die. The interconnect sites are part of traces formed on the substrate. The interconnect site has a width between 1.0 and 1.2 times a width of the trace. The composite interconnect is tapered. The composite interconnects have a fusible portion connected to the interconnect site and non-fusible portion connected to the bump pad. The non-fusible portion can be gold, copper, nickel, lead solder, or lead-tin alloy. The fusible portion can be tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead. An underfill material is deposited between the semiconductor die and substrate. A finish such as Cu-OSP can be formed over the substrate. | 2010-01-14 |
20100007020 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: an insulating film including a porous insulating material and formed above a substrate; an interconnection wire including copper and buried in a groove formed at least in an obverse surface of the insulating film; and a barrier insulating film including an insulating material containing a nitrogen heterocyclic compound and formed over the insulating film and the interconnection wire. | 2010-01-14 |
20100007021 | Methods of Fabricating Semiconductor Devices Including Porous Insulating Layers - Semiconductor devices including a substrate and an uppermost insulating layer formed on the substrate and having pores is provided. A conductive wiring is provided in the uppermost insulating layer. Dummy vias are provided, each penetrating the uppermost insulating layer, being adjacent to the conductive wiring, and having a space therein. Related methods of fabricating semiconductor devices are also provided. | 2010-01-14 |
20100007022 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an insulating film formed on a semiconductor substrate, and a buried interconnect formed in the insulating film and made of copper or a copper alloy. A barrier metal layer made of a platinum group element or a platinum group element alloy is formed between the insulating film and the buried interconnect, and the barrier metal layer partially includes an amorphous structure having a degree of amorphousness that provides a relatively high barrier property. | 2010-01-14 |
20100007023 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE HAVING IMPROVED COPPER DIFFUSION PREVENTIVE FUNCTION OF PLUGS AND WIRINGS MADE OF COPPER OR COPPER ALLOY - (a) A copper alloy film containing at least two types of metal elements in addition to copper is formed on the surface of an insulator containing oxygen and formed on a semiconductor substrate. (b) A metal film made of pure copper or copper alloy is formed on the copper alloy film. (c) After the step (a) or (b), heat treatment is performed under the condition that a metal oxide film is formed on a surface of the insulator through reaction between the oxygen in the insulator and the metal elements in the copper alloy film. | 2010-01-14 |
20100007024 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device. | 2010-01-14 |
20100007025 | ORGANIC SILICA FILM AND METHOD FOR FORMING SAME, COMPOSITION FOR FORMING INSULATING FILM OF SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME, WIRING STRUCTURE AND SEMICONDUCTOR DEVICE - An insulating-film-forming composition for a semiconductor device comprising an organic silica sol with a carbon atom content of 11 to 17 atom % and an organic solvent is disclosed. The organic silica sol comprises a hydrolysis-condensation product P1 and a hydrolysis-condensation product P2. The hydrolysis-condensation product P1 is obtained by hydrolyzing and condensing (A) a silane monomer comprising a hydrolyzable group and (B) a polycarbosilane comprising a hydrolyzable group in the presence of (C) a basic catalyst, and the hydrolysis-condensation product P2 is obtained by hydrolyzing and condensing (D) a silane monomer comprising a hydrolyzable group. | 2010-01-14 |
20100007026 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor chip has a main surface. A conductive portion is provided on the main surface and made from a material having conductivity and malleability. A sealing resin portion has a surface facing the main surface. An electrode is provided on the conductive portion and passes through the sealing resin portion between the conductive portion and the surface. As a result, there is provided a semiconductor device that can be downsized. | 2010-01-14 |
20100007027 | INTEGRATED CONNECTION ARRANGEMENTS - A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure. | 2010-01-14 |
20100007028 | DEVICE INCLUDING AN IMIDE LAYER WITH NON-CONTACT OPENINGS AND METHOD - A device including an imide layer with non-contact openings and the method for producing the device. One embodiment provides a substrate on a main surface of the substrate, an imide layer on the metallization layer, at least one contact opening through the imide layer and a plurality of non-contact openings in the imide layer. The non-contact openings are dimensioned to provide for an increased surface area of the imide layer or a surface area of the imide layer which is not reduced by more than 10 percent. | 2010-01-14 |
20100007029 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED-DOWN RDL AND RECESSED THV IN PERIPHERAL REGION OF THE DEVICE - A semiconductor die has a peripheral region around the die. An insulating layer is formed over the semiconductor die. A portion of the insulating layer and peripheral is removed to form a recess around the semiconductor die. A conductive layer is deposited over the insulating layer and recess. The conductive layer is electrically connected to contact pads on the semiconductor die and conforms to a step into the recess. A gap is created through the conductive layer and peripheral region around the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. The conductive THV is recessed with respect to a surface of the semiconductor die. The conductive THV is electrically connected to the conductive layer. | 2010-01-14 |
20100007030 | Semiconductor device, method for manufacturing semiconductor device, method for manufacturing semiconductor package - There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section. | 2010-01-14 |
20100007031 | AGENT FOR POST-ETCH TREATMENT OF SILICON DIELECTRIC FILM, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - The invention provides an agent for post-etch treating a silicon dielectric film, including: at least one nitrogen-containing substance selected from the group consisting of ammonium bases and amine compounds; an acid; and at least one silicon-containing compound containing silicon, carbon and hydrogen. According to the present invention, it becomes possible to suppress an increase in the dielectric constant of a silicon dielectric film caused by etching. | 2010-01-14 |
20100007032 | FLIP CHIP SEMICONDUCTOR DEVICE HAVING WORKPIECE ADHESION PROMOTER LAYER FOR IMPROVED UNDERFILL ADHESION - A semiconductor device assembly ( | 2010-01-14 |
20100007033 | METHOD FOR CONNECTING BETWEEN SUBSTRATES, FLIP-CHIP MOUNTING STRUCTURE, AND CONNECTION STRUCTURE BETWEEN SUBSTRATES - A resin containing a conductive particle and a gas bubble generating agent is supplied in a space between the substrates each having a plurality of electrodes. The resin is then heated to melt the conductive particle contained in the resin and generate gas bubbles from the gas bubble generating agent. A step portion is formed on at least one of the substrates. In the process of heating the resin, the resin is pushed aside by the growing gas bubbles, and as a result of that, the conductive particle contained in the resin is led to a space between the electrodes, and a connector is formed in the space. At the same time, the resin is led to a space between parts of the substrates at which the step portion is formed, and cured to fix the distance between the substrates. | 2010-01-14 |
20100007034 | LENS SUPPORT AND WIREBOND PROTECTOR - A wirebond protector has an elongated shape that corresponds to the elongated array of wirebonds along the edge of a microelectronic device that connect a semiconductor die to electrical conductors on a substrate. In making the microelectronic device with wirebond protection, wirebonds are first formed in the conventional manner The wirebond protector is then attached to the device in an orientation in which it extends along the array of wirebonds to at least partially cover the wirebonds. | 2010-01-14 |
20100007035 | Semiconductor device and method of manufacturing the same - A semiconductor device includes a substrate; an alignment mark formed on the substrate and composed of a metal film; a cover insulating film formed on the alignment mark and covering an entire surface of the alignment mark; and a polyimide film formed on the cover insulating film, and having an opening, which is opened on the alignment mark and has an end face aligning with an end face of the alignment mark, in plan view. | 2010-01-14 |
20100007036 | RESIN-CEMENTED OPTICAL ELEMENT, MOLD THEREFOR, FABRICATION PROCESS THEREOF, AND OPTICAL ARTICLE - The present invention provides a resin-cemented optical element comprising a base member | 2010-01-14 |
20100007037 | Method and Apparatus for Blow-Molding Containers - The method and the apparatus serve for blow-moulding containers. After thermal conditioning, a parison is formed into the container within a blowing mould of a blow-moulding machine ( | 2010-01-14 |
20100007038 | TIRE VULCANIZER AND TIRE VULCANIZING METHOD - A tire vulcanizing apparatus and a tire vulcanizing method, by which the pressure and temperature of a heating and pressurizing medium to be supplied to the internal space of a raw tire can be controlled without the condition of pressure being affected by the condition of temperature. The tire vulcanizing apparatus has: a medium path, connected to an internal space of a raw tire, for passing a heating and pressurizing medium; a pressure sensor, provided in the medium path, for measuring a pressure of the heating and pressurizing medium; a pressure control valve for controlling a pressure of the heating and pressurizing medium passing through the medium path on the basis of a signal from the pressure sensor; a temperature sensor, provided in the medium path, for measuring a temperature of the heating and pressurizing medium; and a heating unit for controlling the temperature of the heating and pressurizing medium passing through the medium path on the basis of a signal from the temperature sensor, wherein the pressure control valve and the heating unit control the pressure and temperature of the heating and pressurizing medium supplied from the medium path to the internal space of the raw tire respectively and independently. | 2010-01-14 |
20100007039 | METHOD FOR PRODUCING GRANULES FROM THERMOPLASTIC SILOXANE POLYMERS - Non-blocking polymer pellets are produced in spherical or nearly spherical form by introducing molten polymer directly from a polymerization reactor into a coolant and pelletizing just prior to, simultaneously with, or immediately following entry into the coolant such that residual heat allows the polymer pellets to change their shape to eliminate sharp corners, particularly cylindrical shapes, and assume a spherical-type morphology. | 2010-01-14 |
20100007040 | Method of preparing aroma particles - The invention relates to vitreous aroma particles and the preparation thereof, as well as to the use thereof in foods, consumer articles and pharmaceuticals. | 2010-01-14 |
20100007041 | METHOD AND APPARATUS FOR COLLECTING IV TUBING TIPS - Mandrel supported IV tubing is inserted within a mold of a mold assembly to heat the IV tubing and form a tapered end of the tubing. The tip of the tubing extending beyond the tapered end of the tubing is severed by the mandrel bearing against the mold to lodge the tip in an outlet of the mold. Cooling air is introduced to the mold assembly to cool the mold and to create a flow of turbulent air about the outlet of the mold to extract the severed tips. The turbulent air is exhausted through a channel, pipe and fitting into a collection chamber and causes translation of the severed tip to and into the collection chamber. Sensors may be incorporated to sense the translation of the severed tips. | 2010-01-14 |
20100007042 | Method and apparatus for making submicron diameter fibers and webs there from - A method and device for the production of polymer filaments with a diameter of less than one micron. A plurality of polymer components are extruded through a spin pack and then attenuated using gas flows which are accelerated to achieve high velocity by means of a converging, diverging nozzle. The plurality polymer components may be extruded in an islands in the sea or segmented pie configuration. As a result of the high velocity gas flow, the plural components are split apart into their individual components resulting in filaments and fibers having a diameter or minor dimension of less than one micron. | 2010-01-14 |
20100007043 | Multi-Tube Extrusion Apparatus and Method - A method and apparatus for producing a plurality of bi-oriented, heat-shrinkable thermoplastic tubular films is disclosed. Thermoplastic resin is extruded through a plurality of annular dies to form a plurality of molten plastic tubes. The tubes are cooled and solidified and sent through a plurality of pinch rollers to stretch the tubes simultaneously in a machine and transverse direction, creating a plurality of tubular films. The films are cooled and heated, and then relaxed simultaneously in a machine and transverse direction. Winding rollers then wind up the finished tubular films. | 2010-01-14 |
20100007044 | METHOD FOR PRODUCING A FIBRE COMPOSITE COMPONENT - Disclosed is a moulding core for producing a fibre composite component, in particular a stringer on a base component in aerospace, of a spiral construction, wherein the moulding core is a hollow profile with an outer geometry adapted to the moulding core and with a slit provided in the wall of the hollow profile and extending spirally around its periphery; and wherein the slit hollow profile is provided with positional fixing, wherein the slit extending spirally around the periphery penetrates the wall of the hollow profile with the exception of at least three locations arranged such that they are distributed around the circumference of the wall of the hollow profile. A method for producing a fibre composite component, such as a fibre composite component for aerospace, is also disclosed. | 2010-01-14 |
20100007045 | METHOD FOR MANUFACTURING SHELL WITH TEXTURED APPEARANCE - A method is provided for manufacturing a shell with a textured appearance as follows. A mold formed with a textured mold portion is provided. A film is provided into the mold and in contact with the textured mold portion. The shell is formed by injecting a plastic material into the mold to push the film further into the textured mold portion. | 2010-01-14 |
20100007046 | Method for Forming a Tangible Item and a Tangible Item which is Made by a Method which Allows the Created Tangible Item to Efficiently Absorb Energy - A method for creating a tangible item (such as an “A” pillar garnishment | 2010-01-14 |
20100007047 | Recycled thermoplastic composition comprising waste thermoset material and methods of making - The present invention provides methods for making shapeable composite materials or shaped articles from recycled materials comprising forming a crumb slurry by, in any order, increasing the particle size of a composition comprising white water waste from one or more emulsion or dispersion polymer and combining the white water waste polymer with one or more waste thermoset material, preferably, ground tire rubber (GTR), and, then processing the combined material wet or dry as a thermoplastic to form the composite material or article. Additionally, shaped articles and composite materials can be made from substantially all recycled waste materials, such as white water waste from acrylic or vinyl polymer emulsions and waste rubber vulcanizates. The composite materials can consist essentially of reshapeable materials, i.e. without crosslinking agents, thermosettable compositions or compatibilizers to provide reshapeable or recyclable articles. | 2010-01-14 |
20100007048 | METHOD FOR THE PRODUCTION OF A MULTI-LAYER PREFORM AND NOZZLE THEREFOR - A melt feed device for an injection molding apparatus having at least one nozzle element connected both to a first hot runner and a second hot runner for feeding both the first melt and the second melt into an injection molding mold. The nozzle has three substantially concentrically arranged feed passages, wherein the innermost and the outermost feed passage are in communication with the first hot runner and the central feed passage is in communication with the second hot runner. A closure element is provided that can be reciprocated between a first position in which the closure element closes all feed passages, a second position in which the closure element opens the outermost feed passage but closes the other two feed passages and a third position in which the closure element opens all feed passages. The invention also includes process and molds using the device. | 2010-01-14 |
20100007049 | INJECTION MOLD ASSEMBLY - A method and assembly for molding golf balls is disclosed herein. The invention includes an injection mold assembly ( | 2010-01-14 |
20100007050 | EASY-TO-STRAIGHT-TEARING THERMOPLASTIC RESIN FILM AND ITS PRODUCTION METHOD AND APPARATUS - A method for forming substantially parallel linear scratches on a thermoplastic resin film, comprising bringing the film into sliding contact with a means having a lot of fine projections for forming linear scratches, and pressing the film onto the linear-scratch-forming means from the opposite side of the linear-scratch-forming means by a film-pressing means, in a region in which the film is in sliding contact with the linear-scratch-forming means. | 2010-01-14 |
20100007051 | CONCRETE BLOCK MACHINE HAVING A CONTROLLABLE CUTOFF BAR - A concrete block machine including a mold having at least one mold cavity, a feedbox driven back and forth between retracted and extended positions, wherein the feedbox is positioned over a top of the mold deposits concrete in the at least one mold cavity when at the extended position, a cutoff bar coupled to the feedbox and including a moveable cutoff element, and a drive system. The drive system is coupled to the moveable cutoff element and moves the moveable cutoff element to adjust a distance between the moveable cutoff element and the top of the mold as the feedbox is driven from the extended position to the retracted position such that the moveable cutoff element removes varying amounts of concrete deposited in the mold cavity so that a depth of concrete remaining in the mold cavity varies in a desired fashion in a direction of movement of the feedbox. | 2010-01-14 |
20100007052 | METHOD FOR THE AESTHETIC SURFACE TREATMENT OF A MONOLITHIC CONCRETE FLOOR AND PRODUCT OF THE METHOD - This invention relates generally to a method for forming a concrete floor as a monolithic unit, wherein a wet concrete mix is deposited and worked to achieve a generally uniform flatness of concrete and adding to the top layer thereof a decorative aggregate material. Subsequently, the surface of the concrete is worked, allowed to partially cure and then ground and polished to substantially remove surface irregularities and reveal the decorative aggregate. The floor surface may then be coated with a sealant to achieve a terrazzo-like appearance. | 2010-01-14 |
20100007053 | Compression molding method for cutting insert - According to an aspect of the invention, a compression molding method for a cutting insert, in which molding powder filled into a molding space defined by a die, an upper punch, and a lower punch is compression-molded by the upper and lower punches, includes, sliding both the upper and lower punches individually to positions just short of estimated stop positions obtained for design by means of a position controller, and then sliding the punches by means of a load controller so that a predetermined pressure is reached. | 2010-01-14 |
20100007054 | APPARATUS AND METHOD FOR IN-MOLD-DECORATION - An apparatus for in-mold-decoration includes a male mold, a female mold comprising a surface facing the male mold, a foil, a press member, and a supporting member. The surface of the female mold defines a cavity. The foil is applied to the surface of the female mold. The press member is positioned between the male mold and the female mold, and capable of hermetically pressing the foil on the surface of the female mold. The supporting member is movably mounted to the surface of the female mold to prop up the foil toward the male mold before the press member presses the foil on the surface of the female mold. | 2010-01-14 |
20100007055 | METHOD FOR MANUFACTURING CYLINDERS FOR CARTRIDGE CASES AND COMPOSITION - The invention relates to a method for manufacturing cylinders ( | 2010-01-14 |
20100007056 | Clip Integration of Pressure Tube Mold Cores into Hardened Omega-Stringers for the Production of Stiffened Fiber Composite Skin Shells, in particular for Aeronautics and Astronautics - The invention concerns a device for stiffening a flat component, a process for the production of a flat component, in particular a fiber composite component, and a fiber composite component. The device has a portion for producing a space for receiving a mold core for the transmission of a pressure for pressing the flat component and the device. It is characterised by means for positively lockingly and/or frictionally lockingly positioning the mold core in the space of the device. The process according to the invention includes the following steps: introducing the mold core into the portion of the device, positively lockingly and/or frictionally lockingly positioning the mold core in the portion of the device by means of the means, applying the device including the mold core to the non-hardened material layer or layers, pressing the material layers, and hardening the material layer or layers and joining the device to the material layer or layers. | 2010-01-14 |
20100007057 | INJECTION MOLD MANIFOLD AND METHOD OF USING SAME - A manifold for delivering molten plastic material into a mold cavity for forming generally cylindrical parts such as food and beverage containers having large aspect ratios. The manifold includes a manifold block, an inlet, and at least two outlets in fluid communication with the inlet. The outlets are configured for injecting molten plastic material into a single mold cavity in order to ensure that the molten plastic material reaches the outermost portions of the mold cavity prior to setting up. The manifold can also be configured to be attached to a second manifold in place of a single outlet on the second manifold. | 2010-01-14 |