| 02nd week of 2012 patent applcation highlights part 15 |
| Patent application number | Title | Published |
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| 20120007196 | MAGNETORESISTIVE RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetoresistive random access memory includes a magnetoresistive element in a memory cell, the magnetoresistive element including a first metal magnetic layer, a second metal magnetic layer, and an insulation layer interposed between the first and second metal magnetic layers. An area of each of the first and second metal magnetic layers is smaller than an area of the insulation layer. | 2012-01-12 |
| 20120007197 | SOLID-STATE IMAGING APPARATUS AND IMAGING SYSTEM - A solid-state imaging apparatus comprising a plurality of pixels each including a photoelectric conversion element, and a light shielding layer which covers the photoelectric conversion element is provided. The light shielding layer comprises a first light shielding portion which covers at least part of a region between the photoelectric conversion elements that are adjacent to each other, and a second light shielding portion for partially shielding light incident on the photoelectric conversion element of each of the plurality of pixels. An aperture is provided for the light shielding layer, the remaining component of the incident light passing through the aperture. A shape of the aperture includes a cruciform portion including a portion extending in a first direction and a portion extending in a second direction that intersects the first direction. | 2012-01-12 |
| 20120007198 | BACKSIDE ILLUMINATED IMAGE SENSOR - A backside illuminated (BSI) image sensor including a substrate, a plurality of photosensitive regions, a back-end-of-line (BEOL), a pad, a color filter array, a plurality of micro-lenses and a protection layer is provided. The substrate has a first surface and a second surface. The substrate has a pad opening therein through the first surface and the second surface. The photosensitive regions are disposed in the substrate. The BEOL is disposed on the first surface of the substrate. The pad is disposed in the BEOL and exposed by the pad opening. The color filter array is disposed on the second surface of the substrate. The micro-lenses are disposed on the color filter array. The protection layer at least covers the top corner and the sidewall of the pad opening. | 2012-01-12 |
| 20120007199 | PROTECTING BOND PAD FOR SUBSEQUENT PROCESSING - A method for opening a bond pad on a semiconductor device is provided. The method comprises removing a first layer to expose a first portion of the bond pad and forming a protective layer over the exposed first portion of the bond pad. The method further comprises performing subsequent processing of the semiconductor device and removing the protective layer to expose a second portion of the bond pad. | 2012-01-12 |
| 20120007200 | Image Sensor and Method for Manufacturing the Same - Disclosed is an image sensor including a photo-sensing device, a color filter positioned on the photo-sensing device, a microlens positioned on the color filter, and an insulation layer positioned between the photo-sensing device and the color filter, and including a trench exposing the photo-sensing device and a filler filled in the trench. The filler has light transmittance of about 85% or more at a visible ray region, and a higher refractive index than the insulation layer. A method of manufacturing the image sensor is also provided. | 2012-01-12 |
| 20120007201 | MONOLITHIC PHOTODETECTOR - A photodetector including a photodiode formed in a semiconductor substrate and a waveguide element formed of a block of a high-index material extending above the photodiode in a thick layer of a dielectric superposed to the substrate, the thick layer being at least as a majority formed of silicon oxide and the block being formed of a polymer of the general formula R | 2012-01-12 |
| 20120007202 | Radiation-Receiving Semiconductor Component and Optoelectronic Device - A radiation-receiving semiconductor component is specified. A semiconductor body is formed with silicon and has a radiation entrance surface and also an absorption zone. Electromagnetic radiation passes into the semiconductor body through the radiation entrance surface and is absorbed. The absorption zone has a thickness of at most 10 μm. A filter layer is formed with a dielectric material. The filter layer covers the radiation entrance surface of the semiconductor body. A potting body covers the semiconductor body at least at the radiation entrance surface thereof. The potting body contains a radiation-absorbing material. | 2012-01-12 |
| 20120007203 | SOLID-STATE IMAGING APPARATUS AND IMAGING SYSTEM - A solid-state imaging apparatus including pixels each including a photoelectric conversion element, and a light shielding layer covering the photoelectric conversion element is provided. For each of the photoelectric conversion elements, the light shielding layer includes a light shielding portion which shields a portion of incident light to the photoelectric conversion element, and an aperture which passes another portion of the incident light. The pixels include first and second pixels which have different areas on a planar view of the photoelectric conversion element. The area of the photoelectric conversion element in the first pixel is larger than the area of the photoelectric conversion element in the second pixel on the planar view. An area of the light shielding portion included in the first pixel is larger than an area of the light shielding portion included in the second pixel. | 2012-01-12 |
| 20120007204 | METHOD TO OPTIMIZE SUBSTRATE THICKNESS FOR IMAGE SENSOR DEVICE - Provided is a method for fabricating an image sensor device that includes providing a substrate having a front side and a back side; patterning a photoresist on the front side of the substrate to define an opening having a first width, the photoresist having a first thickness correlated to the first width; performing an implantation process through the opening using an implantation energy correlated to the first thickness thereby forming a first doped isolation feature; forming a light sensing feature adjacent to the first doped isolation feature, the light sensing feature having a second width; and thinning the substrate from the back side so that the substrate has a second thickness that does not exceed twice a depth of the first doped isolation feature. A pixel size is substantially equal to the first and second widths. | 2012-01-12 |
| 20120007205 | INFRARED IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME - Certain embodiments provide an infrared imaging device including: an SOI structure that is placed at a distance from a substrate, and includes: heat-sensitive diodes that detect infrared rays and convert the infrared rays into heat; and STI regions that separate the heat-sensitive diodes from one another; an interlayer insulating film that is stacked on the SOI structure; and supporting legs that are connected to the heat-sensitive diodes and vertical signal lines provided in outer peripheral regions of the heat-sensitive diodes. Each of the supporting legs includes: an interconnect unit that transmit signals to the vertical signal lines; and interlayer insulating layers that sandwich the interconnect unit, each bottom side of the interlayer insulating layers being located in a higher position than the SOI structure. | 2012-01-12 |
| 20120007206 | Structures and methods for forming schottky diodes on a p-substrate or a bottomanode schottky diode - This invention discloses bottom-anode Schottky (BAS) device supported on a semiconductor substrate having a bottom surface functioning as an anode electrode with an epitaxial layer has a same doped conductivity as said anode electrode overlying the anode electrode. The BAS device further includes an Schottky contact metal disposed in a plurality of trenches and covering a top surface of the semiconductor substrate between the trenches. The BAS device further includes a plurality of doped JBS regions disposed on sidewalls and below a bottom surface of the trenches doped with an opposite conductivity type from the anode electrode constituting a junction barrier Schottky (JBS) with the epitaxial layer disposed between the plurality of doped JBS regions. The BAS device further includes an ultra-shallow Shannon implant layer disposed immediate below the Schottky contact metal in the epitaxial layer between the plurality of doped JBS regions. | 2012-01-12 |
| 20120007207 | APPARATUS AND METHOD FOR ELECTRONIC CIRCUIT PROTECTION - Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a substrate includes an n-well and a p-well adjacent the n-well. An n-type active area and a p-type active area are disposed in the n-well. The p-type active area, the n-well, and the p-well are configured to operate as an emitter, a base, and a collector of an PNP bipolar transistor, respectively, and the p-type active area surrounds at least a portion of the n-type active area so as to aid in recombining carriers injected into the n-well from the p-well before the carriers reach the n-type active area. The n-well and the p-well are configured to operate as a breakdown diode, and a punch-through breakdown voltage between the n-well and the p-well is lower than or equal to about a breakdown voltage between the p-type active area and the n-well. | 2012-01-12 |
| 20120007208 | Semiconductor Devices and Methods of Manufacturing the Same - Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may include first and second active patterns. The second active patterns may protrude from the first active patterns. The semiconductor devices may also include a device isolation pattern between each of the first active patterns. The semiconductor devices may further include a sidewall mask on the first active patterns and the second active patterns. The semiconductor devices may additionally include a buried conductive pattern on the device isolation pattern. | 2012-01-12 |
| 20120007209 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING DAMASCENE TRENCHES WITH CONDUCTIVE STRUCTURES AND RELATED METHOD - A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure. | 2012-01-12 |
| 20120007210 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE - A semiconductor structure is disclosed. The semiconductor structure includes: a substrate with at least a trench therein, wherein the trench is filled with an insulation layer; a first polysilicon layer disposed on the insulation layer and covering at least two opposite borders of a top surface of the insulation layer; a second polysilicon layer disposed above the first polysilicon layer and the substrate; and a dielectric layer disposed between the first and second polysilicon layers, wherein the first and second polysilicon layers are respectively shaped as first and second strips. | 2012-01-12 |
| 20120007211 | IN-STREET DIE-TO-DIE INTERCONNECTS - The present disclosure relates to the field of microelectronic die packaging, particularly multi-chip packaging, wherein on-substrate modularity is enabled by using in-street die-to-die interconnects to facilitate signal routing between microelectronic dice. These in-street die-to-die interconnects may allow for manufacturing of several products on a single microelectronic substrate, which may lead to improved microelectronic die and/or microelectronic module harvesting and increased product yields. | 2012-01-12 |
| 20120007212 | SEMICONDUCTOR DEVICE HAVING A DIODE - Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well. | 2012-01-12 |
| 20120007213 | SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME - A semiconductor chip includes: a semiconductor substrate in which a bonding pad is provided on a first surface thereof; a through silicon via (TSV) group including a plurality of TSVs connected to the bonding pad and exposed to a second surface opposite to the first surface of the semiconductor substrate; and a fuse box including a plurality of fuses connected to the plurality of TSVs and formed on the first surface of the semiconductor substrate. | 2012-01-12 |
| 20120007214 | INTEGRATED CIRCUIT SYSTEM WITH HIERARCHICAL CAPACITOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor. | 2012-01-12 |
| 20120007215 | ON-CHIP CAPACITOR STRUCTURE - At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit. | 2012-01-12 |
| 20120007216 | Multi-Chip Package Module And A Doped Polysilicon Trench For Isolation And Connection - A circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface. A nonconductive adhesive is on the surface. A plurality of electronic circuit dies are on the surface of the die attach pad. Each die has a top surface and a bottom surface with the bottom surface on the adhesive. The top surface has a plurality of bonding pads. A first electronic circuit die has at least one routing path of a conductive material connecting a first bonding pad to a second bonding pad. A first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die. A second bonding wire connects the second bonding pad of the first electronic circuit die to a lead. Where one of the dies contains vertical circuit element, where a doped layer forms a terminal along the bottom surface of the layer, a trench filled with doped polysilicon extends from the top surface to the terminal to connect to the terminal. The doped polysilicon filled trench also serves to isolate and separate different circuit elements. | 2012-01-12 |
| 20120007217 | ENCAPSULANT CAVITY INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF FABRICATION THEREOF - A method for fabricating an encapsulant cavity integrated circuit package system includes: providing an interposer; forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and the interposer; and attaching a component on the interposer in the encapsulant cavity. | 2012-01-12 |
| 20120007218 | SEMICONDUCTOR DEVICE WITH ONE-SIDE CONTACT AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device includes forming a plurality of first trenches by etching a substrate, forming first spacers covering both sidewalls of each of the first trenches, forming a plurality of second trenches by etching a bottom of each of the first trenches, forming second spacers covering both sidewalls of each of the second trenches, forming a plurality of third trenches by etching a bottom of each of the second trenches, forming an insulation layer covering exposed surfaces of the plurality of the substrate, and forming a contact which exposes one sidewall of each of the second trenches by selectively removing the second spacers. | 2012-01-12 |
| 20120007219 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device, includes: a first storage node contact plug penetrating a first interlayer insulation layer and partially protruding above the first interlayer insulation layer; a second storage node contact plug contacting the first storage node contact plug that protrudes above the first interlayer insulation layer; a storage node contacting a top surface of the second storage node contact plug; and a second interlayer insulation layer formed over the first interlayer insulation layer, wherein the second interlayer insulation layer surrounds an outer sidewall at a bottom region of the first storage node, and the second storage node contact plug, and wherein the first storage node contact plug protruding above the first interlayer insulation layer and the second storage node contact plug. | 2012-01-12 |
| 20120007220 | Method for Reducing Chip Warpage - A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material. | 2012-01-12 |
| 20120007221 | MASK FOR FORMING INTEGRATED CIRCUIT - A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask. | 2012-01-12 |
| 20120007222 | METHOD OF MANUFACTURING DIODE, AND DIODE - The present specification provides a method of efficiently manufacturing diodes in which recovery surge voltage is hardly generated. | 2012-01-12 |
| 20120007223 | Power Semiconductor Element With Two-Stage Impurity Concentration Profile - A power semiconductor component having a pn junction, a body with a first basic conductivity, a well-like region with a second conductivity which is arranged horizontally centrally in the body, has a first two-level doping profile and has a first penetration depth from the first main surface into the body. In addition, this power semiconductor component has an edge structure which is arranged between the well-like region and the edge of the power semiconductor component and which comprises a plurality of field rings with a single-level doping profile, a second conductivity and a second penetration depth, wherein the first penetration depth is no more than about 50% of the second penetration depth. | 2012-01-12 |
| 20120007224 | SEMICONDUCTOR DEVICE - In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package. | 2012-01-12 |
| 20120007225 | SEMICONDUCTOR DEVICE - In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package. | 2012-01-12 |
| 20120007226 | SYSTEM-IN-A-PACKAGE BASED FLASH MEMORY CARD - A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package. | 2012-01-12 |
| 20120007227 | HIGH DENSITY CHIP STACKED PACKAGE, PACKAGE-ON-PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package including a protection layer, a plurality of semiconductor chips stacked on the protection layer, an inner encapsulant disposed on the protection layer to surround side surfaces of the semiconductor chips, and a terminal disposed to be buried in an upper portion of the inner encapsulant. Herein, each of the semiconductor chips includes an active surface, an inactive surface opposite to the active surface, and a chip pad disposed on a portion of the active surface, and an upper surface of the terminal is exposed from an upper surface of the inner encapsulant. | 2012-01-12 |
| 20120007228 | CONDUCTIVE PILLAR FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - An embodiment of the disclosure includes a conductive pillar on a semiconductor die. A substrate is provided. A bond pad is over the substrate. A conductive pillar is over the bond pad. The conductive pillar has a top surface, edge sidewalls and a height. A cap layer is over the top surface of the conductive pillar. The cap layer extends along the edge sidewalls of the conductive pillar for a length. A solder material is over a top surface of the cap layer. | 2012-01-12 |
| 20120007229 | ENHANCED THERMAL MANAGEMENT OF 3-D STACKED DIE PACKAGING - A die stack package is provided and includes a substrate, a stack of computing components, at least one thermal plate, which is thermally communicative with the stack and a lid supported on the substrate to surround the stack and the at least one thermal plate to thereby define a first heat transfer path extending from one of the computing components to the lid via the at least one thermal plate and a fin coupled to a surface of the lid and the at least one thermal plate, and a second heat transfer path extending from the one of the computing components to the lid surface without passing through the at least one thermal plate. | 2012-01-12 |
| 20120007230 | CONDUCTIVE BUMP FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - An embodiment of the disclosure includes a conductive bump on a semiconductor die. A substrate is provided. A bond pad is over the substrate. An under bump metallurgy (UBM) layer is over the bond pad. A copper pillar is over the UBM layer. The copper pillar has a top surface with a first width and sidewalls with a concave shape. A nickel layer having a top surface and a bottom surface is over the top surface of the copper pillar. The bottom surface of the nickel layer has a second width. A ratio of the second width to the first width is between about 0.93 to about 1.07. A solder material is over the top surface of the cap layer. | 2012-01-12 |
| 20120007231 | METHOD OF FORMING CU PILLAR CAPPED BY BARRIER LAYER - A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer. | 2012-01-12 |
| 20120007232 | MICROELECTRONIC PACKAGES WITH DUAL OR MULTIPLE-ETCHED FLIP-CHIP CONNECTORS - A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region. | 2012-01-12 |
| 20120007233 | SEMICONDUCTOR ELEMENT AND FABRICATION METHOD THEREOF - A semiconductor element and a fabrication method thereof. The method includes forming an encapsulating layer on a semiconductor silicon substrate having electrode pads and a passivation layer formed thereon, the encapsulating layer covering the electrode pads and a part of the passivation layer that surrounds the electrode pads; forming a covering layer on the passivation layer and the encapsulating layer with a plurality of openings that expose a part of the encapsulating layer; forming a bonding metallic layer on the part of the encapsulating layer that are exposed from the openings and electrically connecting the bonding metallic layer to the encapsulating layer, wherein the bonding metallic layer is not greater in diameter than the encapsulating layer; and forming a conductive element on the bonding metallic layer. The encapsulating layer provides a good buffering effect to prevent electrode pads from delamination or being broken caused by the direct stress from the conductive element. | 2012-01-12 |
| 20120007234 | SEMICONDUCTOR PACKAGE WITHOUT CHIP CARRIER AND FABRICATION METHOD THEREOF - A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer. | 2012-01-12 |
| 20120007235 | Chip Fanning Out Method and Chip-on-Film Device - A chip fanning out method is disclosed. The chip fanning out method includes mounting a chip on a film, forming a plurality of outer lead bonds spatially arranged in a bump correspondence order on the film, forming a plurality of bumps spatially arranged in a bump arrangement order on the chip, and forming a plurality of wires to connect the plurality of outer lead bonds to the plurality of bumps according to the bump correspondence order, wherein the bump correspondence order is different from the bump arrangement order. | 2012-01-12 |
| 20120007236 | SEMICONDUCTOR DEVICE AND PACKAGE - A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate. | 2012-01-12 |
| 20120007237 | CHIP PACKAGE - A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip. | 2012-01-12 |
| 20120007238 | Method of Manufacturing a Semiconductor Device - Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping. | 2012-01-12 |
| 20120007239 | METHODS, DEVICES, AND MATERIALS FOR METALLIZATION - A method of making an electronic device which in one embodiment comprises providing a substrate, electrolessly depositing a barrier metal at least on portions of the substrate, and using wet chemistry such as electroless deposition to deposit a substantially gold-free wetting layer having solder wettability onto the barrier metal. An electronic device which in one embodiment comprises a metallization stack. The metallization stack comprises a barrier metal deposited electrolessly and a substantially gold-free wetting layer deposited on the barrier metal, and the wetting layer is wettable by solder. | 2012-01-12 |
| 20120007240 | METAL WIRE FOR A SEMICONDUCTOR DEVICE FORMED WITH A METAL LAYER WITHOUT VOIDS THEREIN AND A METHOD FOR FORMING THE SAME - A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO | 2012-01-12 |
| 20120007241 | SEMICONDUCTOR DEVICE - The present teachings provides a semiconductor device which has a semiconductor substrate, and a lower electrode including a first layer in contact with a lower surface of the semiconductor substrate, a second layer in contact with a lower surface of the first layer, and a third layer stacked at a position farther from the semiconductor substrate than the second layer, wherein the first layer is an aluminum layer containing silicon, the second layer is a layer including silicon as a primary component, and the third layer is a solder joint layer. | 2012-01-12 |
| 20120007242 | INTERCONNECTS HAVING SEALING STRUCTURES TO ENABLE SELECTIVE METAL CAPPING LAYERS - Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect. | 2012-01-12 |
| 20120007243 | METHOD OF MAKING CONNECTIONS IN A BACK-LIT CIRCUIT - A method for forming, on a surface of a thinned-down semiconductor substrate, a contact connected to a metal track of an interconnect stack formed on the opposite surface of the thinned-down substrate, including the steps of: forming, on the side of a first surface of a substrate, an insulating region penetrating into the substrate and coated with a conductive region and with an insulating layer crossed by conductive vias, the vias connecting a metal track of the interconnect stack to the conductive region; gluing the external surface of the interconnect stack on a support and thinning down the substrate; etching the external surface of the thinned-down substrate and stopping on the insulating region; etching the insulating region and stopping on the conductive region; and filling the etched opening with a metal. | 2012-01-12 |
| 20120007244 | Backside Processing of Semiconductor Devices - A semiconductor device includes a workpiece having a bottom surface opposite the top surface. Metallization layers are disposed over the top surface and a protective layer is disposed over the metallization layers. The semiconductor device further includes a metal silicide layer disposed on the bottom surface. The metal silicide layer is less than about five atomic layers in thickness. A first metal layer is disposed over the metal silicide layer such that a metal of the first metal layer is the same as a metal of the metal silicide layer. | 2012-01-12 |
| 20120007245 | Via and Method of Forming the Via with a Substantially Planar Top Surface that is Suitable for Carbon Nanotube Applications - A via is formed on a wafer to lie within an opening in a non-conductive structure and make an electrical connection with an underlying conductive structure so that the entire top surface of the via is substantially planar, and lies substantially in the same plane as the top surface of the non-conductive structure. The substantially planar top surface of the via enables a carbon nanotube switch to be predictably and reliably closed. | 2012-01-12 |
| 20120007246 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate, a pattern including a conductive layer and a hard mask layer stacked over the substrate, a capping layer surrounding sidewalls of the pattern, and a stress buffer layer disposed between the hard mask layer and the capping layer. The stress buffer layer is configured to inhibit transfer of stress between the hard mask layer and the capping layer during a thermal process so as to inhibit leaning of the capping layer. | 2012-01-12 |
| 20120007247 | Resin-Encapsulated Semiconductor Device - A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more. | 2012-01-12 |
| 20120007248 | MULTI-CHIP PACKAGE INCLUDING CHIP ADDRESS CIRCUIT - A multi-chip package according to an aspect of this disclosure includes a plurality of multi-chips. Each of the multi-chips includes a lead configured to receive an external power supply voltage, and a pad circuit configured to reset an internal node to the level of a ground voltage and to generate chip address information by controlling the potential of the internal node based on the state of a connection between the pad circuit and the lead. | 2012-01-12 |
| 20120007249 | SILICON BASED SUBSTRATE AND MANUFACTURING METHOD THEREOF - A silicon based substrate includes a silicon wafer, a first circuit substrate and a second circuit substrate. The silicon wafer includes a first surface and a second surface and at least a through silicon via. The first circuit substrate is disposed on the first surface and includes a plurality of first dielectric layers and a plurality of first conductive trace layers alternately stacked. The second circuit substrate is disposed on the second surface and includes a plurality of second dielectric layers and a plurality of second conductive trace layers alternately stacked. The trace density of the first conductive trace layers is higher than the trace density of the second conductive trace layers. Otherwise, the first dielectric layer includes an inorganic material and the second dielectric layer includes an organic material. A manufacturing method of the silicon based substrate is also provided. | 2012-01-12 |
| 20120007250 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first semiconductor chip including a first output circuit which is enabled in a first operation mode and outputs a first output signal and a second output circuit which is enabled in a second operation mode and outputs a second output signal; a second semiconductor chip including a first input circuit which is enabled in the first operation mode and receives the first output signal and a second input circuit which is enabled in the second operation mode and receives the second output signal; and a common through chip via arranged to vertically penetrate through the semiconductor chip, be coupled with the first and second output circuits in one end and coupled with the first and second input circuits in the other end, and interface transfer of the first and second output signals which are enabled in different operation modes, including the first and second operation modes. | 2012-01-12 |
| 20120007251 | STACKED MULTI-CHIP - A stacked multi-chip comprises a base layer, a first chip, a first stacked chip and at least one second stacked chip. The base layer comprises a mounting panel and a redistributed layer. The redistributed layer is mounted on the mounting panel. The first chip comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer abuts the redistributed layer. The first stacked chip is mounted on the first chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel that is connected to the TSV channel of the first chip. The second stacked chip is mounted on the first stacked chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer is connected to the connective layer of the first stacked chip. | 2012-01-12 |
| 20120007252 | SEMICONDUCTOR PACKAGE STRUCTURE AND FABRICATING METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes a dielectric layer, a patterned metal layer, a carrier, a metal layer and a semiconductor die. The dielectric layer has a first surface, a second surface and an opening. The patterned metal layer is disposed on the first surface. The carrier is disposed at the second surface and has a third surface, a fourth surface and at least a through hole. A portion of the third surface and the through hole are exposed by the opening. The metal layer is disposed on the fourth surface and has a containing cavity and at least a heat conductive post extending from the fourth surface and disposed in the through hole. An end of the heat conductive post protrudes away from the third surface, and the containing cavity is located on the end of the heat conductive post. The semiconductor die is located in the containing cavity. | 2012-01-12 |
| 20120007253 | SEMICONDUCTOR CHIP AND STACK PACKAGE HAVING THE SAME - A semiconductor chip includes a semiconductor substrate with a top surface and a bottom surface. An active layer may be formed on the top surface of the semiconductor substrate and may comprise one or more signal pads and one or more chip selection pads on an upper surface of the active layer. First and second through electrodes may be formed to pass through the semiconductor substrate and the active layer, with the first through electrodes being electrically connected with the signal pads and the second through electrodes being electrically connected with the chip selection pads. A side electrode may be formed on a side surface of the semiconductor chip in such a way as to be connected with a second through electrode. | 2012-01-12 |
| 20120007254 | MULTI-LAYER VIA STRUCTURE - Disclosed is a multi-layer via structure, comprising a metal layer, a first via metal layer formed on a first open of a first dielectric layer and a second via metal layer formed on a second open of a second dielectric layer. The first and second via metal layers comprise first and second bottoms, first and second top portions, first and second inclined walls, respectively. The first and second inclined walls comprise first and second top edges, first and second bottom edges respectively. The second top edge has a point closest to a geometric center of the first bottom. A vertical projection of the point falls on the first inclined wall. Alternatively, a point of the second bottom edge, which is closest to the geometric center, has a vertical projection. The vertical projection is vertical to the metal layer and falls on the first inclined wall. | 2012-01-12 |
| 20120007255 | SEMICONDUCTOR DEVICE - A semiconductor device having a power supply wiring and a ground wiring is provided, which can suppress the occurrence of voltage drop in part of wiring and the occurrence of migration caused by voltage drop. The semiconductor device includes a semiconductor substrate having a main surface, a sheet-like power supply wiring spreading in a stratified form along the main surface of the semiconductor substrate, a sheet-like ground wiring spreading along the main surface of the semiconductor substrate in a stratified form and spacedly a predetermined certain distance from the sheet-like power supply wiring in a direction intersecting the main surface of the semiconductor substrate, a power supply wiring formed over the main surface of the semiconductor substrate and extending in one direction within the main surface of the semiconductor substrate, and a ground wiring formed over the main surface of the semiconductor substrate spacedly a predetermined certain distance from the power supply wiring and extending in the one direction. The sheet-like power supply wiring is electrically coupled with the power supply wiring and the sheet-like ground wiring is electrically coupled with the ground wiring. | 2012-01-12 |
| 20120007256 | REDISTRIBUTION LAYERS FOR MICROFEATURE WORKPIECES, AND ASSOCIATED SYSTEMS AND METHODS - Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device. | 2012-01-12 |
| 20120007257 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a first insulating film formed on a substrate and having a first interconnect; a second insulating film as a liner film formed on the first insulating film and the first interconnect so as to contact the first insulating film; and a third insulating film formed on the second insulating film so as to contact the second insulating film. The second insulating film includes pores. | 2012-01-12 |
| 20120007258 | SEMICONDUCTOR DEVICE WITH SIDE-JUNCTION AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench. | 2012-01-12 |
| 20120007259 | LATENT HARDENER WITH IMPROVED BARRIER PROPERTIES AND COMPATIBILITY - A curing agent for epoxy resins that is comprised of the reaction product of an amine, an epoxy resin, and an elastomer-epoxy adduct; compositions containing the curing agent and an epoxy resin; the compositions are useful in electronic displays, circuit boards, semi conductor devices, flip chips and other applications. | 2012-01-12 |
| 20120007260 | MILK FROTH MACHINE - A milk froth machine includes a base and a top cover. A heating element is electrically connected to a controller mounted in the base. First and second electric connectors are respectively mounted to the base and top cover and electrically connected to the controller. The first and second electric connectors are coupled together when an agitator on the top cover is aligned with a supporting top face of the base. A motor is mounted in the top cover and electrically connected to the second electric connector. A container can be placed on the supporting top face with the agitator extending into the container and with the first and second electric connectors electrically coupled together. The controller controls the motor to drive the agitator to agitate milk in the container to form milk froth or controls the heating element to heat the milk. | 2012-01-12 |
| 20120007261 | MOLD AND METHOD FOR PRODUCING PLASTIC LENS | 2012-01-12 |
| 20120007262 | METHOD OF MANUFACTURING OPTICAL ELEMENTS - Provided is a method for manufacturing optical elements, the method including the following processes: a process to determine the wave-front aberration for a lens fabricated using a reference die, and then choose the integer multiple of a predetermined constant that is closest to the difference between a lens design value and the wave-front aberration for the lens fabricated using the reference die; and a process to determine the amount of aberration correction that cancels out the aforementioned integer multiple aberration, change the lens design so that either the low-order spherical aberration or the low-order astigmatism therefor becomes equal to the aberration correction, and fabricate a correction die from either a first or a second die, with the shape of the molding surface thereof changed on the basis of the changed design value. Then the die design value is decided upon, yielding a final die. | 2012-01-12 |
| 20120007263 | MONOMER BEADS FOR PRODUCING A PROTON-CONDUCTING MEMBRANE - Monomer beads which can be obtained according to a process in which
| 2012-01-12 |
| 20120007264 | ICE CAKE MAKING APPARATUS AND METHOD - An ice cake forming apparatus is provided. The ice cake forming apparatus may include a pair of molds formed from a material having a relatively high heat conductivity such as aluminum and so on, and guide rods which guide mutual freely separating and approaching of the pair of molds. Separating and joining surfaces of the pair of molds may be provided with molding concavities respectively and appropriately, and the apparatus may be so constituted that an appropriate blank ice lump is melted at portions contacting to the molds, utilizing a temperature difference between the molds at a temperature equal to or lower than a normal temperature and the blank ice lump, and a desired shape of molded ice cake can be molded by the molding concavities due solely to a heat held in the molds. | 2012-01-12 |
| 20120007265 | PLASTICS PROCESSING METHOD AND APPARATUS - A method for additive delivery during a plastics processing is disclosed. The method includes establishing a network of components in a control loop that uses a feedback method to drive at least one pump, thus enabling continuous, robust proportioning of additive in a difficult to control environment. The feedback method includes sending at least one signal from at least one sensor associated with a plastics melting machine to a controller, sending one or more signals from the controller to the at least one pump, monitoring the pressure in the at least one pump and sensing the position of an injection nozzle valve, and sending one or more signals to the injection nozzle valve instructing the valve to open or close. | 2012-01-12 |
| 20120007266 | FOAM PATTERNS - A method of creating a foam pattern comprises mixing a polyol component and an isocyanate component to form a liquid mixture. The method further comprises placing a temporary core having a shape corresponding to a desired internal feature in a cavity of a mold and inserting the mixture into the cavity of the mold so that the mixture surrounds a portion of the temporary core. The method optionally further comprises using supporting pins made of foam to support the core in the mold cavity, with such pins becoming integral part of the pattern material simplifying subsequent processing. The method further comprises waiting for a predetermined time sufficient for a reaction from the mixture to form a foam pattern structure corresponding to the cavity of the mold, wherein the foam pattern structure encloses a portion of the temporary core and removing the temporary core from the pattern independent of chemical leaching. | 2012-01-12 |
| 20120007267 | Method of Producing Compostable or Biobased Foams - The present invention describes compostable or biobased foams that are useful for fabricating foamed articles. The foams are produced using a compound comprising a compostable or biobased polyester and a blowing agent. Additives including plasticizers and chain extenders are optionally included in the compostable or biobased composition. These foams can be produced using conventional melt processing techniques, such as single and twin-screw extrusion processes. In one embodiment, foamed strand profiles are cooled and cut using conventional strand pelletizing equipment. In another embodiment, foamed beads are produced by cutting the foamed strand at the face of the extrusion die and the foamed bead or strand is subsequently cooled. The resulting compostable or biobased foamed bead has a specific gravity less than 0.15 g/cm | 2012-01-12 |
| 20120007268 | Method of Producing a Semiconductor - A method for manufacturing a semiconductor is disclosed. A mold is providing having an interior defining a planar capillary space. A measure of precursor is placed in fluid communication with the capillary space. The precursor is then melted, and the melted precursor is allowed to flow into the capillary space. The melted precursor is then allowed to cool to form a semiconductor. | 2012-01-12 |
| 20120007269 | METHOD OF MANUFACTURING PRE-BENT WIND TURBINE BLADES - In a method of manufacturing a blade shell half of a pre-bent wind turbine blade by means of vacuum-assisted resin transfer moulding (VARTM), a fibre lay-up ( | 2012-01-12 |
| 20120007270 | THERMOPLASTIC POLYURETHANES AND THEIR USE - This invention concerns thermoplastic polyurethane mouldings with improved surface resistance (resistance to writing and scratching) and very good technical processability as well as their use. | 2012-01-12 |
| 20120007271 | Method for Producing Thin Flake - A process for forming thin flake particles includes coating the liquid release agent over a base substrate, forming a multilayer structure by depositing a thin film over the liquid release agent, collecting the multilayer structure, and separating the thin flake from the multilayer structure using a suitable solvent. The liquid release agent comprises a curable compound that can form a solidified layer less than 0.001 mm thick onto which the thin film can be deposited. Separation requires little solvent because of the thinness of the solidified layer. | 2012-01-12 |
| 20120007272 | HDPE Resins for Use in Pressure Pipe and Related Applications - The present invention provides bimodal polyethylene resins in which the high molecular weight ethylene copolymer component typically has a relatively narrow molecular weight distribution, with short chain branching content being substantially constant across its molecular weight distribution. The resins of this invention are typically characterized by improved toughness and resistance to slow crack propagation properties making them useful for pressure pipe applications. | 2012-01-12 |
| 20120007273 | Method of Molding Polymeric Materials to Impart a Desired Texture Thereto - A method of molding a polymeric material to create a desired texture therein using an alumina mold having a plurality of cylindrical pores disposed therein, the method comprising the steps of: a) providing a porous alumina master having a plurality of cylindrical pores dispersed therein, said plurality of cylindrical pores corresponding to projections to be imparted to a surface of a film; disposing a polymeric material between a film and the porous alumina master; and c) applying mechanical pressure to roll the porous alumina master into the polymeric material, wherein the texture imparted to the polymeric molding material comprises projections corresponding to the cylindrical pores of the porous alumina master. A release agent is applied to the porous alumina master prior to disposing the polymeric molding material between the porous alumina master and the film. | 2012-01-12 |
| 20120007274 | Method for producing a mould element - A method for producing a mould element provided with a conduit arrangement through which a cooling fluid can flow. The method includes providing a first component and a second component of the mould element, the first component being provided with a precursor arrangement of the conduit arrangement, the precursor arrangement having an open channel arrangement; joining the first component and the second component, so that a surface of the second component faces the open channel arrangement to define therewith the conduit arrangement. The step of joining includes making integral the first component with the second component via a third component formed in contact with the first component and with the second component in an auxiliary mould. | 2012-01-12 |
| 20120007275 | METHOD OF MANUFACTURING RETARDATION FILM - A method of manufacturing a retardation film includes: a first step of forming, on the same metal master, a main region having several kinds of groove regions having different extending directions of grooves, and a sub region having one kind of groove region having a predetermined extending direction of grooves or several kinds of groove regions having different extending directions of grooves; and a second step of collectively transferring reverse patterns of the main and sub regions on the metal master to a base, and then forming, on a surface of the base, a layer including an alignable material to be aligned in correspondence to irregularity of the surface of the base, thereby forming a patterned retardation region in a site having a reverse pattern of the main region, and forming an alignment mark region in a site having a reverse pattern of the sub region. | 2012-01-12 |
| 20120007276 | IMPRINT TEMPLATE, METHOD FOR MANUFACTURING IMPRINT TEMPLATE, AND PATTERN FORMATION METHOD - According to one embodiment, an imprint template includes a base substrate and a resin-based pattern transfer portion. The pattern transfer portion is formed on a major surface of the base substrate and includes a protrusion-depression pattern. A shape of the protrusion-depression pattern is transferred to a transfer target. The protrusion-depression portion is provided at the major surface of the base substrate. A major surface side of the pattern transfer portion is provided so as to fit into a depression of the protrusion-depression portion. In another embodiment, a pattern formation method is disclosed. The method can include providing the transfer target on the substrate, and using the imprint template to bring the pattern into contact with the transfer target. In addition, the method can include curing the transfer target and then releasing the imprint template from the transfer target to transfer the shape of the pattern to the transfer target. | 2012-01-12 |
| 20120007277 | DEVICE AND METHOD FOR FORMING MULTILAYERED LAMINATES - Methods and devices for forming a vertically-oriented multilayer laminates, for example, a vertically-oriented multilayer laminates, are provided. The laminates may be fabricated by hardenable fluids, for example, polymers that are directed along flow paths to divide, repossession, and combine streams to provide the desired laminated structure. The flow divisions and recombination may be practiced repeatedly wherein laminates have tens or even tens of thousands of individual layers may be produced. The polymers used may have comparable viscosities, for example, having viscosity ratios of less than 3. Though aspects of the invention may be used packaging, aspects of the invention may be applied to any field where laminated structures are desired. | 2012-01-12 |
| 20120007278 | Variable Material Stretch-Forming Apparatus and Methods - Apparatus's and methods of stretch-forming pre-preg material are provided. In one example embodiment a variable material stretch forming apparatus comprises a stretch-forming assembly configured to stretch-form at least one section along a width of a sheet of pre-preg material to a longer length than at least one other section along the width of the sheet of pre-preg material before the sheet of pre-preg material is applied to a tool. | 2012-01-12 |
| 20120007279 | HOLDING DEVICE, IMPRINT APPARATUS, AND ARTICLE MANUFACTURING METHOD - A holding device of the present invention for holding a mold, the device includes a holder configured to attract the mold to hold the mold; an actuator supported by the holder so as to face a side of the mold, and configured to apply a force to the side to deform the mold; and a detector supported by the holder so as to face the side, and configured to detect a position of the side in a direction of the force. Here, the detector is configured to detect, as the position, a position of a first region in the side, the actuator is configured to apply the force to a second region in the side, and the second region is around the first region. | 2012-01-12 |
| 20120007280 | FINE-STRUCTURE TRANSFER METHOD - A fine-structure transfer method in which a fine-featured pattern formed on one of the two surfaces of a stamper is pressed against a coating of a resist on one of the two surfaces of a transfer element so as to transfer the fine-featured pattern to the resist coating, wherein the atmosphere in the space between the stamper and the transfer element is replaced by the vapor of the resist before the stamper is pressed against the transfer element. | 2012-01-12 |
| 20120007281 | POWDER SLUSH MOLDING PROCESS AND EQUIPMENT - A powder slush molding process and associated equipment utilize a flow restrictor disposed between a powder box and a mold surface to deposit powdered resin onto the mold surface in a controlled manner, thereby forming skins having decreased variation in thickness. | 2012-01-12 |
| 20120007282 | Method for producing composite articles - A method for producing composite articles includes: (a) advancing continuously a lower mold release sheet; (b) disposing prepreg articles in a spaced-apart manner on the lower mold release sheet; (c) advancing continuously an upper mold release sheet above the lower mold release sheet so that each of the prepreg articles is sandwiched between the lower and upper mold release sheets; and (d) thermoforming the prepreg articles that are sandwiched between the lower and upper mold release sheets. | 2012-01-12 |
| 20120007283 | Weathering-stabilized acrylonitrile copolymer molding compositions - The present invention relates to a thermoplastic molding composition comprising
| 2012-01-12 |
| 20120007284 | METHOD OF MAKING STRUCTURAL MEMBERS USING WASTE AND RECYCLED PLASTICS - A composite formulation consisting of agglomerated industrial/residential sewer sludge and recycled high density polyethylene (HDPE) and/or polypropylene (PP) materials. The recycled plastic materials act as a binder for the pozzolan industrial/residential sewer sludge. The composite formulation can be produced in a batching process wherein the sieved dried sewer sludge and the recycled plastic in appropriate small cut pieces is fed into a large plastic extruder, heated and extruded into specific structures. The formulation can also be compounded using a compression mold wherein sieved dry sewer sludge are added to heated chopped recycled plastics and heat mixed to produce pellets or directed into a compression mold to create a structural member of predetermined shape. | 2012-01-12 |
| 20120007285 | MOLD MAKING SYSTEM AND MOLD MAKING METHOD - A mold making system for surface patterning of a roller mold is provided. The roller mold includes a transparent hollow roller and a polymer layer disposed at an outer surface of the transparent hollow roller. The mold making system includes a laser generation device, an optical path changing device, and a control device connected to the optical path changing device. The laser generation device is used for generating an ultrafast laser. The optical path changing device is disposed at an inner space of the transparent hollow roller to receive the ultrafast laser. The control device controls the optical path changing device to guide the ultrafast laser to pass through the transparent hollow roller and to be focused at a focus position in the polymer layer. | 2012-01-12 |
| 20120007286 | LOW TRANSIENT AND STEADY STATE THERMAL STRESS DISK SHAPED COMPONENTS - A process for manufacturing a disk shaped component comprising fabricating a disk shaped component using a composite material having at least a first material and a second material, wherein the first material is disposed at and proximate to a center portion of the disk shaped component and the second material is disposed at and proximate to a rim of the disk shaped component, wherein the first material comprises a first coefficient of thermal expansion, a first stress value and a first oxidation resistance, and the second material comprises a second coefficient of thermal expansion, a second stress value and a second oxidation resistance, wherein the first coefficient of thermal expansion is greater than the second coefficient of thermal expansion, the first stress value is greater than the second stress value and the first oxidation resistance is less than the second oxidation resistance. | 2012-01-12 |
| 20120007287 | METHOD AND APPARATUS FOR LAYERWISE PRODUCTION OF A 3D OBJECT - A system and method for layer-by-layer production of an object is provided. The system includes a construction shape having a carrying surface adapted for carrying a layer of build material, a plate having a holding surface adapted for holding an object in an object build area, a moveable reservoir having a plurality of containment surfaces defining a containment area adapted for containing a volume of build material within the moveable reservoir, and an exposure unit adapted for exposing at least a portion of the layer of build material in the object build area so that the portion of the layer of build material solidifies to form a solidified layer of the object. In one embodiment, the moveable reservoir is moveable between a first position and a second position and at least one of the plurality of containment surfaces of the moveable reservoir includes a portion of the carrying surface when the moveable reservoir is in the first position, and the portion of the carrying surface is positioned in the object build area when the moveable reservoir is in the second position. | 2012-01-12 |
| 20120007288 | Compensation of Actinic Radiation Intensity Profiles for Three-Dimensional Modelers - There is provided methods and apparatus for compensation of intensity profiles of imagers used in three-dimensional modelers. The intensity profile of the actinic radiation projected from the imager is determined by a variety of techniques, including but not limited to manually operated sensors, exposed and scanned actinic radiation-sensitive paper, and intensity profilers. Once the intensity profile of the imager is determined, each layer of the solidifiable liquid material is cured by projecting a plurality of patterns (as opposed to a single pattern) defining the two-dimensional cross-section of the part being cured. The patterns vary in duration, number, and/or shape to correlate to the intensity profile so that a single layer of selectively cured solidifiable liquid material is cured with a substantially equivalent (or otherwise controlled) amount of actinic radiation per unit of surface area to provide generally controlled and consistent part quality. | 2012-01-12 |
| 20120007289 | METHOD AND SYSTEM FOR THERMALLY MONITORING PROCESS FOR FORMING PLASTIC BLOW-MOLDED CONTAINERS - The present invention provides a method of measuring the placement of material forming a blow-molded plastic container after the container is released from a mold of a blow molder having a plurality of molds, wherein each plastic container comprises a continuous sidewall and a base, the method comprising the steps of: detecting with an infrared camera infrared light emitted from the container after the container is released from a mold; converting the detected infrared light into corresponding electrical signals; transmitting the electrical signals to a microprocessor; comparing in the microprocessor the electrical signals with stored data regarding desired material distribution forming the plastic container; and producing output information regarding the placement of material forming the container. | 2012-01-12 |
| 20120007290 | Blow Moulding Machine with Compressed Air Recycling - An apparatus for shaping plastic preforms into plastic containers, including a plurality of blow moulding stations which each have a cavity in which the plastic preforms can be shaped into plastic containers. The blow moulding stations are arranged on a movable carrier and each have a stretching rod which stretches the plastic containers in their longitudinal direction by a movement in a stretching direction. A fluid-actuated drive device is provided for driving the stretching rod in the stretching direction. The apparatus includes a guide cam which is arranged in a stationary manner and by means of which the stretching rod can be moved counter to the stretching direction as a function of a movement of the blow moulding station. At least one portion of the guide cam is adjustable and, for example, by virtue of this adjustment a dependency of the movement of the stretching rod on the movement of the blow moulding station can be varied. | 2012-01-12 |
| 20120007291 | TUYERE STOCK ARRANGEMENT FOR A BLAST FURNACE AND METHOD FOR FEEDING HOT BLAST INTO A BLAST FURNACE - Tuyere stock arrangement ( | 2012-01-12 |
| 20120007292 | METHOD AND APPARATUS FOR PRODUCING REDUCED METAL - A feedstock-feeding step of feeding a feedstock containing a carbonaceous reductant and an iron oxide-containing material into a rotary hearth furnace, a heating/reducing step of heating the feedstock to reduce iron oxide contained in the feedstock into reduced iron, a melting step of melting the reduced iron, a cooling step of cooling the molten reduced iron, and a discharging step of discharging the cooled reduced iron are performed in that order in the direction that a hearth is moved. The furnace includes flow rate-controlling partitions, arranged therein, for controlling the flow of furnace gas and the furnace gas in the cooling step is allowed to flow in the direction of the movement of the hearth with the partitions. | 2012-01-12 |
| 20120007293 | SEAT SUSPENSION DEVICE FOR A VEHICLE SEAT - The invention relates to a seat suspension device for a vehicle seat, in particular a commercial vehicle seat, comprising at least one air spring, said air spring being disposed between an upper seat portion of the vehicle seat and a lower seat portion of the vehicle seat, and at least one hose-like member connected to the air spring via a first connection line for an extension volume of the air spring is provided, said hose-like member being arranged along at least one fold of a bellows-like facing extending between an upper seat portion and a lower seat portion of a vehicle seat. | 2012-01-12 |
| 20120007294 | SEAT SUSPENSION - To expand a body weight adjustment range and achieve thinning. An initial position adjusting member | 2012-01-12 |
| 20120007295 | ENGINE MOUNT AND ELASTOMERIC ELEMENT THEREOF - An isolation mount for supporting and isolating one part from another includes an inner member formed to be connected to one of the parts and an outer member formed to be connected to one of the parts. The inner member has a first and a second inner plates being connected at one end and extending at a first angle with respect to each other; the outer member also has a first and a second outer plates being connected at one end and extending at a second angle with respect to each other. The isolation mount further includes a first and a second individual elastomeric element compressed between respective inner and outer plates. | 2012-01-12 |
