02nd week of 2012 patent applcation highlights part 14 |
Patent application number | Title | Published |
20120007097 | SCHOTTKY DIODE WITH COMBINED FIELD PLATE AND GUARD RING - A Schottky diode comprising a merged guard ring and field plate defining a Schottky contact region is provided. A Schottky metal is formed over at least partially over the Schottky contact region and at least partially over the merged guard ring and field plate. | 2012-01-12 |
20120007098 | TRANSISTOR AND METHOD FOR PRODUCING TRANSISTOR - Certain embodiments provide a transistor including a semiconductor conductive layer, a drain electrode, a source electrode, and a gate electrode. The semiconductor device is III nitride-based semiconductor conductive layer including an active layer, formed on a surface of a substrate. The drain electrode and the source electrode have a titanium layer and an aluminum layer formed on the titanium layer and having a film thickness ratio of 12 to 15 with respect to the titanium layer, and the drain electrode and the source electrode come into ohmic contact with the semiconductor layer. The gate electrode is in Schottky junction with the semiconductor layer between the drain electrode and source electrode. | 2012-01-12 |
20120007099 | MULTI-GAS SENSOR AND METHOD OF FABRICATING THE SENSOR - The present invention is a multi-gas sensor and a method for fabricating the multi-gas sensor. | 2012-01-12 |
20120007100 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device including a substrate, a reflective layer provided on the substrate, and a light emitting structure, which includes a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer placed between the first and second conductive semiconductor layers, wherein the first conductive semiconductor layer is an n-type semiconductor layer including GaN and doped with an n-type dopant, wherein the first conductive semiconductor layer includes a first n-type semiconductor layer and a second n-type semiconductor layer between the first n-type semiconductor layer and the active layer, wherein one surface of the first n-type semiconductor layer contacts the second n-type semiconductor layer, and wherein the surface of the first n-type semiconductor layer contacting the second n-type semiconductor layer is formed in an N-phase. The disclosed light emitting device may have improved luminous efficacy while showing reduction in crystal defects. | 2012-01-12 |
20120007101 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light-emitting device, and a method of manufacturing the same. The semiconductor light-emitting device includes a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked on a substrate, a first contact that passes through the substrate to be electrically connected to the first electrode layer, and a second contact that passes through the substrate, the first electrode layer, and the insulating layer to communicate with the second electrode layer. The first electrode layer is electrically connected to the first semiconductor layer by filling a contact hole that passes through the second electrode layer, the second semiconductor layer, and the active layer, and the insulating layer surrounds an inner circumferential surface of the contact hole to insulate the first electrode layer from the second electrode layer. | 2012-01-12 |
20120007102 | High Voltage Device and Method for Optical Devices - A light emitting device comprising a gallium and nitrogen containing substrate. The device also has an electrically isolating material grown between the substrate and an active region such that the light emitting device is operable at a voltage greater than 10V. | 2012-01-12 |
20120007103 | SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR - The present disclosure relates to a silicon carbide (SiC) bipolar junction transistor (BJT), where the surface region between the emitter and base contacts ( | 2012-01-12 |
20120007104 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device employing silicon carbide, and the like are provided. In the semiconductor device, even when an electrode material and an upper electrode material are different, a problem does not take place at an interface at which these different types of metals are in contact with each other, thus obtaining high reliability in long-term use. | 2012-01-12 |
20120007105 | Fully silicon aled-photodiode optical data link module - In a silicon-based light emitting diode-photodiode (LED-PD) arrangement, the LED is implemented as an avalanche LED (ALED) and the ALED and PD are integrated into a common integrated circuit. The ALED is formed around a cross-shaped PD and is separated from the PD by a deep trench region. In order to create current crowding close to the deep trench the ALED includes an NBL or PBL having a narrowing at its end | 2012-01-12 |
20120007106 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode (OLED) display according to an exemplary embodiment includes an organic light emitting display panel that includes an organic light emitting member, a polarizing plate that is spaced-apart from the organic light emitting display panel and arranged at an upper portion thereof, and a window that is attached to an upper portion of the polarizing plate and protects the organic light emitting display panel. The polarizing plate may include a linear polarizing member and a retardation film that is disposed under the linear polarizing member. According to the exemplary embodiment, the external light visibility can be improved by absorbing light that is incident on the lower portion of the polarizing plate by the polarizing plate by attaching the polarizing plate to the lower portion of the window and separating the polarizing plate from the organic light emitting display panel. | 2012-01-12 |
20120007107 | Organic light emitting diode display and manufacturing method thereof - An organic light emitting diode (OLED) display includes: a first substrate; a display portion that is formed on the first substrate and includes a driving circuit portion and an organic light emitting diode; a thin film encapsulation layer that covers the display portion; an adhesive layer that covers an upper surface and a side of the thin film encapsulation layer; an absorption functional layer that is formed on the adhesive layer and absorbs at least one of oxygen and moisture; and a second substrate that is formed on the absorption functional layer. | 2012-01-12 |
20120007108 | LIGHT EMITTING DEVICE AND DISPLAY APPARATUS - A light emitting device includes: a light emitting chip arranged on a substrate; a resin lens which covers the light emitting chip and focuses irradiation light from the light emitting chip; a mask which covers a region of an upper layer surface of the substrate, other than the resin lens; and a low surface tension film formed on a region of the upper layer surface of the substrate, other than in the proximity of the light emitting chip. | 2012-01-12 |
20120007109 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed are a light emitting device and a method of fabricating the same. The light emitting device comprises a substrate. A plurality of light emitting cells are disposed on top of the substrate to be spaced apart from one another. Each of the light emitting cells comprises a first upper semiconductor layer, an active layer, and a second lower semiconductor layer. Reflective metal layers are positioned between the substrate and the light emitting cells. The reflective metal layers are prevented from being exposed to the outside. | 2012-01-12 |
20120007110 | Light Emitting Device - To provide a light emitting device in which generation of cross talk between adjacent light emitting elements is suppressed, even when the light emitting device uses a light emitting element having high current efficiency. Also, to provide a light emitting device having high display quality even when the light emitting device uses a light emitting element having high current efficiency. The light emitting device has a pixel portion including a plurality of light emitting elements, wherein each of the plurality of light emitting elements includes a plurality of light emitting bodies provided between a first electrode and a second electrode and a conductive layer formed between the plurality of light emitting bodies, wherein the conductive layer is provided for each light emitting element, and wherein an edge portion of the conductive layer is covered with the plurality of light emitting bodies. | 2012-01-12 |
20120007111 | LIGHT EMITTING DEVICE MODULE AND LIGHTING SYSTEM INCLUDING THE SAME - Disclosed herein is a semiconductor light emitting device module comprising: a heat transfer member having a cavity; first conductive layer and second conductive layer contacting the heat transfer member via an insulating layer, the first conductive layer and the second conductive layer being electrically separated from each other in accordance with exposure of the insulating layer or exposure of the heat transfer member; and at least one semiconductor light emitting device electrically connected to the first conductive layer and the second conductive layer, the at least one semiconductor light emitting device is thermally contacted an exposed portion of the heat transfer member, wherein the insulating layer has an exposed portion disposed outside the cavity. | 2012-01-12 |
20120007112 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate, a light emitting element, an additional light emitting element, a light reflecting resin member, an electrically conductive wire, an additional electrically conductive wire, and a sealing member. The substrate is provided with a conductor wiring. The light emitting element is mounted on the substrate. The electrically conductive wire electrically connects the conductor wiring and the light emitting element with at least a part of the electrically conductive wire being embedded in the light reflecting resin member. The additional electrically conductive wire electrically connects the light emitting element and the additional light emitting element, with the additional electrically conductive wire not being in contact with the light reflecting resin member. The sealing member is disposed in a region surrounded by the light reflecting resin member to cover the light emitting element. | 2012-01-12 |
20120007113 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a well layer, a barrier layer, an Al-containing layer, and an intermediate layer. The p-type semiconductor layer is provided on a side of [0001] direction of the n-type semiconductor layer. The well layer, the barrier layer, the Al-containing layer and the intermediate layer are disposed between the n-type semiconductor layer and the p-type semiconductor layer subsequently. The Al-containing layer has a larger band gap energy than the barrier layer, a smaller lattice constant than the n-type semiconductor layer, and a composition of Al | 2012-01-12 |
20120007114 | LIGHT EMITTING DIODE, LIGHT EMITTING DIODE LAMP AND ILLUMINATING DEVICE - A light emitting diode including a compound semiconductor layer having at least a pn junction-type light emitting unit and a strain adjustment layer stacked on the light emitting unit, wherein the light emitting unit has a stacked structure containing a strained light emitting layer having a composition formula of (Al | 2012-01-12 |
20120007115 | PHOSPHOR, LIGHT-EMITTING DEVICE USING SAME, IMAGE DISPLAY AND ILLUMINATING DEVICE - The present invention relates to a phosphor represented by the following general formula (I), comprising: a composite oxide containing a divalent and trivalent metal elements as a host crystal; and at least Ce as an activator element in said host crystal, wherein the phosphor has a maximum emission peak in a wavelength range of from 485 nm to 555 nm in the emission spectrum at room temperature: | 2012-01-12 |
20120007116 | SEMICONDUCTOR LIGHT EMITTING DIODE AND METHOD OF PRODUCING THE SAME - A semiconductor light emitting diode including: a support substrate; an intermediate layer including an intermediate electrode portion, a second conductive semiconductor layer, an active layer, a first conductive semiconductor layer and an upper electrode portion sequentially disposed on the upper surface side of the support substrate in this order; and a lower electrode layer provided on the lower surface side of the support substrate, where: the intermediate layer has at least one intermediate electrode portion extending linearly or in an island-like shape; and the upper electrode portion and the intermediate electrode portion are disposed in such a positional relationship that these electrode portions are in parallel with and offset from each other and a distance between the upper electrode portion and the intermediate electrode portion is within the range of 10 μm to 50 μm. | 2012-01-12 |
20120007117 | Submount for Electronic Die Attach with Controlled Voids and Methods of Attaching an Electronic Die to a Submount Including Engineered Voids - A packaged electronic device includes a submount, a bonding pattern on the submount, and an electronic chip on the bonding pattern. A periphery of the electronic chip defines a die mounting region of the submount. The bonding pattern includes a bonding area within the die mounting region and at least one channel that extends from within the die mounting region to a region of the submount outside the die mounting region. | 2012-01-12 |
20120007118 | LIGHT EMITTING DEVICE - A light emitting device may be provided that includes a conductive support member, a first conductive layer, a second conductive layer, an insulation layer between the first conductive layer and the second conductive layer, and a light emitting structure that includes a second semiconductor layer on the second conductive layer, a first semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer. The first conductive layer may include at least one conductive via that passes through the second conductive layer, the second semiconductor layer and the active layer. A top surface of the at least one conductive via is provided into the first semiconductor layer. The insulation layer may substantially surround a side wall of the conductive via. The first surface of the first semiconductor layer may include a first surface area, a second surface area and a recess having a bottom surface. The recess may be aligned with the bottom surface of the first conductive layer, and the first surface of the first conductive layer may be aligned with the first area of the first surface of the first semiconductor layer. The first surface of the first semiconductor layer and the recess may have a surface roughness. | 2012-01-12 |
20120007119 | LIGHT-EMITTING SEMICONDUCTOR DEVICE, MOUNTED SUBSTRATE, AND FABRICATION METHOD THEREOF - A light-emitting semiconductor device includes a lead frame having lead electrodes, a reflector arranged with the lead frame, and a light-emitting semiconductor chip accommodated in the reflector and having electrodes connected to the lead electrodes by a flip-chip bonding method, wherein: a gap between the lead frame and the light-emitting semiconductor chip is filled with a cured underfill material, and a cured silicon oxide film of 0.05 to 10 μm thickness is formed covering surfaces of the light-emitting semiconductor chip and reflector. | 2012-01-12 |
20120007120 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a light emitting device and a method of manufacturing the same. The light emitting device includes a substrate; a light emitting structure disposed on the substrate and having a stack structure in which a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer are stacked; a lens disposed on the light emitting structure; and a first terminal portion and a second terminal portion electrically connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively. At least one of the first and second terminal portions extends from a top surface of the light emitting structure along respective side surfaces of the light emitting structure and the substrate. | 2012-01-12 |
20120007121 | LIGHT EMITTING DEVICE - A light emitting device is provided that includes a light emitting structure (including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer), a conductive layer, an insulation layer, and a current blocking layer. The conductive layer may have a first conductive portion that passes through the second conductive type semiconductor layer and the active layer to contact the first conductive type semiconductor layer. The insulation layer may have a first insulation portion that surrounds the first conductive portion of the conductive layer. The current blocking layer may substantially surround the first insulation portion of the insulation layer, the first insulation portion provided between the current blocking layer and the first conductive portion. | 2012-01-12 |
20120007122 | LIGHT EMITTING DEVICE PACKAGE AND A LIGHTING DEVICE - Provided are a light emitting device package and a lighting device. The light emitting device package includes a base, a light emitting device on the base, a plurality of electrode pads on the base, the plurality of electrode pads electrically connected to the light emitting device, a frame disposed on the base, wherein a size of the frame is smaller than a size of the base, a silver layer on a portion of the plurality of electrode pads, the silver layer directly contacted with the frame and an optical member covering the light emitting device. | 2012-01-12 |
20120007123 | LIGHT EMITTING APPARATUS, AND METHOD FOR MANUFACTURING THE SAME, AND LIGHTING SYSTEM - A light emitting apparatus includes: a substrate including a first conductive type impurity; a first heatsink and a second heatsink on a first region and a second region of the substrate; second conductive type impurity regions on the substrate and electrically connected to the first heatsink and the second heatsink, respectively; a first electrode electrically connected to the first heatsink on the substrate; a second electrode electrically connected to the second heatsink on the substrate; and a light emitting device electrically connected to the first electrode and the second electrode on the substrate. | 2012-01-12 |
20120007124 | SEMICONDUCTOR LIGHT- EMITTING DEVICE - A semiconductor light emitting device (A) includes a semiconductor light emitting element ( | 2012-01-12 |
20120007125 | LIGHTING USING SOLID STATE DEVICE AND PHOSPHORS TO PRODUCE LIGHT APPROXIMATING A BLACK BODY RADIATION SPECTRUM - Solid state light emitting devices and/or solid state lighting devices use three or more phosphors excited by energy from a solid state source. The phosphors are selected and included in proportions such that the visible light output of such a device exhibits a radiation spectrum that approximates a black body radiation spectrum for the rated color temperature for the device, over at least a predetermined portion of the visible light spectrum. | 2012-01-12 |
20120007126 | METHOD FOR COATING SEMICONDUCTOR DEVICE USING DROPLET DEPOSITION - Methods and systems for coating of semiconductor devices using droplets of wavelength conversion or phosphor particles in a liquid medium. A plurality of nozzles delivers a controlled amount of the matrix material to the surface of the semiconductor device, with each of said nozzles having an opening for the matrix material to pass. The opening has a diameter wherein the diameter of the phosphor particles is less than or approximately equal to one half the diameter of the opening. The phosphor particles are also substantially spherical or rounded. The nozzles are typically arranged on a print head that utilizes jet printing techniques to cover the semiconductor device with a layer of the matrix material. The methods and systems are particularly applicable to covering LEDs with a layer of phosphor materials. | 2012-01-12 |
20120007127 | OPTICAL-SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing an optical-semiconductor device, including forming a plurality of first and second electrically conductive members that are disposed separately from each other on a support substrate; providing a base member formed from a light blocking resin between the first and second electrically conductive members; mounting an optical-semiconductor element on the first and/or second electrically conductive member; covering the optical-semiconductor element by a sealing member formed from a translucent resin; and obtaining individual optical-semiconductor devices after removing the support substrate. | 2012-01-12 |
20120007128 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND LIGHT EMITTING APPARATUS HAVING THE SAME - A semiconductor light emitting device and a light emitting apparatus having the semiconductor light emitting device are provided. The semiconductor light emitting device comprises a substrate, a light emitting structure disposed on the substrate and comprising a first conductive type semiconductor layer, an active layer on the first conductive type semiconductor layer, and a second conductive type semiconductor layer on the active layer, a second electrode electrically connected to the second conductive type semiconductor layer, a plurality of first electrodes disposed on a plurality of sidewalls of the first conductive type semiconductor layer, and wherein the plurality of first electrodes are spaced apart from each other. | 2012-01-12 |
20120007129 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device including a substrate, a light emitting structure arranged on the substrate, the light emitting structure including a first semiconductor layer, a second semiconductor layer and an active layer arranged between the first semiconductor layer and the second semiconductor layer, a first electrode electrically connected to the first semiconductor layer, and a second electrode electrically connected to the second semiconductor layer, wherein the light emitting structure has a top surface including a first side and a second side which face each other, and a third side and a fourth side which face each other. | 2012-01-12 |
20120007130 | ILLUMINATION DEVICE WITH REMOTE LUMINESCENT MATERIAL - The invention provides an illumination device comprising a light source and a transmissive arrangement. The light source is arranged to generate light source light and comprises a light emitting device (LED), arranged to generate LED light and a carrier comprising a first luminescent material. The carrier is in contact with the LED and the first luminescent material is arranged to convert at least part of the LED light into first luminescent material light. The transmissive arrangement of a second luminescent material is arranged remote from the light source and is arranged to convert at least part of the LED light or at least part of the first luminescent material light and/or at least part of the LED light. The invention overcomes current limitations of remote luminescent material systems in spot lighting. In addition, an extremely simple way of realizing light sources with various correlated colour temperatures is allowed, based on just a single type of white (or whitish) light source in combination with various (red-orange) remote luminescent materials. | 2012-01-12 |
20120007131 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND LIGHT SOURCE DEVICE USING THE SAME - A semiconductor light-emitting device according to the present invention is a semiconductor light-emitting device | 2012-01-12 |
20120007132 | REDUCTION OF ETCH MICROLOADING FOR THROUGH SILICON VIAS - The patterns (or layout), and pattern densities of TSVs described above provide layout of TSVs that could be etched with reduced etch microloading effect(s) and with good within-die uniformity. The patterns and pattern densities of TSVs for different groups of TSVs (or physically separated groups, or groups with different functions) should be fairly close amongst different groups. Different groups of TSVs (or TSVs with different functions, or physically separated TSV groups) should have relatively close shapes, sizes, and depths to allow the aspect ratio of all TSVs to be within a controlled (and optimal) range. The size(s) and depths of TSVs should be carefully selected to optimize the etching time and the metal gap-fill time. | 2012-01-12 |
20120007133 | LIGHT EMITTING DEVICE AND LIGHTING SYSTEM - A light emitting device includes:
| 2012-01-12 |
20120007134 | PLANAR LIGHT EMITTING DEVICE - Planar light emitting device includes: anode and cathode feeding parts formed on first surface side of transparent substrate and electrically connected to quadrilateral planar anode and cathode, respectively; quadrilateral frame shaped anode auxiliary electrode formed at the whole circumference of surface of the planar anode; anode feeding auxiliary electrode integrally and continuously formed to the auxiliary electrode and laminated on anode feeding part. Light emitting part is formed of a region where only organic layer intervenes between the planar anode and cathode. Distance between predetermined two parallel sides of the four sides of the light emitting part and the peripheral border of the transparent substrate is smaller than distance between the other two parallel sides and the peripheral border. The cathode and anode feeding parts are located along said other two parallel sides. The anode feeding part is located at each side, in width direction, of the cathode feeding part. | 2012-01-12 |
20120007135 | SEMICONDUCTOR DEVICE - An exemplary semiconductor device is provided. The semiconductor device includes a semiconductor stacked layer and a conductive structure. The conductive structure is located on the semiconductor stacked layer. The conductive structure includes a bottom portion and a top portion on opposite sides thereof. The bottom portion is in contact with the semiconductor stacked layer. A ratio of a top width of the top portion to a bottom width of the bottom portion is less than 0.7. The conductive structure can be a conductive dot structure or a conductive line structure. | 2012-01-12 |
20120007136 | LIGHT EMITTING APPARATUS AND LIGHT UNIT HAVING THE SAME - Provides are a light emitting apparatus and a light unit having the same. The light emitting apparatus comprises a light emitting device comprising a light emitting element and a plurality of external leads, and a plurality of electrode pads under the light emitting device. | 2012-01-12 |
20120007137 | ORGANIC LIGHT-EMITTING APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting apparatus and a method of manufacturing the same are provided. | 2012-01-12 |
20120007138 | SMOKE-FREE ESD PROTECTION STRUCTURE USED IN INTEGRATED CIRCUIT DEVICES - The present invention provides a smoke-free ESD protection structure used in integrated circuit devices. A JFET or n-channel MOS transistor is coupled between an I/O pad, and a transistor and diode, wherein the JFET or n-channel MOS transistor limits the current flowing through the diode and transistor to prevent the integrated circuit device from heating up and catching on fire or smoke during the smoke test. Moreover, the integrated circuit device will not be damaged by the smoke test. | 2012-01-12 |
20120007139 | SEMICONDUCTOR DEVICE - The present teachings provides a bipolar semiconductor device comprising: a main cell region consisting of a trench gate type element region; and a sense cell region including a planar gate type element region. | 2012-01-12 |
20120007140 | ESD self protecting NLDMOS device and NLDMOS array - In an NLDMOS array, the source fingers are terminated by p+ Pbody diffusions or Pbody diffusions. The drain-source spacing is reduced by arranging p+ Pbody regions for contacting the Pbody, in line with n+ source regions to define source fingers with interdigitated p+ Pbody regions. | 2012-01-12 |
20120007141 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR SUBSTRATE INCLUDING DIODE REGION AND IGBT REGION - A semiconductor device, including a semiconductor substrate in which a diode region and an IGBT region are formed, is provided. A lifetime control region is formed within a diode drift region. The diode drift region and the IGBT drift region are a continuous region across a boundary region between the diode region and the IGBT region. A first separation region and a second separation region are formed within the boundary region. The first separation region is formed of a p-type semiconductor, formed in a range extending from an upper surface of the semiconductor substrate to a position deeper than both of a lower end of an anode region and a lower end of a body region, and bordering with the anode region. The second separation region is formed of a p-type semiconductor, formed in a range extending from the upper surface of the semiconductor substrate to a position deeper than both of the lower end of the anode region and the lower end of the body region, and bordering with the body region. The second separation region is separated from the first separation region. | 2012-01-12 |
20120007142 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR SUBSTRATE INCLUDING DIODE REGION AND IGBT REGION - Provided is a semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed. A separation region formed of a p-type semiconductor is formed in a range between the diode region and the IGBT region and extending from an upper surface of the semiconductor substrate to a position deeper than both a lower end of an anode region and a lower end of a body region. A diode lifetime control region is formed within a diode drift region. A carrier lifetime in the diode lifetime control region is shorter than that in the diode drift region outside the diode lifetime control region. An end of the diode lifetime control region on an IGBT region side is located right below the separation region. | 2012-01-12 |
20120007143 | SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions. | 2012-01-12 |
20120007144 | Compound Semiconductor Device and Method of Producing the Same - A semiconductor device comprises an Si substrate 10 and a compound layer | 2012-01-12 |
20120007145 | ASYMMETRIC CHANNEL MOSFET - A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state. | 2012-01-12 |
20120007146 | METHOD FOR FORMING STRAINED LAYER WITH HIGH GE CONTENT ON SUBSTRATE AND SEMICONDUCTOR STRUCTURE - A semiconductor structure and a method for forming the same are provided. The semiconductor structure may comprise a substrate ( | 2012-01-12 |
20120007147 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor film having a heterojunction structure, for example a semiconductor film including a SiGe layer and a Si layer formed on the SiGe layer, impurity concentration is controlled in such a manner that the concentration of impurity in the lower, SiGe layer becomes higher than that in the upper, Si layer by exploiting the fact that there is a difference between the SiGe layer and the Si layer in the diffusion coefficient of the impurity. The impurity contained in the semiconductor film | 2012-01-12 |
20120007148 | SOLID-STATE IMAGE PICKUP DEVICE AND METHOD FOR MANUFACTURING SAME - A solid-state image pickup device includes: a light-transmitting substrate including a terminal electrode for external connection, an inside electrode for bonding a solid-state image pickup element, and a trace that connects the terminal electrode to the corresponding inside electrode; and the solid-state image pickup element which is placed such that a light receiving area opposes the light-transmitting substrate and which is connected to the inside electrode. The trace is made of a light-transmitting conductive film at least in a region opposing the light receiving area of the solid-state image pickup element. | 2012-01-12 |
20120007149 | SOLID IMAGING DEVICE - In a solid-state imaging device | 2012-01-12 |
20120007150 | INTEGRATED DEVICE OF THE TYPE COMPRISING AT LEAST A MICROFLUIDIC SYSTEM AND FURTHER CIRCUITRY AND CORRESPONDING INTEGRATION PROCESS - An embodiment relates to a device integrated on a semiconductor substrate of a type comprising at least one first portion for the integration of at least one microfluidic system, and a second portion for the integration of an additional circuitry. The microfluidic system comprises at least one cavity realized in a containment layer of the integrated device closed on top by at least one portion of a polysilicon layer, this polysilicon layer being a thin layer shared by the additional circuitry and the closing portion of the cavity realizing a piezoresistive membrane for the microfluidic system. | 2012-01-12 |
20120007151 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A high breakdown voltage circuit containing a high breakdown voltage MOSFET in LSI, unlike a quintessential internal circuit, has an operating voltage fixed in a high state due to the relation with the outside and, therefore, miniaturization by the voltage lowering can not be applied, differing from ordinary cases. Consequently, the voltage lowering of an internal circuit part results in a furthermore enlargement of occupying area in the chip. The present inventors evaluated various measures for the problem, and made it clear that such problems as compatibility with the CMOSFET circuit configuration and device configuration, etc. constitute obstacles. | 2012-01-12 |
20120007152 | LOW GATE CHARGING RECTIFIER HAVING MOS STRUCTURE AND P-N JUNCTION, AND MANUFACTURING METHOD OF THE SAME - A low gate charging rectifier having a MOS structure and a P-N junction and a manufacturing method thereof are provided. The low gate charging rectifier is a combination of an N-channel MOS structure and a lateral P-N junction diode. A portion of the gate-covering region is replaced by a thicker dielectric layer or a low conductivity polysilicon layer. In a forward mode, the N-channel MOS structure and the P-N junction diode are connected with each other in parallel. Under this circumstance, like the Schottky diode, the low gate charging rectifier has low forward voltage drop and rapid switching speed. Whereas, in a reverse mode, the leakage current is pinched off and the N-channel is shut off by the depletion region of the P-N junction diode, so that the low gate charging rectifier has low leakage current. | 2012-01-12 |
20120007153 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a compound semiconductor substrate; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially disposed on the compound semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being compound semiconductor materials; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The dopant impurity concentration in the channel layer is inversely proportional to the third power of depth into the channel layer from a top surface of the channel layer. The gate electrode has a gate length in a range from 0.2 μm to 0.6 μm. | 2012-01-12 |
20120007154 | TSV Formation Processes Using TSV-Last Approach - A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad. | 2012-01-12 |
20120007155 | SEMICONDUCTOR DEVICES WITH EXTENDED ACTIVE REGIONS - A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region. | 2012-01-12 |
20120007156 | METHOD AND STRUCTURE TO REDUCE DARK CURRENT IN IMAGE SENSORS - A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel region and a periphery region, forming a light sensing element on the pixel region, and forming at least one transistor in the pixel region and at least one transistor in the periphery region. The step of forming the at least one transistor in the pixel region and periphery region includes forming a gate electrode in the pixel region and periphery region, depositing a dielectric layer over the pixel region and periphery region, partially etching the dielectric layer to form sidewall spacers on the gate electrode and leaving a portion of the dielectric layer overlying the pixel region, and forming source/drain (S/D) regions by ion implantation. | 2012-01-12 |
20120007157 | IMAGE SENSOR WITH COMPACT PIXEL LAYOUT - Solid-state image sensors, specifically image sensor pixels, which have three or four transistors, high sensitivity, low noise, and low dark current, are provided. The pixels have separate active regions for active components, row-shared photodiodes and may also contain a capacitor to adjust the sensitivity, signal-to-noise ratio and dynamic range. The low dark current is achieved by using pinned photodiodes. | 2012-01-12 |
20120007158 | NON-VOLATILE MEMORY TRANSISTOR HAVING DOUBLE GATE STRUCTURE - Provided is a non-volatile memory transistor having a double gate structure, including a first gate electrode formed on a substrate and to which an operating voltage is applied, a first gate insulating layer formed on the first gate electrode, source and drain electrodes formed on the first gate insulating layer at predetermined intervals, a channel layer formed on the first gate insulating layer between the source and drain electrodes, a second gate insulating layer formed on the channel layer, and a second gate electrode formed on the second gate insulating layer and connected to the first gate electrode such that the operating voltage is applied thereto. Accordingly, a turn-on voltage of the memory transistor can be easily controlled. | 2012-01-12 |
20120007159 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - It is an object to provide a semiconductor device integrating various elements without using a semiconductor substrate, and a method of manufacturing the same. According to the present invention, a layer to be separated including an inductor, a capacitor, a resistor element, a TFT element, an embedded wiring and the like, is formed over a substrate, separated from the substrate, and transferred onto a circuit board | 2012-01-12 |
20120007160 | Semiconductor devices including buried gate electrodes - A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed. | 2012-01-12 |
20120007161 | Semiconductor Non-volatile Memory - A method of forming a charge-storing layer in a non-volatile memory cell in a logic process includes forming a select gate over an active region of a substrate, forming long polysilicon gates partially overlapping the active region of the substrate, and filling the charge-storing layer between the long polysilicon gates. | 2012-01-12 |
20120007162 | METHOD OF FORMING SEMICONDUCTOR DEVICES - A semiconductor device includes an insulating layer and an undoped polysilicon layer that are stacked over a semiconductor substrate. The semiconductor substrate is exposed by removing the portions of the undoped polysilicon layer and the insulating layer. The trenches are formed by etching the exposed semiconductor substrate. Isolation layers are formed in the trenches, and a doped polysilicon layer is formed by implanting impurities into the undoped polysilicon layer. | 2012-01-12 |
20120007163 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film. | 2012-01-12 |
20120007164 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method can include forming a plurality of protruding portions in band configurations on a major surface of a semiconductor layer to extend along a first direction parallel to the major surface. The method can include forming an inter-layer insulating film to cover the protruding portions and an inner surface of a trench between the protruding portions. The method can include forming a buried conductive portion by filling a first conductive material into a space inside the trench. The method can include exposing a buried conductive portion side surface by dividing the buried conductive portion along the first direction. The method can include filling a second conductive material into a void of the buried conductive portion exposed at the side surface. In addition, the method can include removing one portion of the second conductive material. | 2012-01-12 |
20120007165 | SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate, a plurality of gate structures, a first insulating interlayer pattern, and a second insulation layer pattern. The substrate has an active region and a field region, each of the active region and the field region extends in a first direction, and the active region and the field region are alternately and repeatedly arranged in a second direction substantially perpendicular to the first direction. The gate structures are spaced apart from each other in the first direction, each of the gate structures extends in the second direction. The first insulation layer pattern is formed on a portion of a sidewall of each gate structure. The second insulation layer pattern covers the gate structures and the first insulation layer pattern, and has an air tunnel between the gate structures, the air tunnel extending in the second direction. | 2012-01-12 |
20120007166 | NON-VOLATILE MEMORY DEVICE USING FINFET AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a non-volatile memory device, comprising a semiconductor fin on an insulating layer; a channel region at a central portion of the semiconductor fin; source/drain regions on both sides of the semiconductor fin; a floating gate arranged at a first side of the semiconductor fin and extending in a direction further away from the semiconductor fin; and a first control gate arranged on top of the floating gate or covering top and sidewall portions of the floating gate. The non-volatile memory device reduces a short channel effect, has an increased memory density, and is cost effective. | 2012-01-12 |
20120007167 | 3D Memory Array With Improved SSL and BL Contact Layout - A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips. Some embodiments include SSL interconnects on a metal layer parallel to the semiconductor material strips, and further SSL interconnects on a higher metal layer, parallel to the word lines. | 2012-01-12 |
20120007168 | SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING SHORT CHANNEL EFFECT - A semiconductor device includes a semiconductor substrate including at least one memory channel region and at least one memory source/drain region, the memory channel region and the memory source/drain region being arranged alternately, and at least one word line on the memory channel region, wherein the memory source/drain region has a higher net impurity concentration than the memory channel region. | 2012-01-12 |
20120007169 | SEMICONDUCTOR DEVICE AND ITS PRODUCTION METHOD - The present invention provides a semiconductor device including:a semiconductor substrate of a first conductive type; a first well region of the first conductive type formed in the semiconductor substrate; an epitaxial region of a second conductive type formed in the semiconductor substrate and arranged in a region adjacent to the first well region; a buried region of the second conductive type that is formed in a region at a lower part of the epitaxial region and that has an impurity concentration higher than that of the epitaxial region; a trench formed at boundaries between the first well region and the epitaxial region, and between the first well region and the buried region; a first semiconductor element that is formed on the first well; and a second semiconductor element that is formed on the epitaxial region. | 2012-01-12 |
20120007170 | High source to drain breakdown voltage vertical field effect transistors - An increase source to drain breakdown voltage vertical channel transistors device having a structure that is similar to that of a conventional metal oxide semiconductor field effect transistor (MOSFET), in that it includes a source, a drain, a gate and a body. According the N+N− and P+P− junction theory of semiconductor, add to N− junction between the source N+ junction to P junction of N-Channel MOSFET; add to P− junction between the source P+ junction to n junction of P-Channel MOSFET; With the proposed MOSFET of which the source to drain breakdown voltage are increase may be achieved. | 2012-01-12 |
20120007171 | SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL TRANSISTOR AND BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device includes an active region protruding upward from a substrate, wherein the active region is arranged next to a trench on the substrate, a first impurity region formed at an upper portion of the active region, a second impurity region formed at a lower portion of the active region, a gate dielectric layer formed along a side of the active region between the first impurity region and the second impurity region, a gate electrode layer formed on the gate dielectric layer, a buried bit line formed at a lower portion of the trench, and a polysilicon layer formed over the buried bit line, wherein the polysilicon layer electrically connects the buried bit line with the second impurity region. | 2012-01-12 |
20120007172 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an active region formed to be sloped or tilted by α° (where 0°<α°<90°) from the bottom of a semiconductor substrate, at least one gate that is formed over the sloped active region and has a surface parallel to the bottom of the semiconductor substrate, and a landing plug that is coupled to the active region and is located between the gates. As a result, the area of the active region is increased thus increasing a channel width, so that the operation of the semiconductor device can be improved as the integration degree of the semiconductor device is rapidly increased. | 2012-01-12 |
20120007173 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes: a substrate; multiple first and second conductive type regions on the substrate for providing a super junction structure; a channel layer on the super junction structure; a first conductive type layer in the channel layer; a contact second conductive type region in the channel layer; a gate electrode on the channel layer via a gate insulation film; a surface electrode on the channel layer; a backside electrode on the substrate opposite to the super junction structure; and an embedded second conductive type region. The embedded second conductive type region is disposed in a corresponding second conductive type region, protrudes into the channel layer, and contacts the contact second conductive type region. The embedded second conductive type region has an impurity concentration higher than the channel layer, and has a maximum impurity concentration at a position in the corresponding second conductive type region. | 2012-01-12 |
20120007174 | Semiconductor device and method of manufacturing the same - The semiconductor device includes a trench having a depth of a distance equal to or shorter than the L length of the transistor, and a buried layer is used in a bottom portion of the trench, whereby an effective channel length from each of a lower end of a high concentration source diffusion layer and a lower end of a high concentration drain diffusion layer to a bottom surface of the trench is made shorter than the shortest length L on a top surface of the trench. Accordingly, a current path is held on the bottom surface of the trench from a side surface thereof which contacts with the source or high concentration drain diffusion layer with a use of the buried layer, whereby the driving performance is enhanced. An effect of suppressing the decrease of the driving performance is obtained for the reduced gate length. | 2012-01-12 |
20120007175 | Metal Oxide Semiconductor (MOS) Transistors Having a Recessed Gate Electrode - A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region. | 2012-01-12 |
20120007176 | High-Voltage Bipolar Transistor with Trench Field Plate - A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate. | 2012-01-12 |
20120007177 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate including a cell area and a peripheral circuit area, a first trench for device isolation formed in the cell area of the semiconductor substrate and a second trench for device isolation formed within the semiconductor substrate of the peripheral circuit area to be deeper than the first trench, a device isolation layer buried within the first and second trenches for device isolation and having the same surface level as the semiconductor substrate in the cell area, a buried gate buried in the semiconductor substrate of the cell area, and a peripheral circuit gate which is in contact with the semiconductor substrate of the peripheral circuit area, is buried within the device isolation layer of the peripheral circuit area, and has the same surface level as the buried gate. It can prevent the same effect from affecting the cell area and the peripheral circuit area so that the number of masks is reduced and the process is simplified so that cost can be reduced and characteristics of the semiconductor device can be improved. | 2012-01-12 |
20120007178 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device having trench gates in element regions R | 2012-01-12 |
20120007179 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A high voltage/power semiconductor device using a low voltage logic well is provided. The semiconductor device includes a substrate, a first well region formed by being doped in a first location on a surface of the substrate, a second well region formed by being doped with impurity different from the first well region's in a second location on a surface of the substrate, an overlapping region between the first well region and the second well region where the first well region and the second well region substantially coexist, a gate insulating layer formed on the surface of the first and the second well regions and the surface of the overlapping region, a gate electrode formed on the gate insulating layer, a source region formed on an upper portion of the first well region, and a drain region formed on an upper portion of the second well region. The semiconductor device may also include a separating unit, which is formed in the second well region on the drain side and may be formed as a shallow trench isolation (STI) region having a lower depth than the second well region. | 2012-01-12 |
20120007180 | FinFET with novel body contact for multiple Vt applications - FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications. | 2012-01-12 |
20120007181 | Schottky FET Fabricated With Gate Last Process - A method for forming a field effect transistor (FET) includes forming a dummy gate on a top semiconductor layer of a semiconductor on insulator substrate; forming source and drain regions in the top semiconductor layer, wherein the source and drain regions are located in the top semiconductor layer on either side of the dummy gate; forming a supporting material over the source and drain regions adjacent to the dummy gate; removing the dummy gate to form a gate opening, wherein a channel region of the top semiconductor layer is exposed through the gate opening; thinning the channel region of the top semiconductor layer through the gate opening; and forming gate spacers and a gate in the gate opening over the thinned channel region. | 2012-01-12 |
20120007182 | CHARGING PROTECTION DEVICE - Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P | 2012-01-12 |
20120007183 | Multi-gate Transistor Having Sidewall Contacts - A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer. | 2012-01-12 |
20120007184 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased. | 2012-01-12 |
20120007185 | Novel method to tune narrow width effect with raised S/D structure - A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width. | 2012-01-12 |
20120007186 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first gate electrode buried within a semiconductor substrate, a second gate electrode buried within a silicon growth layer disposed on the semiconductor substrate, and a bit line disposed on an interlayer insulating layer disposed on the semiconductor substrate between the first gate electrode and a second gate electrode. Therefore, the number of gates disposed in an active region is increased so that a total memory capacity of the semiconductor device, thereby reducing fabrication cost and improving productivity. | 2012-01-12 |
20120007187 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING GATE AND METAL LINE THEREOF - A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction. | 2012-01-12 |
20120007188 | INTEGRATED CIRCUIT DEVICE WITH STRESS REDUCTION LAYER - An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a stress reduction layer that extends between the tensile stress layer and the NMOS gate film stack, and a reduced-stress dual stress liner PMOS device having a stress reduction layer that extends between the compressive stress layer and the PMOS gate film stack. In embodiments of the invention additional reduced-stress dual stress liner NMOS devices and reduced-stress PMOS devices are formed by altering the thickness and/or the material properties of the stress reduction layer. | 2012-01-12 |
20120007189 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. | 2012-01-12 |
20120007190 | STRESS-INDUCED CMOS DEVICE - A semiconductor device including: a silicon dioxide layer; an n-type field effect transistor (NFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a p-type field effect transistor (PFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a nitride stress liner over the NFET and the PFET, the nitride stress liner filling the at least one recessed source/drain trench of the NFET and the at least one recessed source/drain trench of the PFET; and a first contact formed in the silicon dioxide layer, the first contact abutting one of the NFET or the PFET. | 2012-01-12 |
20120007191 | BIPOLAR DEVICE COMPATIBLE WITH CMOS PROCESS TECHNOLOGY - The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An extrinsic base is formed on the substrate with a predetermined distance from either the emitter or the collector, wherein the base, the emitter, the collector and the gate terminal are located in an active area defined by a hole in a surrounding isolation structure in the substrate. | 2012-01-12 |
20120007192 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a plurality of memory cell blocks, a plurality of first wirings, a plurality of second wirings, and a contact. Each of the memory cell blocks includes a plurality of memory cell units. Each of the plurality of memory cell units includes a plurality of memory cells and is provided in a first direction at a prescribed spacing. The plurality of memory cell blocks is arranged in a second direction intersecting with the first direction. The plurality of first wirings extends in the second direction and is provided in the first direction at a prescribed spacing. The plurality of second wirings is provided at least one of above and below the first wiring. The contact is provided at both end portions of the second wiring in the second direction and connects the first wiring to the second wiring. A width dimension of the second wiring along the first direction is larger than a width dimension of the first wiring along the first direction. | 2012-01-12 |
20120007193 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the device isolation layer and the transistors, and a guard region disposed between adjacent transistors. | 2012-01-12 |
20120007194 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME IN WHICH VARIATIONS ARE REDUCED AND CHARACTERISTICS ARE IMPROVED - A method of manufacturing N-type MOSFET includes: implanting a p-type dopant into in a surface layer of a semiconductor substrate to form a channel region; forming a gate insulating film including High-k material and a gate electrode on said channel region; implanting a p-type dopant into both ends of said channel region in an inner portion of said semiconductor substrate to form halo regions; implanting a p-type dopant into both ends of said channel region in a surface layer of said semiconductor substrate to form extension regions. One of said step of forming said channel region and said step of forming halo regions includes: implanting C into one of said channel region and said halo regions. An inclusion amount of said High-k material is an amount that increase of a threshold voltage caused by said High-k material being included in said gate insulating film compensates for decrease of said threshold voltage caused by said C being implanted. | 2012-01-12 |
20120007195 | APPARATUS FOR INTEGRATED CIRCUIT PACKAGING - Apparatuses are disclosed, such as those involving integrated circuit packaging. In one embodiment, a chip package includes: an encapsulation having a top surface and a bottom surface facing away from the top surface. The package further includes a leadframe including a plurality of leads. Each of the leads includes an exposed portion exposed through one of edges of the bottom surface of the encapsulation. The exposed portion has a length. At least one of exposed portions positioned along one of the edges of the bottom surface of the encapsulation has a length different from other exposed portions along the edge. The package can also include a dummy pad exposed through a corner of the bottom surface. The configuration can enhance solder joint reliability of the package when the package is attached to a printed circuit board. | 2012-01-12 |
20120007196 | MAGNETORESISTIVE RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetoresistive random access memory includes a magnetoresistive element in a memory cell, the magnetoresistive element including a first metal magnetic layer, a second metal magnetic layer, and an insulation layer interposed between the first and second metal magnetic layers. An area of each of the first and second metal magnetic layers is smaller than an area of the insulation layer. | 2012-01-12 |