02nd week of 2014 patent applcation highlights part 37 |
Patent application number | Title | Published |
20140013106 | ISSUING, PRESENTING AND CHALLENGING MOBILE DEVICE IDENTIFICATION DOCUMENTS - Methods and systems of authenticating electronic identification (ID) documents may provide for receiving a decryption key and an encrypted ID document from a certificate authority server at a mobile device, wherein the encrypted ID document includes a read only document having a photograph of an individual. Additionally, the decryption key may be applied to the encrypted ID document to obtain a decryption result in response to a display request. The decryption result can be output via a display of the mobile device, wherein the encrypted ID document can be sent to a challenge terminal if a challenge request is received. | 2014-01-09 |
20140013107 | Mobile-Device-Based Trust Computing - In one embodiment, a method includes receiving access data from an application on a mobile device of a particular user. The access data includes authentication data associated with a shared device and a digital credential associated with the mobile device. The shared device is configured for use by at least a number users. The method also includes authenticating the access data based on a comparison of the access data with verification data stored by the verification authority; and transmitting to the shared device a digital certificate signed by the verification authority in response to the authentication. The signed digital certificate provides the particular user access to the shared device. | 2014-01-09 |
20140013108 | On-Demand Identity Attribute Verification and Certification For Services - An apparatus is caused to store identification data of a plurality of clients in memory; cause reception of information indicating at least one identifier of a device corresponding to a client requesting access to a service; verify the identity of the client device on the basis of the received identifier; detect whether or not the identified device is authorized to communicate with the apparatus on the basis of first predetermined criteria; upon detecting that the device is authorized, cause reception of in-formation indicating at least one identifier of the client from the identified device; verify the at least one identifier of the client on the basis of the received identifier and the stored identification data; and determine, on demand, whether to issue a certificate indicating the verifications on the basis of second predetermined criteria in order to enable the client to apply the certificate in accessing the service. | 2014-01-09 |
20140013109 | SECURE DELIVERY OF TRUST CREDENTIALS - A system is configured to receive, by one or more servers, a request for a certificate from a user device. The request may include a first parameter , a second parameter , and a third parameter. The system is further configured to identify a key based on the first parameter, generate a fourth parameter based on the key and the third parameter, authenticate the user device based on the fourth parameter and the second parameter, generate the certificate based on authenticating the user device, store information associated with the certificate, and send the certificate to the user device. The user device may use the certificate to establish a session to interact with an application server. | 2014-01-09 |
20140013110 | NON-HIERARCHICAL INFRASTRUCTURE FOR MANAGING TWIN-SECURITY KEYS OF PHYSICAL PERSONS OR OF ELEMENTS (IGCP/PKI) - A non-hierarchical infrastructure for managing twin-security keys of physical persons or of elements includes a public key and a private key with a public key certificate. The structure does not include any certification authority distinct from the physical persons or elements, but does include at least one registering authority and its electronic notary server. There is provided at least one registering authority and its electronic notary server for a circle of trust. The registering authority includes local registering agencies. The local registering agency establishes, after face-to-face verification of the identity of the physical person or of the identification of the element, a public key certificate, and a “public key ownership certificate”, which does not contain the public key of the person or of the element but the print thereof, and which is transmitted in a secure manner to the associated electronic notary server for storing in a secure manner. | 2014-01-09 |
20140013111 | Systems and Methods for Controlling Electronic Document Use - One exemplary embodiment involves receiving a request for a document key for accessing a document on a client device. The request comprises a user identity identifying a requester requesting access to the document. The request also comprises information about the document. The exemplary embodiment further involves determining, at the server, whether access to the document by the requester is permitted. And, the exemplary embodiment further involves, if access to the document is permitted computing, at the server, the document key using the user identity and using the information about the document. The document key is document specific and, prior to the computing of the document key, the document key is not stored for access by the server. The exemplary embodiment further involves responding to the request by providing the document key for use in accessing the document on the client device. | 2014-01-09 |
20140013112 | ENCRYPTING FILES WITHIN A CLOUD COMPUTING ENVIRONMENT - A system, computer readable medium and a method for encrypting a file, the method may include retrieving the file from a storage service; segmenting the file into multiple file segments; calculating a file segment signature for each of the multiple file segments to provide multiple file segment signatures; encrypting each of the multiple file segments to provide multiple encrypted file segments by using encryption keys that are in response to the multiple file segment signatures; wherein the multiple encrypted file segments form an encrypted file; and sending the multiple encrypted file segments to the storage service. | 2014-01-09 |
20140013113 | SECURE NON-INVASIVE METHOD AND SYSTEM FOR DISTRIBUTION OF DIGITAL ASSETS - A client computer system receives a file that is at least partially encrypted. The client computer also receives a file manager and user input. In response to the user input matching data stored in an encrypted user profile, the client computer uses the file manager to decrypt the file based on a key stored in the encrypted user profile. The file is unusable if copied to another client computer, and the file manager manages usage of the file based on one or more terms of usage. | 2014-01-09 |
20140013114 | ISSUING, PRESENTING AND CHALLENGING MOBILE DEVICE IDENTIFICATION DOCUMENTS - Methods and systems of authenticating electronic identification (ID) documents may provide for receiving a decryption key and an encrypted ID document from a certificate authority server at a mobile device, wherein the encrypted ID document includes a read only document having a photograph of an individual. Additionally, the decryption key may be applied to the encrypted ID document to obtain a decryption result in response to a display request. The decryption result can be output via a display of the mobile device, wherein the encrypted ID document can be sent to a challenge terminal if a challenge request is received. | 2014-01-09 |
20140013115 | CONTENT ENCRYPTION - An audio/video content delivery system includes a content source linked by an internet data connection to a content receiver, the content receiver configured to receive access-controlled encoded broadcast content from a content source by a separate broadcast data path. The content source includes an encryptor sending encrypted content to the content receiver according to a content encryption key. The content receiver includes: a host module including a decryptor decrypting encrypted content received from the content source; and a removable conditional access module (CAM) including an access control unit decoding the access-controlled encoded broadcast content, the host module and removable CAM configured to provide an encrypted communication link therebetween for decoded access-controlled encoded broadcast content. The content source and the CAM are configured to communicate to establish the key required by the decryptor in the host module to decrypt the encrypted content received from the content source. | 2014-01-09 |
20140013116 | APPARATUS AND METHOD FOR PERFORMING OVER-THE-AIR IDENTITY PROVISIONING - A method for controlling access to information includes sending a request from an identity requester to an identity provider through an over-the-air (OTA) link. Data received from the identity provider in response to the request includes information used to establish a first identity of a user for a first service. The first identity information is received during a Sigma session, and a second identity of the user is established for a second service based on the received first identity information. The user may be a user of a mobile communication terminal or other device, which is to receive the first and second services. | 2014-01-09 |
20140013117 | AUTHENTICATION METHOD OF WIRELESS MESH NETWORK - Disclosed is an authentication method of a wireless mesh network capable of reducing overload and communication delay during authentication procedure by performing authentication between nodes without accessing an authentication server. The authentication method of a wireless mesh network according to an exemplary embodiment of the present disclosure includes: selecting, by a new node, a first neighbor node among one or more adjacent nodes; transmitting, by the new node, an authentication request message including a public key of the new node; authenticating, by the first neighbor node, the public key of the new node; transmitting, by the first neighbor node, an authentication response message including a public key of the first neighbor node to the new node; and authenticating, by the new node, the public key of the first neighbor node; transmitting, by the new node, an authentication identification message to the first neighbor node. | 2014-01-09 |
20140013118 | INFORMATION PROCESSING APPARATUS, TERMINAL DEVICE, INFORMATION PROCESSING SYSTEM, METHOD FOR INFORMATION PROCESSING, AND STORAGE MEDIUM - There is provided an information processing apparatus, including a data generation section generating a specified data stream, and also generating a plurality of segment data sets by segmenting the generated specified data stream and by adding authentication data to each of the segmented data streams, and a data transmission section transmitting the plurality of segment data sets generated by the data generation section to respective apparatuses. | 2014-01-09 |
20140013119 | DOCUMENT MODIFICATION DETECTION AND PREVENTION - Methods and apparatus, including computer program products, implementing and using techniques for document authentication. An electronic document is presented to a user. The electronic document has data representing a signed state and a current state. A disallowed difference between the signed state and the current state is detected, based on one or more rules that are associated with the electronic document. A digital signature associated with the electronic document is invalidated in response to the detecting. | 2014-01-09 |
20140013120 | Method, Device and System for Protecting Multimedia Data of Multimedia Message - The present disclosure provides a method, device and system for protecting multimedia data of a multimedia message. By performing digital watermark encryption of the multimedia data in the multimedia message at a sender of the multimedia message and performing digital watermark decryption of the multimedia data in the multimedia message at a receiver of the multimedia message, the encryption protection over the multimedia data in the multimedia message is strengthened, thus implementing the protection over an intellectual property of a user of a terminal, and improving the level and capacity of protection over the intellectual property of the user. | 2014-01-09 |
20140013121 | METHOD AND DEVICE FOR STORING SECURED SENT MESSAGE DATA - Methods and devices for storing sent message data are described. The sent message data corresponds to a message sent to a destination by a communication device via a server. The method includes compiling a first portion of the message which has a plurality of components; applying security encoding to the first portion; and storing the first portion. The first portion includes at least one but not all of the plurality of components in the message, and pointers to the components not included in the first portion. A method of verifying sent message data on a communication device is also described. | 2014-01-09 |
20140013122 | CIPHER TEXT TRANSLATION - A computer system includes memory configured to store information regarding predetermined conditions of an encryption operation and a processor configured to analyze an inbound key and an outbound key of the encryption operation. The processor is also configured to determine that the encryption operation includes a translation from a first class of encryption to a second class of encryption based on the analyzing the inbound key and the outbound key, and to determine whether the translation is permitted based on the predetermined conditions. | 2014-01-09 |
20140013123 | DATA SECURITY USING INTER-ZONE GATE CIRCUITS - A circuit for secure operation includes a plurality of mutually exclusive circuit zones including a first circuit zone having a first level of security and a second circuit zone having a second level of security less than the first level of security and one or more gate circuits each providing limited transfer of data between the circuit zones, the gate circuits providing all data connectivity between the first circuit zone and the second circuit zone and statically configured to prevent unmodified transfer of data from the first circuit zone to the second circuit zone. | 2014-01-09 |
20140013124 | ON-CHIP STORAGE, CREATION, AND MANIPULATION OF AN ENCRYPTION KEY - A system and method for encrypting data provides for retrievial of an encryption key; identification of the address in memory of a first portion of the data to be encrypted; derivation of a first unique key from the encryption key and the address of the first portion of data; encryption of the first portion of data using the first unique key; identification of the address in memory of a second portion of data to be encrypted; derivation of a second unique key from the encryption key and the address of the second portion of data; and encryption of the second portion of data using the second unique key. | 2014-01-09 |
20140013125 | GEOSPATIAL OPTIMIZATION FOR RESILIENT POWER MANAGEMENT EQUIPMENT - Methods and apparatus are provided for geospatial optimization for resilient power management equipment. A method includes predicting a power outage duration based on at least one of geographical data, location data, and historical data. The method further includes rendering a power management decision based on the predicted power outage duration and a remaining backup power duration. | 2014-01-09 |
20140013126 | BRANCH CIRCUIT DETERMINATION WITHOUT EXTERNAL SYNCHRONIZATION - A method, system, and computer program product for relating a data processing system with a power branch circuit are provided in the illustrative embodiments. Each signal in a set of signals is combined with a power signal to form a set of combination signals, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal. An amplitude of a corresponding signal in each combined signal in the set of combined signals is determined over a period. Using a discriminating logic, a determination is made whether the modulating signal is present in the power signal. Responsive to the discriminating logic producing an affirmative result, the data processing system is related with the power branch circuit. | 2014-01-09 |
20140013127 | ADAPTIVE CONTROL OF OPERATING AND BODY BIAS VOLTAGES - Adaptive control of operating and body bias voltages. In accordance with a first embodiment of the present invention, a desirable operating frequency for the microprocessor is determined. Information stored within and specific to the microprocessor is accessed. The information can comprise coefficients of a quadratic approximation of a frequency-voltage characteristic of the microprocessor for a set of body biasing conditions. An efficient voltage for operating the microprocessor at the desirable operating frequency is computed. The microprocessor is operated at the efficient voltage and the set of body biasing conditions. | 2014-01-09 |
20140013128 | Portable Power Bank Device with Projecting Function - A portable power bank device with a projecting function comprises a battery unit, a control unit, and a micro projector unit. The battery unit is electrically coupled to a charge unit and restores power from an external power source. The control unit is electrically coupled to the charge unit and a connection interface unit, respectively. The control unit comprises a charge module, a voltage conversion module, and a video codec. A battery power source of the battery unit is outputted through the voltage conversion module. The micro projector unit is electrically coupled to the control unit and projects and displays video signals of the video codec. | 2014-01-09 |
20140013129 | HYBRID COMPUTING MODULE - A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby allowing the efficient transfer of data between off-chip physical memory and processor die | 2014-01-09 |
20140013130 | EXPANSION CIRCUIT FOR SERVER SYSTEM AND SERVER SYSTEM USING SAME - An expansion circuit for a server system includes a power input terminal, a first output terminal and a second output terminal. The power input terminal is configured to receive a first voltage. The first output terminal is configured to receive the first voltage from the power input terminal and provide the first voltage to a first hard disk drive group of the server system. The second output terminal is configured to receive the first voltage from the power input terminal and provide the first voltage to a second hard disk drive group of the server system when the first hard disk drive group and the second hard disk drive group are controlled by a same server. | 2014-01-09 |
20140013131 | POWER NAPPING TECHNIQUE FOR ACCELERATED NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI) AND/OR POSITIVE BIAS TEMPERATURE INSTABILITY (PBTI) RECOVERY - A logic circuit is operated in a normal mode, with a supply voltage coupled to a supply rail of the logic circuit, and with a ground rail of the logic circuit grounded; It is determined that at least a portion of the logic circuit has experienced degradation due to bias temperature instability. Responsive to the determining, the logic circuit is operated in a power napping mode, with the supply voltage coupled to the ground rail of the circuit, with the supply rail of the circuit grounded, and with primary inputs of the circuit toggled between logical zero and logical one at low frequency. A logic circuit and corresponding design structures are also provided. | 2014-01-09 |
20140013132 | HYBRID COMPUTING MODULE - A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby allowing the efficient transfer of data between off-chip physical memory and processor die. | 2014-01-09 |
20140013133 | SEMICONDUCTOR INTEGRATED CIRCUIT - A power consumption of a semiconductor integrated circuit is reduced. A semiconductor integrated circuit comprises a first path P1 for performing data processing in a data processing circuit and a second path P2 for bypassing the data processing circuit or for performing data processing in a simplified circuit. The semiconductor integrated circuit exclusively selects the first path and the second path depending on an operational mode, and stops a data input into a path that is not selected, resulting in a reduction of the power consumption. | 2014-01-09 |
20140013134 | ADAPTIVE POWER CONSERVATION IN STORAGE CLUSTERS - Each node and volume in a storage cluster makes a decision whether to reduce power consumption based on lack of requests from client applications and nodes over a time period. Node configuration parameters determine how long to wait until idling a node or volume, and how long to wait while idle before performing integrity checks. A bid value is calculated by each node and reflects how much it will cost for that node to write a file, read a file, or keep a copy. A node with the lowest bid wins, and nodes that are idle have a premium added to each bid to ensure that idle nodes are kept idle. In an archive mode, writes bids are reversed, nodes with less capacity submit lower bids, fuller nodes fill up faster and are then idled, while empty or near empty nodes may remain idle before winning a write bid. | 2014-01-09 |
20140013135 | SYSTEM AND METHOD OF CONTROLLING A POWER SUPPLY - A system having a low power operation mode and a normal operation mode, the system including a power supply unit for supplying at least a first voltage and a second voltage; a first circuit which operates during the normal operation mode but does not operate during the low power operation mode; a second circuit which operates during the low power operation mode; and a switching unit for selectively supplying the first circuit with the first voltage or the second voltage from the power supply unit; wherein the power supply unit supplies a power status signal and the switching unit is controlled based on the power status signal. | 2014-01-09 |
20140013136 | POWER EFFICIENT LOCATION NOTIFICATION - Before a device enters a power saving mode, a location-aware application in the device may provide at least one wake trigger (and a trigger limit) to a low power monitoring module (LPMM). In power saving mode, the LPMM receives device locations from a location service module and may determine when the device location corresponds to the at least one wake trigger or trigger limit. In one embodiment, device location may only be provided to the LPMM based on a condition (e.g., timer expiration or reaching a displacement threshold as measured by sensors in the device). When device location corresponds to the trigger limit, the LPMM may notify the device (e.g., cause a transition to an active power mode) so that the location-aware application can redetermine the at least one wake trigger. The device location corresponding to the at least wake trigger may also cause the LPMM to notify the device. | 2014-01-09 |
20140013137 | SYSTEMS AND METHODS FOR SUSPENDING IDLE DEVICES - A method for suspending an idle device includes receiving, by a processor, an indication that a device having a communication channel is connected to a host device. The method then includes determining a first timeout value associated with the communication channel and a second timeout value associated with the first device. The first timeout value corresponds to an amount of time allotted for an operation to complete in the communication channel, and the second timeout value corresponds to an amount of time allotted for the device to be designated as idle before the device is suspended. The device is determined to be idle when the operation is pending in the communication channel for an amount of time that is greater than the first timeout value. The device is suspended when the device has been idle for an amount of time that is greater than the second timeout value. | 2014-01-09 |
20140013138 | MEMORY CONTROL DEVICE, SEMICONDUCTOR DEVICE, AND SYSTEM BOARD - According to an embodiment, a memory control device controls a memory from/to which data are read/written by a processor. The memory control device includes a clock switcher and a control signal switcher. The clock receives as input a first clock and a second clock at a higher frequency than the first clock, supplies the first clock to the memory until the second clock becomes stable, and supplies the second clock after the second clock has become stable. The a control signal switcher starts supplying, to the memory, a first control signal for initializing the memory to a state allowing reading/writing of data by the processor while the first clock is being supplied to the memory, and supplies, to the memory, a second control signal according to the reading/writing of data by the processor, after the second clock is supplied to the memory and the memory is initialized. | 2014-01-09 |
20140013139 | IMAGE PROCESSING APPARATUS, METHOD FOR CONTROLLING THE SAME AND STORAGE MEDIUM - An image processing apparatus of one aspect of the present invention determines, upon receipt of a packet in a power saving state at a second communication rate slower than a first communication rate, whether or not to change the communication rate, on the basis of a communication protocol type and a port number, and an attribute of the packet represented by a data section of the packet. If the communication protocol type, the port number, and the attribute of the received packet indicate a request for a service predetermined as a network service that corresponds to the first communication rate, the image processing apparatus changes the communication rate from the second communication rate to the first communication rate at the time of shifting from the power saving state to the normal power state so as to provide the service. | 2014-01-09 |
20140013140 | INFORMATION PROCESSING APPARATUS AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an information processing apparatus includes a processor, a first memory, and a power supply controller. The processor is configured to execute a program. The first memory is configured to store therein the program. The power supply controller is configured to stop supplying a power to the first memory when the processor transitions to an idle state where the processor waits for an interrupt, and start supplying the power to the first memory when the processor receives the interrupt in the idle state. When the processor receives the interrupt in the idle state, the processor executes initialization of the first memory to set the first memory into a state where the first memory is accessible from the processor. | 2014-01-09 |
20140013141 | METHOD AND APPARATUS FOR CONTROLLING SLEEP MODE IN PORTABLE TERMINAL - A method and an apparatus for controlling a sleep mode in a portable terminal having a main controller and a sub-controller operating at low power are provided. The method includes detecting, by the sub-controller, a first sensor signal generated by a first sensor when the main controller is in the sleep mode, extracting a sensed pattern from the detected first sensor signal, determining whether the extracted sensed pattern is substantially identical with a preset wake-up pattern, and cancelling the sleep mode by waking-up the main controller when the extracted sensed pattern is substantially identical with the wake-up pattern. | 2014-01-09 |
20140013142 | PROCESSING UNIT POWER MANAGEMENT - Methods, apparatus and computer program products for power management of a processing unit. The processing unit can operate in a plurality of operating modes and provides information indicative of memory access miss events. Information indicative of memory access miss events is received, and based at least on the received information, a desired operating mode for the processing unit is determined. The processing unit is then caused to operate in of the desired operating mode based on the determining. | 2014-01-09 |
20140013143 | APPARATUS AND METHOD FOR PERFORMING USER AUTHENTICATION IN TERMINAL - A user authentication apparatus and method for allowing a user to conveniently perform user authentication by a touch and motion-based gesture in a terminal are provided. In the user authentication apparatus, a low-power sensor platform is configured to transfer a wake-up signal to a controller upon detecting a motion of the terminal for waking up while the terminal is in a sleep mode, and to transfer a motion signal generated while the terminal is in a wake-up mode to the controller. The controller is configured to switch the terminal to the wake-up mode in response to the wake-up signal that is received from the low-power sensor platform while the terminal is in the sleep mode, and to switch to a user-authenticated specific application mode upon receiving the motion signal from the low-power sensor platform during a touch occurring in a specific area while the terminal is in the wake-up mode. | 2014-01-09 |
20140013144 | COMMUNICATION CONTROL APPARATUS, COMMUNICATION CONTROL METHOD, AND COMMUNICATION CONTROL CIRCUIT - A communication control apparatus includes a transmitting unit, a monitoring unit, a determining unit, and a control unit. The transmitting unit transmits data to other communication control apparatuses. The monitoring unit monitors an amount of data to be transmitted by the transmitting unit. The determining unit determines whether to shift a state of the transmitting unit to a power-saving state according to the amount of data monitored by the monitoring unit, the power-saving state being a state in which power consumption is lower than power consumption in a normal state. The control unit causes the transmitting unit to enter the power-saving state when the determining unit determines that the state of the transmitting unit is to be shifted to the power-saving state. | 2014-01-09 |
20140013145 | DEBUG ARCHITECTURE - Roughly described, a method of powering down a portion of an integrated circuit chip, the portion of the integrated circuit chip comprising a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, the method comprising: prior to power down, extracting from each debug unit configuration information of that debug unit; storing the configuration information of the debug units in a memory on the integrated circuit chip during power down of the portion of the integrated circuit chip; and on power up, restoring the configuration information of each debug unit to that debug unit prior resuming operation of that debug unit and the peripheral circuit connected to that debug unit. | 2014-01-09 |
20140013146 | Packetized Power - Methods, systems, and devices are disclosed for producing and delivering packetized power within a DC computing environment. Within the DC computing environment a power requirement or request is communicated to a power router. The power router then determines a power source capable of fulfilling the power requirement and then causes the power to be delivered in packetized form. The packetized power is appended to a message header which allows the power packet to be received by the requesting device. | 2014-01-09 |
20140013147 | Apparatus and Method for Providing Network Communications - A system that incorporates teachings of the present disclosure may include, for example, a Power Over Ethernet (PoE) device (PD) having a controller to receive signals over a first cable having twisted pair wires from at least one of a network element and a gateway where the network element is associated with a service provider where the gateway is associated with a premises and where the service provider provides network communications to the premises, adjust the signals, transmit the adjusted signals over a second cable having twisted pair wires to at least one of the network element and the gateway, and receive power from at least one of the network element and the gateway, where the power is received over at least one of the first and second cables, where the power is received according to PoE protocol, and where the PD is positioned between the network element and the gateway. Other embodiments are disclosed. | 2014-01-09 |
20140013148 | BARRIER SYNCHRONIZATION METHOD, BARRIER SYNCHRONIZATION APPARATUS AND ARITHMETIC PROCESSING UNIT - A plurality of barrier blades, a barrier blade identification information storage unit, and a barrier blade identification information selection unit are provided. The plurality of barrier blades synchronize, using a synchronization address set for a plurality of arithmetic processing units, the plurality of arithmetic processing units. The barrier blade identification information storage unit holds barrier blade identification information to identify the barrier blade corresponding to synchronization address identification information to identify the synchronization address, for each of the plurality of arithmetic processing units. When synchronization address identification information is input, the barrier blade identification information selection unit selects and outputs barrier blade identification information corresponding to the input synchronization address identification information, among barrier blade identification information held by the barrier blade identification information storage unit. | 2014-01-09 |
20140013149 | Dynamically Calibrated DDR Memory Controller - A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a sequence of read commands so that a delayed version of a dqs signal toggles continuously. The method delays a core clock signal to sample the delayed dqs signal at different delay increments until a 1 to 0 transition is detected on the delayed dqs signal. This core clock delay is recorded as “A.” The method delays the core clock signal to sample the core clock signal at different delay increments until a 0 to 1 transition is detected on the core clock signal. This core clock delay is recorded as “B.” The optimum delay value is computed from the A and B delay values. | 2014-01-09 |
20140013150 | Monitoring Circuit with a Window Watchdog - A method of monitoring a processing circuit is disclosed. The processing circuit is operable, in a normal operation mode, to generate a sequence of trigger commands, with at least one trigger command of the sequence of trigger commands including time information. At least one window sequence with a closed window period and an open window period is generated such that the duration of the closed window period and/or the open window period is defined, at least in part, by the time information. It is detected if one trigger command is received within the open window period of the at least one sequence. | 2014-01-09 |
20140013151 | I2C MULTIPLEXER SWITCHING AS A FUNCTION OF CLOCK FREQUENCY - In accordance with one embodiment of the invention, an I2C bus multiplexing circuit for use in an I2C bus interface can be provided. The I2C bus multiplexing circuit can facilitate multiplexer switching in an I2C bus interface by detecting a start command from an I2C master device via an I2C bus, buffering data from the I2C master device, detecting a clock frequency of a bus serial clock (SCL) line of the I2C master device, holding the serial data (SDA) line of the I2C master device in a clock stretch state and selecting a port based on the detected clock frequency of the SCL of the I2C master device. The method further can include sending the buffered data to an I2C slave device on the selected port. The method further can include receiving an acknowledgement from the I2C slave device on the selected port. | 2014-01-09 |
20140013152 | SYSTEM FOR INJECTING PROTOCOL SPECIFIC ERRORS DURING THE CERTIFICATION OF COMPONENTS IN A STORAGE AREA NETWORK - An apparatus comprising an initiator circuit and a target circuit. The initiator circuit may be configured to (i) communicate with a network through a first interface and (ii) generate testing sequences to be sent to the network. The target circuit may be configured to (i) receive the testing sequences from the network through a second network interface and (ii) respond to the testing sequences. | 2014-01-09 |
20140013153 | MANAGING USE OF LEASE RESOURCES ALLOCATED ON FALLOVER IN A HIGH AVAILABILITY COMPUTING ENVIRONMENT - Responsive to a cluster manager for a particular node from among multiple nodes allocating at least one leased resource for a resource group for an application workload on the particular node, on fallover of the resource group from another node to the particular node, setting a timer thread, by the cluster manager for the particular node, to track an amount of time remaining for an initial lease period of the at least one leased resource. Responsive to the timer thread expiring while the resource group is holding the at least one leased resource, maintaining, by the cluster manager for the particular node, the resource group comprising the at least one leased resource for an additional lease period and automatically incurring an additional fee, only if the particular node has the capacity to handle the resource group at a lowest cost from among the nodes. | 2014-01-09 |
20140013154 | Method and system for processing email during an unplanned outage - The method and system of the present invention provides an improved technique for processing email during an unplanned outage. Email messages are redirected from the primary server to a secondary server during an unplanned outage such as, for example, a natural disaster. A notification message is sent to users alerting them that their email messages are available on the secondary server by, for example, Internet access. After the termination of the unplanned outage, email messages received during the unplanned outage are synchronized into the users standard email application. | 2014-01-09 |
20140013155 | System and method for facilitating recovery from a document creation error - A system and method for facilitating recovery from an error occurring during creation or alteration of a target document from a form or template. The method may involve gathering some or all input collateral (e.g., the document template, input data, instructions for creating the document) and adding it to the target document. If the target document is not created, the input collateral may be placed in an error document. The target or error document is dispatched to the user and may also be sent to support personnel (e.g., help desk, technical support personnel) or forward to such personnel by the user. Capturing the document creation conditions and parameters in the target or error document allows the support personnel (or user) to diagnose and/or recover from the error without expending the time and effort that would be required to gather the separate input collateral items, log files, configuration parameters, etc. | 2014-01-09 |
20140013156 | METHOD AND SYSTEM FOR MANAGING IMAGE FORMING APPARATUS THROUGH NETWORK - A method of managing an image forming apparatus through a network, the method including: logging in to a server through a diagnostic control unit application from a user terminal; receiving, by the user terminal, device information of an image forming apparatus from the image forming apparatus; requesting for and receiving, by the user terminal, diagnostic control unit information corresponding to the received device information from the server; performing a diagnostic control on the image forming apparatus through the diagnostic control unit application by using the received diagnostic control unit information; and uploading results of performing the diagnostic control on the server. | 2014-01-09 |
20140013157 | DEBUG ARCHITECTURE - Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit, the respective debug unit configured to generate debug information of that peripheral circuit; and a plurality of separate stores for receiving debug information, storing debug information, and outputting debug information; wherein in response to a single trigger signal, the debug units are configured to stream their generated debug information to the plurality of separate stores; and wherein each of the plurality of separate stores is configured to receive debug information at a higher stream rate than it outputs debug information. | 2014-01-09 |
20140013158 | REALTIME TEST RESULT PROMULGATION FROM NETWORK COMPONENT TEST DEVICE - The technology disclosed relates to real-time collection and flexible reporting of test data. In particular, it is useful when collecting packet counts during tests of network devices that simulate thousands or even millions of data sessions conducted through a device under test (“DUT”). | 2014-01-09 |
20140013159 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR TESTING DEVICE PARAMETERS - A system, method, and computer program product are provided for testing device parameters. In use, a plurality of device parameters is determined, utilizing a directed acyclic graph (DAG). Further, the determined plurality of device parameters is tested. | 2014-01-09 |
20140013160 | Independent Hit Testing - In one or more embodiments, a hit test thread which is separate from the main thread, e.g. the user interface thread, is utilized for hit testing on web content. Using a separate thread for hit testing can allow targets to be quickly ascertained. In cases where the appropriate response is handled by a separate thread, such as a manipulation thread that can be used for touch manipulations such as panning and pinch zooming, manipulation can occur without blocking on the main thread. This results in the response time that is consistently quick even on low-end hardware over a variety of scenarios. | 2014-01-09 |
20140013161 | DEBUG ARCHITECTURE - Roughly described, a method of sending a message from a source unit to a destination unit both forming part of a hierarchical debug architecture on a chip, the units in the hierarchy using a protocol in which each unit has an internal address which is the same base address, and in which each unit addresses other units using addresses derivable relative to that unit's internal address given positions of other units in the hierarchy, comprising: the source unit in a first level of the hierarchy sending a message comprising a destination address of the destination unit, the destination address being relative to the source unit's internal address, and an intermediate unit in a second level of the hierarchy: adding an offset to the destination address to form a rebased destination address, being relative to the intermediate unit's internal address, and routing the rebased message onto the destination unit. | 2014-01-09 |
20140013162 | INFORMATION PROCESSING APPARATUS, TRANSMITTING DEVICE AND CONTROL METHOD OF INFORMATION PROCESSING APPARATUS - A transmission device has a first input unit that inputs data, a second input unit that inputs data, a first information processing unit that outputs data resulting from information processing of data input by the first input unit or data input by the second input unit, a first holding unit that holds data output by the first information processing unit, a second holding unit that holds data output by the first information processing unit, a control information holding unit that holds control information, a first selection unit that selects, on the basis of the control information, either the data held by the first holding unit or the data held by the second holding unit, and a first output unit that returns data selected by the first selection unit to the first input unit, on the basis of the control information. | 2014-01-09 |
20140013163 | Verification module apparatus for debugging software and timing of an embedded processor design that exceeds the capacity of a single FPGA - A plurality of Field Programmable Gate Arrays (FPGA), high performance transceivers, and memory devices provide a verification module for timing and state debugging of electronic circuit designs. Signal value compression circuits and gigabit transceivers embedded in each FPGA increase the fanout of each FPGA. Ethernet communication ports enable remote software debugging of processor instructions. | 2014-01-09 |
20140013164 | FAULT-BASED SOFTWARE TESTING METHOD AND SYSTEM - A fault-based software testing method and system are provided. The fault-based software testing method includes: generating a plurality of error programs by injecting faults into a testing target program; grouping the generated error programs into a plurality of groups with respect to respective test data, and selecting representative error programs with respect to the respective groups; and when an error is detected in the execution result of the representative error programs with respect to the corresponding test data, determining that errors are detected in all the error programs of the corresponding group. | 2014-01-09 |
20140013165 | Method for System for Testing Websites - Methods and systems to test of web browser enabled applications are disclosed. In one embodiment, a browser application can allow a user to perform test and analysis processes on a candidate web browser enabled application. The test enabled browser can use special functions and facilities that are built into the test enabled browser. One implementation of the invention pertains to functional testing, and another implementation of the invention pertains to pertains to site analysis. | 2014-01-09 |
20140013166 | POWER SAVING TECHNIQUES THAT USE A LOWER BOUND ON BIT ERRORS - A read back bit sequence and charge constraint information are obtained. A lower bound on a number of bit errors associated with the read back bit sequence is determined based at least in part on the read back bit sequence and the charge constraint information. The lower bound and an error correction capability threshold associated with an error correction decoder are compared. In the event the lower bound is greater than or equal to the error correction capability threshold, an error correction decoding failure is predicted and in response to the prediction a component is configured to save power. | 2014-01-09 |
20140013167 | FAILURE DETECTING DEVICE, FAILURE DETECTING METHOD, AND COMPUTER READABLE STORAGE MEDIUM - A failure detecting device comprising a processor and a memory. The processor executes a process including storing propagation information indicating the other components to which the failure propagates, and a standby time for standing by until the failure propagates to the other components. The process includes detecting the failure of a component. The process includes acquiring, when a first failure was detected, propagation information about a detected component and a standby time about the detected component. The process includes determining notification candidates including a component in which a failure has been detected first and a component in which a new failure has been detected before the acquired standby time has elapsed. The process includes notifying, as a failed component from among the determined notification candidates a user of a component that is not included in the propagation information acquired at the acquiring after the standby time has elapsed. | 2014-01-09 |
20140013168 | DELAY-COMPENSATED ERROR INDICATION SIGNAL - A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices. | 2014-01-09 |
20140013169 | GENERIC ADDRESS SCRAMBLER FOR MEMORY CIRCUIT TEST ENGINE - A generic data scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory; a memory controller for the memory; a built-in self-test (BIST) circuit for the testing of the memory; and a generic data scrambler for scrambling of data according to a scrambling algorithm for the memory, where each algorithm is based on values of an address for data. The generic data scrambler includes a programmable lookup table to hold values for each possible outcome of the algorithm, the lookup table to generate a set of data factors, and a logic for combining the data with the data factors to generate scrambled data. | 2014-01-09 |
20140013170 | SCALABLE PREDICTION FAILURE ANALYSIS FOR MEMORY USED IN MODERN COMPUTERS - One embodiment provides a method for scalable predictive failure analysis. Embodiments of the method may include gathering memory information for memory on a user computer system having at least one processor. Further, the method includes selecting one or more memory-related parameters. Further still, the method includes calculating based on the gathering and the selecting, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information. Yet further, the method includes setting, based on the calculating, the single bit error value for the user computer system. | 2014-01-09 |
20140013171 | INTEGRATED DEFECT DETECTION AND LOCATION SYSTEMS AND METHODS IN SEMICONDUCTOR CHIP DEVICES - Embodiments relate to systems and methods for defect detection and localization in semiconductor chips. In an embodiment, a plurality of registers is arranged in a semiconductor chip. The particular number of registers can vary according to a desired level of localization, and the plurality of registers are geometrically distributed such that defect detection and localization over the entire chip area or a desired chip area, such as a central active region, is achieved in embodiments. In operation, a defect detection and localization routine can be run in parallel with other normal chip functions during a power-up or other phase. In embodiments, the registers can be multi-functional in that they can be used for other operational functions of the chip when not used for defect detection and localization, and vice-versa. Embodiments thereby provide fast, localized defect detection. | 2014-01-09 |
20140013172 | DEBUG ARCHITECTURE - Roughly described, a method of controlling transportation of debug data on an integrated circuit chip, the integrated circuit chip comprising a shared hub and a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, wherein between each respective debug unit and the shared hub there is an interface configured to transport data messages over each of a plurality of flows, the flows being assigned priorities, the method comprising: transporting control data for controlling the state of a debug unit on a priority flow having a first priority; and transporting debug data output by a debug unit as a result of debugging the peripheral circuit connected to that debug unit on a flow having a second priority, wherein the first priority is higher than the second priority. | 2014-01-09 |
20140013173 | Apparatus and Method for Clock Glitch Detection During At-Speed Testing - A method and apparatus for detecting clock glitches during at-speed testing of integrated circuits is disclosed. In one embodiment, an integrated circuit includes a scan chain having a number of scan elements coupled in a series configuration. Each of the scan elements is coupled to receive a clock signal that may be cycled during a test operation. A subset of the scan elements are arranged to form, along with other components, a counter. Test stimulus data shifted into the scan chain to perform a test may include an initial count value that is shifted into the scan elements of the counter. When the test is performed, the count value is updated responsive to cycling of the clock signal. The updated count value is shifted from the counter along with other test result data, and may be used to determine if the number of clock cycles received during the test. | 2014-01-09 |
20140013174 | IEEE 1149.1 INTERPOSER METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack. | 2014-01-09 |
20140013175 | PARALLEL AND SERIAL ACCESS TO TEST COMPRESSION ARCHITECTURES - The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure. | 2014-01-09 |
20140013176 | ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION - A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator | 2014-01-09 |
20140013177 | ON-CHIP FUNCTIONAL DEBUGGER AND A METHOD OF PROVIDING ON-CHIP FUNCTIONAL DEBUGGING - An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node. | 2014-01-09 |
20140013178 | ERROR RECOVERY WITHIN INTEGRATED CIRCUIT - An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate. | 2014-01-09 |
20140013179 | TRANSMISSION DELAY DIFFERENCE CORRECTION METHOD, COMMUNICATION DEVICE, AND COMMUNICATION SYSTEM - Two neighboring receiving units that receive a same signal notify each other of information representing that the signal has been received through the signal line, a process of correcting a transmission delay difference is performed according to a time difference between notification from the other receiving unit and its own signal reception, and selection of one of the neighboring receiving units and a receiving unit that has not performed a correction process with the one receiving unit among receiving units neighboring to the one receiving unit and a transmission delay difference correction process between the selected receiving units are sequentially performed. Thus, even when the number of processing target lanes increases, a transmission delay difference can be reliably absorbed and corrected while implementing an interconnection layout, a noise counter-measure, and a high-speed circuit. | 2014-01-09 |
20140013180 | CODING METHOD AND CODING DEVICE - The present invention relates to coding method and coding device that allow Rate-Compatible LDPC (low-density parity-check) codes to have favorable BER performance both with a low code rate and with a high code rate. In coding of LDPC codes that have plural code rates and whose all parity check matrices are composed of plural cyclic matrices, a coder 121 performs the coding in such a way that 12014-01-09 | |
20140013181 | Error Correction Coding Using Large Fields - An improved error correction system, method, and apparatus provides encoded sequences of finite field symbols, each with a plurality of associated weighted sums equal to zero, and decodes encoded sequences with a limited number of corruptions. Each of the multiplicative weights used in the weighted sums is preselected from a smaller subfield of a large finite field. Decoding proceeds by determining multiplicative weights using various operations over the smaller subfield. When a limited number of corruptions occur, improved system design ensures that the probability of decoding failure is small. The method and apparatus extend to determine one or more decoding solutions of an underdetermined set of equations, including detection of ambiguous solutions. | 2014-01-09 |
20140013182 | DATA PROCESSING METHOD, APPARATUS AND SYSTEM - A method according to an embodiment of the present disclosure comprising: receiving a read instruction transmitted by a host device, the read instruction including a first address; reading first data together with a first CRC code and a first ECC which are associated with the first data from a memory based on the first address; and performing error detection on the first data based on the first CRC code, and performing error correction on the first data based on the first ECC if an error is detected. With the embodiments of the disclosure, the CRC code with better capability of error detection is adopted to perform error detection on the data. If any error is detected, error correction is performed using the ECC. Thus, it is possible to overcome the problem as to insufficient capability of error detection of the ECC in the prior art, thereby improving the system performance. | 2014-01-09 |
20140013183 | MEMORY DEVICES WITH SELECTIVE ERROR CORRECTION CODE - An error correction apparatus includes an error correction circuit configured to selectively perform error correction on a portion of data that is at least one of written to and read from a plurality of memory cells of a memory device. The portion of data is at least one of written to and read from a subset of the plurality of memory cells, and the subset includes only fail cells among the plurality of memory cells. The error correction apparatus further includes a fail address storage circuit configured to store address information for the fail cells. | 2014-01-09 |
20140013184 | SEMICONDUCTOR STORAGE CIRCUIT AND OPERATION METHOD THEREOF - A semiconductor storage circuit includes a memory core which includes multiple memory cells; an error checking and correction (ECC) encoder; and an ECC decoder. The memory core is activated in response to input of a command for each operation cycle. The ECC encoder performs ECC encoding of input data which is input together with a write command and thus generates ECC data, and generates write data including the input data and the ECC data. The ECC decoder performs ECC decoding of read data which has been read from the memory core according to a read command, using ECC data included in the read data, and thus generates output data. An adjustment is made to equalize a delay from input of a write command until activation of the memory core and a delay from input of a read command until activation of the memory core. | 2014-01-09 |
20140013185 | ON CHIP REDUNDANCY REPAIR FOR MEMORY DEVICES - On chip redundancy repair for memory devices. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM. The system element includes a memory controller for control of the DRAM, and repair logic coupled with the memory controller, the repair logic to hold addresses identified as failing addresses for defective areas of the DRAM. The repair logic is configured to receive a memory operation request and to implement redundancy repair for an operation address for the request. | 2014-01-09 |
20140013186 | COMPUTING SYSTEM UTILIZING DISPERSED STORAGE - A computing system comprises at least a processing module, a main memory, a memory controller, and a plurality of memory components. A method begins by the memory controller receiving a memory access request regarding a data segment. The method continues with the memory controller interpreting the memory access request to determine whether an error encoding dispersal function of the data segment is applicable. The method continues with the memory controller identifying at least a threshold number of memories based on the memory access request, wherein the threshold number of memories includes at least one of the main memory and/or one or more of the plurality of memory components, when the error encoding dispersal function is applicable. The method continues with the memory controller addressing the at least a threshold number of memories to facilitate the memory access request. | 2014-01-09 |
20140013187 | USING SLOW RESPONSE MEMORY DEVICE ON A FAST RESPONSE INTERFACE - A method includes receiving a request to read data at a data storage device from an external device. In response to determining that the data is in a first memory of the data storage device, a first read operation is initiated to read the data from the first memory and a response is sent to the external device. The response indicates an error correction code (ECC) error. A read latency of the first read operation exceeds a reply time period corresponding to the request. The response is sent prior to completion of the first read operation and within reply time period. | 2014-01-09 |
20140013188 | ERROR RECOVERY FOR FLASH MEMORY - A set of data associated with a page in flash storage is received. Error correction decoding is performed on the set of data; if event error correction decoding fails, it is determined whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page. If it is determined the page is a MSB page, one or more MSB read thresholds are adjusted and the is re-read page using the adjusted MSB read threshold(s). If it is determined the page is a LSB page, one or more LSB read thresholds are adjusted and the page is re-read using the adjusted LSB read threshold(s). | 2014-01-09 |
20140013189 | APPARATUS FOR DEDICATED HARDWARE AND SOFTWARE SPLIT IMPLEMENTATION OF RATE MATCHING AND DE-MATCHING - In the method of rate-matching, software is used to calculate at least one rate-matching parameter for data, and dedicated hardware is used to perform at least one of a puncturing and repetition process on data based on the calculated rate-matching parameter. In rate de-matching, software is again used to calculate at least one rate de-matching parameter for received data, and dedicated hardware is used to compensate for puncturing and repetition based on the calculated rate de-matching parameter. | 2014-01-09 |
20140013190 | Iterative Decoding Device and Related Decoding Method - An iterative decoding device includes a decoder, a dual mode determination unit and a dual mode scaling unit. The decoder is utilized for receiving a set of soft information (SI) and iteratively decoding the set of SI and updating the set of SI accordingly to generate a set of updated SI. The dual mode determination unit is coupled to the decoder for generating a determination result according to the set of updated SI. The dual mode scaling unit is coupled to the dual mode determination unit and the decoder for scaling the set of updated SI according to the determination result to generate a set of scaled SI acting as an input of the decoder for next iteration. | 2014-01-09 |
20140013191 | Method and Apparatus for Decoding and Checking Tail-Biting Convolutional Code - The disclosure discloses a method and apparatus for decoding and checking a tail-biting convolutional code, so as to solve the problem of reducing a processing time delay in decoding and checking the tail-biting convolutional code in the prior art. The disclosure fully utilizes structural features of the tail-biting convolutional code to re-sort Log-Likelihood Ratio (LLR) values input into a decoder, and by reconstructing a derivative generator polynomial of a convolutional code, allows the decoder to output in serial according to a normal ordering of information bits during backtracking, that is, a first bit of an information sequence is first decoded successfully. Thus, CRC checking may be activated as soon as possible, so that part of the backtracking process and the CRC checking may be performed in parallel, thereby achieving the objective of reducing a processing time delay in decoding and checking the tail-biting convolutional code. The disclosure does not increase any hardware expense, belongs to an improvement of low cost, and does not cause any decoding performance downgrade. | 2014-01-09 |
20140013192 | TECHNIQUES FOR TOUCH-BASED DIGITAL DOCUMENT AUDIO AND USER INTERFACE ENHANCEMENT - Techniques for digital document audio and user interface enhancement are generally described herein. In one embodiment, for example, an apparatus may comprise a processor circuit and a digital document application operative on the processor circuit. The digital document application may comprise a document recorder component arranged for execution by the processor circuit to receive a source document file and generate an annotated document file, the document recorder component arranged to retrieve a text element from the source document file, generate a user interface view with the text element and an audio narration guide proximate to the text element for presentation on an output device, receive positions of an object on the audio narration guide from an input device, and generate an audio element for the text element based on the positions. Other embodiments are described and claimed. | 2014-01-09 |
20140013193 | METHODS AND SYSTEMS FOR CAPTURING INFORMATION-ENHANCED IMAGES - The approaches of the present disclosure provide for the efficient technology of intelligent association of still images with contextual information relating to sounds such as a sound that may have been ambient when a still image was captured. In particular, a user may use a media device, such as a smart phone or tablet computer, to capture a still image and record first audio, for example, at the time of capturing the still image for a predetermined period of time. The first audio may be then processed and analyzed so as to recognize a particular song or melody, and then a high quality second audio related to the recognized song or melody is downloaded and associated with the still image. Accordingly, the visual nature of still images is enhanced with data relating to contextual auditory information, which boosts the sensory and memory experience for the user. | 2014-01-09 |
20140013194 | SYSTEM AND METHOD FOR COLLECTING FINANCIAL INFORMATION OVER A GLOBAL COMMUNICATIONS NETWORK - A system comprises a combination of user examination decisions and semi-automated extraction tools, integrated into a web-based administration interface, to permit a user to quickly catalog a publically available financial website and extract financial rate data in a reproducible manner. The reproducibility of the extraction process allows for automated processes to re-extract the rate data as often as necessary to attain at least daily accuracy of recorded financial rates for a financial institution. The system allows for the tracking of over a quarter of a million financial rates, across varying website technologies and display formats, and the daily tracking of financial institution product data and especially financial products with frequently changing rates. A stable repository of rate data is also created to allow for data mining of financial trends to syndicated parties. | 2014-01-09 |
20140013195 | CONTENT REFERENCE IN EXTENSIBLE MARKUP LANGUAGE DOCUMENTS - A method includes creating a content reference to content within a first document, where the content reference includes an action parameter that indicates that the content referenced by the content reference is automatically fetched and inserted at a time that the content reference is resolved. The method further includes inserting the content reference within a second document. The method further includes dynamically resolving the content reference. The method further includes automatically fetching the content referenced by the content reference from the first document. The method further includes automatically inserting the content within the second document. | 2014-01-09 |
20140013196 | ON-SCREEN ALERT DURING CONTENT PLAYBACK - Embodiments of the disclosed herein relate to providing an on-screen alert during playback of content where the on-screen alert permits the user to connect to one of the characters (or an entity) shown or referred to in a web video or the program associated therewith. In addition, an authoring tool is disclosed herein for inserting an on-screen alert into a video (or other content) at a predetermined time reference, where the on-screen alert enables a first user to connect to a social networking system of a second user (or entity). A content management server or system may insert an on-screen alert into a video (or other content). The timing and selection of an alert may be tailored using user profile information which may be input by the user or inferred or ascertained based on a user's online activity, such as the user's selection of content to view on a site. | 2014-01-09 |
20140013197 | INTER-DOCUMENT LINKS INVOLVING EMBEDDED DOCUMENTS - Systems and methods provide a mechanism to create and traverse inter-document links involving embedded documents. One aspect of the systems and methods includes creating and traversing inter-document links to and from documents that are embedded in a host document. A further aspect of the systems and methods includes creating and traversing inter-document links to an from documents that may be embedded at more than one level in an embedded document hierarchy. A still further aspect of the systems and methods includes creating and traversing inter-document links from a first document to an embedded document in a second document. | 2014-01-09 |
20140013198 | REFERENCE MANAGEMENT IN EXTENSIBLE MARKUP LANGUAGE DOCUMENTS - A method includes defining one or more property fields within a document of a collection of one or more documents, where the one or more property fields store reference information. The method further includes performing an operation on the document. The method further includes extracting reference information associated with one or more references within the document. The method further includes populating the one or more property fields with the reference information associated with the one or more references within the document. The method further includes creating an index of the reference information populated within the one or more property fields. | 2014-01-09 |
20140013199 | GENERATING A REPORT BASED ON IMAGE DATA - A system for generating a report based on image data is disclosed. A template selector ( | 2014-01-09 |
20140013200 | VIDEO COMMENT FEED WITH PRIORITIZATION - Comments are displayed in conjunction with a video or other content. A submitted reference point in the video is recorded when a viewer submits a comment. The submitted comment is added to a comment feed at the reference point if no existing comment is displayed at that point already. If an existing comment is already displayed at the reference point, at least one type of the submitted comment is compared to at least one type of the existing comment to produce a comparison result. Based on the comparison result, the submitted comment can be given priority over the existing comment, which can be moved, deleted or otherwise modified so that the submitted comment can be shown at the reference point in the comment feed. | 2014-01-09 |
20140013201 | DYNAMIC ANNOTATION IN USER INFORMATION SYSTEM OF IR CAMERA - The present invention relates in general to the field of applications and functions of an IR-camera device operated by a user in connection with the recording of IR images and to processing of IR images on a computer application program. A system for managing annotations to IR images comprising selectable annotation input functions that are actuatable by means of control commands displayed on the display is disclosed. | 2014-01-09 |
20140013202 | WEB PAGE DISPLAY SYSTEM - A system for displaying a web page in which a server | 2014-01-09 |
20140013203 | SYSTEMS AND METHODS FOR MODIFYING A WEBSITE WITHOUT A BLINK EFFECT - Systems and methods for mitigating a blink effect during modification of a webpage, while minimizing delay. In an embodiment, a display of webpage content in a browser application is prevented. Modifications for at least some elements of the webpage content are received. Before one or more elements of the webpage content have loaded, elements to be modified are polled to determine whether they are available for modification. Elements to be modified, which are available for modification, are modified. Once all elements have been modified, the webpage content is displayed in the browser application. | 2014-01-09 |
20140013204 | METHOD AND APPARATUS FOR SYCHRONIZING FINANCIAL REPORTING DATA - A method and apparatus accurately synchronizes one or more items of financial information between a plurality of representations, or presentations, of marked up financial data stored in electronic form. The different representations may include balance sheets, income statements, and cash flow statements, among various other financial data, that may share common financial facts that are presented in a selected reporting format corresponding to the representations. Identifiers are assigned to the data so that instances of the facts may be automatically and simultaneously updated throughout the different representations each time a fact is updated in one representation. | 2014-01-09 |
20140013205 | METHODS FOR MATCHING XML DOCUMENTS - Methods, systems, and devices related to determining differences between XML documents. Two XML documents to be compared are first each decomposed into ordered labelled trees. Sets of operations which convert one tree into the other tree are then determined and a cost function is applied to each set of operations. The set of operations with the lowest cost is then selected. The cost function uses an affine-cost policy which adjusts a cost of each operation based a context in which the operation is applied. | 2014-01-09 |