02nd week of 2009 patent applcation highlights part 43 |
Patent application number | Title | Published |
20090011510 | Device and method for biolistic transformation of cells - The present invention provides a device and method for biolistic bombardment of cells. In a preferred embodiment, the device comprises a hollow tube or cylinder that attaches to a standard biolistic transformation apparatus, and focuses the nucleic acids at cells and tissue sections. In a typical configuration, the device has two barrels that deliver equal or substantially equal amounts of nucleic acids to cells of a tissue, such as a plant leaf. | 2009-01-08 |
20090011511 | Single-Point Genome Signature Tags - Disclosed is a method for analyzing the organismic complexity of a sample through analysis of the nucleic acid in the sample. In the disclosed method, through a series of steps, including digestion with a type II restriction enzyme, ligation of capture adapters and linkers and digestion with a type IIS restriction enzyme, genome signature tags are produced. The sequences of a statistically significant number of the signature tags are determined and the sequences are used to identify and quantify the organisms in the sample. Various embodiments of the invention described herein include methods for using single point genome signature tags to analyze the related families present in a sample, methods for analyzing sequences associated with hyper- and hypo-methylated CpG islands, methods for visualizing organismic complexity change in a sampling location over time and methods for generating the genome signature tag profile of a sample of fragmented DNA. | 2009-01-08 |
20090011512 | CONDITIONING SYSTEM AND METHOD FOR USE IN THE MEASUREMENT OF MERCURY IN GASEOUS EMISSIONS - Embodiments of the invention relate generally to systems used to measure mercury in gaseous emissions. In one aspect, the invention is directed to the use of silicon carbide as material for a thermal pyrolysis unit. In another aspect, at least one of silicon nitride, silicon boride, and/or boron nitride is used as material for a thermal pyrolysis unit. In another aspect, the invention is directed to an improved pyrolyzer design, in which a thermal pyrolysis unit comprises a tailpiece that allows water to be injected at the heated exit of the thermal pyrolysis unit. In another aspect, the invention is directed to the use of a coalescing filter in a scrubbing unit. In another aspect, the invention is directed to the use of a hydrophobic filter element in a scrubbing unit. One or more of these elements may be used in a conditioning module of a continuous emissions monitoring system, for example. | 2009-01-08 |
20090011513 | METHOD OF DETECTING NUCLEIC ACID BY USING NUCLEIC ACID MICROARRAY - The present invention provides a method of detecting a nucleic acid which is not restricted by the design of the base sequence of a nucleic acid probe. By repeating washing and detection in multiple stages, the present invention can improve the precision of sequence-specific hybridization stepwise and also can ease restrictions in designing the nucleic acid probes, in particular, restrictions on the Tm value (the temperature at which the nucleic acid double strand is dissociated into single strands) or the sequence length of the nucleic acid probes. | 2009-01-08 |
20090011514 | Dna Crosslinking for Primer Extension Assays - Provided herein are compositions and methods for inhibiting false signals associated with mispriming in primer extension assays. | 2009-01-08 |
20090011515 | Control of N-(Phosphonomethyl)Iminodiacetic Acid Conversion in Manufacture of Glyphosate - This invention relates to the preparation of N-(phosphonomethyl)glycine (“glyphosate”) from N-(phosphonomethyl)iminodiacetic acid (“PMIDA”), and more particularly to methods for control of the conversion of PMIDA, for the identification of reaction end points relating to PMIDA conversion and the preparation of glyphosate products having controlled PMIDA content. | 2009-01-08 |
20090011516 | Methods and Assays for the Detection of Nitrogen Uptake by a Plant and Uses Thereof - The invention provides a rapid and efficient method and assay for monitoring nitrogen uptake by a plant using a pH indicator. The plant is exposed to medium comprising one or more sources of nitrogen, such as nitrate or ammonia, and a pH indicator. The plant is exposed to the source of nitrogen for a time sufficient for it to be taken up by the plant. As nitrate is taken up from the medium, the medium becomes more basic, that is the pH increases. Conversely, as ammonia is taken up from the medium, the medium becomes more acidic and the pH decreases. The change in the pH of the medium may be optically detected and correlated to the amount of nitrate or ammonia remaining in the medium. Accordingly, the amount of nitrate or ammonia taken up by the plant or remaining in the medium may be determined. | 2009-01-08 |
20090011517 | Sample Plate for Fluid Analysis in a Refinery Process - A sample plate for use with a portable apparatus containing at least two different analytical devices, said plate ( | 2009-01-08 |
20090011518 | Device and Method for Detection of Fluorescence Labelled Biological Components - A sample acquiring device for detection of biological components in a liquid sample is provided comprising a measurement cavity for receiving a liquid sample, wherein the measurement cavity has a predetermined fixed thickness, and a reagent, which is arranged in a dry form inside the measurement cavity. The reagent comprises a fluorophore conjugated molecule. | 2009-01-08 |
20090011519 | DEVICE AND METHOD FOR MICRO SORBENT EXTRACTION AND DESORPTION - This invention relates to a micro cartridge and to a method of using the micro cartridge to sample and extract components of interest from a gas or a liquid. The cartridge contains a sorbent and has passages through which a pressure drop can be created to permit access between the gas or liquid and the sorbent. The micro cartridge is elongated and has one pointed end to fit into the injection port of a suitable analysis instrument where the components of interest are desorbed. The cartridge has two ends that are covered by removable closures and preferably has a diameter of less than 1 millimeter. The cartridge can be used with micro machine components and components made using nano technology. | 2009-01-08 |
20090011520 | Stable D-dimer liquid preparation - The invention is in the field of coagulation diagnosis and relates to a liquid, buffer-based D-dimer composition, which additionally contains fibrinogen and which is suitable as a standard material for control or calibration purposes for D-dimer test procedures. | 2009-01-08 |
20090011521 | Streptavidin surface acoustic wave immunosensor apparatus - The invention, the manufacturing process and operation method for forming the streptavidin surface acoustic wave (SAW) immunosensor apparatus is disclosed. Firstly, the PZT film is formed on silicon substrate by using the micro-powder-sol-gel method. Then, the metal transducer electrodes are coated on the PZT film using semiconductor process technology to produce the SAW. Finally, the sensing area of the SAW element is modified by streptavidin to form the streptavidin SAW immunosensor. The invention could be used for examining the ligand decorated by biotin, also for examining antibody. | 2009-01-08 |
20090011522 | Semiconductor Device Package Disassembly - Systems and methods are disclosed for the disassembly and preferably reassembly of semiconductor device packages. A method of the invention includes steps for excavating a portion of a semiconductor device package to expose a target surface within the interior of the package. The technique further includes steps of focusing a laser at a selected distance from the target surface in order to ablate the package material, exposing the target surface. Preferred embodiments of the invention are disclosed in which a cavity is excavated through the package to expose portions of leadfingers within. A temporary chip mount plate is affixed to an exterior surface of the package to cover one side of the cavity. A chip is attached to the temporary chip mount plate where it is electrically coupled to the leadfingers in the interior of the package. The contents of the cavity are then encapsulated with dielectric mold compound and the temporary chip mount plate is preferably removed to expose the backside of the chip. | 2009-01-08 |
20090011523 | Processing method and processing apparatus - A processing method of subjecting at least two stacked films, which comprise a first film and a second film of a target object to be processed, to a removing process by wet etching comprises bringing a first process liquid into contact with the first film of the target object, thereby etching the first film, determining whether the first film has been removed or not, switching the first process liquid to a second process liquid differing in a condition from the first process liquid when it has been determined that the first film has been removed, and bringing the second process liquid into contact with the second film, thereby etching the second film. | 2009-01-08 |
20090011524 | Method for determining suitability of a resist in semiconductor wafer fabrication - In one disclosed embodiment, the present method for determining resist suitability for semiconductor wafer fabrication comprises forming a layer of resist over a semiconductor wafer, exposing the layer of resist to patterned radiation, and determining resist suitability by using a scatterometry process prior to developing a lithographic pattern on the layer of resist. In one embodiment, the semiconductor wafer is heated in a post exposure bake process after scatterometry is performed. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source in a lithographic process. In other embodiments, patterned radiation is provided by an electron beam, or ion beam, for example. In one embodiment, the present method determines out-gassing of a layer of resist during exposure to patterned radiation. | 2009-01-08 |
20090011525 | METHOD FOR JOINING ADHESIVE TAPE TO SEMICONDUCTOR WAFER AND METHOD FOR SEPARATING PROTECTIVE TAPE FROM SEMICONDUCTOR WAFER - An arithmetic processing part in a controller detects a position of a defect such as a chip or a crack that occurs at an outer periphery of a semiconductor wafer, and then a memory in the controller stores position information of the defect. The controller reads the position information of the defect through a network in each process. On the basis of this position information, the controller determines a direction of joining a dicing tape to the semiconductor wafer or a direction of separating a protective tape from a front face of the semiconductor wafer. | 2009-01-08 |
20090011526 | INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY NITRIDIZATION - A method for increasing an electrical resistance of a resistor. A semiconductor structure that includes the resistor is placed in a chamber that includes a gas including nitrogen-containing molecules at an nitrogen concentration. A fraction F of an exterior surface of a surface layer of the resistor is exposed to the nitrogen-comprising molecules. A portion of the surface layer is heated at a heating temperature. A combination of the nitrogen concentration and the heating temperature is sufficient to nitridize the portion of the surface layer by reacting the portion with the nitrogen-containing molecules. Heating the portion of the surface layer includes directing a beam of radiation or particles into the portion of the surface layer heat the portion of the surface layer. The portion of the surface layer is nitridized by being reacted with the nitrogen-containing molecules such that an electrical resistance of the resistor is increased. | 2009-01-08 |
20090011527 | PRODUCING A SURFACE-MOUNTABLE RADIATION EMITTING COMPONENT - A radiation-emitting surface-mountable component has a light-emitting diode chip mounted on a leadframe. A molding material encapsulates the leadframe and the light emitting diode chip. | 2009-01-08 |
20090011528 | METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DEVICE HAVING PHOTO DIODE - A method for manufacturing an organic light emitting device including a photo diode and a transistor includes forming a first semiconductor layer and a second semiconductor layer on separate portions of a buffer layer formed on the substrate; forming a gate metal layer on the first semiconductor layer, the gate metal layer covering a central region of the first semiconductor layer; forming a high-concentration P doping region and a high-concentration N doping region in the first semiconductor layer by injecting impurities into regions of the first semiconductor layer not covered by the gate metal layer to form the photodiode; forming a source and drain region and a channel region in the second semiconductor layer; and removing the gate metal layer from the central region of the first semiconductor layer by etching and simultaneously forming a gate electrode by etching, the gate electrode being insulated from the channel region of the second semiconductor layer, to form the transistor. | 2009-01-08 |
20090011529 | IR-LIGHT EMITTERS BASED ON SWNT'S (SINGLE WALLED CARBON NANOTUBES), SEMICONDUCTING SWNTS-LIGHT EMITTING DIODES AND LASERS - The present invention relates to a new light emitters that exploit the use of semiconducting single walled carbon nanotubes (SWNTs). Experimental evidences are given on how it is possible, within the standard silicon technology, to devise light emitting diodes (LEDs) emitting in the infrared IR where light emission results from a radiative recombination of electron and holes on semiconducting single walled carbon nanotubes (SWNTs-LED). We will also show how it is possible to implement these SWNTs-LED in order to build up a laser source based on the emission properties of SWNTs. A description of the manufacturing process of such devices is also given. | 2009-01-08 |
20090011530 | NITRIDE-COMPOSITE SEMICONDUCTOR LASER ELEMENT, ITS MANUFACTURING METHOD, AND SEMICONDUCTOR OPTICAL DEVICE - A nitride semiconductor laser device with a reduction in internal crystal defects and an alleviation in stress, and a semiconductor optical apparatus comprising this nitride semiconductor laser device. First, a growth suppressing film against GaN crystal growth is formed on the surface of an n-type GaN substrate equipped with alternate stripes of dislocation concentrated regions showing a high density of crystal defects and low-dislocation regions so as to coat the dislocation concentrate regions. Next, the n-type GaN substrate coated with the growth suppressing film is overlaid with a nitride semiconductor layer by the epitaxial growth of GaN crystals. Further, the growth suppressing film is removed to adjust the lateral distance between a laser waveguide region and the closest dislocation concentrated region to 40 μm or more. | 2009-01-08 |
20090011531 | Semiconductor Laser With Narrow Beam Divergence - The invention relates to a method of reducing vertical divergence of a high-power semiconductor laser with a negligible threshold current and conversion efficiency penalty. The low divergence is achieved by increasing the thickness of the n-cladding layer in an asymmetric laser diode stack structure, to a value ranging from 1 to 4 times the laser mode size measured at 10% level. The divergence may be tuned by adjusting the n-cladding layer parameters in an area of the tail the optical mode, measuring 0.03% or less of the maximal optical power density of said optical mode. | 2009-01-08 |
20090011532 | PHOTOELECTRIC-CONVERSION APPARATUS AND IMAGE-PICKUP SYSTEM - A photoelectric-conversion apparatus includes a photoelectric-conversion area where a plurality of photoelectric-conversion elements configured to convert incident light into electrical charges, a plurality of floating-diffusion areas, a plurality of transfer-MOS transistors configured to transfer electrical charges of the photoelectric-conversion element to the floating-diffusion area, and a plurality of amplification-MOS transistors configured to read and transmit a signal generated based on the transferred electrical charges to an output line are provided. An antireflection film is provided on a light-receiving surface of the photoelectric-conversion element. The gate of the amplification-MOS transistor is electrically connected to one floating-diffusion area by providing one conductor in a single contact hole, and the anti-reflection film covers the photoelectric-conversion area except a base part of the contact hole. | 2009-01-08 |
20090011533 | ISOLATION TECHNIQUES FOR REDUCING DARK CURRENT IN CMOS IMAGE SENSORS - Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench. | 2009-01-08 |
20090011534 | Solid-state imaging device and method of manufacturing solid-state imaging device - A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being buried around a contact layer that connects an electrode layer of a pad portion and an interconnection layer of the surface side. A method of manufacturing such a solid-state imaging device is also provided. | 2009-01-08 |
20090011535 | Apparatus and Method of Manufacturing Solar Cells - The present invention relates to the field of thin film solar cells and particularly to an apparatus and method for manufacturing thin film solar cells. At least one material is deposited onto a substrate, whereby the deposited material is heated by means of heating means on a limited area of the deposited material. The substrate and the heating means are continuously moved in relation to each other until a predetermined area of the deposited material is heated, whereby the heated material is cooled in a controlled way, thus, obtaining a desired crystalline structure of the deposited material. | 2009-01-08 |
20090011536 | OPTICAL DEVICE WITH IROX NANOSTRUTURE ELECTRODE NEURAL INTERFACE - An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x≦4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO | 2009-01-08 |
20090011537 | Semiconductor device and method for manufacturing same - The present invention is to obtain an MIS transistor which allows considerable reduction in threshold fluctuation for each transistor and has a low threshold voltage. First gate electrode material for nMIS and second gate electrode material for pMIS can be mutually converted to each other, so that a process can be simplified. Such a fact that a dependency of a work function on a doping amount is small is first disclosed, so that fluctuation in threshold voltage for each transistor hardly occurs. | 2009-01-08 |
20090011538 | Packaging system - A mounting system is provided with a substrate loader section, a chip mounting section, and a substrate unloader section for sequentially taking out substrates whereupon chips are mounted. The mounting system is characterized in that the substrate loader section is provided with an oven capable of heat insulating a substrate together with a substrate magazine capable of containing a plurality of substrates, a stage heater for heating/heat insulating a substrate is provided, respectively, at a substrate conveying portion from a substrate waiting stage for the chip mounting section to the chip mounting section, at the chip mounting section, and at a substrate conveying portion from the chip mounting section to the substrate unloader section, and the substrate unloader section is provided with an oven capable of heat insulating a substrate together with a substrate magazine capable of containing a plurality of substrates whereupon chips are mounted. The substrate can be sustained at a desirable temperature over the substantially entire mounting process having a series of steps, and in particular, occurrence of problems ascribed to moisture absorption can be suppressed or prevented. | 2009-01-08 |
20090011539 | Flexible Structures for Interconnect Reliability Test - A method for forming an integrated circuit structure includes forming a test wafer. The step of forming the test wafer includes providing a first semiconductor substrate; and forming a first plurality of unit blocks over the first semiconductor substrate. Each of the first plurality of unit blocks includes a plurality of connection block cells arranged as an array. Each of the connection block cells includes two connection blocks, and a metal line connecting the two connection blocks. The method further includes forming a plurality of unit block boundary lines separating the first plurality of unit blocks from each other; and forming a first plurality of metal lines connecting a portion of the first plurality of unit blocks. | 2009-01-08 |
20090011540 | DIE-WAFER PACKAGE AND METHOD OF FABRICATING SAME - A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a second opposing surface thereof. Each of the first and second pluralities of bond pads includes an under-bump metallization (UBM) layer. The singulated semiconductor die is disposed on a semiconductor die site of a semiconductor wafer and a first plurality of conductive bumps electrically couples the first plurality of bond pads of the singulated semiconductor die with a first set of bond pads formed on the semiconductor die site. A second plurality of conductive bumps is disposed on a second set of bond pads of the semiconductor die site. A third plurality of conductive bumps is disposed on the singulated semiconductor die's second plurality of bond pads. The second and third pluralities of conductive bumps are configured for electrical interconnection with an external device. | 2009-01-08 |
20090011541 | STACKED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Stacked microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such microelectronic device can include a support member and a first known good microelectronic die attached to the support member. The first die includes an active side, a back side opposite the active side, a first terminal at the active side, and integrated circuitry electrically coupled to the first terminal. The first die also includes a first redistribution structure at the active side of the first die. The microelectronic device can also include a second known good microelectronic die attached to the first die in a stacked configuration such that a back side of the second die is facing the support member and an active side of the second die faces away from the support member. The second die includes a second redistribution structure at the active side of the second die. The device can further include a casing covering the first die, the second die, and at least a portion of the support member. | 2009-01-08 |
20090011542 | Structure and manufactruing method of chip scale package - A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure. | 2009-01-08 |
20090011543 | Enhanced Reliability of Wafer-Level Chip-Scale Packaging (WLCSP) Die Separation Using Dry Etching - An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die. | 2009-01-08 |
20090011544 | METHOD OF FORMING MOLDED STANDOFF STRUCTURES ON INTEGRATED CIRCUIT DEVICES - A method of forming molding standoff structures on integrated circuit devices is disclosed which includes forming a plurality of standoff structures on a substantially rectangular sheet of transparent material and, after forming the standoff structures, singulating the substantially rectangular sheet of transparent material into a plurality of individual transparent members, each of which comprise at least one of the plurality of standoff structures. | 2009-01-08 |
20090011545 | CHIP PACKAGE PROCESS - The present invention further provides a chip package process, which includes providing a substrate, disposing a chip on the substrate and forming a buffering compound on the substrate and the chip, wherein the buffering compound covers the chip. The present invention further provides another chip package process, which includes providing a substrate, forming a buffering compound on the substrate and disposing a chip in the buffering compound. | 2009-01-08 |
20090011546 | COOLING OF SUBSTRATE USING INTERPOSER CHANNELS - A method of forming structure. A substrate and an interposer are provided. The substrate includes a heat source and N continuous substrate channels on a first side of the substrate (N≧2). N interposer channels are coupled to the N substrate channels so as to form M continuous loops (1≦M≦N). Each loop independently consists of K substrate channels and K interposer channels in an alternating sequence. For each loop, K is at least 1 and is subject to an upper limit consistent with a constraint of the M loops collectively consisting of the N interposer channels and the N substrate channels. Each loop is independently open ended or closed. The first side of the substrate is connected to the interposer. The interposer is adapted to be thermally coupled to a heat sink such that the interposer is interposed between the substrate and the heat sink. | 2009-01-08 |
20090011547 | COOLING OF SUBSTRATE USING INTERPOSER CHANNELS - A method of forming a structure. An interposer is provided. The interposer is adapted to be interposed between a heat source and a heat sink and to transfer heat from the heat source to the heat sink. The interposer includes an enclosure that encloses a cavity. The enclosure is made of a thermally conductive material. The cavity includes a thermally conductive foam material. The foam material includes pores and includes at least one serpentine channel. Each serpentine channel has at least two contiguously connected channel segments. Each serpentine channel independently forms a closed loop or an open ended loop. The foam material is adapted to be soaked by a liquid filling the pores. Each serpentine channel is adapted to be partially filled with a fluid that serves to transfer heat from the heat source to the heat sink. | 2009-01-08 |
20090011548 | HYBRID INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a hybrid integrated circuit device of the present invention includes the steps of preparing a lead frame which constituted by units each having a plurality of leads, and fixing a circuit substrate on each unit of the lead frame by fixing pads which are formed on the surface of the circuit substrate to the leads, where a space between a first pad which is formed at an end edge of the circuit substrate and a second pad which is adjacent to the first pad is set narrower than a space between the pads themselves. | 2009-01-08 |
20090011549 | PROCESS AND SYSTEM FOR MANUFACTURING AN ENCAPSULATED SEMICONDUCTOR DEVICE - A process for manufacturing a semiconductor device envisages the steps of: positioning a frame structure, provided with a supporting plate carrying a die of semiconductor material, within a molding cavity of a mold; and introducing encapsulating material within the molding cavity for the formation of a package, designed to encapsulate the die. The frame structure is further provided with a prolongation element mechanically coupled to the supporting plate inside the molding cavity and coming out of the molding cavity, and the process further envisages the steps of: controlling positioning of the supporting plate within the molding cavity with the aid of the prolongation element; and, during the step of introducing encapsulating material, separating and moving the prolongation element away from the supporting plate. | 2009-01-08 |
20090011550 | FLAT PANEL DISPLAY DEVICE AND FABRICATING METHOD THEREOF - A flat panel display device (FPD) and fabricating method thereof are disclosed, which reduce the number of masks during fabrication and prevent electro-chemical corrosion problems. In the FPD, a cell area and a pad area are defined on a substrate. A storage electrode traverses an active layer in parallel to a gate line. Source and drain regions of the active layer in the vicinity of both sides of a gate electrode are not formed below the storage electrode. An insulating interlayer over the substrate has first and second contact holes on the source and drain regions, respectively. A source electrode contacts the source region via a first contact hole and a drain electrode contacts the drain region via a second contact hole to directly contact a pixel electrode. A protective layer is disposed over the substrate including the pixel electrode. | 2009-01-08 |
20090011551 | Method for manufacturing semiconductor device - A method for manufacturing a semiconductor device is provided, which comprises at least a steps of forming a gate insulating film over a substrate, a step of forming a microcrystalline semiconductor film over the gate insulating film, and a step of forming an amorphous semiconductor film over the microcrystalline semiconductor film. The microcrystalline semiconductor film is formed by introducing a silicon hydride gas or a silicon halide gas when a surface of the gate insulating film is subjected to hydrogen plasma to generate a crystalline nucleus over the surface of the gate insulating film, and by increasing a flow rate of the silicon hydride gas or the silicon halide gas. | 2009-01-08 |
20090011552 | METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS - A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric. | 2009-01-08 |
20090011553 | THERMALLY STABLE BiCMOS FABRICATION METHOD AND BIPOLAR JUNCTION TRANSISTOR FORMED ACCORDING TO THE METHOD - A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step. | 2009-01-08 |
20090011554 | Component With Sensitive Component Structures and Method for the Production Thereof - An electrical component has electrically conducting structures placed on an electrically isolating or semiconductive substrate and component structures sensitive to a voltage or an electrical arcing and galvanically separated from one another. To prevent an arcing between the galvanically separated component structures, the component structures are short-circuited with a shunt line having a smaller cross-section than the remaining electrical conductor tracks. The shunt lines can be burnt through by application of an electrical current at any given time, whereby a galvanic separation of the component structures is effected, if necessary, for the function of the component. | 2009-01-08 |
20090011555 | Method of manufacturing CMOS integrated circuit - In a method of manufacturing a CMOS integrated circuit according to the present invention, a PSD step (step of forming P-type source/drain regions) is first carried out, and an NSD step (step of forming N-type source/drain regions) is thereafter carried out, in order to create a mixed structure of a silicide transistor and a non-silicide transistor. Thus, a step of depositing an oxide film on a substrate surface may be carried out only once, the oxide film can be removed by a single step of etching with hydrofluoric acid, and the operating characteristics of formed devices can be excellently maintained. | 2009-01-08 |
20090011556 | Method for producing a microelectronic structure - A method for producing a microelectronic structure is suggested in which a layer structure ( | 2009-01-08 |
20090011557 | METHOD FOR MANUFACTURING A FLASH MEMORY - A method for manufacturing a flash memory includes providing a substrate with a sacrificial oxide layer, a sacrificial poly-Si layer, a hard mask layer and a trench exposing part of the substrate and filled with an oxide layer, later depositing a oxide layer conformally on the sacrificial oxide layer and the oxide layer, and afterwards removing the oxide layer on the sacrificial oxide layer and on the top of the oxide layer and the sacrificial oxide layer to form a spacer as a STI oxide spacer. | 2009-01-08 |
20090011558 | METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A method of manufacturing a NAND nonvolatile semiconductor memory which involves forming a bit line contact between adjacent select transistors of the NAND nonvolatile semiconductor memory, the method has patterning memory cells and said select transistors of said NAND nonvolatile semiconductor memory; forming a first insulating film between adjacent two of said memory cells, between said memory cells and said select transistors, and between adjacent two of said select transistors; selectively etching the first insulating film between said select transistors to form a side wall spacer on each of said select transistors; forming a second insulating film on said memory cells, said first insulating film between said memory cells, said select transistors and said side wall spacers; forming a resist pattern on said second insulating film; and simultaneously forming an opening in an insulating film and a control gate on a floating gate of each of said select transistors using said resist pattern and an opening between said adjacent select transistors using said resist pattern. | 2009-01-08 |
20090011559 | NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING A NON-VOLATILE SEMICONDUCTOR MEMORY - An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors. | 2009-01-08 |
20090011560 | MULTIPLE SELECT GATE ARCHITECTURE WITH SELECT GATES OF DIFFERENT LENGTHS - The invention provides methods and apparatus. A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the string of two or more non-volatile memory cells, and a second select gate coupled in series with the first select gate. A length of the second select gate is greater than a length of the first select gate. | 2009-01-08 |
20090011561 | Method of fabricating high-voltage mos having doubled-diffused drain - A method of fabricating high-voltage MOS having double-diffused drain (DDD) is disclosed. The original photoresist used to define a gate is used to define double-diffused drains without increasing the complexity of the whole process. A dielectric layer and a conductive layer are sequentially formed on a substrate. A patterned photoresist is then formed on the conductive layer and then used to etch the conductive layer and the dielectric layer to form a gate and a gate dielectric layer, respectively. After stabilizing the photoresist layer, a first ion implantation is performed to form lightly doped region having deep junction. The photoresist is removed and two spacers are formed on the sidewalls of the gate. Next, a second ion implantation is performed to form heavily doped region in the substrate on outer side of the spacers. | 2009-01-08 |
20090011562 | Process for Fabricating a Field-Effect Transistor with Self-Aligned Gates - A first gate, formed on a substrate, is surmounted by a hard layer designed, with first spacers surrounding the first gate, to act as etching mask to bound the channel and a pad that bounds a space subsequently used to form a gate cavity. The hard layer is preferably made of silicon nitride. Before flipping and bonding, a bounding layer, preferably made of amorphous silicon or polysilicon, is formed to bound drain and source areas. After flipping and bonding of the assembly on a second substrate, a second gate is formed in the gate cavity. At least partial silicidation of the bounding layer is then performed before the metal source and drain electrodes are produced. | 2009-01-08 |
20090011563 | Fabrication of Self-Aligned Gallium Arsenide Mosfets Using Damascene Gate Methods - A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are implanted into the substrate adjacent the dummy gate. Dummy spacers are formed along dummy gate sidewalls and over a portion of the source-drain extensions. Source-drain regions are implanted. Insulating spacers are formed on dummy oxide spacer sidewalls. A conductive layer is formed over the source-drain regions. The conductive layer is annealed to form contacts to the source-drain regions. The dummy gate and the dummy oxide spacers are removed to form a gate opening. A passivation layer is in-situ deposited in the gate opening. The surface of the passivation layer is oxidized to create an oxide layer. A dielectric layer is ex-situ deposited over the oxide layer. A gate metal is deposited over the dielectric layer to form a gate stack in the gate opening. | 2009-01-08 |
20090011564 | Method of forming a gate oxide layer - A nitrogen implantation to a substrate on the edges of an active area is added before filling an insulating layer in a trench during a shallow trench isolation process to reduce the thickness of a gate oxide formed later on the edges of the active area. | 2009-01-08 |
20090011565 | Field effect transistor structure with abrupt source/drain junctions - Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type. | 2009-01-08 |
20090011566 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - After gate insulating films, gate electrodes, and n | 2009-01-08 |
20090011567 | Method for manufacturing display substrate - A method for manufacturing a display substrate is disclosed, which includes the following steps: providing a substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on a non-active area of the substrate; and staining the marking pattern or filling a material having low transmittance ratio into the marking pattern. The present invention further discloses a method for making a display substrate, including the steps: providing a substrate; forming a shadow layer on a non-active area of the substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on the shadow layer of the non-active area on the substrate; and removing a part of the shadow layer not covered by the marking pattern. | 2009-01-08 |
20090011568 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURE THEREOF AND SEMICONDUCTOR INTEGRATED CIRCUIT - An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region. | 2009-01-08 |
20090011569 | ELECTRICAL DEVICE AND METHOD FOR FABRICATING THE SAME - A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches. | 2009-01-08 |
20090011570 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer. | 2009-01-08 |
20090011571 | WAFER WORKING METHOD - A wafer working method is provided which is capable of feeding a wafer diced by a laser dicing apparatus to a subsequent step without breaking up the wafer. The wafer working method comprises: a first machining step of grinding a reverse side of a wafer W and then polishing the reverse side of the wafer thus ground to a thickness T2 which is larger than a finally worked wafer thickness T1 by 50 μm to 150 μm; a modified region forming step of irradiating laser light to the wafer thus subjected to the first machining to form a modified region inside the wafer; and a second machining step of grinding the reverse side of the wafer thus formed with the modified region and then polishing the reverse side of the wafer thus ground to the finally worked wafer thickness T1. | 2009-01-08 |
20090011572 | Wafer Working Method - A wafer working method is provided which is capable of feeding a wafer diced by a laser dicing apparatus to a subsequent step without breaking up the wafer. The wafer working method comprises: a first machining step of grinding a reverse side of a wafer W and then polishing the reverse side of the wafer thus ground to a thickness T | 2009-01-08 |
20090011573 | Carrier used for deposition of materials on a non-planar surface - A carrier for effectuating semiconductor processing on a non-planar substrate is disclosed. The carrier is configured for holding at least one non-planar substrate throughout a semiconductor processing step and concurrently rotating non-planar substrates as they travel down a translational path of a processing chamber. As the non-planar substrates simultaneously rotate and translate down a processing chamber, the rotation exposes the whole or any desired portion of the surface area of the non-planar substrates to the deposition process, allowing for uniform deposition as desired. Alternatively, any predetermined pattern is able to be exposed on the surface of the non-planar substrates. Such a carrier effectuates manufacture of non-planar semiconductor devices, including, but not limited to, non-planar light emitting diodes, non-planar photovoltaic cells, and the like. | 2009-01-08 |
20090011574 | Method for surface modification of semiconductor layer and method of manufacturing semiconductor device - A method for surface modification of a semiconductor layer and a method of manufacturing a semiconductor device are provided. The method for surface modification of the silicon layer includes following steps. First, a semiconductor layer having several particles on its surface is provided. Next, these particles are removed through a clean process. In the clean process, the semiconductor layer is exposed to an organic matter remover, a first peroxide mixture solution and a second peroxide mixture solution sequentially. | 2009-01-08 |
20090011575 | Manufacturing method of SOI substrate and manufacturing method of semiconductor device - It is object to provide a manufacturing method of an SOI substrate provided with a single-crystal semiconductor layer, even in the case where a substrate having a low allowable temperature limit, such as a glass substrate, is used and to manufacture a high-performance semiconductor device using such an SOI substrate. Light irradiation is performed on a semiconductor layer which is separated from a semiconductor substrate and bonded to a support substrate having an insulating surface, using light having a wavelength of 365 nm or more and 700 nm or less, and a film thickness d (nm) of the semiconductor layer which is irradiated with the light is made to satisfy d=λ/2n×m±α (nm), when a light wavelength is λ (nm), a refractive index of the semiconductor layer is n, m is a natural number greater than or equal to 1 (m=1, 2, 3, 4, . . . ), and 0≦α≦10 is satisfied. | 2009-01-08 |
20090011576 | Ultra-Violet Protected Tamper Resistant Embedded EEPROM - A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon layer located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the amorphous silicon layer. | 2009-01-08 |
20090011577 | METHOD OF MAKING PHASE CHANGE MATERIALS ELECTROCHEMICAL ATOMIC LAYER DEPOSITION - A method of making phase change materials on a substrate by electrochemical atomic layer deposition, which includes sequentially electrodepositing at least one atomic layer of a first element of a first solution and at least one atomic layer of a second element of a second solution on a substrate; and repeating the sequential electrodepositing until at least one film of a phase change material is formed on the substrate. | 2009-01-08 |
20090011578 | METHODS TO FABRICATE MOSFET DEVICES USING A SELECTIVE DEPOSITION PROCESS - In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsilane, a first etchant, and hydrogen gas to deposit a first silicon-containing layer thereon. The first silicon-containing layer may be selectively deposited on the source/drain regions of the substrate while the first silicon-containing layer may be etched away on the surface of the dielectric materials of the substrate. Subsequently, the process further provides exposing the substrate to a second process gas comprising dichlorosilane and a second etchant to deposit a second silicon-containing layer selectively over the surface of the first silicon-containing layer on the substrate. | 2009-01-08 |
20090011579 | Quantum Dot Array And Production Method Therefor, And Dot Array Element And Production Method Therefor - The present invention is a method of manufacturing a quantum dot array having a plurality of columnar parts including a quantum dot on a substrate, the method comprising the steps of obliquely vapor-depositing a material constituting a first barrier layer to become an energy barrier against the quantum dot onto a surface of the substrate, so as to form a plurality of first barrier layers; obliquely vapor-depositing a material constituting the quantum dot with respect to the surface of the substrate, so as to form the quantum dots on the first barrier layers; and obliquely vapor-depositing a material constituting a second barrier layer to become an energy barrier against the quantum dot with respect to the surface of the substrate, so as to form the second barrier layers on the quantum dots. | 2009-01-08 |
20090011580 | METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE - A method for fabricating a semiconductor memory device includes forming a channel region in a substrate, selectively etching the substrate to form a first trench, performing an impurity ion implantation process on the channel region, and etching a lower portion of the first trench to form a second trench. | 2009-01-08 |
20090011581 | CARBON CONTROLLED FIXED CHARGE PROCESS - Carbon may be implanted into a p-type silicon channel to form a carbon region in an n-type metal oxide semiconductor (NMOS) transistor. After an annealing process, the implanted carbon may diffuse from the channel into an interface of a gate dielectric layer and the channel. The diffusion may cause an increase in fixed charge at the silicon surface. Thus, the threshold voltage of the NMOS transistor may be reduced. | 2009-01-08 |
20090011582 | Method for Depositing a Vapour Deposition Material - Method for depositing a vapour deposition material on a base material, in particular for doping a semiconductor material, in which a vapour deposition batch, in which the vapour deposition material is enclosed in an air-tight manner by a shell, is introduced into a vapour deposition chamber and the shell is opened in the vapour deposition chamber, so that the vapour deposition material in the vapour deposition chamber then evaporates and is deposited on the base material, wherein the shell is opened by at least partially melting by heating a meltable shell material which at least partially forms the shell at a melting temperature which is lower than an evaporation temperature of the vapour deposition material. | 2009-01-08 |
20090011583 | Method of manufacturing a semiconductor device - A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten. | 2009-01-08 |
20090011584 | Method for forming transistor of semiconductor device - A method for forming a transistor of a semiconductor device, includes forming a trench by etching a semiconductor substrate on which a pad oxide film and a pad nitride film are sequentially formed; forming a isolation oxide film by filling the trench with oxide; removing an upper portion of the isolation oxide film until an upper lateral portion of the semiconductor substrate is exposed; forming a barrier nitride film over the isolation oxide film, the semiconductor substrate, and the pad nitride film; forming a sacrificial oxide film over the barrier nitride film; performing a planarization process until the pad nitride film is exposed; performing a wet etching process until the active region is exposed; forming a photoresist pattern over the active region and the barrier nitride film; and performing a dry etching process by using the photoresist pattern as an etching mask, thereby forming a recessed gate trench. | 2009-01-08 |
20090011585 | Methods of Etching Nanodots, Methods of Removing Nanodots From Substrates, Methods of Fabricating Integrated Circuit Devices, Methods of Etching a Layer Comprising a Late Transition Metal, and Methods of Removing a Layer Comprising a Late Transition Metal From a Substrate - Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exposing such nanodots to a gas comprising a phosphorus and halogen-containing compound and an oxidizing agent. After the exposing, the nanodots which are remaining and were exposed are etched (either partially or completely) with an aqueous solution comprising HF. | 2009-01-08 |
20090011586 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a first insulating film provided on a surface of a semiconductor substrate, a charge accumulation layer provided on the first insulating film, a second insulating film provided above the charge accumulation layer and contains silicon and nitrogen, a third insulating film provided on the second insulating film, and composed of a single-layer insulating film containing oxygen or a plural-layer stacked insulating film at least whose films on a top layer and a bottom layer contain oxygen, relative dielectric constant thereof being larger than it of a silicon oxide film, a fourth insulating film provided on the third insulating film and contains silicon and nitrogen, a control gate provided above the fourth insulating film, and a fifth insulating film provided between the charge accumulation layer and the second insulating film or between the fourth insulating film and the control gate, and contains silicon and oxygen. | 2009-01-08 |
20090011587 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises providing a substrate. Next, an insulating layer, a conductive layer and a silicide layer are formed on the substrate in sequence. Next, a hard masking layer is formed on the silicide layer exposing a portion of the silicide layer. A first etching step is performed to remove the silicide layer and the underlying conductive layer which are not covered by the hard masking layer, thereby forming a gate stack. And next, a second etching step is performed to remove any remaining conductive layer not covered by the hard masking layer after the first etching step. The second etching step is performed with an etchant comprising ammonium hydroxide. | 2009-01-08 |
20090011588 | Flash Memory and Methods of Fabricating Flash Memory - Flash memory and methods of fabricating flash memory are disclosed. A disclosed method comprises: forming a first floating gate; and extending the first floating gate by forming a second floating gate adjacent a first sidewall of the floating gate. The second floating gate extends upward above the first floating gate. The method also includes depositing a dielectric layer on the first floating gate and the second floating gate; and forming a control gate on the dielectric layer. | 2009-01-08 |
20090011589 | METHOD OF MANUFACTURING SPLIT GATE TYPE NONVOLATILE MEMORY DEVICE - A method of manufacturing a split gate type nonvolatile semiconductor memory device in which control gates are formed by a self aligning process. | 2009-01-08 |
20090011590 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns. | 2009-01-08 |
20090011591 | Film substrate, fabrication method thereof, and image display substrate - In a film substrate (FB) including a film base material ( | 2009-01-08 |
20090011592 | METHOD OF MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N | 2009-01-08 |
20090011593 | METHOD OF DEPOSITING AMORPHOUS FILM ON CAPACITOR ASSEMBLY - A capacitor assembly includes a semiconductor substrate having an interlayer insulation film on a first main surface of the semiconductor substrate, and a conductive barrier layer formed on the interlayer insulation film. The capacitor assembly also includes a contact plug electrically connected to the conductive barrier layer through the interlayer insulation film, and a lower electrode formed on the barrier layer. The capacitor assembly also includes a capacitor insulation film formed on the lower electrode, and an upper electrode formed on the capacitor insulation film. The capacitor insulation film is made from a ferroelectric material. The barrier layer is an amorphous film which includes titanium and aluminum. | 2009-01-08 |
20090011594 | Methods of Trench and Contact Formation in Memory Cells - Methods of contact formation and memory arrays formed using such methods, which methods include providing a substrate having a contacting area; forming a plurality of line-shape structures extending in a first direction; forming a hard mask spacer beside the line-shape structure; forming an insulating material layer above the hard mask spacer; forming a contiguous trench in the insulating material layer extending in a second direction different from the first direction and exposing the contacting area; and forming a conductive line in the trench to contact the contacting area. | 2009-01-08 |
20090011595 | METHOD OF FORMING A LAYER ON A SEMICONDUCTOR SUBSTRATE AND APPARATUS FOR PERFORMING THE SAME - In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjusted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved. | 2009-01-08 |
20090011596 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - An electronic device includes an element group which generates a specific identification number and is composed of a plurality of elements. The specific identification number is set based on irregular deviation in electric characteristic of the elements which is caused due to a random failure in a manufacturing process. | 2009-01-08 |
20090011597 | MASS PRODUCTION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE - In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film). | 2009-01-08 |
20090011598 | Method of manufacturing semiconductor device including silicon carbide substrate - In a manufacturing method of a silicon carbide semiconductor device, a silicon carbide substrate is prepared by slicing an ingot that is made of silicon carbide single crystal. The silicon carbide substrate is heat treated for exposing a substrate defect generated at a surface portion of the silicon carbide substrate and the surface portion of the silicon carbide substrate is chemical-mechanical polished in such a manner that the exposed substrate defect is removed. Then, a semiconductor element is formed on the silicon carbide substrate. | 2009-01-08 |
20090011599 | SLURRY COMPOSITIONS FOR SELECTIVELY POLISHING SILICON NITRIDE RELATIVE TO SILICON OXIDE, METHODS OF POLISHING A SILICON NITRIDE LAYER AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - Slurry compositions for selectively polishing silicon nitride relative to silicon oxide, methods of polishing a silicon nitride layer and methods of manufacturing a semiconductor device using the same are provided. The slurry compositions include a first agent for reducing an oxide polishing rate, an abrasive particle and water, and the first agent includes poly(acrylic acid). The slurry composition may have a high polishing selectivity of silicon nitride relative to silicon oxide to be employed in selectively polishing a silicon nitride layer in a semiconductor manufacturing process. | 2009-01-08 |
20090011600 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention is directed to a method and an apparatus for manufacturing a semiconductor device including step S | 2009-01-08 |
20090011601 | Over-coating agent for forming fine patterns and a method of forming fine patterns using such agent - It is disclosed an over-coating agent for forming fine-line patterns which is applied to cover a substrate having thereon photoresist patterns and allowed to shrink under heat so that the spacing between adjacent photoresist patterns is lessened, with the applied film of the over-coating agent being removed substantially completely to form or define fine trace patterns, further characterized by containing a copolymer or a mixture of polyvinyl alcohol with a water-soluble polymer other than polyvinyl alcohol. Also disclosed is a method of forming fine-line patterns using the over-coating agent. According to the invention, one can effectively increase the shrinkage amount (the amount of heat shrinking) of the agent, thereby achieving a remarkably improved effect of forming or defining fine-line patterns and which also present satisfactory profiles and meet the characteristics required of today's semiconductor devices. | 2009-01-08 |
20090011602 | Film Forming Method of Amorphous Carbon Film and Manufacturing Method of Semiconductor Device Using the Same - Disclosed is a film forming method of an amorphous carbon film, including: disposing a substrate in a processing chamber; supplying a processing gas containing carbon, hydrogen and oxygen into the processing chamber; and decomposing the processing gas by heating the substrate in the processing chamber and depositing the amorphous carbon film on the substrate. | 2009-01-08 |
20090011603 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The invention prevents a wiring layer in a memory region from being exposed to prevent a change in wire resistance and degradation of reliability. A SiO | 2009-01-08 |
20090011604 | PHOTON INDUCED REMOVAL OF COPPER - Preferred embodiments provide a method for removing at least part of a copper comprising layer from a substrate, the substrate comprising at least a copper comprising surface layer. The method comprises in a first reaction chamber converting at least part of the copper comprising surface layer into a copper halide surface layer and in a second reaction chamber removing at least part of the copper halide surface layer by exposing it to a photon comprising ambient, thereby initiating formation of volatile copper halide products. During exposure to the photon comprising ambient, the method furthermore comprises removing the volatile copper halide products from the second reaction chamber to avoid saturation of the volatile copper halide products in the second reaction chamber. The method according to preferred embodiments may be used to pattern copper comprising layers. For example, the method according to preferred embodiments may be used to form copper comprising interconnect structures in a semiconductor device. | 2009-01-08 |
20090011605 | Method of manufacturing semiconductor device - The present invention is an apparatus for manufacturing a semiconductor device comprising: a process vessel including a stage on which a substrate is placed, the substrate having a low dielectric constant film with a resist pattern being formed in an upper layer of the low dielectric constant film; an etching-gas supply unit that supplies an etching gas into the process vessel so as to etch the low dielectric constant film; an ashing-gas unit means that supplies an ashing gas into the process vessel so as to ash the resist pattern formed in the upper layer of the low dielectric constant film after the low dielectric constant film has been subjected to an etching process; a plasma generating means that generates a plasma by supplying an energy to the etching gas and the ashing gas in the process vessel; a unit that supplies a dipivaloylmethane gas into the process vessel, after the low dielectric constant film has been subjected to an ashing process, in order to recover a damage layer of the low dielectric constant film which has been damaged by the plasma; and a heating unit that enables the dipivaloylmethane gas to come into contact with a surface of the substrate under a heated condition. | 2009-01-08 |
20090011606 | Substrate Processing Apparatus and Semiconductor Device Producing Method - A substrate processing apparatus, comprising: a processing chamber which provides a space for flowing desired gas and for depositing a desired film on a substrate; a lamp unit group having at least one lamp unit which is disposed in the processing chamber and which includes a filament for heating the substrate and a lamp tube surrounding the filament; at least first and second casings which surround the lamp unit, the first casing surrounding the lamp unit and the second casing surrounding the first casing; and a refrigerant flowing apparatus for flowing cooling medium to a first space formed between the lamp unit and the first casing, and to a second space formed between the first casing and the second casing, is disclosed. | 2009-01-08 |
20090011607 | Silicon Dioxide Deposition Methods Using at Least Ozone and TEOS as Deposition Precursors - Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated. | 2009-01-08 |
20090011608 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The transistor characteristics of a MIS transistor provided with a gate insulating film formed to contain oxide with a relative dielectric constant higher than that of silicon oxide are improved. After a high dielectric layer made of hafnium oxide is formed on a main surface of a semiconductor substrate, the main surface of the semiconductor substrate is heat-treated in a non-oxidation atmosphere. Next, an oxygen supplying layer made of hafnium oxide deposited by ALD and having a thickness smaller than that of the high dielectric layer is formed on the high dielectric layer, and a cap layer made of tantalum nitride is formed. Thereafter, the main surface of the semiconductor substrate is heat-treated. | 2009-01-08 |
20090011609 | RADICAL OXIDATION PROCESS FOR FABRICATING A NONVOLATILE CHARGE TRAP MEMORY DEVICE - A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process. | 2009-01-08 |