02nd week of 2009 patent applcation highlights part 14 |
Patent application number | Title | Published |
20090008608 | Sodium/silicon "treated" water - A sodium, silicon and water composition characterized predominantly a by sodium to silicon ratio of less than 1.0 and an absence of significant metal hydride, the composition useful in a diluted product with approximately 100 parts de-ionized water, the product further useful in approximately 50/50 ratio with an amine in a gas treatment facility and as an additive to fuel, the invention including the process of making the concentrate and the concentrate defined by process as well as a process of making the diluted product and an amine combination. | 2009-01-08 |
20090008609 | Derivatized 3,4-Alkylenedioxythiophene Monomers, Methods of Making Them, and Use Thereof - The present invention relates to methods of making derivatized 3,4-alkylenedioxythiophene monomers and methods of using the 3,4-alkylenedioxythiophene monomers. | 2009-01-08 |
20090008610 | PROCESS FOR PRODUCING CARBON NANOTUBES FROM RENEWABLE RAW MATERIALS - A subject of the present invention is a process for producing carbon nanotubes, the process comprising:
| 2009-01-08 |
20090008611 | CARBON NANOFIBER, PRODUCTION PROCESS AND USE - [Problems to be Solved] The invention provides inexpensive carbon fiber filler material, which has a low content of metal impurity and enables the resin composite material to exhibit conductivity when added thereto in a small amount. | 2009-01-08 |
20090008612 | EXOTHERMIC POLYPHENYLENE SULFIDE COMPOUNDS - Use of an exothermic additive in a polyphenylene sulfide compound results in an extruded or molded thermoplastic article that is electrically conductive and exothermic when connected to a source of electrical energy. Electronic devices benefit from these articles, particularly where ink must be melted for imaging of commercial graphics on a substrate. | 2009-01-08 |
20090008613 | HYBRID POLYISOCYANATES - The present invention relates to hybrid organic-inorganic polyisocyanates based on polyfunctional organosilanes, metal alkoxides and alkoxysilane-containing blocked polyisocyanates for the preparation of organic-inorganic coating compositions and adhesives. | 2009-01-08 |
20090008614 | Pulling tool - A multi-function tool having a handle portion and a plurality of structures operable therewith for the performance of a plurality of functions. The multi-function tool allows fast and convenient transition between any of the plurality of functions in order to enable completion of jobs or tasks requiring such functions without acquisition, storage, and/or maintenance of a plurality of specialized tools. | 2009-01-08 |
20090008615 | ROLLER CHAIN AND SPROCKET SYSTEM - A roller chain and sprocket system utilizes an involute profile on the sprocket teeth to engage rollers in the links of a roller chain. The links, when aligned linearly, bear upon one another when pushed to form a substantially rigid column which has an axis. The system results in substantially 100% of the rotational energy imparted to the sprocket being translated into linear motion of the chain along the column axis. | 2009-01-08 |
20090008616 | Log cradle for lifting logs - A log lifting beam with structural attachments that allow it to be fastened to a downed tree trunk. A means is provided for coupling the beam to a portable jack. The beam is positioned on a downed tree trunk with its forward end resting perpendicularly on the top of the tree trunk. The lower end of the beam rests on the ground. A tongue assembly hangs downward from the forward end of the beam. A steel chain stretched from the lower end of the tongue assembly and extended under the tree trunk to an attachment point mid-section the beam serves as a cradle for the tree trunk. The tongue of a jack is inserted under a short chain also bolted to the lower end of the said tongue assembly. The jack tongue is raised against this chain and the downed tree trunk is lifted. | 2009-01-08 |
20090008617 | DEMOLITION TOOL - The invention provides a demolition tool that can be used in many ways for the demolition of construction materials or other materials. The demolition tool includes a handle having a head at one end. The head has a longitudinal central plane that bisects the head, a strike contact face, and toothed, stepped grasping jaws that accommodate multiple sizes of lumber or other material. The head may also include a blunt blade edge below the strike contact face for striking and demolishing material. The demolition tool includes a bent end pry bar at a second end of the handle. The bent end pry bar being offset 90 degrees from the longitudinal central plane of the tool head enabling full range of motion without interfering with other tool functions. The demolition tool may comprise a single piece of material and may be softer than tools used to strike it, but harder than materials which it is used to strike. | 2009-01-08 |
20090008618 | Gate Post Assembly - A gate post assembly including at least one gate post ( | 2009-01-08 |
20090008619 | Security fence module - A fence module is adapted for installation without required anchoring buy providing a base frame and a plurality of upright supporting posts extending from the base frame. At least three fence sections extend between the supporting posts. A first fence section at a first extreme end of the fence module, a second fence section at a second extreme end of the fence module, and a third fence section angularly positioned between the first and second fence sections. A pair of vibration sensing modules are used to detect intruders, one applied to the first fence section and a second applied to the third fence section, with the first fence section positioned on the secure end of the protected zone. | 2009-01-08 |
20090008620 | Nonvolatile Memory Cells Employing a Transition Metal Oxide Layers as a Data Storage Material Layer and Methods of Manufacturing the Same - Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer are provided. The non-volatile memory cells include a lower and upper electrodes overlapped with each other. A transition metal oxide layer pattern is provided between the lower and upper electrodes. The transition metal oxide layer pattern is represented by a chemical formula M | 2009-01-08 |
20090008621 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element is provided. The phase-change memory element of an embodiment of the invention comprises a phase-change material layer with a concave, and a heater with an extended part, wherein the extended part of the heater is wedged in the concave of the phase-change material layer. Specifically, the extended part of the heater has a length of 10˜5000 Å. | 2009-01-08 |
20090008622 | Phase Change Memory Devices and Methods of Fabricating the Same - Phase change memory devices are provided including a selection element electrically connected to a phase change material pattern. The selection element includes a metallic conductor and a semiconductor that are in contact with each other. A depletion region in contact with a metallic pattern is generated in the semiconductor in an equilibrium state. The depletion region includes a high barrier region having an electric potential barrier higher than an interface electric potential barrier and a low barrier region having an electric potential barrier lower than the interface electric potential barrier. Related methods are also provided. | 2009-01-08 |
20090008623 | Methods of fabricating nonvolatile memory device and a nonvolatile memory device - Methods of fabricating a nonvolatile memory device using a resistance material and a nonvolatile memory device are provided. According to example embodiments, a method of fabricating a nonvolatile memory device may include forming at least one semiconductor pattern on a substrate, forming a metal layer on the at least one semiconductor pattern, forming a mixed-phase metal silicide layer, in which at least two phases coexist, by performing at least one heat treatment on the substrate so that the at least one semiconductor pattern may react with the metal layer, and exposing the substrate to an etching gas. | 2009-01-08 |
20090008624 | Optoelectronic device - The present invention provides an optoelectronic device, which includes a first electrode, a substrate on the first electrode, and a buffer layer on the substrate. The buffer layer further includes a first gallium nitride based compound layer on the substrate, a II-V group compound layer on the first gallium nitride based compound layer, a second gallium nitride based compound layer on the II-V group compound layer, and a third gallium nitride based compound layer on the second gallium nitride based compound layer. Then, a first semiconductor conductive layer is formed on the buffer layer; an active layer is formed on the first semiconductor conductive layer, in which the active layer is an uneven Multi-Quantum Well; a second semiconductor conductive layer on the active layer; a transparent conductive layer on the second semiconductor conductive layer; and a second electrode on the transparent conductive layer. | 2009-01-08 |
20090008625 | Optoelectronic device - The present invention provides an optoelectronic device, which includes a substrate having a first surface and a second surface, and an atomization layer located therebetween; a multi-layer semiconductor layer is formed on the first surface of the substrate, which further includes a first semiconductor structure that is formed on the substrate, a second semiconductor structure, and an active layer is located between the first semiconductor structure and the second semiconductor structure. | 2009-01-08 |
20090008626 | Optoelectronic device - The present invention provides an optoelectronic device which includes a first electrode, a substrate on the first electrode; a buffer layer on the substrate, in which the buffer layer includes a first gallium nitride based compound layer on the substrate, a second gallium nitride based compound layer, and a II-V group compound layer between the first gallium nitride based compound layer and the second gallium nitride based compound layer; a first semiconductor conductive layer on the buffer layer; an active layer on the first semiconductor conductive layer, in which the active layer is an uneven Multi-Quantum Well; a semiconductor conductive layer on the active layer; a transparent layer on the second semiconductor conductive layer; and a second electrode on the transparent layer. | 2009-01-08 |
20090008627 | Luminous device and method of manufacturing the same - A luminous device and a method of manufacturing the luminous device are provided. The luminous device includes a light emitting layer and first and second electrodes connected to the light emitting layer. The light emitting layer is a strained nanowire. | 2009-01-08 |
20090008628 | LIGHT-EMITTING DEVICE AND LIGHT-RECEIVING DEVICE USING TRANSISTOR STRUCTURE - Disclosed is a light-emitting device using a transistor structure, including a substrate, a first gate electrode, a first insulating layer, a source electrode, a drain electrode, and a light-emitting layer formed between the source electrode and the drain electrode in a direction parallel to these electrodes. In the light-emitting device using the transistor structure, it is possible to adjust the mobility of electrons or holes and to selectively set a light-emitting region through the control of the magnitude of voltage applied to the gate electrode, thus increasing the lifespan of the light-emitting device, facilitating the manufacturing process thereof, and realizing light-emitting or light-receiving properties having high efficiency and high purity. | 2009-01-08 |
20090008629 | N-TYPE TRANSISTOR, PRODUCTION METHODS FOR N-TYPE TRANSISTOR AND N-TYPE TRANSISTOR-USE CHANNEL, AND PRODUCTION METHOD OF NANOTUBE STRUCTURE EXHIBITING N-TYPE SEMICONDUCTOR-LIKE CHARACTERISTICS - An object of the present invention is to provide a new n-type transistor, different from the prior art, using a channel having a nanotube-shaped structure, and having n-type semiconductive properties. To realize this, a film of a nitrogenous compound | 2009-01-08 |
20090008630 | TUNNELING TRANSISTOR WITH BARRIER - The invention suggests a transistor ( | 2009-01-08 |
20090008631 | NANOWIRE TUNNELING TRANSISTOR - A transistor comprises a nanowire ( | 2009-01-08 |
20090008632 | SUPERCONDUCTING SHIELDING FOR USE WITH AN INTEGRATED CIRCUIT FOR QUANTUM COMPUTING - An integrated circuit for quantum computing may include a superconducting shield to limit magnetic field interactions. | 2009-01-08 |
20090008633 | NONVOLATILE MEMORY DEVICE USING CONDUCTIVE ORGANIC POLYMER HAVING NANOCRYSTALS EMBEDDED THEREIN AND METHOD OF MANUFACTURING THE NONVLATILE MEMORY DEVICE - A nonvolatile memory device and a method of manufacturing the same are provided. The nonvolatile memory device which is convertible among a high current state, an intermediate current state, and a low current state, said device includes upper and lower conductive layers; a conductive organic layer comprising a conductive organic polymer and which is formed between the upper and lower conductive layers and has a bistable conduction property; and nanocrystals are formed in the conductive organic layer. The conductive organic polymer may be poly-N-vinylcarbazole (PVK) or polystyrene (PS). The method is characterized in that a conductive organic layer is formed by applying a conductive organic material such as PVK or PS using spin coating. Therefore, it is possible to provide a highly-integrated memory device that consumes less power and provides high operating speed. In addition, it is possible to provide the thermal stability of a memory device by using a conductive organic polymer. Moreover, it is possible to reduce the time required to deposit a conductive organic layer by forming a conductive layer using spin coating. Furthermore, it is possible to form a conductive organic layer in various shapes by using mask patterns that can be formed on a substrate in various shapes. | 2009-01-08 |
20090008634 | Transistor Structures and Methods of Fabrication Thereof - An electronic device is presented, such as a thin film transistor. The device comprises a patterned electrically-conductive layer associated with an active element of the electronic device. The electrically-conductive layer has a pattern defining an array of spaced-apart electrically conductive regions. This technique allows for increasing an electric current through the device. | 2009-01-08 |
20090008635 | COLUMNAR ELECTRIC DEVICE AND PRODUCTION METHOD THEREOF - A sensor whose size can be decreased without marring the performance and which can be installed in a narrow place, an electric device, and a method for easily manufacturing the electric device. By vacuum deposition of semiconductor on a columnar body or by applying a melt, solution, or gel of semiconductor to the columnar body, a coating of semiconductor is formed. Four insulating wires, a stripe band of the connected four insulating wires are wound around the columnar body. Then, one of the insulating wires is removed to form a copper wire in the vacant portion by copper vacuum deposition. Lastly, another insulating wire not adjacent to the copper wire is removed to form an aluminum wire in the vacant portion by aluminum vacuum deposition. By measuring the resistance between the copper and aluminum wires, the intensity of light striking the semiconductor can be determined. | 2009-01-08 |
20090008636 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device that includes a phase change material for protecting the device from failure caused by overheating. The semiconductor device is adapted to detect a rapid increase in current due to heat and also adapted to break a circuit in the detected rapid increase in current by depositing a phase change material inside or outside a cell actually operated in the semiconductor device. | 2009-01-08 |
20090008637 | METHODS OF FABRICATING NANOSTRUCTURED ZnO ELECTRODES FOR EFFICIENT DYE SENSITIZED SOLAR CELLS - The present invention provides methods of forming metal oxide semiconductor nanostructures and, in particular, zinc oxide (ZnO) semiconductor nanostructures, possessing high surface area, plant-like morphologies on a variety of substrates. Optoelectronic devices, such as photovoltaic cells, incorporating the nanostructures are also provided. | 2009-01-08 |
20090008638 | Oxide semiconductor, thin film transistor including the same and method of manufacturing a thin film transistor - Example embodiments relate to an oxide semiconductor including zinc oxide (ZnO), a thin film transistor including a channel formed of the oxide semiconductor and a method of manufacturing the thin film transistor. The oxide semiconductor may include a Ga | 2009-01-08 |
20090008639 | Semiconductor Device and Manufacturing Method Thereof - An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region. | 2009-01-08 |
20090008640 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of bonding pads as bonding option, and a test circuit for performing an operation test using particular bonding pads and testing interconnects connecting internal circuits to the remaining bonding pads which are not used in the operation test. | 2009-01-08 |
20090008641 | Probe resistance measurement method and semiconductor device with pads for probe resistance measurement - A probe resistance measuring method includes measuring first resistances at three or more nodes by making contact at least a part of a plurality of probes of a probe unit with three or more pads for resistance measurement based on a first correspondence relation. The measured resistances are stored as a first measurement result and contact resistances of the plurality of probes of the probe unit are calculated based on the first measurement result. | 2009-01-08 |
20090008642 | DISPLAY DEVICE - A display device is disclosed. The display device includes a substrate, a display area on the substrate, the display area including a plurality of subpixels, a pad area on the substrate, the pad area including a pad electrode, a conductive adhesive layer on the pad electrode, and a driver on the conductive adhesive layer, the driver being attached to the pad electrode using the conductive adhesive layer. One surface of the conductive adhesive layer includes one surface of the driver. A vertical distance ranging from a shorter side of one surface of the driver to a shorter side of one surface of the conductive adhesive layer lies substantially in a range between 0.2 mm and 4 mm. | 2009-01-08 |
20090008643 | Light Emitting Device, Method of Manufacturing the Same, and Manufacturing Apparatus Therefor - A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision. | 2009-01-08 |
20090008644 | THIN FILM TRANSISTOR SUBSTRATE AND LIQUID CRYSTAL DISPLAY - A TFT substrate comprises a substrate, a gate electrode and a lower electrode of a capacitor formed thereon, a first insulating layer formed thereon, a channel layer above the gate electrode and a lower layer of an upper electrode of the capacitor, a channel protection layer formed on an intermediate part of said channel layer and a capacitor protection layer formed on a connection region of the lower layer, source/drain electrodes formed on said channel layer and an upper layer of the upper electrode of the capacitor formed on the lower layer and covering the capacitor protection layer, a second insulating layer covering them, a first connection hole exposing the source electrode and a second connection hole exposing a connection region of said upper layer, which are penetrating the second insulating layer, and a pixel electrode formed thereon. | 2009-01-08 |
20090008645 | Light-emitting device - A method of manufacturing, with high mass productivity, light-emitting devices having highly reliable thin film transistors with excellent electric characteristics is provided. In a light-emitting device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions. | 2009-01-08 |
20090008646 | Display substrate, method of manufacturing the same, and display device having the same - A display substrate includes a switching member, a color filter layer, an inorganic insulation layer and a pixel electrode. The switching member includes a gate line, a data line crossing the gate line, and a thin-film transistor (TFT) electrically connected to the gate line and the data line. The color filter layer is formed on the switching member. The inorganic insulation layer is formed on the color filter layer. The inorganic insulation layer has a hole formed thereon, which exposes a portion of the color filter layer in correspondence with the TFT The pixel electrode is formed on the inorganic insulation layer. | 2009-01-08 |
20090008647 | Gallium nitride-on-silicon interface using multiple aluminum compound buffer layers - A thermal expansion interface between silicon (Si) and gallium nitride (GaN) films using multiple buffer layers of aluminum compounds has been provided, along with an associated fabrication method. The method provides a (111) Si substrate and deposits a first layer of AlN overlying the substrate by heating the substrate to a relatively high temperature of 1000 to 1200° C. A second layer of AlN is deposited overlying the first layer of AlN at a lower temperature of 500 to 800° C. A third layer of AlN is deposited overlying the second layer of AlN by heating the substrate to the higher temperature range. Then, a grading Al | 2009-01-08 |
20090008648 | GALLIUM NITRIDE-BASED SEMICONDUCTOR ELEMENT, OPTICAL DEVICE USING THE SAME, AND IMAGE DISPLAY APPARATUS USING OPTICAL DEVICE - A GaN-based semiconductor element which can suppress a leakage current generated during reverse bias application, an optical device using the same, and an image display apparatus using the optical device are provided. The GaN-based semiconductor element has a first GaN-based compound layer including an n-type conductive layer; a second GaN-based compound layer including a p-type conductive layer; and an active layer provided between the first GaN-based compound layer and the second GaN-based compound layer. In this GaN-based semiconductor element, the first GaN-based compound layer includes an underlayer having an n-type impurity concentration in the range of 3×10 | 2009-01-08 |
20090008649 | Silicon carbide semiconductor device and method of manufacturing the same - A silicon carbide semiconductor device includes a substrate having one of a first conductivity type and a second conductivity type, a drift layer having the first conductivity type, a plurality of base regions having the second conductivity type, a plurality of source regions having the first conductivity type, a surface channel layer having the first conductivity type, a plurality of body layers having the second conductivity type, a gate insulation layer, a gate electrode, a first electrode, a second electrode, and a plurality of second conductivity-type regions. The first electrode is electrically coupled with the source regions and the body layers. The second conductivity-type regions are disposed at portions of the drift layer located under the body layers so as to be connected with the base regions respectively. | 2009-01-08 |
20090008650 | FIELD-EFFECT TRANSISTOR AND THYRISTOR - A decrease in breakdown voltage can be prevented as much as possible. A field-effect transistor includes: a drain region made of SiC; a drift layer which is formed on the drain region and is made of n-type SiC; a source region which is formed on the surface of the drift layer and is made of n-type SiC; a channel region which is formed on the surface of the drift layer located on a side of the source region and is made of SiC; an insulating gate which is formed on the channel region; and a p-type base region interposed between the bottom portion of the source region and the drift region, and containing two kinds of p-type impurities. | 2009-01-08 |
20090008651 | Silicon carbide semiconductor device having junction barrier schottky diode - A silicon carbide semiconductor device includes a drift layer having first conductive type on a substrate, a cell region in the drift layer, a schottky electrode on the drift layer and multiple second conductive type layers in the cell region. The second conductive type layers are separated from each other and contact the schottky electrode. A size and an impurity concentration of the second conductive type layers and a size and an impurity concentration of a portion of the drift layer sandwiched between the second conductive type layers are determined so that a charge quantity of the second conductive type layers is equal to a charge quantity of the portion. Hereby, the pressure-proof JBS and low resistivity second conductive type layers arranged on a surface of the drift layer to provide a PN diode, can be obtained. | 2009-01-08 |
20090008652 | Free-Standing Substrate, Method for Producing the Same and Semiconductor Light-Emitting Device - The present invention provides a free-standing substrate, a method for producing the same and a semiconductor light-emitting device. The free-standing substrate comprises a semiconductor layer and inorganic particles, wherein the inorganic particles are included in the semiconductor layer. The method for producing a free-standing substrate comprises the steps of: (a) placing inorganic particles on a substrate, (b) growing a semiconductor layer thereon, and (c) separating the semiconductor layer from the substrate, in that order. The semiconductor light-emitting device comprises the free-standing substrate, a conductive layer, a light-emitting device, and electrodes. | 2009-01-08 |
20090008653 | LIGHT EMITTING DEVICE - A light emitting device includes an active layer including atoms A of a matrix semiconductor having a tetrahedral structure, a heteroatom D substituted for the atom A in a lattice site, and a heteroatom Z inserted into an interstitial site positioned closest to the heteroatom D, the heteroatom D having a valence electron number differing by +1 or −1 from that of the atom A, and the heteroatom Z having an electron configuration of a closed shell structure through charge compensation with the heteroatom D, and an n-electrode and a p-electrode adapted to supply a current to the active layer. | 2009-01-08 |
20090008654 | Semiconductor Light Emitting Device, Illumination Module, Illumination Apparatus, Method For Manufacturing Semiconductor Light Emitting Device, and Method For Manufacturing Semiconductor Light Emitting Element - A semiconductor light emitting device ( | 2009-01-08 |
20090008655 | White Light Source - A white light source ( | 2009-01-08 |
20090008656 | Penetrating hole type LED chip package structure using a ceramic material as a substrate and method for manufacturing the same - An LED chip package structure includes a ceramic substrate, a conductive unit, a hollow ceramic casing, many LED chips, and a package colloid. The ceramic substrate has a main body, many protrusions extended from the main body, many penetrating holes respectively penetrating through the protrusions, and many half through holes formed on a lateral side of the main body and respectively formed between each two protrusions. The conductive unit has many first conductive layers respectively formed on the protrusions, many second conductive layers respectively formed on inner surfaces of the half through holes and a bottom face of the main body, and many third conductive layers respectively filled in the penetrating holes. The hollow ceramic casing is fixed on the main body to form a receiving space. The LED chips is received in the receiving space. The package colloid is filled in the receiving space for covering the LED chips. | 2009-01-08 |
20090008657 | Semiconductor light-emitting device with low-density defects and method of fabricating the same - A semiconductor light-emitting device and a method of fabricating the same are provided. The semiconductor light-emitting device includes a substrate, a multi-layer structure and an ohmic electrode structure. The substrate has a first upper surface and a plurality of first recesses formed in the first upper surface. The multi-layer structure is formed on the first upper surface of the substrate and includes a light-emitting region. A bottom-most layer of the multi-layer structure is formed on the first upper surface of the substrate. The bottom-most layer has a second upper surface and a plurality of second recesses formed in the second upper surface. The second recesses project on the first upper surface. The ohmic electrode structure is formed on the multi-layer structure. | 2009-01-08 |
20090008658 | Infrared Emitting Diode and Method of Its Manufacture - An infrared emitting diode that can be utilized as a high power and rapidly responsive infrared light source for both infrared and remote control communications is disclosed which comprises at least one p-type clad layer containing Al | 2009-01-08 |
20090008659 | NITRIDE SEMICONDUCTOR STACKED STRUCTURE AND SEMICONDUCTOR OPTICAL DEVICE, AND METHODS FOR MANUFACTURING THE SAME - A nitride semiconductor stacked structure having good working efficiency includes a p-type nitride semiconductor layer of low resistance, which is formed from an organometallic compound, compounds including Group V elements, including ammonia and a hydrazine derivative, and a p-type impurity material on a substrate. The p-type nitride layer has a carbon concentration not higher than 1×10 | 2009-01-08 |
20090008660 | ZnO-CONTAINING SEMICONDUCTOR LAYER AND ZnO-CONTAINING SEMICONDUCTOR LIGHT EMITTING DEVICE - A ZnO-containing semiconductor layer contains Se or S added to ZnO and has an emission peak wavelength of ultraviolet light and an emission peak wavelength of visual light. By combining the ZnO-containing semiconductor layer with phosphor or semiconductor which is excited by the emitted ultraviolet light and emits visual light, visual light at various wavelengths can be emitted. | 2009-01-08 |
20090008661 | LIGHT-EMITTING DIODE AND FABRICATION METHOD THEREOF - A light-emitting diode ( | 2009-01-08 |
20090008662 | LIGHTING DEVICE PACKAGE - The invention provides a lighting device package with one or more light-emitting elements operatively coupled to a substrate; a compound lens disposed to interact with light emitted by the one or more light-emitting elements, the compound lens including at least an inner lens element and an outer lens element, the inner lens element having a first index of refraction and the outer lens element having a second index of refraction, the first index of refraction being greater than the second index of refraction; the compound lens, the one or more light-emitting elements and the substrate defining an enclosed space between them; and an encapsulation material filling at least part of said space, the encapsulation material having a third index of refraction equal or greater than the first index of refraction. | 2009-01-08 |
20090008663 | PHOSPHOR AND METHOD FOR PRODUCTION THEREOF, AND APPLICATION THEREOF - A phosphor containing a crystal phase having a chemical composition expressed by the following general formula [1], and exhibiting an average variation rate of the emission intensity of 1.3 or less upon excitation with light having a peak in the wavelength range of 420 nm to 480 nm, the variation rate of the emission intensity being calculated by the following general formula [2]. | 2009-01-08 |
20090008664 | NANOWIRE LIGHT EMITTING DEVICE - A nanowire light emitting device is provided. The nanowire light emitting device includes a substrate, a first conductive layer formed on the substrate, a plurality of nanowires vertically formed on the first conductive layer, each nanowire comprising a p-doped portion and an n-doped portion, a light emitting layer between the p-doped portion and the n-doped portion, a second conductive layer formed on the nanowires, and an insulating polymer in which a light emitting material is embedded, filling a space between the nanowires. The color of light emitted from the light emitting layer varies according to the light emitting material. | 2009-01-08 |
20090008665 | ORGANIC LIGHT EMITTING ELEMENT AND METHOD OF MANUFACTURING THE SAME - An organic light emitting element includes an organic light emitting diode formed on a substrate, coupled to a transistor including a gate, a source and a drain and including a first electrode, an organic thin film layer and a second electrode; a photo diode formed on the substrate and having a semiconductor layer including a high-concentration P doping region, a low-concentration P doping region, an intrinsic region and a high-concentration N doping region; and a controller that controls luminance of light emitted from the organic light emitting diode, to a constant level by controlling a voltage applied to the first electrode and the second electrode according to the voltage outputted from the photo diode. | 2009-01-08 |
20090008666 | OPTICAL SEMICONDUCTOR DEVICE - A semiconductor light-emitting element is disposed in a depression of a container. A first fluorescent material layer is located in the depression. At least a portion of the first fluorescent material layer is provided between the opening of the depression and the semiconductor light-emitting element. A second fluorescent material layer having first and second portions is disposed in the depression. The first portion is provided between the bottom of the depression and the semiconductor light-emitting element. The second portion is provided between the side surface of the depression and the semiconductor light-emitting element. The first and second fluorescent material layers are excited by the light radiated from the semiconductor light-emitting element to emit a light having a first wavelength longer than the emission wavelength of the semiconductor light-emitting element and another light having a second wavelength longer than the first wavelength respectively. | 2009-01-08 |
20090008667 | METHOD FOR FORMING PATTERN, METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE, AND LIGHT EMITTING DEVICE - Oxidation treatment is performed to the surface of a substrate provided with a photocatalytic conductive film and an insulating film; treatment with a silane coupling agent is performed, so that a silane coupling agent film is formed and the surface of the substrate is modified to be liquid-repellent; and the surface of the substrate is irradiated with light of a wavelength (less than to equal to 390 nm) which has energy of greater than or equal to a band gap of a material for forming the photocatalytic conductive film, so that only the silane coupling agent film over the surface of the photocatalytic conductive film is decomposed and the surface of the photocatalytic conductive film can be modified to be lyophilic. | 2009-01-08 |
20090008668 | Semiconductor Light Emitting Device and Method for Fabricating the Same - A semiconductor light emitting device, which includes: a first conductivity-type semiconductor layer; a second conductivity-type semiconductor layer; a semiconductor light emitting portion having a light emitting layer which is disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer; a first conductivity-type semiconductor side electrode connected to the first conductivity-type semiconductor layer; and a second conductivity-type semiconductor side electrode connected to the second conductivity-type semiconductor layer, wherein the second conductivity-type semiconductor side electrode is disposed separated from an insulator film covering the semiconductor light emitting portion by a separation area. | 2009-01-08 |
20090008669 | Package for micromirror device - The present invention discloses a mirror device that includes a mirror element which further comprising an elastic hinge and a mirror and which modulates incident light emitted from a light source, a device substrate on which a drive circuit for driving the mirror element is placed, a package substrate which is made of transparent glass or a silicon material and on which the device substrate is placed, a metallic thermal transfer path connected to the device substrate, and a cover glass connected to the package substrate so that the device substrate is covered. | 2009-01-08 |
20090008670 | LED packaging structure with aluminum board and an LED lamp with said LED packaging structure - An LED lamp is provided. The LED lamp has an aluminum board, a semiconductor substrate, at least a LED chip, a metal layer structure, and heat sink. The aluminum board has a cup structure thereon. The semiconductor substrate is assembled on a bottom surface of the cup structure. The LED chips are assembled on the semiconductor substrate. The metal layer structure is formed on a bottom surface of the aluminum board. The metal layer structure is composed of solderable materials. The heat sink is connected to the metal layer structure through solder joint. | 2009-01-08 |
20090008671 | LED packaging structure with aluminum board and an LED lamp with said LED packaging structure - An LED lamp is provided. The LED lamp has an aluminum board, a buffer substrate, at least a LED chip, a metal layer structure, and heat sink. The aluminum board has a cup structure thereon. The buffer substrate is assembled on a bottom surface of the cup structure. The LED chips are assembled on the buffer substrate. The metal layer structure is formed on a bottom surface of the aluminum board. The metal layer structure is composed of solderable materials. The heat sink is connected to the metal layer structure through solder joint. | 2009-01-08 |
20090008672 | LIGHT-EMITTING DEVICE, MANUFACTURING METHOD THEREOF, AND LAMP - There is provided a light-emitting device having high reliability and excellent light extraction efficiency, a manufacturing method thereof, and a lamp. A light-emitting device includes a transparent electrode, wherein a titanium oxide-based conductive film is used for at least one layer of said transparent electrode, an emission wavelength is within a range of 300 to 550 nm, and a photocatalytic reaction-prevention layer is formed so as to cover said titanium oxide-based conductive film. | 2009-01-08 |
20090008673 | Semiconductor Light Emitting Device Member, Method for Manufacturing Such Semiconductor Light Emitting Device Member and Semiconductor Light Emitting Device Using Such Semiconductor Light Emitting Device Member - A semiconductor light-emitting device member excellent in transparency, light resistance, and heat resistance and capable of sealing a semiconductor light-emitting device without causing cracks and peeling even after a long-time use is provided. Therefore, a semiconductor light-emitting device member that comprises (1) in a solid Si-nuclear magnetic resonance spectrum, at least one peak selected from a group consisting of (i) peaks whose peak top position is in an area of a chemical shift of −40 ppm to 0 ppm inclusive, and whose full width at half maximum is 0.3 ppm to 3.0 ppm inclusive, and (ii) peaks whose peak top position is in an area of the chemical shift of −80 ppm or more and less than −40 ppm, and whose full width at half maximum is 0.3 ppm to 5.0 ppm inclusive, wherein (2) silicon content is 20 weight % or more and (3) silanol content is 0.1 weight % to 10 weight % inclusive is used. | 2009-01-08 |
20090008674 | DOUBLE GATE INSULATED GATE BIPOLAR TRANSISTOR - Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n− drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel. | 2009-01-08 |
20090008675 | SOI TRENCH LATERAL IGBT - To enable driving at a high withstand voltage and a large current, increase latchup immunity, and reduce ON resistance per unit area in an IGBT, a trench constituted by an upper stage trench and a lower stage trench is formed over an entire wafer surface between an n | 2009-01-08 |
20090008676 | NORMALLY-OFF FIELD-EFFECT SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATION - A normally-off HEMT is made by first providing a substrate having its surface partly covered with an antigrowth mask. Gallium nitride is grown by epitaxy on the masked surface of the substrate to provide an electron transit layer comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections are formed on unmasked parts of the substrate surface whereas the V-notch-surfaced section, defining a V-sectioned notch, is created by lateral overgrowth onto the antigrowth mask. Aluminum gallium nitride is then deposited on the electron transit layer to provide an electron supply layer which is likewise comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections of the electron supply layer are sufficiently thick to normally generate two-dimensional electron gas layers due to heterojunctions thereof with the first and the second flat-surfaced section of the electron transit layer. The V-notch-surfaced section of the electron supply layer is not so thick, normally creating an interruption in the two-dimensional electron gas layer. | 2009-01-08 |
20090008677 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An AlN layer ( | 2009-01-08 |
20090008678 | SEMICONDUCTOR DEVICE - An electron supply layer ( | 2009-01-08 |
20090008679 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes, a first silicon layer of a first conductivity type; a second silicon layer provided on the first silicon layer and having a higher resistance than the first silicon layer, a third silicon layer of a second conductivity type provided on the second silicon layer, a first nitride semiconductor layer provided on the third silicon layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a larger bandgap than the first nitride semiconductor layer, a first main electrode being in contact with a surface of the second nitride semiconductor layer and connected to the third silicon layer, a second main electrode being in contact with the surface of the second nitride semiconductor layer and connected to the first silicon layer, and a control electrode provided between the first main electrode and the second main electrode on the second nitride semiconductor layer. | 2009-01-08 |
20090008680 | SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a semiconductor chip, a memory cell array arranged on the semiconductor chip and first and second decoder strings arranged along both ends of the memory cell array. The arrangement position of the first decoder string is deviated from the arrangement position of the second decoder string and a space caused by the deviation is arranged in the corner of the semiconductor chip. | 2009-01-08 |
20090008681 | ALKALOID SENSOR - An alkaloid sensor, systems comprising the same, and measurement using the systems. The alkaloid sensor has an extended gate field effect transistor (EGFET) structure and comprises a metal oxide semiconductor field effect transistor (MOSFET) on a semiconductor substrate, a sensing unit comprising a substrate, a tin oxide film on the substrate, and an alkaloid acylase film immobilized on the tin oxide film, and a conductive wire connecting the MOSFET and the sensing unit. | 2009-01-08 |
20090008682 | Light-Receiving Device - Disclosed is a light-receiving device comprising a substrate provided with at least one light-receiving element and a transparent cover ( | 2009-01-08 |
20090008683 | IMAGING APPARATUS - An imaging apparatus comprises: a semiconductor imaging device having a plurality of photodiodes and a color filter; and an imaging optical system for guiding light from a subject to the semiconductor imaging device, where a diameter of an aperture ( | 2009-01-08 |
20090008684 | PHOTOELECTRIC CONVERSION DEVICE, METHOD OF MANUFACTURING THE SAME, AND IMAGE SENSING SYSTEM - A photoelectric conversion device comprises a photoelectric conversion unit, a floating diffusion region, a transfer transistor, and an output unit. A control electrode of the transfer transistor includes a first portion which extends along a channel width direction and overlaps a first boundary side when seen through from a direction perpendicular to a light receiving surface of the photoelectric conversion unit, and a second portion which extends along a channel length direction from one end of the first portion and overlaps a second boundary side when seen through from the direction perpendicular to the light receiving surface, and the control electrode of the transfer transistor has an L shape when viewed from the direction perpendicular to the light receiving surface. | 2009-01-08 |
20090008685 | Image Sensor and Controlling Method Thereof - A controlling method of an image sensor is disclosed. The method includes: measuring a first output voltage of a drive transistor, a gate of which is combined to a floating diffusion region, after a predetermined integration time; resetting the floating diffusion region by turning on a reset transistor connected between the floating diffusion region and a power supply group; measuring a reference voltage outputted from the drive transistor; transferring electric charges generated in a photo diode by sensing light inputted from the outside to the floating diffusion region by turning on a transfer transistor connected to the photo diode; and measuring a second output voltage of the drive transistor; wherein an image is generated by using a voltage difference between the first output voltage and the reference voltage, and a voltage difference between the second output voltage and the reference voltage. | 2009-01-08 |
20090008686 | SOLID-STATE IMAGING DEVICE WITH IMPROVED CHARGE TRANSFER EFFICIENCY - A transfer gate is formed such that both end portions thereof in a second direction, which crosses a first direction in which a photodiode and a floating diffusion layer that is formed with a distance from the photodiode are arranged, are located inside boundaries with element isolation regions. Channel stopper layers are formed on surface portions of a device region in the vicinity of lower parts of both end portions of the transfer gate in the second direction in such a manner to extend to the boundaries with the element isolation regions. | 2009-01-08 |
20090008687 | SOLID-STATE IMAGING DEVICE AND METHOD FOR FABRICATING THE SAME - A solid-state imaging device includes: an imaging area in which light receiving portions are disposed; an interconnect layer disposed on the light receiving portions, the interconnect layer including metal interconnects having openings and first insulating films; inner-layer lenses formed over the interconnect layer in one-to-one relationship with the light receiving portions; a transparent second insulating film formed on the interconnect layer and the inner-layer lenses; top lenses formed on the second insulating film in one-to-one relationship with the light receiving portions, an upper face of each of the top lenses being a convexly curved face; and a transparent film on the top lenses, the transparent film being formed of a material having a refractive index smaller than a refractive index of the top lenses. In this way, a focal point of at least part of incident light can be situated above a semiconductor substrate. | 2009-01-08 |
20090008688 | Unit pixels, image sensors and methods of manufacturing the same - Unit pixels, image sensors and methods for fabricating the image sensor are provided. A unit pixel includes: a photodiode for accumulating photocharges; a floating diffusion region for detecting the photocharges accumulated in the photodiode; a reset element for periodically resetting the floating diffusion region; a drive element for amplifying the photocharges accumulated in the floating diffusion region; a selection element for selecting the unit pixel; and a silicide layer formed on top surfaces of the transfer gate. The photocharges are transferred to the floating diffusion region via a transfer gate. | 2009-01-08 |
20090008689 | Spin Transistor Using Ferromagnet - A spin transistor comprises a semiconductor substrate part having a lower cladding layer, a channel layer and an upper cladding layer sequentially stacked therein, a ferromagnetic source and drain on the substrate part, and a gate on the substrate part to control spins of electrons passing through the channel layer. The lower cladding layer comprises a first lower cladding layer and a second lower cladding layer having a higher band gap than that of the first lower cladding layer. The upper cladding layer comprises a first upper cladding layer and a second upper cladding layer having a higher band gap than that of the first upper cladding layer. The source and the drain are buried in an upper surface of the substrate part and extend downwardly to or under the first upper cladding layer. | 2009-01-08 |
20090008690 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - The data retention characteristics of a nonvolatile memory circuit are improved. In a memory cell array on a main surface of a semiconductor substrate, a floating gate electrode for accumulating charges for information is arranged. The floating gate electrode is covered with a cap insulating film and a pattern of an insulating film | 2009-01-08 |
20090008691 | DRAM STRUCTURE AND METHOD OF MAKING THE SAME - A DRAM structure has a substrate, a buried transistor with a fin structure, a trench capacitor, and a surface strap on the surface of the substrate. The surface strap is used to electrically connect a drain region to the trench capacitor. | 2009-01-08 |
20090008692 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness. | 2009-01-08 |
20090008693 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate ( | 2009-01-08 |
20090008694 | Integrated circuit and corresponding manufacturing method - The present invention provides an integrated circuit including a field effect transistor formed in an active area segment of a semiconductor substrate, the transistor comprising:
| 2009-01-08 |
20090008695 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is provided. The semiconductor device comprises a substrate. A lamination structure is on the substrate along a first direction. The lamination structure comprises a plurality of conductive layers arranged from bottom to top and separated from each other, and each of the conductive layers has a channel region and an adjacent source/drain doped region along the first direction. A first gate structure is on a sidewall of the channel region of each conductive layer. The first gate structure comprises an inner first gate insulating layer and an outer first gate conductive layer. | 2009-01-08 |
20090008696 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate. | 2009-01-08 |
20090008697 | SRAM CELLS WITH REPRESSED FLOATING GATE MEMORY, LOW TUNNEL BARRIER INTERPOLY INSULATORS - Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell which can be programmed to provide the SRAM cell with a definitive asymmetry so that the cell always starts in a particular state. The SRAM cells include a pair of cross coupled transistors. At least one of the cross coupled transistors includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. | 2009-01-08 |
20090008698 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAM - A nonvolatile memory device includes an active region which is defined by an isolation layer formed in a substrate and has a recess therein in a channel width direction, wherein an upper portion of the active region having the recess projects over an upper portion of the isolation layer, a lower insulation layer formed along a surface of the active region and a top surface of the isolation layer, a charge storage layer formed over the lower insulation layer, an upper insulation layer formed over the charge storage layer, and a gate electrode formed over the upper insulation layer. | 2009-01-08 |
20090008699 | Non-volatile semiconductor memory device and method of manufacturing the same - Example embodiments relate to a non-volatile semiconductor memory device and a method of manufacturing the same. A semiconductor device includes an isolation layer protruding from a substrate, a spacer, a tunnel insulation layer, a floating gate, a dielectric layer pattern and a control gate. The spacer may be formed on a sidewall of a protruding portion of the isolation layer. The tunnel insulation layer may be formed on the substrate between adjacent isolation layers. The floating gate may be formed on the tunnel insulation layer. The floating gate contacts the spacer and has a width that gradually increases from a lower portion toward an upper portion. The dielectric layer pattern and the control gate may be sequentially formed on the floating gate. | 2009-01-08 |
20090008700 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - In methods of manufacturing a memory device, a tunnel insulation layer is formed on a substrate. A floating gate having a substantially uniform thickness is formed on the tunnel insulation layer. A dielectric layer is formed on the floating gate. A control gate is formed on the dielectric layer. A flash memory device including the floating gate may have more uniform operating characteristics. | 2009-01-08 |
20090008701 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device includes a semiconductor substrate, a charge trap layer formed on the semiconductor substrate, a blocking layer formed on the charge trap layer, and a gate electrode formed on the blocking layer. Sides of blocking layer extend laterally beyond sides of the charge trap layer and lateral sides of the gate electrode. | 2009-01-08 |
20090008702 | DIELECTRIC CHARGE-TRAPPING MATERIALS HAVING DOPED METAL SITES - Dielectric materials having implanted metal sites and methods of their fabrication have been described. Such materials are suitable for use as charge-trapping nodes of non-volatile memory cells for memory devices. By incorporating metal sites into dielectric charge-trapping materials using an ammonia plasma and a metal source in contact with the plasma, improved programming and erase voltages may be facilitated. | 2009-01-08 |
20090008703 | NON-VOLATILE MEMORY CELL AND FABRICATING METHOD THEREOF - A super-silicon-rich oxide (SSRO) non-volatile memory cell includes a gate conductive layer on a substrate, a source/drain in the substrate at respective sides of the gate conductive layer, a tunneling dielectric layer between the gate conductive layer and the substrate, a SSRO layer serving as a charge trapping layer between the gate conductive layer and the tunneling dielectric layer, and an upper-dielectric layer between the gate conductive layer and the SSRO layer. | 2009-01-08 |
20090008704 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor substrate having a projection, an upper end portion of the projection being curved, a first element isolation insulating film formed on the substrate surface at the root of the projection, having an upper surface lower than an upper surface of the projection, a second element isolation insulating film formed in the projection, a gate insulating film formed on the projection, and including a charge storage layer, and a gate electrode formed on the gate insulating film. A height of a first portion where the gate electrode is in contact with the gate insulating film above the upper surface of the first element isolation insulating film is smaller than that of a second portion where the gate electrode is in contact with the gate insulating film above an upper end of the second element isolation insulating film. | 2009-01-08 |
20090008705 | BODY-CONTACTED FINFET - A silicon containing fin is formed on a semiconductor substrate. A silicon oxide layer is formed around the bottom of the silicon containing fin. A gate dielectric is formed on the silicon containing fin followed by formation of a gate electrode. While protecting the portion of the semiconductor fin around the channel, a bottom portion of the silicon containing semiconductor fin is etched by a isotropic etch leaving a body strap between the channel of a finFET on the silicon containing fin and an underlying semiconductor layer underneath the silicon oxide layer. The fin may comprise a stack of inhomogeneous layers in which a bottom layer is etched selectively to a top semiconductor layer. Alternatively, the fin may comprise a homogeneous semiconductor material and the silicon containing fin may be protected by dielectric films on the sidewalls and top surfaces of the silicon containing fin. | 2009-01-08 |
20090008706 | Power Semiconductor Devices with Shield and Gate Contacts and Methods of Manufacture - A semiconductor power device includes active trenches that define an active area and an edge area that is located outside of the active area. The active trenches include a lower shield poly, an upper gate poly, a first oxide layer and a second oxide layer wherein the first oxide layer separates the lower shield poly from the upper gate poly and the second oxide layer covers the upper gate poly. The lower shield poly, upper gate poly, first oxide layer and second oxide layer conform to the shape of the active trench and extend from the active trench to a surface of the edge area. The edge area includes a first opening that extends through the first oxide layer to the lower shield poly and a second opening that extends through the second oxide layer to the upper gate poly. The first opening is filled with a conductive material that makes electrical contact with the lower shield poly and the second opening is filled with conductive material that makes electrical contact with the upper gate poly. The lower shield poly is electrically insulated from the substrate. The second oxide layer can be directly over the upper gate poly, the upper gate poly can be directly over the first oxide layer, the first oxide layer can be directly over the lower shield poly, and the first opening can be lower than the second opening. The device can further include a perimeter trench with extensions in the longitudinal direction that are staggered with respect to the active trenches so that there can be offset between the extensions of the perimeter trench and the active trenches. | 2009-01-08 |
20090008707 | SRAM DEVICE - An integrated circuit device has a base area defining a longitudinal axis. Four in-line transistors, which are NMOS transistors in exemplary embodiments, are each centered on the longitudinal axis. Two off-set transistors, which are PMOS transistors in exemplary embodiments, are off-set to first and second sides of the longitudinal axis, respectively. | 2009-01-08 |