01st week of 2010 patent applcation highlights part 53 |
Patent application number | Title | Published |
20100005213 | Access Table Lookup for Bus Bridge - Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master port. The caching registers may allow for a rapid lookup of one or more access table entries associated with each master, as well as allow for the simultaneous lookup by multiple masters without adding ports to the access table. A segment identifier may be stored in the caching registers to indicate how to route a matching request to the appropriate slave segment. | 2010-01-07 |
20100005214 | ENHANCING BUS EFFICIENCY IN A MEMORY SYSTEM - A communication interface device, system, method, and design structure for enhancing bus efficiency and utilization in a memory system. The communication interface device includes a first bus interface to communicate on a high-speed bus, a second bus interface to communicate on a lower-speed bus, and clock ratio logic configurable to support multiple clock ratios between the high-speed bus and the lower-speed bus. The clock ratio logic reduces a high-speed clock frequency received at the first bus interface and outputs a reduced ratio of the high-speed clock frequency on the lower-speed bus via the second bus interface supporting variable frame sizes. | 2010-01-07 |
20100005215 | Control Unit Including a Computing Device and a Peripheral Module which are Interconnected via a Serial Multiwire Bus - A control unit includes at least one computing device and at least one separate peripheral module which is connected to the computing device via a serial multiwire bus, the peripheral module including at least one output stage for transferring serial data to means outside of the control unit. In order to keep the number of pins required on a peripheral module to a minimum, thereby reducing costs for the entire control unit, the peripheral module has an asynchronous single-wire interface between one interface for the serial multiwire bus and the output stage. The asynchronous single-wire interface is preferably a UART (universal asynchronous receiver/transmitter) interface. The serial multiwire bus is preferably a microsecond bus. | 2010-01-07 |
20100005216 | DOUBLE NETWORK PHYSICAL ISOLATION CIRCUIT - A double network physical isolation circuit includes a north bridge chip, a bus switch circuit, a first memory, and a second memory. The bus switch circuit includes a first and a second bus switch chip. The first and second memories are connected to different networks. The north bridge chip is connected to the first and second memory. When the bus switch circuit receives a high level signal, the first input pin of the first bus switch chip is in electrical communication with the first output pin of the first bus switch chip, and the first memory is activated. The second memory is grounded through the second bus switch chip. When the bus switch circuit receives a low level signal, the second input pin is in electrical communication with the second output pin of the first bus switch chip, and the second memory is activated. The first memory is grounded through the second bus switch chip. | 2010-01-07 |
20100005217 | MULTI-MODE MEMORY DEVICE AND METHOD - Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice. | 2010-01-07 |
20100005218 | ENHANCED CASCADE INTERCONNECTED MEMORY SYSTEM - A system, memory hub device, method and design structure for providing an enhanced cascade interconnected memory system are provided. The system includes a memory controller, a memory channel, a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device, and multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices. The memory channel includes unidirectional downstream link segments coupled to the memory controller and operable for transferring configurable data frames. The memory channel further includes unidirectional upstream link segments coupled to the memory controller and operable for transferring data frames. | 2010-01-07 |
20100005219 | 276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES - A memory module including a plurality of memory channel connectors for communicating with a memory controller via a plurality of high-speed channels. The memory module also includes a plurality of memory devices arranged in one or more ranks, and a plurality of independently operable hub devices. Each hub device includes an interface for receiving signals from and driving signals to the memory controller on one of the high-speed channels via one or more of the memory channel connectors. Each hub device also includes a plurality of independently operable ports to communicate with all or a subset of the ranks of memory devices. | 2010-01-07 |
20100005220 | 276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES - A memory module that includes a first group of memory devices arranged in one or more ranks and a second group of memory devices arranged in one or more ranks. The memory module also includes a first and second port, wherein the first port is operable simultaneously with and independently of the second port. The memory module further includes a first memory device bus in communication with the first port and the first group of memory devices, and a second memory device bus in communication with the second port and the second group of memory devices. The memory module further includes a hub device configured to re-drive information in a cascade interconnect system. The hub device includes logic for reading data from and writing data to the ranks of memory devices via the first and second ports and the first and second memory device buses. | 2010-01-07 |
20100005221 | Address generation for multiple access of memory - A memory bank has a plurality of memories. In an embodiment, a forward unit applies logical memory addresses to the memory bank in a forward twofold access order, a backward unit applies logical memory addresses to the memory bank in a backward twofold access order, and a half butterfly network (at least half, and barrel shifters in 8-tuple embodiments) is disposed between the memory bank and the forward unit and the backward unit. A set of control signals is generated which are applied to the half or more butterfly network (and to the barrel shifters where present) so as to access the memory bank with an n-tuple parallelism in a linear order in a first instance, and a quadratic polynomial order in a second instance, where n=2, 4, 8, 16, 32, . . . . This access is for any n-tuple of the logical addresses, and is without memory access conflict. In this manner memory access may be controlled data decoding. | 2010-01-07 |
20100005222 | OPTIMIZING VIRTUAL MEMORY ALLOCATION IN A VIRTUAL MACHINE BASED UPON A PREVIOUS USAGE OF THE VIRTUAL MEMORY BLOCKS - The allocation of virtual memory within a virtual machine based upon the previous mapping of virtual memory blocks to physical memory blocks is optimized. Virtual memory blocks that have been mapped to a corresponding physical memory block over virtual memory blocks that are unmapped when fulfilling an allocation request can be reallocated preferentially. | 2010-01-07 |
20100005223 | Method for field-programming a solid-state memory device with a digital media file - The preferred embodiments described herein provide a method for field-programming a solid-state memory device with a digital media file. In one preferred embodiment, a solid-state memory device is provided that comprises a memory array comprising a plurality of field-programmable memory cells. A digital media file is selected for storage in the memory device, and a digital media source field-programs the memory cells of the memory device with the selected digital media file. After the digital media file is stored in the memory device, the stored digital media file can be played using a digital playback device. In some embodiments, the memory array is a three-dimensional memory array, and the memory cells are write-once memory cells. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another. | 2010-01-07 |
20100005224 | Foldable USB flash memory device that can be manufactured in any desired shape and size suitable for different types of host devices - An enhanced design for the USB flash memory devices implemented with the USB specifications. The main idea in this design is to create two-section USB flash memory devices and both the sections be joined together with the help of rotating hinges and pivots so that both the sections can rotate with respect to each other. In this design, one section contains the USB connector that is used to connect the USB device with the host device and the other section contains the USB controller, memory controller, and flash memory components of a standard USB device. This arrangement provides the ability to both the sections in the device to rotate against each other and adjust at any desired angle and be folded together. While the rotating hinges are required at both the end sides of two sections where both the sections join together to be able to rotate around each other, rotating hinges or ribbon cables are used between the two sections to provide path for the data flow and the required power between the USB flash memory device and the USB host. | 2010-01-07 |
20100005225 | NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND HOST DEVICE - A nonvolatile memory device has a file system manager and manages the file system of a file to be recorded. The nonvolatile memory device measures time by obtaining time information from outside in each writing file data or based on time information preliminarily obtained. At the time of writing file data, management information of the file system is configured based on the time information at the time. Thus, the time information can be stored in a file entry table, and the time information can be used as file management information. The nonvolatile memory system with high user's convenience can be provided. | 2010-01-07 |
20100005226 | NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - An access device | 2010-01-07 |
20100005227 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - A file to be read or written is designated and accessed from an access device side to a nonvolatile memory device. In an initialization after start-up of the power source, an empty capacity detector detects empty capacity parameters of a nonvolatile memory with dividing the memory into a plurality of regions. An empty capacity parameter notification part notifies the access device of the empty capacity parameters in a stepwise fashion whenever the empty capacity detector detects an empty capacity. With this, at the time when the empty capacity becomes not less than a capacity required to write file data, the data can be written to the nonvolatile memory without waiting for completion of the initialization, resulting in improvement of a response in the recording. | 2010-01-07 |
20100005228 | DATA CONTROL APPARATUS, STORAGE SYSTEM, AND COMPUTER PROGRAM PRODUCT - A data control apparatus includes a mapping-table managing unit that manages a mapping table that is associated with a corrupted-data recovery function of recording data and error correcting code data as redundant data that is given separately from the data, distributed and stored in units of stripe blocks in the plural nonvolatile semiconductor memory devices, the mapping table containing arrangement information of the data and the error correcting code data; a determining unit that determines whether to differentiate frequencies of writing the data into the semiconductor memory devices; and a changing unit that changes the arrangement information by switching the data stored in units of the stripe blocks managed using the mapping table to differentiate the frequencies of writing the data into the semiconductor memory devices, when the determining unit determines that the frequencies of writing the data into the semiconductor memory devices are to be differentiated. | 2010-01-07 |
20100005229 | FLASH MEMORY APPARATUS AND METHOD FOR SECURING A FLASH MEMORY FROM DATA DAMAGE - A method for securing a flash memory from data damage is provided. After writing of data to a plurality of written pages of a first block of a flash memory is completed, a last weak page of the written pages is determined. A first strong page corresponding to the last weak page is then determined. A plurality of strong pages between the first strong page and the last weak page are then determined. Data of the plurality of strong pages is the coped to a backup area of the flash memory for data recovery. | 2010-01-07 |
20100005230 | DATA STORING METHODS AND APPARATUS THEREOF - A data storing method for non-volatile memory is provided, wherein the non-volatile memory includes at least one memory block having a plurality of strong pages and weak pages. A logic block writing command is received for storing the corresponding writing data into the memory block. It is then determined whether the writing data is larger than one page. The writing data is divided into a plurality of page data according to the memory size of the page when the writing data is larger than one page. Next, a first storing page for each page data is determined according to a starting writing page according to the logic block writing command. And, the page data are sequentially written into the first storing pages. Note that each first storing page is a strong page within the memory block. | 2010-01-07 |
20100005231 | METHOD AND SYSTEM FOR HARDWARE IMPLEMENTATION OF RESETTING AN EXTERNAL TWO-WIRED EEPROM - Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without initiation by a central processing unit (CPU). The resetting may occur via a virtual CPU. The CPU and the virtual CPU may be integrated on a single chip. The signal generation and EEPROM resetting may occur via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM. | 2010-01-07 |
20100005232 | MEMORY CONTROLLER INTERFACE - A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and SRAM memory devices to instead operate using NAND flash and SDRAM. The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor. | 2010-01-07 |
20100005233 | STORAGE REGION ALLOCATION SYSTEM, STORAGE REGION ALLOCATION METHOD, AND CONTROL APPARATUS - There are provided a memory space allocation method and a memory space allocation device that aim at higher-speed accesses when a memory is shared by a plurality of circuits. In this memory, one data is accessed by issuing addresses a plurality of times. Memory allocation is performed so that high-order addresses of memory spaces of an external memory | 2010-01-07 |
20100005234 | Enabling functional dependency in a multi-function device - In one embodiment, the present invention includes a method for reading configuration information from a multi-function device (MFD), building a dependency tree of a functional dependency of functions performed by the MFD based on the configuration information, which indicates that the MFD is capable of performing at least one function dependent upon another function, and loading software associated with the functions in order based at least in part on the indicated functional dependency. Other embodiments are described and claimed. | 2010-01-07 |
20100005235 | COMPUTER SYSTEM - A computer system includes a CPU and a system on chip (SoC) processor electronically connected with the CPU in the computer system. The CPU and the SoC processor do not work simultaneously. The CPU processes work and a service when the computer system is powered on. The SoC processor continues processing the work and the service that are unfinished after the computer system is shut down. | 2010-01-07 |
20100005236 | AUTOMATICALLY ASSIGNING A MULTI-DIMENSIONAL PHYSICAL ADDRESS TO A DATA STORAGE DEVICE - A method of assigning a multi-dimensional physical address to a tape-based data storage device is provided. The method includes accessing a first signal from a first communication path electrically coupled to a first tape-based data storage device, wherein the first signal indicates a physical position of the first tape-based data storage device with respect to a first axis. The method further includes accessing a second signal from a second communication path electrically coupled to the first tape-based data storage device, wherein the second signal is associated with a physical position of the first tape-based data storage device with respect to a second axis. The method also includes determining a unique physical location of the first tape-based data storage device in the second axis based on the second signal and assigning a unique physical address to the first tape-based data storage device, wherein the unique physical address is based on the physical position of the first tape-based data storage device in the first axis and based on the physical position of the first tape-based data storage device in the second axis. | 2010-01-07 |
20100005237 | SCHEDULING READ OPERATIONS DURING DRIVE RECONSTRUCTION IN AN ARRAY OF REDUNDANT DISK DRIVES - Some embodiments of the present invention provide a system that schedules read operations for disk drives in a set of disk drives. During operation, the system monitors a write rate for write operations to a given disk drive in the set of disk drives, wherein vibrations generated by the read operations directed to disk drives in the set of disk drives are transmitted to the given disk drive. Then, the read operations for disk drives in the set of disk drives are scheduled based on the write rate for the given disk drive, thereby limiting interference between the write operations and the vibrations generated by the read operations. | 2010-01-07 |
20100005238 | MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE - Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults. | 2010-01-07 |
20100005239 | Methods and apparatus for copying data - In one embodiment, the method includes modifying data being copied such that portions of the data that include defects are replaced with dummy data. For example, a defective portion of the data is detected during a copy operation, and the data being copied is modified such that detected defective portions of the data are replaced with the dummy data. | 2010-01-07 |
20100005240 | DISPLAY APPARATUS AND ITS METHOD FOR DISPLAYING CONNECTIONS AMONG A HOST, A LOGICAL UNIT AND A STORAGE SYSTEM IN A VIRTUAL STORAGE SYSTEM - This invention provides a user or an operator with a management apparatus or method for displaying logical connection information between an interface connected to a computer and a switch and a storage system or a logical unit in the storage system in a virtual storage system, wherein the switch receives a first access request from said computer, converts said first access request to a second access request to one of said plural storage systems, and sends said second access request to one of said plural storage systems or one logical unit | 2010-01-07 |
20100005241 | DETECTION OF STREAMING DATA IN CACHE - An apparatus to detect streaming data in memory is presented. In one embodiment the apparatus use reuse bits and S-bits status for cache lines wherein an S-bit status indicates the data in the cache line are potentially streaming data. To enhance the efficiency of a cache, different measures can be applied to make the streaming data become the next victim during a replacement. | 2010-01-07 |
20100005242 | Efficient Processing of Data Requests With The Aid Of A Region Cache - A method and system for configuring a cache memory system in order to efficiently process processor requests. A group of cache elements, which include a Region Cache, a Region Coherence Array, and a lowest level cache, is configured based on a tradeoff of latency and power consumption requirements. A selected cache configuration differs from other feasible configurations in the order in which cache elements are accessed relative to each other. The Region Cache is employed in a number of configurations to reduce the power consumption, latency, and bandwidth requirements of the Region Coherence Array. The Region Cache is accessed by processor requests before (or in parallel with) the larger Region Coherence Array, providing the region coherence state and power efficiently to requests that hit in the Region Cache. | 2010-01-07 |
20100005243 | Rendering Apparatus Which Parallel-Processes a Plurality of Pixels, and Data Transfer Method - A rendering apparatus includes a memory device, a cache memory, a cache control unit and a rendering process. The memory device stores image data. The cache memory executes transmission/reception of the image data to/from the memory device. The cache memory includes a plurality of entries, each of which is capable of storing the image data. The cache control unit manages data transfer between the memory device and the cache memory and stores information relating to a state of the cache memory. The cache control unit stores, in association with each of the entries, identification information of the image data transferred from the memory device to the entry of the cache memory and transfer information which is indicative of whether the image data is already transferred to the entry or not. The rendering process unit executes image rendering by using the image data in the cache memory. | 2010-01-07 |
20100005244 | Device and Method for Storing Data and/or Instructions in a Computer System Having At Least Two Processing Units and At Least One First Memory or Memory Area for Data and/or Instructions - A device and method for storing data and/or instructions in a computer system having at least two processing units and at least one first memory or memory area for data and/or instructions, wherein a second memory or memory area is included in the device, the device being designed as a cache memory system and equipped with at least two separate ports, and the at least two processing units accessing via these ports the same or different memory cells of the second memory or memory area, the data and/or instructions from the first memory system being stored temporarily in blocks. | 2010-01-07 |
20100005245 | SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL WRITES AND NON-SNOOP ACCESSES - A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, when a conflict associated with a partial memory access, such as a partial write, is detected, a write-back phase is inserted at the conflict phase to write-back the partial data to a home agent. Examples messages to initiate a write-back phase at a conflict phase include: an Acknowledge Conflict Write-back message to acknowledge a conflict and provide a write-back marker at the beginning of the conflict phase, a write-back marker message before the conflict phase, a write-back marker message within the conflict phase, a write-back marker message after the conflict phase, and a postable message after the conflict phase. | 2010-01-07 |
20100005246 | SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND NON-SNOOP ACCESSES - A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data. | 2010-01-07 |
20100005247 | Method and Apparatus for Global Ordering to Insure Latency Independent Coherence - A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to apply global ordering to the requests. A bus interface having request, snoop, and response logic is provided for each agent. A bus interface having request, snoop and response logic is provided for the global arbiter, and a bus interface is provided to couple the global arbiter to each type of fabric it is responsible for. Global ordering and arbitration logic tags incoming requests from the multiple agents and insures that snoops are responded to according to the global order, without regard to latency differences in the fabrics. | 2010-01-07 |
20100005248 | PSEUDO LEAST RECENTLY USED REPLACEMENT/ALLOCATION SCHEME IN REQUEST AGENT AFFINITIVE SET-ASSOCIATIVE SNOOP FILTER - The storage locations of a snoop filter are segregated into a number of groups, and some groups are associated with some processors in a system. When new data enter a cache line of a processor, one of the storage locations associated with the processor is selected for further operations. | 2010-01-07 |
20100005249 | Finding the Source Statement of the Definition of a Storage Location - In an embodiment, an identifier of a storage location that is accessed by a program is received. While execution of the program is halted at a halted statement, a first source statement is determined that must have stored to the storage location. The program comprises the halted statement and the first source statement, and the halted statement is different than the first source statement. The first source statement is presented, in response to the determination. In an embodiment, while execution of the program is halted at the halted statement, a second source statement is determined that might have stored to the storage location, and the second source statement is presented. | 2010-01-07 |
20100005250 | SIZE AND RETRY PROGRAMMABLE MULTI-SYNCHRONOUS FIFO - A size and retry programmable multi-synchronous FIFO. In one embodiment, a multi-synchronous FIFO memory generally comprises a selectable number of addressable memory locations for storing information; read control means synchronized by a read clock for controlling pop transactions configured to read from one or more of the selected number of addressable memory locations; write control means synchronized by a write clock asynchronous to the read clock for controlling push transactions to write to one or more of the selected number of addressable memory locations; and selectable transaction retry control means configured to cause read control means to repeat selected pop transactions and/or cause write control means to repeat selected push transactions. In another embodiment a method of retrying a transaction in a multi-synchronous FIFO having a selectable number of addressable memory locations generally comprises the steps of receiving a transaction request; storing the starting address of the transaction register in a start register; executing the transaction; incrementing the starting address in the transaction register after comparing the incremented address to the selected number of addressable memory locations; receiving a retry request; and retrying the transaction. | 2010-01-07 |
20100005251 | Memory control circuit and integrated circuit - The memory unit is compatible with a plurality of operation modes. The plurality of operation modes include the normal mode allowing access and the standby mode consuming a lower power than the normal mode. The branch detection section detects a branch instruction from an instruction fetched from the memory unit by the CPU. The mode control section changes an operation mode of the memory unit according to a detection result by the branch detection section. | 2010-01-07 |
20100005252 | STORAGE CONTROL SYSTEM - A storage control system includes a storage device and a UPS electrically connected to and communicating with the storage device. The storage device has a write back process and a write through process for writing data into the storage device, and includes a monitoring module. The UPS includes a control chip. The control chip of the UPS sends state signals to the storage device. The monitoring module receives the state signals and selects one of the write back process and the write through process to replace the other one of the write back process and the write through process for writing data into the storage device, depending on the state signals. | 2010-01-07 |
20100005253 | MEMORY CONTROLLER, PCB, COMPUTER SYSTEM AND MEMORY ADJUSTING METHOD - A memory controller, a PCB and a computer system employing the memory controller, and a memory adjusting method using the memory controller. The memory controller interfaces data reading from and writing to a memory and includes: a characteristic estimating part estimating a characteristic of a memory output signal outputted from the memory for the data reading and writing; and a characteristic adjusting part controlling the memory so that the characteristic of the memory output signal is within a predetermined reference range if the characteristic of the memory output signal estimated by the characteristic estimating part is beyond the predetermined reference range. | 2010-01-07 |
20100005254 | Nearest Neighbor Serial Content Addressable Memory - A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs. | 2010-01-07 |
20100005255 | Method for providing atomicity for host write input/outputs (I/Os) in a continuous data protection (CDP)-enabled volume using intent log - The present invention is a method for providing atomicity for host write Input/Outputs (I/Os) in a Continuous Data Protection (CDP)-enabled volume. When a host overwrite Input/Output (I/O) is initiated by a host against a data block of the CDP-enabled volume, the method may include creating an in-flight write log entry and providing the in-flight write log entry to an in-flight write log of the CDP-enabled volume. The in-flight write log entry may correspond to the host overwrite I/O. The method may further include locating mapping table information in a mapping table of the CDP-enabled volume. The mapping table information may correspond to the data block. The method may further include recording a journal entry in a journal of the CDP-enabled volume. The journal entry may include a journal entry timestamp which corresponds to the host overwrite I/O. The method may further include allocating a storage location for the host overwrite I/O. | 2010-01-07 |
20100005256 | METHOD OF MANAGING A MEMORY INCLUDING ELEMENTS PROVIDED WITH IDENTITY INFORMATION INDICATIVE OF THE ANCESTRY OF SAID ELEMENTS - A method of managing a memory having stored elements that are organized in a hierarchy, each having a header containing individual identity information and a body containing data, the identity information of each element being encoded on a plurality of bits each of which can take a first value or a second value. The identity information of each element is obtained by repeating the identity information of an element constituting a direct antecedent of the element in question in the hierarchy, and in said identity information of the antecedent, by changing the value of a first value bit that follows the last second value bit in a direction for reading the identity information. | 2010-01-07 |
20100005257 | STORAGE DEVICE, CONTROLLING METHOD FOR STORAGE DEVICE, AND CONTROL PROGRAM - A storage device includes a first storage unit that stores data read from a recording medium based on an instruction received from a processing device, and transmitting the data stored in the first storage unit to the processing device. The storage device also includes a second storage unit that stores the instruction received from the processing device; a counter that counts the number of pieces of data stored in the first storage unit; and a control unit that transmits the data stored in the first storage unit to the processing device based on a count value of the counter and, when the data read upon the instruction is stored in the first storage unit, writes identification information indicating that storing data has been completed in the second storage unit and, based on the identification information, transmits the data stored in the first storage unit to the processing device. | 2010-01-07 |
20100005258 | BACKUP SYSTEM AND METHOD - Backup of a production instance of an application in a production machine environment is performed by creating a snapshot image that captures the state of the production machine, and then backing up the application from a backup machine created using the snapshot image. The backup of the application can be effected by shutting down the backup machine and backing up its storage, or by using backup software to act on the backup version of the application. | 2010-01-07 |
20100005259 | CONTINUOUS DATA PROTECTION OVER INTERMITTENT CONNECTIONS, SUCH AS CONTINUOUS DATA BACKUP FOR LAPTOPS OR WIRELESS DEVICES - A portable data protection system is described for protecting, transferring or copying data using continuous data protection (CDP) over intermittent or occasional connections between a computer system or mobile device containing the data to be protected, transferred or copied, called a data source, and one or more computer systems that receive the data, called a data target. CDP can be broken down logically into two phases: 1) detecting changes to data on a data source and 2) replicating the changes to a data target. The portable data protection system uses a method that performs the first phase continuously or near continuously on the data source, and the second phase when a connection is available between the data source and the data target. | 2010-01-07 |
20100005260 | STORAGE SYSTEM AND REMOTE COPY RECOVERY METHOD - Data written in the primary logical volume of the first storage device are transmitted to the third storage device via the second storage device, the data being written in the same location as the primary logical volume within the secondary logical volume in the third storage device; when transmission of the data stops among the first to the third storage devices, the respective second storage device and the third storage device manage locations in the secondary logical volume where the data held thereby are to be written; and, when transmission of the data resumes among the first to the third storage devices, the locations in the secondary logical volume managed by the respective second and the third storage devices are aggregated, the data to be written in the respective aggregated location in the secondary logical volume being transmitted from the first storage device to the third storage device via the second storage device. | 2010-01-07 |
20100005261 | STORAGE DEVICE AND POWER CONTROL METHOD - The storage device of the present invention has: a first recording unit that records a time zone history of access to each storage area assigned to a virtual volume; a second recording unit that executes a predetermined calculation based on the time zone history of access to a plurality of storage areas belonging to a plurality of pool areas and records the calculation result for each of the plurality of pool areas; a comparison unit that acquires, from the first recording unit, the time zone history of access to an optional storage area among the plurality of storage areas and compares the acquired access time zone history with the calculation result recorded in the second recording unit; and a migration unit that selects, from among the plurality of pool areas, a pool area for which the calculation result is similar to the acquired access time zone history on the basis of the result of the comparison by the comparison unit, and migrates the data stored in the optional storage area to a storage area in the selected pool area. | 2010-01-07 |
20100005262 | Information Processing Apparatus, Data Restoring Method of Information Processing Apparatus, and Data Restoring Program of Information Processing Apparatus - According to the present invention, an information processing apparatus includes: a first storage module; a second storage module; a first acquiring module configured to acquire data from the first storage module when a failure occurs; a determination module configured to determine whether the data acquired by the first acquiring module includes system data having a possibility of changing system operation; and a first copying module configured to copy the data to the second storage device with a destination information, wherein, when the determination module determines that the data does not include the system data, a previous location of the data before occurrence of the failure is set as the destination information, and wherein, when the determination module determines that the data includes the system data, a certain location in the first storage module is set as the destination information. | 2010-01-07 |
20100005263 | INFORMATION BACKUP METHOD, FIREWALL AND NETWORK SYSTEM - An information backup method, a firewall, and a network system are provided in the embodiments of the present disclosure. The method of the present disclosure implements information backup between at least two firewalls. The method includes: receiving a packet; and backing up changed session information to the another firewall if it is detected that the received packet causes the recorded session information to have changed. As such, session information recorded in the firewalls is consistent in real time. | 2010-01-07 |
20100005264 | INFORMATION PROCESSING DEVICE, INTEGRATED CIRCUIT, METHOD, AND PROGRAM - To aim to provide an information processing device capable of improving a processing capability and securely handling programs and data to be protected. According to a system LSI | 2010-01-07 |
20100005265 | METHOD FOR ISOLATING OBJECTS IN MEMORY REGION - Method for isolating an object that has not been accessed for a certain period of time in a virtual memory space. When a garbage collection operates on a computer, the following steps are executed: detecting the object which has not been accessed for a certain period of time as a non-access object; moving the non-access object to a newly reserved virtual memory region when a certain time period elapses after detecting the non-access object; and setting the newly reserved virtual memory region to be an inaccessible region so that the garbage collection does not access the inaccessible region after a certain further time period elapses after moving the non-access object to the newly reserved virtual memory region. | 2010-01-07 |
20100005266 | Technique for estimating the size of an in-memory cache - This Sampling Object Cache System (“SOCS”) estimates the size of an in-memory heap-based object cache without the need to serialize every object within the cache. SOCS samples objects at a user-determined rate and then computes a “sample size average” for each type of class-whether a top class, type of top class or non top class. Using these sample size averages, a statistically accurate measure of the overall size of the cache is calculated by adding together the total size of the objects in the cache for each class type. | 2010-01-07 |
20100005267 | Memory management for hypervisor loading - Techniques related to personal computers and devices sharing similar architectures are disclosed. Particularly shown is a system and method for enabling improved performance and security in hypervisor programs and related applications programs achieved through the use of multiple non-volatile memories. | 2010-01-07 |
20100005268 | MAINTAINING CORRESPONDING RELATIONSHIPS BETWEEN CHAT TRANSCRIPTS AND RELATED CHAT CONTENT - A method, apparatus, and system for maintaining corresponding relationships between at least one chat transcript and related chat content in an instant messaging system may include establishing a chat session in the instant messaging system. Corresponding chat content may be displayed synchronously according to a changed address of the chat content. The changed address of the chat content may be inserted into a chat transcript, and the chat transcript may be segmented into at least two segments to create a segmented chat transcript. The segmented chat transcript and corresponding relationship between the changed address of the chat content and corresponding chat transcript segments may be stored. | 2010-01-07 |
20100005269 | Translation of virtual to physical addresses - Address translation circuitry for translating virtual addresses to physical addresses for a data processor in response to access requests from said data processor targeting virtual addresses is disclosed. The address translation circuitry comprises: a data store comprising a plurality of entries for storing a plurality of mappings of ranges of virtual addresses to ranges of physical addresses for said data processor and additional data associated with each of said plurality of mappings within a table; updating circuitry for updating said table in response to an access request for a virtual address that is not mapped by said table, said updating circuitry being responsive to receipt of a mapping for said virtual address to: select a plurality of entries in said table suitable for storing said received mapping; and determine one of said plurality of selected entries to be overwritten by said received mapping in dependence upon at least a portion of said additional data stored in said one of said plurality of selected entries. | 2010-01-07 |
20100005270 | STORAGE UNIT MANAGEMENT METHODS AND SYSTEMS - Storage unit management methods and systems are provided. The storage unit comprises a plurality of physical blocks, wherein each has one of a plurality of block type definitions. First, a sub-write command is obtained, wherein the sub-write command requests to write data to at least one logical page of a logical block. It is determined whether a candidate block having a first block type definition exists in the storage unit, wherein the logical page of the logic block cannot map to the candidate block based on the first block type definition. If the candidate block exists, the block type definition of the candidate block is transformed from the first block type definition to a second block type definition. Data is written to a specific page of the candidate block, and a mapping relationship between the logical page of the logical block and the specific page of the candidate block is recorded. | 2010-01-07 |
20100005271 | MEMORY CONTROLLER - A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region. | 2010-01-07 |
20100005272 | Virtual memory window with dynamic prefetching support - Reconfigurable Systems-an-Chip (RSoCs) on the market consist of full-fledged processors and large Field-Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and application-specific coprocessors. Using FPGAs for application-specific coprocessors has certain speedup potentials, but it is less present in practice because of the complexity of interfacing the software application with the coprocessor. In the present application, we present a virtualisation layer consisting of an operating system extension and a hardware component. It lowers the complexity of interfacing and increases portability potentials, while it also allows the coprocessor to access the user virtual memory through a virtual memory window. The burden of moving data between processor and coprocessor is shifted from the programmer to the operating system. | 2010-01-07 |
20100005273 | METHOD FOR SELECTING NODE IN NETWORK SYSTEM AND SYSTEM THEREOF - The present invention relates to a method for selecting a node in a network system and a system thereof. The method performs a writing operation on a majority of the nodes included in at least one cell selected by dividing a network area including a plurality of nodes existing on a large-capacity cluster into a plurality of cells and performs a reading work on the majority of the nodes included in the cells selected by selecting predetermined cells of the divided cells. The present invention minimizes the accessibility of the network by binding the adjacent nodes to form the cells and access to each cell and optimizes hierarchy for the network access by selecting the node for each cell, thereby making it possible to minimize the network access cost. | 2010-01-07 |
20100005274 | VIRTUAL FUNCTIONAL UNITS FOR VLIW PROCESSORS - A virtual functional unit design is presented that is employed in a statically scheduled VLIW processor “Virtual” views of the function unit appear to the processor scheduler that exceed the number of physical instantiations of the functional unit. As a result, significant processor performance improvements can be achieved for those types of functional units that are too difficult or too costly to physically duplicate. By providing different virtual views to the different clusters of a VLIW processor, the compiler/scheduler can generate more efficient code for the processor, than a processor without virtual views and the physical unit restricted to a subset of the processor's clusters. The compiler/scheduler guarantees that the restrictions with respect to scheduling of operations for functional units with multiple virtual views is met. NON-clustered processors also benefit from virtual views. By providing multiple virtual views in multiple issue slots of a physical function unit, the compiler/scheduler has more freedom to schedule operations for the functional unit. | 2010-01-07 |
20100005275 | MULTIPROCESSING SYSTEM - A multiprocessing system includes a storage part that stores to a memory, a first operating system (OS) task set that is constituted by a combination of a first task and a first OS corresponding to the first task, the first task being designated by an execution instruction; and a task executing part that refers to the first OS task set stored to the memory, loads the OS constituting the first OS task set, and executes the first task designated by the execution instruction. | 2010-01-07 |
20100005276 | INFORMATION PROCESSING DEVICE AND METHOD OF CONTROLLING INSTRUCTION FETCH - An information processing device includes an instruction fetch unit, an instruction buffer, an instruction executing unit, and an instruction fetch control unit. The instruction fetch unit supplies a fetch address to an instruction memory. The instruction buffer stores an instruction read out from the instruction memory. The instruction executing unit decodes and executes the instruction supplied from the instruction buffer. The instruction fetch control unit stops supply of the fetch address to the instruction memory by the instruction fetch unit when the fetch address corresponds to a first address or an address after the first address while the instruction executing unit executes loop processing. The loop processing is repeatedly executed for a predetermined number of times in accordance with decoding of the loop instruction by the instruction executing unit. The first address is an address after an address of an end instruction included in the loop processing. | 2010-01-07 |
20100005277 | Communicating Between Multiple Threads In A Processor - In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed. | 2010-01-07 |
20100005278 | DEVICE AND METHOD FOR CONTROLLING AN INTERNAL STATE OF INFORMATION PROCESSING EQUIPMENT - The state control device for controlling an internal state of information processing equipment includes a scenario table, an information recorder, an information player and a state change controller. The information recorder acquires sync information and one item or a plurality of items of state information from the information processing equipment and records the acquired sync information and state information in association with each other in the scenario table. The information player, receiving sync information from the information processing equipment, acquires state information associated with sync information corresponding to the received sync information, among the sync information stored in the scenario table, from the scenario table, and supplies the acquired state information to the state change controller. The state change controller controls the inside of the information processing equipment based on the state information received from the information player. The sync information is information for identifying an execution state of the information processing equipment at a given time point, and the state information is information representing an internal state of the information processing equipment at a given time point synchronous with the sync information. | 2010-01-07 |
20100005279 | Data processor - The data processor executes an instruction having a direction for write to a reference register of other instruction flow and an instruction having a direction for reference register invalidation. The data processor is arranged as a data processor having typical functions as an integrated whole of processors (CPU | 2010-01-07 |
20100005280 | Virtualized service tool and virtualized control tool - A computer-readable medium is disclosed. The computer-readable medium stores a virtualized service tool application program for running on a computer running an existing operating system platform. The virtualized service tool application program has operating system software configured to execute as an internal operating system platform separate from the existing operating system platform, and that is configured with settings that permit the computer to communicate with one or more machines coupled to the computer. The virtualized service tool application additionally has a service module configured to perform service-related tasks for the one or more machines coupled to the computer. | 2010-01-07 |
20100005281 | POWER-ON INITIALIZATION AND TEST FOR A CASCADE INTERCONNECT MEMORY SYSTEM - A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller. | 2010-01-07 |
20100005282 | METHOD AND APPARATUS FOR BOOTING FROM A FLASH MEMORY - Techniques for booting a computing device with a flash memory without knowledge of parametric information of the flash memory are described herein. In one embodiment of the invention, the computing device receives input requesting the computing device to begin operation and executes a set of one or more instructions stored in a non-volatile memory. The execution of the set of instructions configures a first read routine for accessing the flash memory based on a common denominator format of candidate flash memories, and the first read routine is not configured based on information located in a flash memory identification table. The computing device reads a bootstrapping code image based on the first read routine into a volatile memory and executes that first bootstrapping code image. Other methods and apparatuses are also described. | 2010-01-07 |
20100005283 | COMPUTER SYSTEM AND CONTROL METHOD OF THE SAME - A computer system includes a device which transmits data through a predetermined interface and outputs first recognition information in response to a predetermined power on self test (POST) control signal, a device controller which has second recognition information about whether the device is mounted, and a system controller which outputs the POST control signal to the device when powering on, and recognizes the device on the basis of the first recognition information and the second recognition information. | 2010-01-07 |
20100005284 | DEVICE HAVING SHARED MEMORY AND METHOD FOR TRANSFERRING CODE DATA - The present invention relates to a device having a shared memory and a code data transmitting method. According to an embodiment of the present invention, the digital processing device can include n processors, n being a natural number of 2 or greater; and a shared memory, coupled to each of the processors through independent buses and having a boot section allotted, the boot section being for writing a boot program code to be used for booting of at least one processor. | 2010-01-07 |
20100005285 | COMPUTER SYSTEM AND METHOD OF BOOTING THE SAME - Provided are a computer system and a method of booting the same. The computer system includes: a first storage unit for storing a booting-related program including an operating system program and data, the stored program and data being retained even when a power voltage is not supplied; and a second storage unit for storing data, the data being lost when the power voltage is not supplied for a predetermined time or longer. The method includes: a first step of performing a booting operation using the booting-related program stored in the first storage unit and storing the booting-related program stored in the first storage unit in the second storage unit when the second storage unit is detected and the booting-related program is not stored in the second storage unit; a second step for performing a booting operation by executing the booting-related program stored in the second storage unit when the second storage unit is detected and the booting-related program is stored in the second storage unit; and a third step of backing up the booting-related program stored in the second storage unit to the first storage unit when a predefined backup condition is met. | 2010-01-07 |
20100005286 | METHOD FOR BOOTING COMPUTER SYSTEM - A method for booting a computer system is provided. In the method for booting the computer system, a memory space is created using a BIOS to simulate a virtual disk. The virtual disk is used to execute operations which have to be executed via a floppy disk drive. The operations are executed in the virtual disk via the BIOS. Thus, the floppy disk drive is not needed, and the cost is reduced. In addition, time consumed in reading data from the floppy disk is reduced, and installing speed also increases. | 2010-01-07 |
20100005287 | DATA SECURITY FOR DIGITAL DATA STORAGE - A computing system includes data encryption in the data path between a data source and data storage devices. The data storage devices may be local or they may be network resident. The data encryption may utilize a key which is derived at least in part from an identification code stored in a non-volatile memory. The key may also be derived at least in part from user input to the computer. In a LAN embodiment, public encryption keys may be automatically transferred to a network server for file encryption prior to file transfer to a client system. | 2010-01-07 |
20100005288 | SYSTEMS AND METHODS FOR ADJUSTING THE MAXIMUM TRANSMISSION UNIT BY AN INTERMEDIARY DEVICE - The present invention is generally directed towards a remote access architecture for providing peer-to-peer communications and remote access connectivity. In one embodiment, the remote access architecture of the present invention provides a method for establishing a direct connection between peer computing devices via a third computing device, such as a gateway. Additionally, the present invention provides the following techniques to optimize peer-to-peer communications: 1) false acknowledgement of receipt of network packets allowing communications via a lossless protocol of packets constructed for transmission via a lossy protocol, 2) payload shifting of network packets allowing communications via a lossless protocol of packets constructed for transmission via a lossy protocol, 3) reduction of packet fragmentation by adjusting the maximum transmission unit (MTU) parameter, accounting for overhead due to encryption, 4) application-aware prioritization of client-side network communications, and 5) network disruption shielding for reliable and persistent network connectivity and access. | 2010-01-07 |
20100005289 | Methods and apparatus for protecting digital content - A processing system to serve as a source device for protected digital content comprises a processor and control logic. When used by the processor, the control logic causes the processing system to generate cipher data, based at least in part on (a) a session key and (b) at least one constant value obtained from a certificate authority. The processing system may use the cipher data to encrypt data, and the processing system may transmit the encrypted data to a receiving device via a wireless connection. Other embodiments are described and claimed. | 2010-01-07 |
20100005290 | METHOD OF IDENTITY PROTECTION, CORRESPONDING DEVICES AND COMPUTER SOFTWARES - A method is provided for authenticating a client terminal with an authentication server. The client terminal holds an authentication certificate. The method includes the following phases: obtaining at least once encryption parameter by the client terminal; encrypting the authentication certificate by the client terminal, based on the at least one encryption parameter, delivering an encrypted authentication certificate; transmitting the encrypted authentication certificate to the server, obtaining the at least one encryption parameter by the server; obtaining the at east one encryption parameter by the server; decrypting the encrypted authentication certificate, based on the at least one encrypting parameter, authenticating and delivering an authentication assertion if the authentication is positive. | 2010-01-07 |
20100005291 | APPLICATION REPUTATION SERVICE - The claimed subject matter is directed to the use of an application reputation service to assist users with minimizing their computerized machines' exposure to and infection from malware. Specifically, the claimed subject matter provides a method and system of an application reputation service that contains the reputations for elements that are known to be non-malicious as well as those known to be malicious. | 2010-01-07 |
20100005292 | METHOD AND APPARATUS FOR EFFICIENT CERTIFICATE REVOCATION - Revocation of digital certificates in a public-key infrastructure is disclosed, particularly in the case when a certificate might need to be revoked prior to its expirations. For example, if an employee was terminated or switched roles, his current certificate should no longer be valid. Accordingly, novel methods, components and systems are presented for addressing this problem. A solution set forth herein is based on the construction of grounded dense hash trees. In addition, the grounded dense hash tree approach also provides a time-communication tradeoff compared to the basic chain-based version of NOVOMODO, and this tradeoff yields a direct improvement in computation time in practical situations. | 2010-01-07 |
20100005293 | Systems and Methods for Accessing Secure and Certified Electronic Messages - The present disclosure provides systems and methods for accessing secure and certified electronic messages using a combination of biometric security, a separate and secure network and email infrastructure, email management processes, and the addition of text, audio and visual format options to sending emails messages. | 2010-01-07 |
20100005294 | Security in Wireless Environments Using Out-Of-Band Channel Communication - A methodology of using an (preferably uni-directional) out-of-band channel for secure information transmission between two devices capable for LPRF communication is provided. Information, which is intended for secure transmission from one of the devices to the other device, is encoded into a time dependent visual sequence. The visual sequence may comprise one or more visual signals, in particular lighted-up and dark states. The visual sequence is emitted in a time-dependent visual signal by a light emitter of the one device and the emitted signal is detected by a light sensor of the other device on the basis of the detected signal. The time-dependent signal especially timely varies in the light intensity. The light sensor generates a (time-dependent) sequence of detection signals. These detection signals are decoded to reconstruct the information intended for secure transmission. The out-of-band channel transmission of the information being separate from the LPRF communication enables to transmit a shared secret. The shared secret is required for secure authentication of the devices during initialization of the LPRF communication. | 2010-01-07 |
20100005295 | SYSTEM AND METHOD FOR PROVIDING UNIQUE ENCRYPTION KEY - A system and method for providing a unique encryption key including a receiver, at a Voice over Internet Protocol (VoIP) adapter, configured to receive a configuration file, a processor, at the VoIP adapter, configured to decrypt the configuration file using a default key stored in the VoIP adapter, update one or more profile parameters of the configuration file, and install an encryption key at the VoIP adapter using the configuration file, and a transmitter, at the VoIP adapter, configured to register, with a network element, for network service using the updated configuration file such that the receiver is configured to receive network service from the network element when the updated configuration file is authenticated by the network element. | 2010-01-07 |
20100005296 | Systems and Methods for Controlling Access to Encrypted Data Stored on a Mobile Device - Encrypted data on mobile devices is protected by remotely storing a decryption key. In order to decrypt the encrypted data on the mobile device, the mobile device obtains the decryption key from an access control system that is remote from the mobile device. The access control system can control access to the encrypted data by controlling access to the decryption key. For example, the access control system can implement user authentication as a condition for providing the decryption key. Access to the encrypted data can also be controlled by withholding the decryption key where, for instance, a mobile device has been reported to be lost or stolen, or once an individual's access privilege has been revoked, or at certain times of the day. | 2010-01-07 |
20100005297 | MASHSSL: A NOVEL MULTI PARTY AUTHENTICATION AND KEY EXCHANGE MECHANISM BASED ON SSL - The present invention provides a method that allows three parties to mutually authenticate each other and share an encrypted channel. The invention is based on a novel twist to the widely used two party transport level SSL protocol. One party, typically a user at a browser, acts as a man in the middle between the other two parties, typically two web servers with regular SSL credentials. The two web servers establish a standard mutually authenticated SSL connection via the user's browser, using a novel variation of the SSL handshake that guarantees that a legitimate user is in the middle. | 2010-01-07 |
20100005298 | Resource scheduling in workflow management systems - A system for improved scheduling of resources within a Workflow-Management-System or a computer system with comparable functionality (WFMS). Based on a new resource specification comprised within a process model and associated with an activity, the WFMS determines the resources required for execution of said activity. The invention further schedules a request for allocation of said resources on behalf and in advance of starting execution of said activity. This approach reduces the execution time of the activity as all resources required by the activity will be available when execution of the activity begins; the activity does not have to wait for these resources. Moreover, a WFMS knowing the required resources of the activities it is administrating is able to schedule resource requests to avoid resource conflicts between the activities. | 2010-01-07 |
20100005299 | METHOD FOR MANUFACTURING A PRODUCT, SYSTEM FOR MANUFACTURING A PRODUCT, AND PRODUCT - Provided is a product on which is imprinted an encrypted message obtained by encrypting a message sent along with the product from a sender to a recipient, a method for manufacturing the product, and a system for manufacturing the product. The product manufacturing system has a general web server, an encryption calculating apparatus, an issued encryption values database, a specialized web server, an archive database, and an imprinting apparatus. The product manufacturing system is provided with a message acquiring section that acquires the original message sent along with the product from the sender to the recipient, an encryption calculating apparatus that generates a calculated encryption value by using a hash function to compress a calculation target message extracted from the original message, and an imprinting control section that controls imprinting of the calculated encryption value onto the product. | 2010-01-07 |
20100005300 | METHOD IN A PEER FOR AUTHENTICATING THE PEER TO AN AUTHENTICATOR, CORRESPONDING DEVICE, AND COMPUTER PROGRAM PRODUCT THEREFORE - The invention concerns a method in a peer ( | 2010-01-07 |
20100005301 | AUTHENTICATION AND ENCRYPTION UTLIZING COMMAND IDENTIFIERS - A data processing system, recording device, data processing method and program providing medium are provided to execute authentication processing and content storing processing between apparatuses. Program localization is employed to restrict access to program content. A plurality of key blocks store key data for authentication processing. Key block designation information is set in a recorder/reproducer, which is configured for executing authentication processing with the recording device by designating a key block. The recorder/reproducer can set a key block for each product, model or the like. In addition, data stored according to a selected key block cannot be utilized in a recorder/reproducer in which a different key block is set. Furthermore, an encryption processing controlling section of a recording device executes control in accordance with a pre-defined setting sequence. Furthermore, an illegal instrument that has not completed the authentication processing can be prevented from utilizing program content. | 2010-01-07 |
20100005302 | TECHNIQUES FOR VALIDATING AND SHARING SECRETS - Techniques for validating and sharing secrets are presented. A secret is divided into a plurality of parts. Each part is represented by a unique value. Each value is distributed to a unique user that shares in the secret. The secret is recreated when each user presents each user's unique value. Each unique value is then used to recreate its corresponding part of the key and when all parts are present and validated, the secret is reproduced. | 2010-01-07 |
20100005303 | UNIVERSAL AUTHENTICATION METHOD - The object of the current invention is to provide the user with an authentication method that is more secure than conventional authentication methods and can be used on personal computers, PDAs, cell phones, personal digital media devices, home and car lock and security systems, television/VCR/DVD remote controls, credit card authentication systems, automatic teller machine authentication systems, among others. | 2010-01-07 |
20100005304 | Security and ticketing system control and management - A security device of this invention includes a nonvolatile storage unit | 2010-01-07 |
20100005305 | APPARATUSES, AND METHODS FOR INSERTING USER DATA INTO DIGITAL MULTIMEDIA SIGNALS - Apparatuses, and methods for inserting user data into digital multimedia signals are provided in which user data is inserted into the digital multimedia signals in a substantially imperceptible fashion. In one embodiment of the invention, digital watermarking techniques are used to embed user data into the digital multimedia signal, such that user data is later helpful in indexing the digital multimedia signal. User data can be in any generic form such as text, audio or video signals. In another embodiment of the invention, user data is superimposed on the digital multimedia signal at a location which contains the least amount of information. In yet another embodiment of the invention, user data is inserted at a location chosen by the user. The color in which user data is superimposed can also be chosen by the user by using either a color palette or by pointing to an area in the digital image or video. | 2010-01-07 |
20100005306 | STORAGE MEDIA STORING ELECTRONIC DOCUMENT MANAGEMENT PROGRAM, ELECTRONIC DOCUMENT MANAGEMENT APPARATUS, AND METHOD TO MANAGE ELECTRONIC DOCUMENT - An electronic document management apparatus acquires an electronic document comprised of a plurality of components for each of which a first digital signature and a second digital signature are uniquely specified. The electronic document is linked to an aggregate digital signature which aggregates the first digital signatures. After that the apparatus accepts designation of a component to be “hiding prohibited” within the electronic document. Whether or not the component designated to be “hiding prohibited” is at that time in a state of “hiding allowed and deletion allowed” is judged. When the judgment reveals that the state is “hiding allowed and deletion allowed”, the second digital signature specified for the component designated to be “hiding prohibited” is deleted. Then the state of the component subject to be “hiding prohibited” is changed from “hiding allowed and deletion allowed” to “hiding prohibited and deletion allowed”. | 2010-01-07 |
20100005307 | SECURE APPROACH TO SEND DATA FROM ONE SYSTEM TO ANOTHER - A secure approach for sending a original message from a sender to a receiver. The sender may encrypt the original message by performing an XOR (or XNOR) operation of the original message and a first random message (same size as original message) on a bit by basis to generate a second message. The receiver may also perform an XOR of the second message with a locally generated second random message. The resulting message is sent to the sender system. The sender system may again perform XOR operation of the received message and the first random message, and send the resulting message to receiver. The receiver may perform XOR operation on the received output to generate the original message sent by the sender. Other technologies such as digital signatures and key pairs (public key infrastructure) may be used in each communication between the sender and receiver to further enhance security. | 2010-01-07 |
20100005308 | Optimization methods for the insertion, protection, and detection of digital watermarks in digital data - Disclosed herein are methods and systems for encoding digital watermarks into content signals. Also disclosed are systems and methods for detecting and/or verifying digital watermarks in content signals. According to one embodiment, a system for encoding of digital watermark information includes: a window identifier for identifying a sample window in the signal; an interval calculator for determining a quantization interval of the sample window; and a sampler for normalizing the sample window to provide normalized samples. According to another embodiment, a system for pre-analyzing a digital signal for encoding at least one digital watermark using a digital filter is disclosed. According to another embodiment, a method for pre-analyzing a digital signal for encoding digital watermarks comprises: (1) providing a digital signal; (2) providing a digital filter to be applied to the digital signal; and (3) identifying an area of the digital signal that will be affected by the digital filter based on at least one measurable difference between the digital signal and a counterpart of the digital signal selected from the group consisting of the digital signal as transmitted, the digital signal as stored in a medium, and the digital signal as played backed. According to another embodiment, a method for encoding a watermark in a content signal includes the steps of (1) splitting a watermark bit stream; and (2) encoding at least half of the watermark bit stream in the content signal using inverted instances of the watermark bit stream. Other methods and systems for encoding/decoding digital watermarks are also disclosed. | 2010-01-07 |
20100005309 | METHOD AND APPARATUS FOR AUTHENTICATION OF DATA STREAMS WITH ADAPTIVELY CONTROLLED LOSSES - Methods, components, and systems for efficient authentication, either through a digital signature or message authentication codes, and verification of a digital stream sent from a source to a receiver via zero or more intermediaries, such that the source or intermediary (or both) can remove certain portions of the data stream without inhibiting the ability of the ultimate receiver to verify the authenticity and integrity of the data received. According to the invention, a source may sign an entire data stream once, but may permit either itself or an intermediary to efficiently remove certain portions of the stream before transmitting the stream to the ultimate recipient, without having to re-sign the entire stream. Applications may include the signing of media streams which often need to be further processed to accommodate the resource requirements of a particular environment. Another application allows an intermediary to choose an advertisement to include in a given slot. | 2010-01-07 |
20100005310 | METHOD AND APPARATUS FOR AUTHENICATION OF DATA STREAMS WITH ADAPTIVELY CONTROLLED LOSSES - Methods, components, and systems for efficient authentication, either through a digital signature or message authentication codes, and verification of a digital stream sent from a source to a receiver via zero or more intermediaries, such that the source or intermediary (or both) can remove certain portions of the data stream without inhibiting the ability of the ultimate receiver to verify the authenticity and integrity of the data received. According to the invention, a source may sign an entire data stream once, but may permit either itself or an intermediary to efficiently remove certain portions of the stream before transmitting the stream to the ultimate recipient, without having to re-sign the entire stream. Applications may include the signing of media streams which often need to be further processed to accommodate the resource requirements of a particular environment. Another application allows an intermediary to choose an advertisement to include in a given slot. | 2010-01-07 |
20100005311 | Electronic-data authentication method, Elctronic-data authentication program, and electronic-data, authentication system - An electronic-data authentication method is for authenticating electronic data provided by a virtual person anonymously used on a network, performed by a virtual-person management system including a user terminal, a user management device, and a virtual-person management device. The method includes receiving, by the virtual-person management device, the electronic data, a first electronic signature generated by encrypting the electronic data with a first signature-creation key, and an virtual person ID for uniquely identifying the virtual person from the user terminal; authenticating, by the user management device, the first electronic signature received at the receiving by using a first signature-authentication key corresponding to the first signature-creation key; generating, by the virtual-person management device, a second electronic signature by encrypting the electronic data received at the receiving with a second signature-creation key issued for the virtual person; and transmitting, by the virtual-person management device, the second electronic signature to the user terminal. | 2010-01-07 |
20100005312 | Mutually Excluded Security Managers - Techniques for controlling access to at least one resource are provided. At least one shared key and at least one private key unique to one or more resource sets are generated. Each of the one or more resource sets identify the at least one resource. The at least one shared key and the at least one private key are transmitted to a security access point. The security access point controls access to the at least one resource. At least one resource key is generated. The resource key is a cryptographic function of the at least one private key and at least one resource identifier. The at least one resource key and the at least one shared key are transmitted to one or more local security managers. Each of the one or more local security managers is assigned to manage one of the one or more resource sets. In accordance with one or more policies, the one or more local security managers generate at least one credential using the at least one resource key and the at least one shared key. The at least one credential is distributed to one or more authenticated clients. Further, the at least one credential is used to grant the one or more authenticated clients access to the one or more resource sets through the security access point. | 2010-01-07 |