01st week of 2010 patent applcation highlights part 14 |
Patent application number | Title | Published |
20100001301 | ORGANIC LIGHT EMITTING DEVICE, METHOD FOR PRODUCING THEREOF AND ARRAY OF ORGANIC LIGHT EMITTING DEVICES - The present invention is directed to an organic light emitting device (OLED) including a first electrode, a second electrode, at least one layer of organic material arranged between the first electrode and the second electrode, and a dielectric capping layer arranged on the second electrode opposite to the first electrode, wherein the capping layer comprises an outer surface, opposite to the second electrode, for emission of light generated in the at least one layer of organic material. The capping layer has the effect that a reflectance of external light is reduced whereas outcoupling of the light generated in the at least one layer of organic material through the capping layer is increased. | 2010-01-07 |
20100001302 | Group-III Nitride for Reducing Stress Caused by Metal Nitride Reflector - A device structure includes a substrate; a group-III nitride layer over the substrate; a metal nitride layer over the group-III nitride layer; and a light-emitting layer over the metal nitride layer. The metal nitride layer acts as a reflector reflecting the light emitted by the light-emitting layer. | 2010-01-07 |
20100001303 | RED EMITTING OXYNITRIDE LUMINESCENT MATERIALS - The invention relates to an improved red light emitting material of the formula M | 2010-01-07 |
20100001304 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode includes an LED element, a fluorescent material provided so as to cover the LED element, a substrate on which the LED element is mounted and made of ceramics or silicon, and a pair of electrode pads which are electrically connected to the LED element on the substrate. | 2010-01-07 |
20100001305 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - A semiconductor device and a fabrication method thereof are provides. The semiconductor device comprises a semiconductor substrate having a cavity and a light-emitting diode chip disposed in the cavity. The cavity is filled with an encapsulating resin to cover the light-emitting diode chip. Two isolated metal lines are disposed on the encapsulating resin and electrically connected to the light-emitting diode chip. At least two isolated inner wiring layers are disposed in the cavity and electrically connected to the isolated metal lines. At least two isolated outer wiring layers are disposed on a bottom surface of the semiconductor substrate and electrically connected to the isolated inner wiring layers. | 2010-01-07 |
20100001306 | LIGHT EMITTING DIODE PACKAGE - The present invention provides a light emitting diode package which includes a lead frame with a cavity; a mold exposing the cavity and housing the lead frame; and an LED chip mounted on the cavity, wherein light passing an upper edge of the LED chip passes an upper edge of the cavity. | 2010-01-07 |
20100001307 | ENCAPSULATION FOR ELECTRONIC AND/OR OPTOELECTRONIC DEVICE - A method of processing a flexible encapsulation scheme to encapsulate a flexible device, such as a display device in order to provide structural support for the display module. An upper transparent encapsulation layer covers and protects the media and active area of the device. A lower encapsulation layer is deposited over the under side of the display to complete the encapsulation and the two protective encapsulation layers are sealed. A driver housing may be positioned at the opposite end of the device to the overlap region of the encapsulation layers in order to protect the driver electronics. | 2010-01-07 |
20100001308 | SIDE VIEW LIGHT EMITTING DIODE PACKAGE - Provided is a side view light emitting diode package including a housing that includes a front side part and a rear side part integrally formed with the front side part, the front side part having a light emission part; and a lead frame that is located between the front side part and the rear side part, wherein the lead frame includes a first lead connected to a first electrode of a Light Emitting Diode (LED) chip and a second lead connected to a second electrode of the LED chip, wherein the front side part includes a first groove, a second groove, and a third groove, wherein the first lead and the second lead are extended through the first groove and the second groove, respectively, and a heat dissipation part is extended from the first lead through the third groove to an outside of the LED package. | 2010-01-07 |
20100001309 | SEMICONDUCTOR CHIP ASSEMBLY WITH POST/BASE HEAT SPREADER AND HORIZONTAL SIGNAL ROUTING - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a substrate and an adhesive. The semiconductor device is electrically connected to the substrate and thermally connected to the heat spreader. The heat spreader includes a post and a base. The post extends upwardly through an opening in the adhesive into an aperture in the substrate, and the base extends laterally from the post. The adhesive extends between the post and the substrate and between the base and the substrate. The substrate includes first and second conductive layers and a dielectric layer therebetween and provides horizontal signal routing between a pad and a terminal at the first conductive layer. | 2010-01-07 |
20100001310 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - An exemplary light emitting diode (LED) includes a substrate, a LED chip and an encapsulation unit. The encapsulation unit includes a first encapsulation material located over the LED chip and a second encapsulation material located around the first encapsulation material. A plurality of first particles with a first distributing density is distributed in the first encapsulation material. A plurality of second particles with a second distributing density is distributed in the second encapsulation material. The first distributing density is larger than the second distributing density, a central portion of light from the light emitting diode chip transmits through the first encapsulation material and exits the encapsulation unit from a top surface thereof, and a periphery portion of light from the light emitting diode chip transmits through the second encapsulation material and exits the encapsulation unit from the top surface thereof. | 2010-01-07 |
20100001311 | HEAT-CURABLE SILICONE RESIN-EPOXY RESIN COMPOSITION, AND PREMOLDED PACKAGE MOLDED FROM SAME - A heat-curable silicone resin-epoxy resin composition that is ideal as a premolded package for a high-brightness LED or solar cell. The composition contains (A) a heat-curable silicone resin, (B) a combination of a triazine derivative epoxy resin and an acid anhydride, or a prepolymer obtained by reaction of them, (C) an inorganic filler, and (D) a curing accelerator. The composition exhibits excellent curability, and yields a uniform cured product that displays excellent retention of heat resistance and light resistance over long periods of time, and suffers minimal yellowing. | 2010-01-07 |
20100001312 | Light-emitting device and method for manufacturing the same - A light-emitting device is disclosed. The light-emitting device comprises a substrate, wherein an ion implanted layer on the top surface of the substrate; a thin silicon film disposing on the ion implanted layer; and a light-emitting stack layer on the thin silicon film. This invention also discloses a method of manufacturing a light-emitting device comprising providing a substrate; forming an ion implanted layer on the top surface of the substrate; providing a light-emitting stack layer; forming a thin silicon film on the bottom surface of the light-emitting stack layer; and bonding the light-emitting stack layer to the substrate with the anodic bonding technique. | 2010-01-07 |
20100001313 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light emitting device and a method of manufacturing the same are provided. The light emitting device comprises a first conductive type lower semiconductor layer, a current diffusion layer, a first conductive type upper semiconductor layer, an active layer, and a second conductive type semiconductor layer. The current diffusion layer is formed on the first conductive type lower semiconductor layer. The first conductive type upper semiconductor layer is formed on the current diffusion layer. The active layer is formed on the first conductive type upper semiconductor layer. The second conductive type semiconductor layer is formed on the active layer. | 2010-01-07 |
20100001314 | Bidirectional switch having control gate embedded in semiconductor substrate and semiconductor device - A bidirectional switch includes a first switch and a second switch. The switch includes a well region of a first-conductivity-type formed on a semiconductor substrate, and serving as drains of the first switch and the second switch, a gate electrode of the first switch provided in a first trench formed in the well region through a first gate insulating film, a gate electrode of the second switch formed in a second trench formed in the well region so as to be spaced apart from the first trench with a second gate insulating film, a source region of the first switch formed on a side wall of the first trench, and on a surface of the well region via a first channel region of a second-conductivity-type, and a source region of the second switch formed on a side wall of the second trench, and on a surface of the well region via a second channel region of the second-conductivity-type. The well region is formed in a region between the first trench and the second trench. | 2010-01-07 |
20100001315 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first diffusion region of a second conductivity type formed in an upper portion of a semiconductor substrate of a first conductivity type, a second diffusion region formed in a surface portion of the first diffusion region, a third diffusion region of the second conductivity type formed a predetermined distance spaced apart from the second diffusion region in the surface portion of the semiconductor substrate, a fourth diffusion region of the first conductivity type formed adjacent to the third diffusion region and electrically connected to the third diffusion region, a gate electrode formed on a part between the first diffusion region and the third diffusion region, and an insulating film formed thereon. The impurity concentration of the first diffusion region is set higher than an impurity concentration at which a depletion region extending from an junction interface between the first diffusion region and the semiconductor substrate is formed in a part of the first diffusion region which is between the second diffusion region and the gate electrode when a voltage is applied to the second diffusion region. | 2010-01-07 |
20100001316 | EPITAXIAL LIFT OFF STACK HAVING A NON-UNIFORM HANDLE AND METHODS THEREOF - Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming a thin film material during an epitaxial lift off process is provided which includes forming an epitaxial material over a sacrificial layer on a substrate, adhering a non-uniform support handle onto the epitaxial material, and removing the sacrificial layer during an etching process. The etching process further includes peeling the epitaxial material from the substrate while forming an etch crevice therebetween and bending the support handle to form compression in the epitaxial material during the etching process. In one example, the non-uniform support handle contains a wax film having a varying thickness. | 2010-01-07 |
20100001317 | CMOS TRANSISTOR AND THE METHOD FOR MANUFACTURING THE SAME - A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion. | 2010-01-07 |
20100001318 | Field effect transistor, method of manufacturing the same, and semiconductor device - A J-FET includes a channel layer of a first conductivity type (a Si-doped n-type AlGaAs electron supply layers | 2010-01-07 |
20100001319 | Method for Making a Heterojunction Bipolar Transistor - The invention concerns a heterojunction bipolar transistor comprising a support, and epitaxially grown from said support, at least: one collecting, respectively emitting, layer; at least one base layer; and at least one emitting, respectively collecting, layer. The collecting, respectively emitting, layer comprises: at least one first undercoat contacted with said base layer, substantially of similar composition as said emitting, respectively collecting, layer; and at least one second undercoat on the side opposite said base layer relative to said first undercoat. | 2010-01-07 |
20100001320 | THIN FILM TRANSISTOR ARRAY DEVICES - A transistor circuit for an array device comprises a plurality of thin film transistors electrically connected in parallel and provided on a common substrate. The transistors are arranged on the substrate as at least two rows ( | 2010-01-07 |
20100001321 | Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions - A restricted layout region in a layout of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout is defined to include a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. Each of a number of interconnect level layouts is defined to pattern conductive features within corresponding interconnect levels above the gate electrode level. | 2010-01-07 |
20100001322 | SEMICONDUCTOR DEVICE - The invention relates to a method of manufacturing a semiconductor device ( | 2010-01-07 |
20100001323 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Provided is a semiconductor device manufacturing method by which sufficient stress can be applied to a channel region within allowable ranges of concentrations of Ge and C in a mixed crystal layer. A semiconductor device is also provided. A dummy gate electrode | 2010-01-07 |
20100001324 | SEMICONDUCTOR DEVICE WITH A SUPERPARAELECTRIC GATE INSULATOR - A semiconductor device includes a channel region | 2010-01-07 |
20100001325 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an insulating film provided over a semiconductor substrate, a conductive plug buried in the insulating film, an underlying conductive film which is provided on the conductive plug and on the insulating film and which has a flat upper surface, and a ferroelectric capacitor provided on the underlying conductive film. At least in a region on the conductive plug, the concentration of nitrogen in the underlying conductive film gradually decreases from the upper surface to the inside. | 2010-01-07 |
20100001326 | ONE TRANSISTOR DRAM CELL STRUCTURE AND METHOD FOR FORMING - A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region. | 2010-01-07 |
20100001327 | Semiconductor device - In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved. | 2010-01-07 |
20100001328 | SEMICONDUCTOR DEVICE HAVING AN ANTI-PAD PEELING-OFF STRUCTURE - A bonding pad having an anti-pad peeling-off structure is disclosed. In a method of forming the bonding pad, after a metal pad layer is formed, a slit is formed in the metal pad layer. A protecting layer is formed on the metal pad layer. The protecting layer is partially removed to expose the metal pad such that a portion of the protecting layer remains in the slits to be connected to the main protecting layer. The protecting layer formed in the slit is connected to the protecting layer such that the residual protecting layer pattern buffer when physical impacts are generated, to prevent peeling-off of the metal pad layer. | 2010-01-07 |
20100001329 | METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING CAPACITOR ELEMENT - In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance. | 2010-01-07 |
20100001330 | SEMICONDUCTOR DEVICE, DATA ELEMENT THEREOF AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device is provided. The method comprises: (a) providing a first and a second conductor; (b) providing a conductive layer; (c) forming a part of the conductive layer into a data storage layer by a plasma oxidation process, wherein the data storage layer is positioned between the first and the second conductor. | 2010-01-07 |
20100001331 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a transistor having source and drain regions; first and second contact electrodes embedded in a first interlayer insulating film, and electrically connected to the source region and the drain region, respectively; a third electrode embedded in a second interlayer insulating film positioned in an upper layer of the first interlayer insulating film, and electrically connected to the first contact electrode; a wiring pattern embedded in a third interlayer insulating film positioned in an upper layer of the second interlayer insulating film, and electrically connected to the third contact electrode; and a fourth contact electrode embedded in at least the second and third interlayer insulating films, and electrically connected to the second contact electrode, wherein side surfaces of the wiring pattern along an extending direction of the wiring pattern coincide with side surfaces of the third contact electrode along an extending direction of the wiring pattern. | 2010-01-07 |
20100001332 | INTEGRATING A CAPACITOR IN A METAL GATE LAST PROCESS - A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, and at least one capacitor formed in the second region. The capacitor includes a top electrode having at least one stopping structure formed in the top electrode, the at least one stopping structure being of a different material from the top electrode, a bottom electrode, and a dielectric layer interposed between the top electrode and the bottom electrode. | 2010-01-07 |
20100001333 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches ( | 2010-01-07 |
20100001334 | ATOMIC LAYER DEPOSITION EPITAXIAL SILICON GROWTH FOR TFT FLASH MEMORY CELL - A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH | 2010-01-07 |
20100001335 | Flash Memory Cells Having Leakage-Inhibition Layers - A semiconductor device includes a semiconductor substrate; a tunneling layer over the semiconductor substrate, wherein the tunneling layer has a first conduction band; a storage layer over the tunneling layer, wherein the storage layer has a second conduction band; a blocking layer over the storage layer, wherein the blocking layer has a third conduction band; a gate electrode over the blocking layer; and at least one of a first leakage-inhibition layer and a second leakage-inhibition layer. The first leakage-inhibition layer is between the tunneling layer and the storage layer, and has a fourth conduction band lower than the first conduction band. The second leakage-inhibition layer is between the blocking layer and the gate electrode, and has a fifth conduction band lower than the third conduction band. | 2010-01-07 |
20100001336 | SONOS-NAND DEVICE HAVING A STORAGE REGION SEPARATED BETWEEN CELLS - The present invention is a semiconductor device including a semiconductor substrate having a trench, a first insulating film provided on side surfaces of the trench, a second insulating film of a material different from the first insulating film provided to be embedded in the trench, a word line provided extending to intersect with the trench above the semiconductor substrate, a gate insulating film of a material different from the first insulating film separated in an extending direction of the word line by the trench and provided under a central area in a width direction of the word line, and a charge storage layer separated in the extending direction of the word line by the trench and provided under both ends in the width direction of the word line to enclose the gate insulating film, and a method for manufacturing the same. | 2010-01-07 |
20100001337 | Semiconductor memory device - A semiconductor memory device includes: sequentially stacked first and second semiconductor layers; at least one first memory transistor disposed on the first semiconductor layer; and at least one second memory transistor disposed on the second semiconductor layer, wherein a gate electrode of the first memory transistor has a broader width than that of the second memory transistor. | 2010-01-07 |
20100001338 | Non-volatile semiconductor memory device, and manufacture method for non-volatile semiconductor memory device - A non-volatile semiconductor memory device includes a semiconductor substrate, a charge-storage layer that is formed above the semiconductor substrate, a first gate that is formed above the charge-storage layer, and that includes a first surface and a second surface, a second gate that is formed beside the first surface of the first gate, an insulating layer that is formed above the second surface of the first gate, a diffusion region that is formed on the semiconductor substrate at a position corresponding to the second surface of the first gate, and a silicide layer that is formed above the insulating layer and the diffusion region. | 2010-01-07 |
20100001339 | Semiconductor device and methods of forming and operating the same - Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars. | 2010-01-07 |
20100001340 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a step-type recess pattern formed in a substrate, a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern, an insulation layer filling the gap, and a source and drain region formed in a portion of the substrate at two sides of the recess pattern. The semiconductor device is able to secure a required data retention time by suppressing the increase of leakage current caused by the reduction of a design rule. | 2010-01-07 |
20100001341 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has a first-conductivity-type substrate having second-conductivity-type base regions exposed to a first surface thereof; trench gates provided to a first surface of the substrate; first-conductivity-type source regions formed shallower than the base regions; a plurality of second-conductivity-type column regions located between two adjacent trench gates in a plan view, while being spaced from each other in a second direction normal to the first direction; the center of each column region and the center of each base contact region fall on the center line between two trench gates; and has no column region formed below the trench gates. | 2010-01-07 |
20100001342 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed. The method includes: forming a LDMOS region, an offset drain MOS region, and a CMOS region; simultaneously forming a first well in the LDMOS region and the offset drain MOS region; simultaneously forming a second well in the first well of the LDMOS region and the CMOS region; and forming a second well in the CMOS region, wherein a depth of the first well is larger than a depth of the second well and the second well is a retrograde well formed by a high energy ion implantation method. | 2010-01-07 |
20100001343 | HIGH VOLTAGE SEMICONDUCTOR DEVICE INCLUDING FIELD SHAPING LAYER AND METHOD OF FABRICATING THE SAME - Provided are a high voltage semiconductor device in which a field shaping layer is formed on the entire surface of a semiconductor substrate and a method of fabricating the same. Specifically, the high voltage semiconductor device includes a first conductivity-type semiconductor substrate. A second conductivity-type semiconductor layer is disposed on a surface of the semiconductor substrate, and a first conductivity-type body region is formed in semiconductor layer. A second conductivity-type source region is formed in the body region. A drain region is formed in the semiconductor layer and is separated from the body region. The field shaping layer is formed on the entire surface of the semiconductor layer facing the semiconductor layer. | 2010-01-07 |
20100001344 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device. | 2010-01-07 |
20100001345 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region. | 2010-01-07 |
20100001346 | Treatment of Gate Dielectric for Making High Performance Metal Oxide and Metal Oxynitride Thin Film Transistors - Embodiments of the present invention generally include TFTs and methods for their manufacture. The gate dielectric layer in the TFT may affect the threshold voltage of the TFT. By treating the gate dielectric layer prior to depositing the active channel material, the threshold voltage may be improved. One method of treating the gate dielectric involves exposing the gate dielectric layer to N | 2010-01-07 |
20100001347 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device, comprising: a metal oxide semiconductor field effect transistor (MOSFET) formed on an SOI substrate, the MOSFET including a drain region connected to an input/output terminal, a source region connected to a ground terminal, a body region, a gate electrode above the body region, and a body contact region; and a trigger circuit including a diode array having at least one diode connected in series in the forward direction between the input/output terminal, and the gate electrode and the body contact region of the MOSFET, and a resistance portion connected between the ground terminal, and the gate electrode and the body contact region of the MOSFET. | 2010-01-07 |
20100001348 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor device includes a first transistor and a second transistor formed in a semiconductor substrate. The first transistor includes: a first gate insulating film formed on the semiconductor substrate; and a first gate electrode formed on the first gate insulating film. The second transistor includes: a second gate insulating film formed on the semiconductor substrate; and a second gate electrode formed on the second gate insulating film. The first gate insulating film includes a first insulating material with a first element diffused therein, the second gate insulating film includes the first insulating material, and the amount of the first element contained in the first gate insulating film is greater than the amount of the first element contained in the second gate insulating film. | 2010-01-07 |
20100001349 | SEMICONDUCTOR DEVICE - A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer. | 2010-01-07 |
20100001350 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate. | 2010-01-07 |
20100001351 | TRIPLE WELL TRANSMIT-RECEIVE SWITCH TRANSISTOR - A transistor arrangement including a triple well structure, the triple well structure including a substrate of a first conductivity type, a first well region of a second conductivity type formed within the substrate and a second well region of the first conductivity type being separated from the substrate by the first well region. The transistor arrangement further includes a first transistor formed on or in the second well region, the first transistor including a body terminal being connected to the second well region and a second well region switch being connected to the body terminal of the first transistor. | 2010-01-07 |
20100001352 | Semiconductor device and method of manufacturing the same - A semiconductor device includes a MOSFET having: a gate electrode provided over a silicon substrate; and a first impurity diffusion region and a second impurity diffusion region provided in the silicon substrate in different sides of said first gate electrode, wherein the MOSFET has an extension region in an upper section of the first impurity diffusion region and no extension region in an upper section of the second impurity diffusion region, and has a first silicide layer over the first impurity diffusion region and has no silicide layer over the second impurity diffusion region in vicinity of a side edge of the gate electrode. | 2010-01-07 |
20100001353 | SANOS Memory Cell Structure - A semiconductor device having a silicon-aluminum oxide-nitride-oxide-semiconductor (SANOS) memory cell structure is provided. The device includes a silicon substrate including a surface, a source region and a drain region in the surface. The drain region and the source region are separate from each other. The device further includes a confined dielectric structure on the surface and between the source region and the drain region. The confined dielectric structure includes sequentially a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer. Additionally, the device includes a gate region overlying the aluminum oxide layer. In a specific embodiment, the gate region is made from patterning an amorphous silicon layer. In another specific embodiment, the gate region includes a polysilicon layer. In an alternative embodiment, a method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally or embedded for system-on-chip applications. | 2010-01-07 |
20100001354 | SELF ALIGNED MOS STRUCTURE WITH POLYSILICON CONTACT - A method for fabricating a semiconductor integrated circuit and resulting structure. The method includes providing a semiconductor substrate with an overlying dielectric layer and forming a polysilicon gate layer and an overlying capping layer. The gate layer is overlying the dielectric layer. The method also includes patterning the polysilicon gate layer to form a gate structure and a local interconnect structure. The gate structure and the local interconnect structure include a contact region defined therebetween. The gate structure also includes the overlying capping layer. The method includes forming sidewall spacers on the gate structure and the local interconnect structure and removing the sidewall spacer on the local interconnect structure. The method also includes forming contact polysilicon on the contact region and implanting a dopant impurity into the contact polysilicon. The method diffuses the dopant impurity from the contact polysilicon into the contact region in the substrate to form a diffused junction region. The method selectively removes the capping layer overlying the gate structure. The method then forms a silicide layer overlying the gate structure and surface of the contact polysilicon, whereupon the sidewall spacers isolate the silicide layer on the gate structure from the silicide layer on the contact polysilicon. | 2010-01-07 |
20100001355 | RF MEMS Switch - An RF MEMS switch having a beam composed of a material having a high resistivity and a large Young's modulus may provide a large restoring force, a large electrostatic force at a low actuation voltage, and good isolation between signal input and output. RF MEMS switch reliability may be improved by reducing failures due to stiction by providing a large restoring force. A reliable contact may be provided with a large electrostatic force. | 2010-01-07 |
20100001356 | MAGNETIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A magnetic memory device and a method for manufacturing the same are disclosed. The magnetic memory device includes a plurality of gates formed on a semiconductor substrate, a source line connected to a source/drain region shared between the gates neighboring with each other, a plurality of magnetic tunnel junctions connected to non-sharing source/drain regions of the gates on a one-to-one basis, and a bit line connected to the magnetic tunnel junctions. The magnetic memory device applies a magnetic memory cell to a memory so as to manufacture a higher-integration magnetic memory, and uses the magnetic memory cell based on a transistor of a DRAM cell, resulting in an increase in the availability of the magnetic memory. | 2010-01-07 |
20100001357 | INTEGRATED CIRCUIT PACKAGE, NOTABLY FOR IMAGE SENSOR, AND METHOD OF POSITIONING - The invention relates to the fabrication of integrated circuits in general, and notably the circuits of image sensors intended to form the electronic core of photographic apparatus or cameras. The chip is first aligned with respect to the package and then the package is aligned with respect to the optical system. The alignment of the chip with respect to the package is done optically. The alignment of the package with respect to the system is done mechanically with respect to the edges of the package. According to the invention, provision is made for optical marks to be provided on the package, these marks each having an edge aligned with a lateral edge of the package, so as to minimize the positioning errors which would be due to inaccurate positioning of the chip with respect to the edges of the package. | 2010-01-07 |
20100001358 | PHOTODETECTOR AND METHOD FOR MANUFACTURING PHOTODETECTOR - A photodetector | 2010-01-07 |
20100001359 | TRANSPARENT CONDUCTIVE LAYER AND METHOD OF MANUFACTURING THE SAME - A transparent conductive layer includes a substrate, a first conductive layer disposed on the substrate, and a second conductive layer disposed on the first conductive layer, wherein the second conductive layer comprises a textured surface and an opening which exposes the first conductive layer, wherein the opening comprises a diameter of about 1 micrometer to about 3 micrometers. Also disclosed is a method of manufacturing the transparent conductive layer and a photoelectric device. | 2010-01-07 |
20100001360 | LEVEL POSTURE SENSING CHIP AND ITS MANUFACTURING METHOD, LEVEL POSTURE SENSOR - The present invention discloses a gas pendulum style level posture sensing chip and its manufacturing method and a level posture sensor. The gas pendulum style level posture sensing chip includes: a semiconductor substrate; two sets of arm thermosensitive fuses formed on the surface of the semiconductor substrate, each set of the thermosensitive fuses including two thermosensitive fuses in parallel to each other, the two sets of thermosensitive fuses being vertical to each other; electrodes formed at the two ends of the thermosensitive fuses. For the level posture sensing chip and sensor provided by the present invention, the parallelism and verticality of the thermosensitive fuses is high in precision such that the more accurate measurement can be implemented. | 2010-01-07 |
20100001361 | SUSPENDED GETTER MATERIAL-BASED STRUCTURE - Getter structure comprising a substrate and at least one getter material-based layer mechanically connected to the substrate by means of at least one support, in which the surface of the support in contact with the substrate is smaller than the surface of a first face of the getter material layer, in which said first face is in contact with the support, and a second face of the getter material layer, opposite said first face is at least partially exposed. | 2010-01-07 |
20100001362 | EDGE TERMINATION FOR SEMICONDUCTOR DEVICE - A semiconductor device has active region ( | 2010-01-07 |
20100001363 | Semiconductor Device and Method of Providing Electrostatic Discharge Protection for Integrated Passive Devices - A semiconductor device has an integrated passive device (IPD) formed on a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed on the front side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed on the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed on the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed on the substrate and electrically connects the conductive layer to a ground point. | 2010-01-07 |
20100001364 | Semiconductor Device Having Improved Oxide Thickness at a Shallow Trench Isolation Edge and Method of Manufacture Thereof - One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer. | 2010-01-07 |
20100001365 | ISOLATION TECHNIQUE ALLOWING BOTH VERY HIGH AND LOW VOLTAGE CIRCUITS TO BE FABRICATED ON THE SAME CHIP - An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000 s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk. | 2010-01-07 |
20100001366 | Semiconductor device having shared bit line structure and method of manufacturing the same - A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions. | 2010-01-07 |
20100001367 | Method and Resulting Structure DRAM Cell with Selected Inverse Narrow Width Effect - A shallow trench isolation structure for integrated circuits. The structure includes a semiconductor substrate and a buffered oxide layer overlying the semiconductor substrate. A pad nitride layer is overlying the buffered oxide layer. An implanted region is formed around a perimeter of the trench region. A trench region is formed within the semiconductor substrate. The trench region has a bottom width of less than 0.13 microns and an upper width of less than 0.13 microns. A rounded edge region is within a portion of the semiconductor substrate surrounding a periphery of the trench region. The rounded edges have a radius of curvature greater than about 0.02 um. A planarized high density plasma fill material is formed within the trench region. The structure has a P-well region within the semiconductor substrate and bordering a vicinity of the trench region. A channel region is within the P-well region within the semiconductor substrate. The implanted region has a concentration of more than double an amount of impurities as impurities in the channel region. | 2010-01-07 |
20100001368 | Microelectromechanical device packaging with an anchored cap and its manufacture - Integrated circuit ( | 2010-01-07 |
20100001369 | DEVICE LAYOUT FOR GATE LAST PROCESS - A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region. | 2010-01-07 |
20100001370 | INTEGRATED CIRCUIT SYSTEM EMPLOYING ALTERNATING CONDUCTIVE LAYERS - An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace. | 2010-01-07 |
20100001371 | SEMICONDUCTOR DEVICE HAVING CAPACITOR INCLUDING A HIGH DIELECTRIC FILM AND MANUFACTURE METHOD OF THE SAME - A semiconductor device includes a substrate, a plurality of lower electrodes arranged on the substrate, a high dielectric film disposed continuously on the plurality of lower electrodes, and an upper electrode disposed on the high dielectric film. | 2010-01-07 |
20100001372 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Stable contact hole forming is attained even when an aluminum oxide film is present between layers provided with contact holes. The process comprises the steps of forming a first element layer on a semiconductor substrate; forming a first interlayer insulating film on the first element layer; forming a second element layer on the first interlayer insulating film; forming a second interlayer insulating film on the second element layer; forming a hole resist pattern on the second interlayer insulating film; conducting a first etching for forming of holes by etching the second interlayer insulating film; and conducting a second etching for extending of holes to the first element layer by etching the first interlayer insulating film. | 2010-01-07 |
20100001373 | CORRESPONDING CAPACITOR ARRANGEMENT AND METHOD FOR MAKING THE SAME - The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability. | 2010-01-07 |
20100001374 | EPITAXIAL LIFT OFF STACK HAVING A MULTI-LAYERED HANDLE AND METHODS THEREOF - Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods for forming such films and devices. In one embodiment, a method for forming an ELO thin film includes depositing an epitaxial material over a sacrificial layer on a substrate, adhering a multi-layered support handle onto the epitaxial material, and removing the sacrificial layer during an etching process. The etching process further includes peeling the epitaxial material from the substrate and forming an etch crevice therebetween while maintaining compression in the epitaxial material. The method further provides that the multi-layered support handle contains a stiff support layer adhered to the epitaxial material, a soft support layer adhered to the stiff support layer, and a handle plate adhered to the soft support layer. In one example, the stiff support layer may contain multiple inorganic layers, such as metal layers, dielectric layers, or combinations thereof. | 2010-01-07 |
20100001375 | Patterned Substrate for Hetero-epitaxial Growth of Group-III Nitride Film - A circuit structure includes a substrate and a film over the substrate and including a plurality of portions allocated as a plurality of rows. Each of the plurality of rows of the plurality of portions includes a plurality of convex portions and a plurality of concave portions. In each of the plurality of rows, the plurality of convex portions and the plurality of concave portions are allocated in an alternating pattern. | 2010-01-07 |
20100001376 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR SELF-SUPPORTING SUBSTRATE AND NITRIDE SEMICONDUCTOR SELF-SUPPORTING SUBSTRATE - The present invention provides a method for manufacturing a nitride semiconductor self-supporting substrate and a nitride semiconductor self-supporting substrate manufactured by this manufacturing method, the method including at least: a step of preparing a nitride semiconductor self-supporting substrate serving as a seed substrate; a step of epitaxially growing the same type of nitride semiconductor as the seed substrate on the seed substrate; and a step of slicing an epitaxially grown substrate subjected to the epitaxial growth into two pieces in parallel to an epitaxial growth surface. As a result, there is provided a method for manufacturing a large-diameter nitride semiconductor self-supporting substrate having an excellent crystal quality and small warp with good productivity at a low cost, etc. | 2010-01-07 |
20100001377 | Semiconductor device - A semiconductor device ( | 2010-01-07 |
20100001378 | Through-substrate vias and method of fabricating same - An through-substrate via fabrication method requires forming a through-substrate via hole in a semiconductor substrate, depositing an electrically insulating, continuous and substantially conformal isolation material onto the substrate and interior walls of the via using ALD, and depositing a conductive material into the via and over the isolation material using ALD such that it is electrically continuous across the length of the via hole. The isolation material may be prepared by activating it with a seed layer deposited by ALD. The via hole is preferably formed by dry etching first and second cavities having respective diameters into the substrate's top and bottom surfaces, respectively, to form a single continuous aperture through the substrate. The present method may be practiced at temperatures of less than 200° C. The basic fabrication method may be extended to provide vias with multiple conductive layers, such as coaxial and triaxial vias. | 2010-01-07 |
20100001379 | Multi-chip package (MCP) having three dimensional mesh-based power distribution network, and power distribution method of the MCP - A MCP includes a plurality of semiconductor memory devices, the plurality of semiconductor memory devices being stacked to define a three-dimensional (3D) structure, and a mesh structure, the mesh structure interconnecting the plurality of semiconductor memory devices to define a 3D mesh-based power distribution network. | 2010-01-07 |
20100001380 | Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device includes: forming a groove portion in a dicing region of an insulating layer and forming a via hole in an internal circuit formation region; providing a first resist film on the insulating layer; providing a second resist film to cover the first resist film; forming an interconnect opening in a region covering an internal circuit formation region of the second resist film and forming a position aligning opening in a region covering the dicing region of the second resist film; and detecting a positional relationship between the groove portion and the position aligning opening so as to detect whether the interconnect opening of the second resist film exists at a predetermined position with respect to the via hole of the insulating layer. In selective removing of the second resist film, the position aligning opening is formed such that a region of the position aligning opening covers the groove portion of the insulating layer. | 2010-01-07 |
20100001381 | SEMICONDUCTOR DEVICE - Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of performing an exposure process for forming a first photoresist on a semiconductor substrate at one side of the outside of a trench pattern which will be formed, a first etching step of performing a predetermined dry etching method with respect to the first photoresist, a second exposure step of performing an exposure process for forming a second photoresist at the other side of the outside of the trench pattern, which is a side opposite to the first photoresist, and a second etching step of performing the predetermined dry etching method with respect to the second photoresist. | 2010-01-07 |
20100001382 | MANUFACTURING METHOD FOR INTEGRATING A SHUNT RESISTOR INTO A SEMICONDUCTOR PACKAGE - An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads. | 2010-01-07 |
20100001383 | INTEGRATED CIRCUIT PACKAGE WITH MOLDED INSULATION - A variety of improved arrangements and processes for packaging integrated circuits are described. More particularly, methods of encapsulating dice in lead frame based IC packages are described that facilitate covering some portions of the bottom surface of the lead frame while leaving other portions of the bottom surface of the lead frame exposed. In some embodiments, a method of encapsulating integrated circuits mounted on a lead frame panel is described. The lead frame panel includes a plurality of leads having associated contacts and supports. A shim having a plurality of cavities is positioned under the lead frame such that the cavities are adjacent to the supports and not adjacent to the contacts. During the encapsulation process, encapsulant material flows under the supports such that the bottom surfaces of the supports are electrically insulated by the encapsulant while the bottom surfaces of the contacts remain exposed. | 2010-01-07 |
20100001384 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD-FRAME PADDLE SCHEME FOR SINGLE AXIS PARTIAL SAW ISOLATION - An integrated circuit package system includes: providing a die-pad with a predefined slot and an integrated circuit attached to the die-pad; connecting the integrated circuit to the die-pad with a bond wire; encapsulating the integrated circuit and the bond wire with an encapsulation; and partitioning the die-pad with partial saw isolation grooves along a single axis, and into a side pad, and a die attach pad. | 2010-01-07 |
20100001385 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH BUMPED LEAD AND NONBUMPED LEAD - An integrated circuit package system includes: forming an external interconnect; forming a terminal having a cavity adjacent to and downset from a portion the external interconnect; connecting a first integrated circuit with the external interconnect; and forming an encapsulation over the first integrated circuit with cavity filled with the encapsulation, the terminal extending from the encapsulation, and the external interconnect partially exposed from the encapsulation. | 2010-01-07 |
20100001386 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device and a manufacturing method therefor wherein a wire for coupling an inner lead and a semiconductor chip with each other can be prevented from being electrically short-circuited to any other conductive part are provided. An inner lead portion has a tip arranged outside the outer circumferential end of the semiconductor chip as viewed on a plane. A power supply bar has a jutted portion extended between the outer circumferential end of the semiconductor chip and the tip of the inner lead portion as viewed on a plane. The upper face of the jutted portion is in a position lower than the upper face of the tip of the inner lead portion. A bonding wire for electrically coupling the semiconductor chip and the inner lead portion with each other has a bent portion outside the outer circumferential end of the semiconductor chip as viewed on a plane. | 2010-01-07 |
20100001387 | ELECTRONIC DEVICE, ELECTRONIC APPARATUS MOUNTED WITH ELECTRONIC DEVICE, ARTICLE EQUIPPED WITH ELECTRONIC DEVICE AND METHOD OF PRODUCING ELECTRONIC DEVICE - An electronic device includes: a base; a conductor pattern formed on the base; and a circuit chip electrically connected to the conductor pattern. The electronic device further includes a reinforcing member which is disposed on the base to surround the circuit chip, whose outer shape is like a ring, and which includes layers stacked in the thickness direction of the base. The lowermost layer of the layers is closest to the base and softer than the layer that is at least one of the remaining layers. The electronic device further includes a sealing member which fills an inside of the reinforcing member while covering the top of the circuit chip, thereby sealing the circuit chip on the base. | 2010-01-07 |
20100001388 | ELECTRONIC DEVICE, ELECTRONIC APPARATUS MOUNTED WITH ELECTRONIC DEVICE, ARTICLE EQUIPPED WITH ELECTRONIC DEVICE AND METHOD OF PRODUCING ELECTRONIC DEVICE - An electronic device includes: a base; a conductor pattern formed on the base; a circuit chip electrically connected to the conductor pattern; and a reinforcing member which is disposed on the base to surround the circuit chip, whose outer shape is like a ring, and which includes concentric rings as an internal structure. The electronic device further includes a sealing member which fills an inside of the reinforcing member while covering the top of the circuit chip, thereby sealing the circuit chip on the base. | 2010-01-07 |
20100001389 | PACKAGE STRUCTURE FOR RADIO FREQUENCY MODULE AND MANUFACTURING METHOD THEREOF - A package structure for radio frequency module and a manufacturing method thereof are provided. The package structure includes a multi-layer substrate, a first chip, a second chip, a number of solder bumps, a first molding compound and a second molding compound. The substrate includes a metallic middle layer and has a first and a second surfaces. The first and the second chips respectively disposed on the first and the second surfaces are electrically connected to the substrate. The first molding compound is disposed on the first surface and covers the first chip. The solder bumps disposed on the second surface are respectively electrically connected to the first and the second chips via the substrate. The second molding compound disposed on the second surface covers the second chip and encircles the sidewalls of the solder bumps, and the connection surfaces of solder bumps are exposed outside the second molding compound. | 2010-01-07 |
20100001390 | SYSTEM IN PACKAGE MODULE - A System in Package (SIP) module includes a printed circuit board with at least one cavity formed therein. The module also includes at least one first device mounted in the cavity and a circuit pattern formed on an undersurface of the cavity and electrically connected to the first device. The module further includes at least one second device mounted on a printed circuit board surface corresponding to the undersurface of the cavity. | 2010-01-07 |
20100001391 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORTED STACKED DIE - An integrated circuit package system provides a leadframe having a short lead finger, a long lead finger, and a support bar. A first die is placed in the leadframe. An adhesive is attached to the first die, the long lead finger, and the support bar. A second die is offset from the first die. The offset second die is attached to the adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant. | 2010-01-07 |
20100001392 | Semiconductor package - Provided is a semiconductor package including a substrate and a semiconductor chip formed on the substrate. The semiconductor chip may include a chip alignment mark on a surface of the semiconductor chip, and wiring patterns formed on a surface of the substrate, wherein the chip alignment mark is bonded to the wiring patterns. Accordingly, the surface area of the semiconductor chip may be reduced. | 2010-01-07 |
20100001393 | SEMICONDUCTOR DEVICE - A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other. | 2010-01-07 |
20100001394 | CHIP PACKAGE WITH ESD PROTECTION STRUCTURE - A chip package comprises a semiconductor chip, a plurality of pins coupled to the semiconductor chip, and a conductive structure configured to form an electrical connection between the pins, wherein the electrical connection is configured to be disabled as the chip package is inserted into a socket. Since the pins are electrically connected by the conductive structure, the surge current caused by an ESD event can be distributed to all pins rather than to a single pin as the ESD event occurs. Consequently, all ESD protection circuits connected to the pins can be used to dissipate the surge current during the ESD event, and the circuit damage caused by the ESD can be dramatically reduced. | 2010-01-07 |
20100001395 | SEMICONDUCTOR CHIP ASSEMBLY WITH POST/BASE HEAT SPREADER AND VERTICAL SIGNAL ROUTING - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a substrate and an adhesive. The semiconductor device is electrically connected to the substrate and thermally connected to the heat spreader. The heat spreader includes a post and a base. The post extends upwardly through an opening in the adhesive into an aperture in the substrate, and the base extends laterally and supports the substrate. The adhesive extends between the post and the substrate and between the base and the substrate. The substrate includes first and second conductive layers and a dielectric layer therebetween, and the assembly provides vertical signal routing between a pad at the first conductive layer and a terminal below the adhesive. | 2010-01-07 |
20100001396 | REPAIRABLE SEMICONDUCTOR DEVICE AND METHOD - Repairable semiconductor device and method. In one embodiment a method, provides a first body having a first semiconductor chip and a first metal layer. A second body includes a second semiconductor chip and a second metal layer. Metal of the first metal layer is removed. The first semiconductor chip is removed from the first body. The second body is attached to the first body. The first metal layer is electrically coupled to the second metal layer. | 2010-01-07 |
20100001397 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of NAND memory dies each including: a first wiring layer formed in the NAND memory die; a second wiring layer formed in the NAND memory die; a first insulation layer formed between the first wiring layer and the second wiring layer; and a first interlayer connector formed in the first insulation layer, a controller configured to control the NAND memory dies; a package housing the NAND memory dies and the controller; a connecting portion electrically connecting an inner side of the package and an outer side of the package; a first connecting wire; and a second connecting wire, wherein a resistance value per unit length of the first interlayer connector is larger than a resistance value per unit length of the first wiring layer, and wherein the first interlayer connector is cut off when a first current flows through the first interlayer connector. | 2010-01-07 |
20100001398 | SEMICONDUCTOR CHIP MODULE AND MANUFACTURING METHOD THEREOF - A semiconductor chip module includes a first flip-chip unit and a second flip-chip unit. The first flip-chip unit has a first chip and a first glass circuit board. The first chip is connected with the first glass circuit board by flip-chip bonding. The second flip-chip unit has a second chip and a second glass circuit board. The second chip is connected with the second glass circuit board by flip-chip bonding. The first flip-chip unit and the second flip-chip unit are attached to each other. A method for manufacturing the semiconductor chip module is also disclosed. | 2010-01-07 |
20100001399 | Semiconductor Chip Passivation Structures and Methods of Making the Same - Various semiconductor chip passivation structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymeric passivation layer to a side of a semiconductor chip. The side of the semiconductor chip includes plural conductor pads. Plural openings are formed in the polymeric passivation layer to expose the plural conductor pads. Plural conductor structures are formed on the plural conductor pads. | 2010-01-07 |
20100001400 | SOLDER CONTACT - A low melting temperature solder is provided for producing a solder contact between a connection element and a contact structure of a semiconductor component. | 2010-01-07 |