01st week of 2011 patent applcation highlights part 16 |
Patent application number | Title | Published |
20110001504 | METHOD AND APPARATUS OF DEEMBEDDING - Provided is a method of de-embedding. The method includes forming a test structure having a device-under-test embedded therein, the test structure having left and right pads coupling the device-under-test, the device-under-test dividing the test structure into left and right half structures, the left and right half structures each having intrinsic transmission parameters; forming a plurality of dummy test structures, each dummy test structure including a left pad and a right pad; measuring transmission parameters of the test structure and the dummy test structures; and deriving intrinsic transmission parameters of the device-under-test using the intrinsic transmission parameters of the left and right half structures and the transmission parameters of the test structure and the dummy test structures. | 2011-01-06 |
20110001505 | TEST SOCKETS FABRICATED BY MEMS TECHNOLOGY FOR TESTING OF SEMICONDUCTOR DEVICES - The present invention dicloses test sockets fabricated by MEMS technology for testing of semiconductor devices. Semiconductor device test sockets fabricated by MEMS technology in accordance with one or more embodiments of the invention offer many unique advantages over conventional test sockets (e.g. sockets utilizing pogo-pins). In one embodiment of the invention, a novel test socket includes a substrate with multiple cavities of certain depths in middle region of one side, electrical contacts (electrodes) of cantilever type directly above the cavities making individual contact with each contactor of semiconductor device, and multiple signal paths electrically connecting the cantilever type contacts on one side of the substrate and the loadboard PCB(printed circuit board) or motherboard PCB placed on the other side of the substrate. | 2011-01-06 |
20110001506 | TESTING APPARATUS FOR INTEGRATED CIRCUIT - An apparatus for testing an integrated circuit comprises: a chip unit with a plurality of electronic parts such as chip units arranged on the upside of a chip support; a probe unit having a plurality of contacts arranged on the underside of a probe support and spaced downward from the chip unit; a connection unit supporting the probe unit spaced downward from the chip unit on a pin support so as to penetrate the pin support in an up-down direction; and a coupling unit which couples separably the chip unit, the probe unit and the connection unit and displaces one of the chip support and the probe support and the pin support in a direction to approach each other and to be away from each other relative to the connection unit. | 2011-01-06 |
20110001507 | SEMICONDUCTOR DEVICE AND METHOD OF PERFORMING ELECTRICAL TEST ON SAME - A semiconductor device comprises a substrate, a plurality of bonding pads formed on the substrate, a reference pad comprising a plurality of sensing lines located in a reference pad area of the substrate, and a plurality of detection wirings electrically connected to the respective sensing lines. The bonding pads are configured to make contact with a plurality of probe pins of a test apparatus to receive electrical test signals for an electrical test of the semiconductor device. The reference pad is configured to make contact with a reference pin of the test apparatus, and the reference pad area has substantially the same shape and size as the bonding pads such that positions in the reference pad area correspond one-to-one with positions in each of the bonding pads. | 2011-01-06 |
20110001508 | SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT - In order to reduce the number of electrodes included in test patterns, the semiconductor integrated circuit includes, a plurality of first and second chains, a first common electrode connected to one end of each first chain, a second common electrode connected to one end of each second chain, and a plurality of selection electrodes. Each selection electrode is connected to the other end of any one of the plurality of first chains and to the other end of any one of the plurality of second chains. When a test target chain is selected from the plurality of first chains, a first reference voltage is applied to the first common electrode, a second reference voltage is applied to a target selection electrode that is connected to the test target chain, and a current flowing in the target selection electrode is measured to obtain a resistance value of the test target chain. | 2011-01-06 |
20110001509 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR TESTING THE SAME - A semiconductor integrated circuit device includes: terminals | 2011-01-06 |
20110001510 | SEMICONDUCTOR DEVICE - A semiconductor device is able to terminate internal transmission lines and including a pre-driving unit configured to generate a pull-up driving signal and a pull-down driving signal corresponding to an output data signal, and transfer the pull-up driving signal and the pull-down driving signal to a first transmission line and a second transmission line, respectively, a main driving unit configured to drive an output data in response to the pull-up driving signal and the pull-down driving signal transferred through the first transmission line and the second transmission line and a termination unit configured to be supplied with a termination voltage to terminate the first transmission line and the second transmission line. | 2011-01-06 |
20110001511 | OUTPUT CIRCUIT FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE HAVING OUTPUT CIRCUIT, AND METHOD OF ADJUSTING CHARACTERISTICS OF OUTPUT CIRCUIT - To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased. | 2011-01-06 |
20110001512 | INTELLIGENT CELLULAR ELECTRONIC STRUCTURES - An apparatus and method controlling cellular automata containing a plurality of cascaded circuit cells having logic units. The cells are interleaved in groups toward supporting multiple directions, for example quad cells in which each cells of the quad is directed in a different directions separated by a fixed angle, such as 90 degrees (i.e., north, east, south, and west). These cells are triggered asynchronously as each cell is stabilized in preparation for receiving the trigger. The cells process data selectively based on the configuration of the cell and in response to receipt of data and trigger (or combined data and trigger) conditions from neighboring cells. The array can be utilized within a wide range of digital logic. As there is no need for distributing a global clock across the array of cells, the size of the array can be extended to any desired dimension. | 2011-01-06 |
20110001513 | CMOS INPUT BUFFER CIRCUIT - Provided is a complementary metal oxide semiconductor (CMOS) input buffer circuit that is capable of lower voltage operation with lower current consumption. The CMOS input buffer circuit includes: a depletion type NMOS transistor including a drain connected to a power supply terminal (VDD), and a gate connected to an output terminal; a PMOS transistor including a source connected to a source of the depletion type NMOS transistor, a drain connected to the output terminal, and a gate connected to an input terminal; and an NMOS transistor including a source connected to a reference terminal (GND), a gate connected to the input terminal, and a drain connected to the output terminal. | 2011-01-06 |
20110001514 | COMMAND CONTROL CIRCUIT FOR SEMICONDUCTOR INTEGRATED DEVICE - A command control circuit of a semiconductor integrated device includes a plurality of latches sequentially connected and receiving a command signal, and a plurality of selection switches configured to pass or to interrupt the command signal inputted to each one of the plurality of latches. | 2011-01-06 |
20110001515 | COMPARATOR WITH SELF-LIMITING POSITIVE FEEDBACK - A method and circuit for attenuating positive feedback in a comparator in one embodiment includes an amplifier configured to compare a first input signal with a second input signal and to provide an output based upon the comparison, a non-linear function with a first input operably connected to an output of the amplifier, and a feedback loop operably connected to the output of the non-linear function and to a second input of the non-linear function, the feedback loop including a feedback limiting circuit configured to attenuate a feedback signal to the second input of the non-linear function. | 2011-01-06 |
20110001516 | CIRCUIT, APPARATUS, AND METHOD FOR SIGNAL TRANSFER - A signal transfer circuit according to the present invention includes a differential signal generation unit that generates a differential signal according to a voltage difference between two input signals, a voltage difference detection unit that detects a voltage difference between the two input signals input to the differential signal generation unit, and a signal output unit that outputs a signal including a predetermined value if the voltage difference is not detected by the voltage difference detection unit, and outputs the differential signal generated by the differential signal generation unit if the voltage difference is detected by the voltage detection unit. | 2011-01-06 |
20110001517 | SEMICONDUCTOR DEVICE - A disclosed semiconductor device includes an input terminal, a power line, a pnp-bipolar transistor connected to the power line, a first resistor connecting an emitter of the transistor to the input terminal, a second resistor connecting a collector of the transistor to ground, an operation circuit operable when the input voltage is a predetermined voltage or higher, the predetermined voltage being set within a first voltage region in which the input voltage cannot turn on the transistor, a comparator comparing an internal voltage with a reference voltage, the internal voltage being changed from a voltage value in a non-conductive state in which the transistor is not turned on, and an output terminal configured to output an output voltage which changes in response to a result of comparing the internal voltage with the reference voltage. | 2011-01-06 |
20110001518 | OPERATING A SWITCHED-CAPACITOR CIRCUIT WITH REDUCED NOISE - Techniques for operating a switched-capacitor circuit to reduce input and feedback dependence and/or reduce reference modulation. A switched-capacitor circuit can be operated in four phases. In a first phase at a start of a cycle, the capacitor is charged/discharged by a common mode signal to mask any residual charge stored in the capacitor from a previous cycle. In a second phase, the capacitor is charged with an input signal. During a third phase, the capacitor is charged with a wide-bandwidth auxiliary reference signal, and during a fourth phase the capacitor is charged with a reference signal. During the third and fourth phases, the capacitor may be coupled to an integrating to circuit to integrate a difference between the input signal and the reference signal. | 2011-01-06 |
20110001519 | SYSTEM FOR CONVERTING CHARGE INTO VOLTAGE AND METHOD FOR CONTROLLING THIS SYSTEM - The invention relates to controlling a device for converting charge into voltage comprising an amplifier and at least one capacitor mounted in inverse feedback between an input and an output of said amplifier, whereby said amplifier can be connected between at least one input stage, to receive a charge therefrom, and at least one output stage to deliver voltage thereto, said voltage being representative of the charge received at the input, said method comprising at least one phase comprising the voltage conversion of a charge received at the input. According to the invention the conversion phase comprises at least: one first sub-phase during which the amplifier is connected to the input stage and the amplifier is disconnected from the output stage; followed, by a second sub-phase during which the amplifier is disconnected from the input stage and the amplifier is connected to the output stage. | 2011-01-06 |
20110001520 | Driver circuit and image forming apparatus - A driver circuit includes a memory cell for storing data and a data switching circuit. The memory cell includes a first inverter having a first output terminal and a first input terminal and a second inverter having a second output terminal and a second input terminal. The first output terminal is connected to the second input terminal and the second output terminal is connected to the first input terminal. A switch is connected to the first input terminal so that the data is fed to the memory cell through the switch. A voltage shifter supplies a first supply voltage to the first inverter and second inverter while the data is being written into the memory cell and a second supply voltage to the first inverter and second inverter after the data has been written into the memory cell. | 2011-01-06 |
20110001521 | Frequency Divider - This disclosure relates to a divide-by-N frequency divider system and frequency dividing method. The system includes a ring oscillator having M stages, where M is an integer, and a zero mean current component coupled to one or more of the stages to provide a zero mean current flow path. | 2011-01-06 |
20110001522 | HIGH SPEED DIVIDE-BY-TWO CIRCUIT - A high frequency divider involves a plurality of differential latches. Each latch includes a pair of cross-coupled P-channel transistors and a variable resistance element. The latch is controlled to have a lower output resistance at high operating frequencies by setting a multi-bit digital control value supplied to the variable resistance element. Controlling the latch to have a reduced output resistance at high frequencies allows the 3 dB bandwidth of the latch to be maintained over a wide operating frequency range. The variable resistance element is disposed between the two differential output nodes of the latch such that appreciable DC bias current does not flow across the variable resistance element. As a consequence, good output signal voltage swing is maintained at high frequencies, and divider current consumption does not increase appreciably at high frequencies as compared to output signal swing degradation and current consumption increases in a conventional differential latch divider. | 2011-01-06 |
20110001523 | FREQUENCY SYNTHESIZER - Provided is a frequency synthesizer capable of fine setting over a wide band and having a wide frequency pull-in range. A sine wave signal of an output frequency of a voltage controlled oscillating part is quadrature-detected, and in a PLL utilizing a vector rotating at a frequency (velocity) equal to a difference from a frequency of a frequency signal used for the detection, a frequency pull-in means integrates a first constant for increasing the output frequency as a pull-in voltage when a control voltage from the PLL to the voltage controlled oscillating part is larger than a prescribed set range, and integrates a second constant for decreasing the output frequency as the pull-in voltage when the control voltage is smaller than the set range. Then, an adding means adds the control voltage from the PLL and the pull-in voltage from the frequency pull-in means to output an addition result to the voltage controlled oscillating part. | 2011-01-06 |
20110001524 | Phase locked loop circuit - A Phase Locked Loop circuit, includes: a main path through which an input signal is propagated, and an actual signal is output; a main feedback path through which the actual signal is fed back to an input stage of the main path; and a local feedback path through which feedback is carried out from a path middle of the main path to a path middle of an input stage side; the main path including a phase detector, a loop filter, and a controlled oscillator, and the local feedback path including a replica portion, a delay portion, a first subtracter, and a second subtracter. | 2011-01-06 |
20110001525 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes: a voltage level detector for detecting of an external power source voltage level; a phase comparator for comparing phases of reference clock and feedback clock; a clock delayer for designating one of a first delay cell unit and a second delay cell unit as initial delay cell unit and the other as connected delay cell unit, delaying the reference clock by the initial delay cell unit until delay amount of the reference clock reaches a predetermined delay amount, delaying the reference clock by the connected delay cell unit after the delay amount of the reference clock reaches the predetermined delay amount in response to an output signal of the phase comparator, and outputting a delay locked clock; and a delay duplication modeler for changing the delay locked clock to reflect an actual delay condition of the reference clock and outputting the feedback clock. | 2011-01-06 |
20110001526 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a phase comparison unit configured to compare a reference clock with a feedback clock and to output a phase comparison signal, a clock delay unit configured to delay a first reference clock in response to the phase comparison signal, to output a first delay locked clock, to delay one of the first delay locked clock and a second reference clock according to a frequency information signal, and to output a second delay locked clock, a delay locked clock generating unit configured to output a delay locked clock as a phase-mixed clock of the first delay locked clock and the second delay locked clock, the first delay locked clock, or the second delay locked clock in response to the frequency information signal and a delay transfer signal, and a delay replica model unit configured to reflect a delay condition of the reference clock. | 2011-01-06 |
20110001527 | DUTY-CYCLE ERROR CORRECTION CIRCUIT - A duty cycle error correction circuit is disclosed. The circuit includes an inversion and delay circuit and a phase interpolator. The inversion and delay circuit is configured to receive an input signal having a waveform that includes a duty cycle error, delay and invert the input signal to form an inverted delayed signal, a determine whether the input signal and the inverted delayed signal are in phase. The phase interpolator is configured to receive the input signal, receive the inverted delayed signal, interpolate the received input signal and the received inverted delayed signal, and based on the interpolation, output a duty cycle error corrected signal. | 2011-01-06 |
20110001528 | PERIODIC SIGNAL SYNCHRONIZATION APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are disclosed that operate to generate a periodic output signal from a periodic input signal, obtain a plurality of samples of a phase difference between the output signal and the input signal, and to adjust a phase of the output signal based on the samples of the phase difference. Additional apparatus, systems, and methods are disclosed. | 2011-01-06 |
20110001529 | SIGNAL PROCESSING CIRCUIT, AGC CIRCUIT, AND RECORDING AND PLAYBACK DEVICE - Disclosed herein is a signal processing circuit including: a main path configured to transmit an input signal and output an actual signal; and a negative feedback path configured to feed back the actual signal to an input stage of the main path, wherein the main path includes a main path block that receives an input signal and outputs an actual signal, the negative feedback path includes a negative feedback block that generates a control signal and supplies the control signal to an input part of an input signal of the main path; a replica block that is supplied with a control signal of the negative feedback block to output a pseudo actual signal, and imitates the main path block; and a signal delay block that delays a pseudo actual signal of the replica block by a dead time of a loop. | 2011-01-06 |
20110001530 | METHOD AND APPARATUS FOR RECEIVING BURST DATA WITHOUT USING EXTERNAL DETECTION SIGNAL - Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data. | 2011-01-06 |
20110001531 | Method and apparatus for receiving burst data without using external detection signal - Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data. | 2011-01-06 |
20110001532 | SEMICONDUCTOR DEVICE - A semiconductor device includes a phase division unit, a clock delay unit, a duty cycle correction clock generation unit, and a duty cycle correction voltage generation unit. The phase division unit is configured to divide a phase of a source clock to generate a first division clock. The clock delay unit is configured to delay the first division clock by a delay amount corresponding to a voltage level of a duty cycle correction voltage to output a second division clock. The duty cycle correction clock generation unit is configured to generate a duty cycle correction clock whose logic level changes at respective edges of the first division clock and the second division clock. The duty cycle correction voltage generation unit is configured to generate the duty cycle correction voltage whose voltage level changes depending on a duty cycle of the duty cycle correction clock. | 2011-01-06 |
20110001533 | SAMPLING CIRCUIT - A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal. | 2011-01-06 |
20110001534 | Voltage Generator Capable of Preventing Latch-up and Method Thereof - A voltage generator capable of preventing latch-up is disclosed. The voltage generator includes a positive charge pump unit, a negative charge pump unit, a second stage charge pump unit, and a control unit. The positive charge pump unit is utilized for generating a positive charge pump voltage according to a first enable signal. The negative charge pump is utilized for generating a negative charge pump voltage according to a second enable signal. The second stage charge pump unit is utilized for generating a gate-on voltage and a gate-off voltage according to a third enable signal and a fourth enable signal. The control unit is utilized for generating the first enable signal, the second enable signal, the third enable signal, and the fourth enable signal and make the second stage charge pump unit generate the gate-on voltage (or the gate-off voltage) in a successively-increasing (or decreasing) manner. | 2011-01-06 |
20110001535 | SEQUENTIAL CIRCUIT WITH DYNAMIC PULSE WIDTH CONTROL - A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit. | 2011-01-06 |
20110001536 | STATIC LATCH - A static latch includes a clock-based driver, an actuation circuit, and a weak latched unit. The clock-based driver includes first node, second node, a driving unit, first pass switch, and second pass switch. The driving unit drives the first node corresponding to first voltage in response to first level of an input signal and drives the second node having second voltage in response to second level of the input signal. The first pass switch drives an output node having a latched signal corresponding to the first voltage in response to the clock signal. The second pass switch drives the output node corresponding to the second voltage in response to the inverted clock signal. The actuation circuit drives the output node corresponding to the second voltage in response to the clock signal. The weak latch unit keeps the level of the latched signal when the static latch is disabled. | 2011-01-06 |
20110001537 | DELAY LINE - A delay line includes a delay amount adjusting unit configured to adjust a delay amount of an input signal in response to a first delay control code, and a delay unit configured to determine a number of first delay blocks having a delay amount with a first variation width and a number of second delay blocks having a delay amount with a second variation width in response to a second delay control code, wherein the delay amount with the first variation width and the delay amount with the second variation width are determined by the delay amount adjusting unit and the first and second variation widths correspond to a level change of a power supply. | 2011-01-06 |
20110001538 | Voltage level shifter - A voltage level shifter is provided for receiving an input signal from an input voltage domain and converting said signal to a shifted signal in a shifted voltage domain. The voltage level shifter has an input, switching circuitry, a pass transistor and an output. The switching circuitry is configured to isolate an output of said pass transistor from said supply voltage rail when said input voltage domain corresponds to a logical zero. | 2011-01-06 |
20110001539 | MIXER-TRANSCONDUCTANCE INTERFACE - Techniques for providing an efficient interface between a mixer block and a transconductance (Gm) block. In an exemplary embodiment, the output currents of at least two unit cells of the transconductance block are conductively coupled together, and coupled to the mixer block using a single conductive path. For a differential signal, the conductive path may include two conductive leads. Within the mixer block, the single conductive path may be fanned out to at least two unit cells of the mixer block. At least one Gm unit cell may be selectively enabled or disabled to control the gain setting of the mixer-transconductance block. The techniques may further be applied to transceiver architectures supporting in-phase and quadrature mixing, as well as multi-mode and/or multi-band operation. | 2011-01-06 |
20110001540 | COMBINED MIXER AND BALUN DESIGN - A circuit with inputs for first (LO) and second (IF) unbalanced signals at respective first and second frequencies, also comprising a mixer for the first and second input signals to produce a third signal (RF) at a third frequency at an output port. The mixer comprises first and second transistors which are cross-coupled to each other. Output terminals of the transistors are connected to the output port, and the mixer also comprises a first impedance connected to ground. The mixer, by means of the transistors and the first impedance is an active balun for the first input signal (IF), and the input port for the second signal (LO) comprises a second impedance, so that the first and second impedances together act as a passive balun for the second signal (LO). | 2011-01-06 |
20110001541 | POWER AMPLIFICATION DEVICE AND COMMUNICATION DEVICE - In a case where two constant envelope signals corresponding to an input signal are generated through analog signal processing, variation in detection sensitivities of amplitudes of those signals is suppressed. At least one of a mixer ( | 2011-01-06 |
20110001542 | Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals - Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack. | 2011-01-06 |
20110001543 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - SOI MOSFETs are used for the transistors for switching of an antenna switch and yet harmonic distortion is significantly reduced. Capacitance elements are respectively added to either the respective drains or gates of the transistors comprising the through MOSFET group of reception branch of the antenna switch. This makes the voltage amplitude between source and gate and that between drain and gate different from each other. As a result, the voltage dependence of source-drain parasitic capacitance becomes asymmetric with respect to the polarity of voltage. This asymmetry property produces signal distortion having similar asymmetry property. Therefore, the following can be implemented by setting it so that it has the same amplitude as that of second-harmonic waves arising from the voltage dependence of substrate capacitance and a phase opposite to that of the same: second-order harmonic distortion can be canceled out and thus second-order harmonic distortion can be reduced. | 2011-01-06 |
20110001544 | Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals - Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack. | 2011-01-06 |
20110001545 | DISPLAY DEVICE AND DRIVING METHOD THEREOF - A display device in which not only a variation in a current value due to a threshold voltage but also a variation in a current value due to mobility are prevented from influencing luminance with respect to all the levels of grayscale to be displayed. After applying an initial potential for correction to a gate and a drain of a driving transistor, the gate and the drain of the driving transistor is kept connected in a floating state, and a voltage is held in a capacitor before a voltage between the gate and a source of the driving transistor becomes equal to a threshold voltage. When a voltage obtained by subtracting the voltage held in the capacitor from a voltage of a video signal is applied to the gate and the source of the driving transistor, a current is supplied to a light-emitting element. A value of an initial voltage for correction differs in accordance with the voltage of the video signal. | 2011-01-06 |
20110001546 | SUB-THRESHOLD CMOS TEMPERATURE DETECTOR - A CMOS temperature detection circuit includes a start-up circuit for generating a start-up voltage (VN), and a proportional to absolute temperature (PTAT) current generator coupled to the start-up circuit for generating a PTAT current. The start-up voltage turns on the PTAT current generator, and the PTAT current generator uses the sub-threshold characteristics of CMOS to generate the PTAT current. A PTAT voltage generator coupled to the PTAT current generator receives the PTAT current and generates a PTAT voltage and an inverse PTAT voltage (VBE). A comparator circuit coupled to the voltage generator compares the inverse PTAT voltage to first and second alarm limits, which are defined using the generated PTAT voltage, and generates an alarm signal based on the comparison results. | 2011-01-06 |
20110001547 | THRESHOLD VOLTAGE DIGITIZER FOR ARRAY OF PROGRAMMABLE THRESHOLD TRANSISTORS - A system includes a voltage generator, current sensing amplifiers, and a control module. The voltage generator outputs a first voltage, which is generated based on received codewords, to a first word line that communicates with N transistors each having programmable threshold voltages, where N is an integer greater than 1. The current sensing amplifiers sense currents through the N transistors via N bit lines, respectively, and generate control signals when current through a corresponding one of the N transistors is greater than or equal to a predetermined current. The control module generates measured values of the threshold voltages of the N transistors by compensating the ones of the codewords based on at least one of a position of the corresponding ones of the N transistors and a temperature. | 2011-01-06 |
20110001548 | Device and method for detecting an approach or contact - A device for detecting an approach or a touch related to at least one sensor element, in particular in an electrical appliance, the device comprising an input side and an output side, between which a first signal path with a first input and a first output and a second signal path with a second input and a second output are arranged, wherein the first signal path comprises a delay device with a delay, the delay device configured to delay a digital first input signal at the first input into a digital first output signal at the first output, wherein the delay is dependent on a capacitance value resulting from the approach or the touch related to the sensor element, and wherein the second signal path comprises an XOR-element, which is configured to generate an edge in a digital second output signal at the second output, when the digital first output signal outputted by the delay device exhibits an edge. | 2011-01-06 |
20110001549 | CAPACITIVE SENSOR ARRANGEMENT WITH A SENSOR ELECTRODE, A SCREEN ELECTRODE AND A BACKGROUND ELECTRODE - A capacitive sensor array comprises a sensor electrode by which the intrusion of an object into a space in front of the sensor electrode is detected, a shield electrode and a background electrode. A control and evaluation circuit is coupled with the sensor electrode. This control and evaluation circuit detects a change in the capacitance of the sensor electrode in comparison to a reference potential, in that the sensor electrode, at a given frequency, periodically and repeatedly couples with a given first potential evaluates at least one parameter of a current and voltage profile dependent on the periodic charging and discharging of the sensor electrode in order to detect the capacitance change, The background electrode is arranged at a distance behind the sensor electrode. The shield electrode is arranged between the sensor electrode and the background electrode and coupled with the sensor electrode through the control and evaluation circuit such that it has no influence on the capacitance measured in comparison to the reference potential and its potential is essentially adjusted to the potential of the sensor electrode. The background electrode is controlled by the control and evaluation circuit such that its potential is periodically switched, at the given frequency, between the reference potential and a second potential that has the same polarity as the first potential in comparison to the reference potential. At least during part of those times in which the sensor electrode is coupled with the first potential, the background electrode is located on the reference potential. At least during part of those times in which the sensor electrode is not coupled with the first potential, the background electrode is located on the second potential. | 2011-01-06 |
20110001550 | PROXIMITY SWITCH - The invention relates to a proximity switch for the detection of objects, comprising a sleeve-type housing, comprising a transducer unit disposed at a measuring end of said sleeve-type housing, the transducer unit comprising a transducer receptacle and a transducer element disposed therein for detecting a physical measurand, comprising a connecting piece disposed at a connecting end of said sleeve-type housing, comprising an electronic assembly disposed on a printed circuit board accommodated in said sleeve-type housing and having a control and evaluation unit adapted to control said transducer element, to evaluate signals measured by said transducer element and to emit switching signals to an environment, wherein variously colored light-emitting diodes are disposed on said printed circuit board at the measuring end and at the connecting end for indicating operational and/or switching states, wherein said transducer receptacle exhibits a transparent region disposed around a housing axis and/or a transparent region at an end face. The proximity switch is characterized in that said connecting piece has a peripheral transparent region, that said transparent regions at said measuring end and at said connecting end are optically homogeneous, that said transparent regions are each capable of being monochromatically illuminated by said light-emitting diodes and that said control and evaluation unit is adapted to control the respective variously colored light-emitting diodes for indicating different operational and/or switching states. | 2011-01-06 |
20110001551 | CIRCUIT STRUCTURE AND METHOD FOR PROGRAMMING AND RE-PROGRAMMING A LOW POWER, MULTIPLE STATES, ELECTRONIC FUSE (E-FUSE) - Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods. | 2011-01-06 |
20110001552 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse. | 2011-01-06 |
20110001553 | METHOD OF DRIVING REVERSE CONDUCTING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND POWER SUPPLY DEVICE - A technique for a reverse conducting semiconductor device including an IGBT element domain and a diode element domain that utilize body regions having a mutual impurity concentration, that makes it possible to adjust an injection efficiency of holes or electrons to the diode element domain, is provided. When a return current flows in the reverse conducting semiconductor device that uses an NPNP-type IGBT, a second voltage that is higher than a voltage of an emitter electrode is applied to second trench gate electrodes of the diode element domain. N-type inversion layers are formed in the periphery of the second trench gate electrodes, and the electrons flow therethrough via a first body contact region and a drift region which are of the same n-type. The injection efficiency of the electrons to the return current is increased, and the injection efficiency of the holes is decreased. Due to this, an increase in a reverse recovery current can be prevented, and a switching loss caused in the diode element domain can be decreased. | 2011-01-06 |
20110001554 | CHARGE PUMP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is a charge pump circuit which is preferably used for reducing noise generated when electric charges are accumulated in a capacitor of the charge pump circuit. A load driving system | 2011-01-06 |
20110001555 | TEST CIRCUIT FOR MONITORING A BANDGAP CIRCUIT - A test circuit provided to monitor a bandgap circuit that outputs a bandgap reference voltage The test circuit includes a reference voltage test module to output a first pass signal when an operating voltage of the bandgap circuit is greater than a first threshold voltage; an output test module to output a second pass signal when an output voltage of the bandgap circuit is greater than a second threshold voltage; and an overdrive test module to output a third pass signal when a minimum operating voltage of the test circuit is detected. Furthermore, a logic circuit is provided and coupled to outputs of each of the test modules. The logic circuit is further configured to output an operating signal, which indicates that the bandgap reference voltage is stable, after receiving the first, second, and third pass signals. | 2011-01-06 |
20110001556 | INTEGRATED CIRCUIT - An integrated circuit includes a first internal voltage generating unit configured to receive an external power and to generate a first internal voltage, and a second internal voltage generating unit configured to receive the first internal voltage, and to generate a second internal voltage having an absolute value of a target voltage level that is less than an absolute value of the first internal voltage, wherein the second internal voltage generating unit is initially enabled at a later time than the first internal voltage generating unit is initially enabled. | 2011-01-06 |
20110001557 | VOLTAGE REFERENCE CIRCUIT WITH TEMPERATURE COMPENSATION - A voltage reference circuit with temperature compensation includes a power supply, a reference voltage supply, a first PMOS transistor with its source connected to the power supply voltage, a second PMOS transistor with its source connected to the power supply and its gate and drain connected to the first PMOS gate, a first NMOS transistor with its gate and drain connected the first PMOS drain, a second NMOS transistor with its drain connected to the second PMOS drain and its gate connected with the first NMOS gate to the reference voltage supply, a resistor connected to the second NMOS source and ground, and an op-amp with its inverting input and its output connected the first NMOS source and its non-inverting input connected to the ground. In another aspect, a voltage reference circuit output is coupled to an NMOS gate in saturation mode connected to another voltage reference circuit. | 2011-01-06 |
20110001558 | INTEGRATED CIRCUIT COMPRISING A BROADBAND HIGH VOLTAGE BUFFER - The disclosure relates to an integrated circuit comprising a data buffer circuit comprising first and second transistors coupled to a contact pad and third and fourth transistors. A first bias voltage is applied on a conduction terminal of the third transistor and a second bias voltage is applied on a conduction terminal of the fourth transistor. A third bias voltage less than the second bias voltage is applied on a control terminal of the first transistor and a fourth bias voltage greater than the first bias voltage is applied on a control terminal of the second transistor. Application notably for the production of a so-called “High Speed” USB port. | 2011-01-06 |
20110001559 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device and a method for driving the same rapidly detect failure of a through-semiconductor-chip via and effectively repairing the failure using a latching unit assigned to each through-semiconductor-chip via. The semiconductor device includes a plurality of semiconductor chips that are stacked, and a plurality of through-semiconductor-chip vias to commonly transfer a signal to the plurality of semiconductor chips, wherein each of the semiconductor chips includes a multiplicity of latching units assigned to the through-semiconductor-chip vias and the multiplicity of latching units of each of the semiconductor chips constructs a boundary scan path including the plurality of through-semiconductor-chip vias to sequentially transfer test data. | 2011-01-06 |
20110001560 | Amplifiers with Input Offset Trim and Methods - Amplifiers with power-on trim and methods using an amplifier system having an amplifier system input and an amplifier system output, an amplifier, a comparator, a successive approximation register having an input coupled to an output of the comparator, a first switch for switching an input of the amplifier from the amplifier system input to shorting the amplifier input, a second switch for switching an output of the amplifier from the amplifier system output to an input of the comparator, an output of the successive approximation register being coupled to an N bit digital to analog (D/A) converter, the D/A converter being a non-binary converter using a radix of less than 2 for at least the most significant bits, and an output of the D/A converter being coupled to the amplifier to control the input offset of the amplifier. Novel embodiments for the amplifier, comparator and D/A converter are disclosed. | 2011-01-06 |
20110001561 | SEMICONDUCTOR DIFFERENTIAL AMPLIFIER - There is provided a circuit to make a bias for adjusting a threshold voltage of MOS devices available in a wide range, to extend the amplitude range of the input voltage range of a semiconductor differential amplifier from a power supply potential to a ground potential, and automatically to ensure an operation of a differential pair in the saturation region as rejecting the common-mode signal in the entire voltage range. The semiconductor differential amplifier is configured by the first gates of two four-terminal fin type FETs serving as an input terminal of differential pair, and in that the second gates of the four-terminal fin type FETs interconnected with each other, wherein a signal decreasing monotonously along with the increase in the input common-mode component is input. | 2011-01-06 |
20110001562 | HIGH SPEED LINEAR DIFFERENTIAL AMPLIFIER - A high speed linear differential amplifier (HSLDA) having automatic gain adjustment to maximize linearity regardless of manufacturing process, changes in temperature, or swing width change of the input signal. The HSLDA comprises a differential amplifier, and a control signal generator including a replica differential amplifier, a reference voltage generator, and a comparator. The comparator outputs a control signal that automatically adjusts the gain of the high speed linear differential amplifier and of the replica differential amplifier. The replica differential amplifier receives predetermined complementary voltages as input signals and outputs a replica output signal to the comparator. The reference voltage generator outputs a voltage to the comparator at which linearity of the output signal of the differential amplifier is maximized. The control signal equalizes the voltage level of the replica output signal and the reference voltage, and controls the gain of the differential amplifier. | 2011-01-06 |
20110001563 | PIN-DIODE Linearized Automatic Gain Control Circuits - Automatic Gain Control AGC circuit comprising a PIN-diode attenuator having an input and an output and a control circuit connected to the attenuator so as to read a signal at the attenuator output. The control circuit is configured to supply a feedback control signal to the attenuator based on an error signal between the signal read at the attenuator output and a reference signal, so as to modulate an attenuation level of said attenuator and maintain a substantially constant power level at the attenuator output. The control circuit particularly comprises at least a resistor and a capacitor which define a time constant of the AGC circuit, so that the AGC circuit features a main pole depending on such time constant and on a voltage of the feedback control signal. The control circuit also comprises a variable gain block, which receives the feedback control signal and which is configured to modulate the main pole proportionally to a variable gain (G) of the gain block. Such gain (G) is varied substantially inversely to the feedback control signal voltage. | 2011-01-06 |
20110001564 | VARIABLE GAIN AMPLIFIER - A variable gain amplifier which includes a plurality of individual amplifiers and variably controls the gain by switching to and using one of the individual amplifier circuits includes an individual amplifier ( | 2011-01-06 |
20110001565 | HIGH-SPEED, MULTI-STAGE CLASS AB AMPLIFIERS - A multi-stage Class AB amplifier system includes a first Class AB amplifier circuit and a second Class AB amplifier circuit. A current mirror circuit is in communication with the first Class AB amplifier circuit. A bias circuit is in communication with the current mirror circuit. A frequency compensation circuit is arranged between the bias circuit and the second Class AB amplifier circuit. A common-mode feedback circuit is in communication with the second Class AB amplifier circuit. The common-mode feedback circuit is configured to generate a feedback signal. | 2011-01-06 |
20110001566 | RADIO FREQUENCY POWER AMPLIFIER - A radio frequency power amplifier includes: an input terminal to which a radio frequency signal is applied; a first HBT which amplifies the radio frequency signal; a second HBT which amplifies the radio frequency signal; a matching circuit connected to an output node of the second HBT; a switch connected to an output node of the matching circuit; and an output matching circuit connected to an output node of the first HBT. The output node of the switch is connected to the output node of the first HBT via the output matching circuit, and an impedance looking into an output side of the radio frequency power amplifier from the output node of the switch is higher than an impedance looking into the output side of the radio frequency power amplifier from the output node of the first HBT. | 2011-01-06 |
20110001567 | SYSTEM AND METHOD FOR BUILT IN SELF TEST FOR TIMING MODULE HOLDOVER - Embodiments of the invention include a method for use in a device having a local oscillator. The method includes performing, for the local oscillator that is disciplined by an external reference signal, while locked to the external reference signal, training at least two mathematical models of the oscillator to determine a predicted correction signal for each mathematical model based at least in part on a correction signal that is a function of the external reference signal and which is used to discipline drift in the oscillator. The method also includes selecting a mathematical model of the at least two mathematical models that results in a smallest time error when disciplining the oscillator to use when the external reference signal is unavailable and an alternative correction signal is to be used to discipline drift in the oscillator. The method further includes testing the selected mathematical model using a sampled version of the correction signal such that the selected mathematical model can be used without the need for a testing duration that is in addition to a period of time used for the training. | 2011-01-06 |
20110001568 | INTEGRATED CIRCUIT WITH LOW TEMPERATURE COEFFICIENT AND ASSOCIATED CALIBRATION METHOD - An integrated circuit (IC) with a low temperature coefficient and an associated calibration method are provided to lower the effect of the environmental temperature on the IC and at the same time to maintain the small area and low power consumption of the IC. The IC includes a first circuit, a second circuit and a calibration control circuit. The first circuit has a low temperature coefficient and generates a first output. The second circuit has a high temperature coefficient and generates a second output. The calibration control circuit detects the first and second outputs, and compares the first and second outputs according to a predefined relationship therebetween so as to generate an adjusting signal. The adjusting signal is for adjusting the second circuit such that the second circuit can have the characteristic of the low temperature coefficient. | 2011-01-06 |
20110001569 | OSCILLATION CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - An oscillation circuit and a semiconductor device incorporating same are provided. The oscillation circuit includes an oscillation unit including a plurality of inverters and configured to perform signal transmission between first and second nodes of the inverters such that each of the inverters performs an oscillation operation to generate clock signals having different phases, when a control signal is activated, and latch a clock signal of the second node and cut off the signal transmission between the first and second nodes to stop the oscillation operations of the inverters, when the control signal is deactivated, and a control unit configured to activate the control signal when an oscillation enable signal is activated, and deactivate the control signal using one of a clock signal output from an inverter connected to the second node among the plurality of inverters and clock signals of which the phases lead that of a clock signal of the first node, when the oscillation enable signal is deactivated. | 2011-01-06 |
20110001570 | Oscillation Circuit - An oscillation circuit includes a piezoelectric oscillator, a resistive element, and an exciting circuit connected between an input node and an output node in parallel with one another, a first capacitor connected between the input node and a ground node, and a second capacitor connected between the output node and the ground node. The exciting circuit includes a NAND circuit and first and second inverters that are cascade-connected. Oscillation of the piezoelectric oscillator is started when an enable signal input to the NAND circuit is switched to an H level. | 2011-01-06 |
20110001571 | CRYSTAL OSCILLATOR EMULATOR - A crystal oscillator emulator integrated circuit includes a first temperature sensor configured to sense a first temperature of the crystal oscillator emulator integrated circuit. The memory is configured to (i) store calibration parameters and (ii) select at least one of the calibration parameters based on the first temperature. A semiconductor oscillator is configured to generate an output signal, wherein (i) the output signal has a frequency and an amplitude and (ii) the frequency is based on the at least one of the calibration parameters. An amplitude adjustment module is configured to (i) compare the amplitude to a predetermined amplitude and (ii) generate a control signal to adjust the amplitude based on the comparison. | 2011-01-06 |
20110001572 | RELAXATION OSCILLATOR - A relaxation oscillator. The relaxation oscillator includes a comparator and a latch. The comparator includes a comparator output and a comparator input that is configured to receive a first input signal in response to a first signal and configured to receive a second input signal in response to a second signal. The latch includes a latch-set input that is configured to be coupled to the comparator output in response to a third signal, a latch-reset input that is configured to be coupled to the comparator output in response to a fourth signal and a latch output that is configured to output the second signal. The relaxation oscillator is configured to achieve an approximately fifty percent duty cycle without requiring the use of a second comparator. | 2011-01-06 |
20110001573 | FREQUENCY HOPPING BAND-STOP FILTER - A digitally-tunable filter includes a tunable filter circuit ( | 2011-01-06 |
20110001574 | BALUN - A balun is provided. The balun includes a first substrate, a feed conductor, a second substrate, a first ground layer, a second ground layer and a common ground element. The feed conductor includes a feed portion and an extended feed portion. The feed conductor is disposed on the first substrate. The first ground layer is disposed on the second substrate corresponding to the feed portion. The second ground layer is disposed on the second substrate corresponding to the extended feed portion. A gap is formed between the first and second ground layers. The common ground element is disposed on the second substrate. The common ground element is electrically connected to the first and second ground layers. The common ground element includes a first common ground portion parallel and corresponding to the feed conductor. | 2011-01-06 |
20110001575 | MULTIBAND COUPLING CIRCUIT - A distributed multiband coupling circuit including: a number n of first and of second terminals equal to the number of frequency bands; a third terminal and a fourth terminal; a number n of distributed couplers equal to the number of frequency bands, all couplers being identical and sized according to the highest frequency band, and each coupler including a first conductive line between first and second ports intended to convey a signal to be transmitted in the concerned frequency band, and a second conductive line coupled to the first one between third and fourth ports; a first set of resistive splitters in cascade between the third ports of the couplers, a terminal of the splitter associated with the first coupler being connected to the third terminal of the coupling circuit; and a second set of resistive splitters in cascade between the fourth ports of the couplers, a terminal of the splitter associated with the first coupler being connected to the fourth terminal of the coupling circuit. | 2011-01-06 |
20110001576 | POWER AMPLIFIER MODULE - A power amplifier module comprises a power amplifier disposed in a coreless substrate and a directional coupler disposed in a coreless substrate and connected to the power amplifier. | 2011-01-06 |
20110001577 | SEQUENTIAL ROTATED FEEDING CIRCUIT - A sequential rotated feeding circuit for sequential rotated feeding of a signal with a wavelength λ | 2011-01-06 |
20110001578 | SURFACE ACOUSTIC WAVE FILTER AND DUPLEXER USING THE SAME - A SAW filter includes a piezoelectric body, an IDT electrode on the piezoelectric body, and signal wiring electrically connected to the IDT electrode. The signal wiring has a thickness not less than a skin depth specified based on the frequency of a signal passing through the signal wiring and the electrical conductivity of the signal wiring. As a result, the signal wiring has low propagation loss of the signal passing through it, so that the SAW filter has excellent transmission characteristics. | 2011-01-06 |
20110001579 | TUNABLE RIDGE WAVEGUIDE DELAY LINE - A tunable delay line for radiofrequency or microwave frequency applications consists of at least one ridge waveguide in which the ridge is movable in the waveguide body so as to vary the width of an air gap defined between the longitudinal end surface of the ridge and a confronting member of the waveguide. The ridge is moved by an actuator external to the waveguide body. | 2011-01-06 |
20110001580 | Variable phase shifter - A variable phase shifter is provided. In the variable phase shifter, a fixed substrate, which is a dielectric substrate, is fixedly mounted in a housing and has at least one arc-shaped microstrip line on one surface thereof. A rotation substrate, which is a dielectric substrate, is rotatably mounted in the housing, in contact with the other surface of the fixed substrate and has a slot line on the contact surface thereof. Microstrip-slot line coupling takes place between the microstrip line and the slot line even during rotation. Both ends of the microstrip line are connected to an output port of the variable phase shifter and the slot line is electrically connected to an input port of the variable phase shifter, for receiving an input signal. | 2011-01-06 |
20110001581 | ACOUSTIC WAVE DEVICE - An acoustic wave device includes an input terminal; a balun that is connected to the input terminal, converts a signal input from the input terminal into two anti-phase signals, and outputs the two anti-phase signals; and a filter that is connected to the balun, and outputs the two anti-phase signals input from the balun as balanced output signals. An output impedance of the balun is equal to an input impedance of the filter, and is larger than an output impedance of the filter. | 2011-01-06 |
20110001582 | MICRO-ELECTROMECHANICAL DEVICE AND METHOD FOR FABRICATING THE SAME - A micro-electromechanical device of the present invention includes a resonator and an electrode facing each other, a pair of thermal oxide film formed on the surfaces of the resonator and electrode facing each other and a narrow gap provided between the thermal oxide films. A process for fabricating a micro-electromechanical device includes a step of processing an Si layer to be the resonator and the electrode by using photolithography and etching to form a groove to be a gap, and a step of performing thermal oxidation on the Si layer to form a pair of thermal oxide films of Si on the opposite surfaces of the groove. | 2011-01-06 |
20110001583 | FILTER APPARATUS AND METHOD - A filter includes a cross-coupling link which includes a crossbar, a first vertical support attached to one end of the crossbar, a second vertical support attached to another end of the crossbar, a first coupling arm attached to the first vertical support, a second coupling arm attached to the second vertical support, a first adjustable support attached to the first coupling arm at one end and grounded at another end, and a second adjustable support attached to the second coupling arm at one end and grounded at another end. | 2011-01-06 |
20110001584 | RADIO-FREQUENCY FILTER DEVICE USING DIELECTRIC WAVEGUIDE WITH MULTIPLE RESONANT MODES - A radio-frequency filter device is provided with: a dielectric layer, a pair of conductive layers on both surfaces of the dielectric layer, shielding via conductors short-circuiting the conductive layers, a waveguide resonator portion formed by the shielding via conductors, another conductive layer on a surface of the dielectric layer, a pair of strip conductors on the dielectric layer, a pair of input and output coupling via conductors. The coupling via conductors pass through the conductive layer and the waveguide resonator portion without contacting with the conductive layer. One end of each coupling via conductor is short-circuited to the conductive layer, and the other end is connected to one strip conductor. By inputting a radio-frequency signal, fundamental and second-order resonant modes are excited in the waveguide resonator portion. | 2011-01-06 |
20110001585 | TUNEABLE FILTER AND A METHOD OF TUNING SUCH A FILTER - A tuneable filter comprising a filter body defining a tuning cavity; a tuning member within the tuning cavity; and, a linear actuator adapted to displace the tuning member within the cavity to tune the filter; the linear actuator comprising a motor; a drive arm connected to the motor and extending along a drive axis, the drive arm being adapted to be rotated about the drive axis by the motor; an extension arm extending along the drive axis being connected at one end to the tuning member and being in engagement with the drive arm at the other end; the engagement between the drive arm and extension arm being arranged such that rotation of the drive arm about the drive axis displaces the extension arm along the drive axis; each of the drive arm and extension arm comprising an end stop, the end stops being arranged such that as the extension arm reaches the end of its range of travel towards the drive arm the drive arm end stop rotates into abutment with the extension arm end stop, preventing further rotation of the drive arm. | 2011-01-06 |
20110001586 | Dielectric Ceramics, Method of Manufacturing the Same, and Resonator - Provided is a dielectric ceramics having crystals of a composition formula: aBaO.bCoO.cZnO.dNb | 2011-01-06 |
20110001587 | DIE-TO-DIE ELECTRICAL ISOLATION IN A SEMICONDUCTOR PACKAGE - Some of the embodiments of the present disclosure provide a semiconductor package comprising a first die; a second die; and an inductor arrangement configured to inductively couple the first die and the second die while maintaining electrical isolation between active circuit components of the first die and active circuit components of the second die. Other embodiments are also described and claimed. | 2011-01-06 |
20110001588 | WAVEFORM EQUALIZATION CIRCUIT WITH PULSE WIDTH MODULATION - There is provided a waveform equalization circuit with pulse width modulation that includes pulse-width adjust-level generation circuits PWCLC | 2011-01-06 |
20110001589 | ELECTROMAGNETIC RELAY FOR STARTERS - Terminal-bolts and a fixed contact are formed with different kinds of metals, and fixed to a fixing hole formed in the fixed contact by press fitting one end of the terminal-bolts. A plurality of concavo-convex parts is provided on a surface of the fixed contact that faces the movable contact. A plurality of concavo-convex portions is provided on another surface of the fixed contact that faces an anti movable-contact side. The concavo-convex portions are arranged so that positions of concave parts of the concavo-convex portions match positions of convex parts of the concavo-convex portions provided in the opposite surface of the fixed contact. The concavo-convex parts are at least partly curved, and have the same height and project in a height direction from the fixed contact. | 2011-01-06 |
20110001590 | MAGNETIC ASSEMBLY AND FABRICATING METHOD THEREOF - A magnetic assembly includes a magnetic core, a circuit board and multiple conductive elements. The circuit board includes multiple conductive regions. The conductive elements stride over the magnetic core. Each of the conductive elements includes a first terminal, a second terminal and a connecting part. The connecting part is arranged between the first terminal and the second terminal for connecting the first terminal with the second terminal. The first terminal and the second terminal of each conductive element are respectively connected to two adjacent conductive regions. The multiple conductive elements and the multiple conductive regions collectively define multiple loops. The multiple loops interact with the magnetic core to generate inductance. | 2011-01-06 |
20110001591 | ELECTROMAGNETIC ACTUATING MECHANISM - An electromagnetic control mechanism ( | 2011-01-06 |
20110001592 | Method and Device for Controlling of a Magnetic Flux - A device for controlling a magnetic flux in an electromagnetic system, wherein the system includes magnetically connected magnetic cores, between which a volume is arranged. The volume includes a controllable magnetic flux region and the magnetic flux region includes a magnetic material having a relative permeability that may be varied by influencing the temperature of the material. The magnetic material includes a magnetic material, the Curie point of which lies within the temperature operating range of the device and exhibits paramagnetic properties within the temperature range. Also a method of controlling a magnetic flux. | 2011-01-06 |
20110001593 | PERMANENT MAGNET AND METHOD OF MANUFACTURING SAME - By eliminating the necessity of a prior step for cleaning a sintered magnet before adhering Dy and/or Tb to the surface of the sintered magnet S, the productivity of a permanent magnet having diffused Dy and/or Tb into grain boundary phase is improved. Iron-boron-rare earth based sintered magnet (S) disposed in a processing chamber ( | 2011-01-06 |
20110001594 | Magnetic Article and Method for Producing a Magnetic Article - A magnetic article comprises, in total, elements in amounts capable of providing at least one (La | 2011-01-06 |
20110001595 | Coil component - A coil component ensuring adhesive bonding between first and second cores. The coil component also includes an inductive component and a pair of terminal electrodes. The first core has a first adhesion surface. The second core is connected to the first core by an adhesive agent and has a second adhesion surface in confrontation with the first adhesion surface. At least one of the first adhesion surface and the second adhesion surface is formed of a glass surface layer to which the adhesive agent is applied. The inductive component is wound over the first core. The pair of terminal electrodes are provided at one of the first core and the second core. The inductive component has one end portion electrically connected to one of the terminal electrodes and has another end portion electrically connected to remaining one of the terminal electrodes. | 2011-01-06 |
20110001596 | Electrical Device Including A Transformer With A Core Having Two Holes And Connector Incorporating The Same - An electrical device is produced by winding wires around a core. The device may be used as a transformer. Wires are inserted into, through and around a first hole and a first side of a core a desired number of times. Thereafter, the wires are extended along either a top or a bottom of the core and then passed through and around a second hole of the core. After the wires are wound around the second hole of the core and a second side of the core, the production of the device is complete. | 2011-01-06 |
20110001597 | COMPONENT FIXING DEVICE AND ELECTRICAL DEVICE HAVING THE SAME - A component fixing device includes a holding portion for holding a component with a hollow portion while restricting a movement of the component; and a fixed portion elastically connected to the holding portion and to be fixed to an object. The holding portion is inserted into the hollow portion of the component for holding the component. The holding portion may have a center holding portion abutting against an outer surface of the component and a pair of arm portions disposed at both sides of the center holding portion and capable of bending relative to the center holding portion, so that the center holding portion and the arm portions sandwich the component. | 2011-01-06 |
20110001598 | TRANSFORMER AND METHOD OF MANUFACTURING THE SAME - There is provided a transformer and a method of manufacturing the same. The transformer includes a bobbin wound with coils; cores having center leg parts inserted from both ends of the bobbin and contacting each other; and a shielding member preventing an inflow of an impregnant into the center leg parts inside the bobbin during a varnish impregnation of the cores. | 2011-01-06 |
20110001599 | LAMINATED INDUCTOR - A laminated inductor includes a laminate having a plurality of insulating layers, a helical coil and first and second external electrodes on an underside of the laminate. The helical coil has coiled electrodes, each coiled up in one turn, and the first and second external electrodes are connected to respective, or corresponding, ends of the helical coil. Each of the coiled electrodes of the helical coil follow a path along the periphery of one of the insulating layers and include first end located in the path and second end located outside the path. The helical coil and the first external electrode are connected to each other by a lead via conductor formed in a space that is enclosed by parts of the coiled electrodes including the first and second ends. | 2011-01-06 |
20110001600 | TWO- OR MULTIPHASE TRANSFORMER - The disclosure relates to a transformer having a yoke which has a crosspiece and at least two limbs, over which limbs a coil is placed in each case, and having at least one carrier on which the crosspiece is fixed and which has bearing faces for the coils. At least two supporting blocks for each coil are mounted on each bearing surface. The supporting blocks are fitted with elastic compensation elements on the coil-side carrying face and have, on their longitudinal side faces, which run perpendicular to a carrying surface, at least one strip which extends the creepage path and runs in the longitudinal direction and parallel to the carrying surface of the supporting block. | 2011-01-06 |
20110001601 | INDUCTIVE ELEMENT HAVING A GAP AND A FABRICATION METHOD THEREOF - An inductive element having a gap and a fabrication method thereof are disclosed. The fabrication method is for fabricating an inductive element having a first core body, a second core body and a gap, and includes: coating an adhesive on a gap-facing side of the first core body and/or the second core body; providing a linear spacer and installing the linear spacer between the first core body and the second core body; and combining the side of the first core body where the adhesive is coated with the side of the second core body where the adhesive is coated, allowing the linear spacer to form the gap when the first core body is combined with the second core body. Thereby, the linear spacer establishes the size of the gap of the inductive element and improves the adhesion of the first core body to the second core body. | 2011-01-06 |
20110001602 | METHOD FOR TRACKING PROCEDURES PERFORMED ON PERSONAL PROTECTION EQUIPMENT AND ACTIONS OF INDIVIDUALS - A method for tracking procedures performed on personal protection equipment (PPE) and actions of individuals includes the following steps. An article of PPE configured with a smart tag is provided to an individual prior to performance of a task. After the individual performs the task, the article of PPE is processed. Information is retrieved from the smart tag during at least one of: before, during and after processing the article of PPE. After the performance of the task, the individual's data is read and the individual enters into a designated area. | 2011-01-06 |
20110001603 | METHODS AND APPARATUS RELATING TO A SECURITY SYSTEM - A method of receiving secure information from a mobile communication device to control an authorisation device in a security system, the method including the steps of the authorisation device: receiving an electronic key transmitted by the mobile communication device; decoding the key using a decoding technique to retrieve a hidden token; and decrypting the retrieved token to retrieve the secure information. | 2011-01-06 |