01st week of 2012 patent applcation highlights part 13 |
Patent application number | Title | Published |
20120001201 | RADIATION IMAGE DETECTION APPARATUS AND MANUFACTURING METHOD OF RADIATION IMAGE DETECTOR - In a radiation image detection apparatus having a radiation image detector that includes the following stacked in the order listed below: a bias electrode, a photoconductive layer, a substrate side charge transport layer, and an active matrix substrate, the radiation image detector does not include an area adjacent to the interface between the substrate side charge transport layer and photoconductive layer having an oxygen or chlorine element density not less than two times the average density of oxygen or chlorine element in the substrate side charge transport layer. | 2012-01-05 |
20120001202 | Semiconductor Light Emitting Device and Method for Manufacturing the Same - A method for manufacturing a semiconductor light emitting device includes: (a) providing a temporary substrate; (b) forming a multi-layered LED epitaxial structure, having at least one light emitting unit, on the temporary substrate, wherein a first surface of the light emitting unit contacts the temporary substrate, and the light emitting unit includes a n-type layer, an active region, and a p-type layer; (c) forming a n-electrode on the n-type layer; (d) forming a p-electrode on the p-type layer; (e) bonding a permanent substrate on the light emitting unit, the n-electrode and the p-electrode; (f) removing the temporary substrate to expose the first surface of the light emitting unit; and (g) removing a portion of the light emitting unit from the first surface, to expose at least one of the n-electrode and the p-electrode. | 2012-01-05 |
20120001203 | LED CHIP PACKAGE STRUCTURE - A LED chip package structure includes a substrate unit, a light-emitting unit, and a package unit. The substrate unit includes a strip substrate body. The light-emitting unit includes a plurality of LED chips disposed on the strip substrate body and electrically connected to the strip substrate body. The package unit includes a strip package colloid body disposed on the strip substrate body to cover the LED chips, wherein the strip package colloid body has an exposed top surface and an exposed surrounding peripheral surface connected between the exposed top surface and the strip substrate body, and the strip package colloid body has at least one exposed lens portion projected upwardly from the exposed top surface thereof and corresponding to the LED chips. Hence, light beams generated by the LED chips pass through the strip package colloid body to form a strip light-emitting area on the strip package colloid body. | 2012-01-05 |
20120001204 | COLOR ADJUSTING ARRANGEMENT - Disclosed is a color adjusting arrangement comprising: i) a first wavelength converting material arranged to receive ambient light and capable of converting ambient light of a first wavelength range into light of a second wavelength range, and/or reflecting ambient light of said second wavelength range, said second wavelength range being part of the visible light spectrum; and ii) a complementary wavelength converting material arranged to receive ambient light and capable of converting part of said ambient light into light of a complementary wavelength range, which is complementary to said second wavelength range, and arranged to allow mixing of light of said second wavelength range and said complementary wavelength range; such that light of said second wavelength range that is emitted and/or reflected by said first wavelength converting material and light of said complementary wavelength range is mixed when leaving the color adjusting arrangement towards a viewing position, the light leaving the color adjusting arrangement thereby appearing less colored, i.e. having a color point substantially near the black body line. The invention thus allows an undesirable colored appearance of a semiconductor-phosphor based light source to be at least partly extinguished or neutralized. | 2012-01-05 |
20120001205 | LIGHT EMITTING DEVICE HAVING STRONTIUM OXYORTHOSILICATE TYPE PHOSPHORS - Exemplary embodiments of the present invention relate to light emitting devices including strontium oxyorthosilicate-type phosphors. The light emitting device includes a light emitting diode, which emits light in the UV or visible range, and phosphors disposed around the light emitting diode to absorb light emitted from the light emitting diode and emit light having a different wavelength from the absorbed light. The phosphors include an oxyorthosilicate phosphor having a general formula of Sr | 2012-01-05 |
20120001206 | Organic light emitting diode display and fabricating method thereof - An organic light emitting diode display and a fabrication method thereof, the display including a substrate; a thin film transistor on the substrate; and an organic light emitting diode on the substrate, the organic light emitting diode including a pixel electrode, an organic emission layer, and a common electrode, wherein the organic emission layer includes a red (R) pixel, a green (G) pixel, and a blue (B) pixel, the pixel electrode includes a first pixel electrode, a second pixel electrode, and a third pixel electrode that respectively correspond to the red pixel, the green pixel, and the blue pixel, the first pixel electrode, the second pixel electrode, and the third pixel electrode each have different thicknesses, and the first pixel electrode, the second pixel electrode, and the third pixel electrode each include a first hydrophobic layer. | 2012-01-05 |
20120001207 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode (OLED) display is disclosed. In one embodiment, the OLED display includes i) a plurality of pixels comprising a blue light emitting region, a green light emitting region, and a red light emitting region on a substrate and formed by stacking a lower electrode, an organic layer, and an upper electrode. In one embodiment, the blue and green light emitting regions are formed in a microcavity structure, and the red light emitting region is formed in a non-microcavity structure. | 2012-01-05 |
20120001208 | Optoelectronic Semiconductor Component and Display Means - In at least one embodiment, an optoelectronic semiconductor component includes at least two optoelectronic semiconductor chips, which are designed to emit electromagnetic radiation in mutually different wavelength ranges when in operation. The semiconductor chips are mounted on a mounting surface of a common carrier. Furthermore, the optoelectronic semiconductor component contains at least two non-rotationally symmetrical lens bodies, which are designed to shape the radiation into mutually different emission angles in two mutually orthogonal directions parallel to the mounting surface. One of the lens bodies is here associated with or arranged downstream of each of the semiconductor chips in an emission direction. | 2012-01-05 |
20120001209 | LIGHT EMITTING DIODE MODULE FOR LINE LIGHT SOURCE - A light emitting diode module for a line light source includes a circuit board having a wire pattern formed thereon and a plurality of LED chips directly mounted and disposed in a longitudinal direction on the circuit board and electrically connected to the wire pattern. The module also includes a reflecting wall installed on the circuit board to surround the plurality of LED chips, reflecting light from the LED chips. The module further includes a heat sink plate underlying the circuit board to radiate heat generated from the LED chip. | 2012-01-05 |
20120001210 | LIGHT-EMITTING DEVICE AND PROJECTOR - A light-emitting device includes a first layer, a second layer, and a semiconductor body interposed between the first and second layers, wherein the semiconductor body has a first fine-wall-shape member, a second fine-wall-shape member, and a semiconductor member interposed between the first and second fine-wall-shape members, the first and second fine-wall-shape members have a third layer, a fourth layer, and a fifth layer interposed between the third and fourth layers, the fifth layer is a layer that generates light and guides the light, the third and fourth layers are layers that guide the light generated in the fifth layer, the first and second layers are layers that suppress leakage of the light generated in the fifth layer, and the propagating direction of the light generated in the fifth layer intersects with the first and second fine-wall-shape members. | 2012-01-05 |
20120001211 | Double layer injection mould LED bulb - The present invention relates to a double layer injection mould LED bulb, in which the main improvements are: the epoxy resin light body at the top of the conducting bracket of a traditional LED light is specially designed as one epoxy resin injection mould body integrated with a PC or injection mould shell; two positioning grooves are provided on the right and left of the opening at the lower part of the shell so that the two shoulders of the conducting bracket may slide into the grooves for positioning and a small quantity of injection mould body may be condensed and moulded shortly after injection. The upper end of the internal opening of the shell is a semi-round flat convex space to give the injection the light source amplifying convex lens block function, which, together with the convex or concave structure design at the top of the shell, provides the special function of amplifying or concentrating the light source already amplified inside, so as to significantly simplify the manufacture process and increase the output capacity of mass production. | 2012-01-05 |
20120001212 | Light-Emitting Diode Packaging Structure and Substrate Therefor - A light-emitting diode (LED) packaging structure and a substrate for the packaging structure are provided. The light-emitting diode packaging structure includes a metal substrate having a first surface and a second surface opposite to the first surface, and the first surface has a concave portion with a sidewall and a bottom, allowing an anode film to be formed on the metal substrate; a plurality of electrically conductive pads formed on the bottom of the concave portion; an optical treatment layer formed on the sidewall of the concave portion; and an LED die mounted on the bottom of the concave portion and electrically connected to the electrically conductive pads. Desired electrical insulating property between any two adjacent electrically conductive pads can be obtained by the anode film formed on the metal substrate, while a good thermal conductivity of the metal substrate is maintained. | 2012-01-05 |
20120001213 | III-NITRIDE LIGHT-EMITTING DEVICES WITH REFLECTIVE ENGINEERED GROWTH TEMPLATES AND METHODS OF MANUFACTURE - A light emitter includes a first mirror that is an epitaxially grown metal mirror, a second mirror, and an active region that is epitaxially grown such that the active region is positioned at or close to, at least, one antinode between the first mirror and the second mirror. | 2012-01-05 |
20120001214 | PHOSPHOR CERAMIC AND LIGHT-EMITTING DEVICE - A phosphor ceramic includes at least one fluorescent layer that is capable of emitting fluorescent light; and at least one non-fluorescent layer that does not emit fluorescent light and is laminated onto the fluorescent layer. | 2012-01-05 |
20120001215 | LIGHT-EMITTING MODULE AND ILLUMINATION DEVICE - According to one embodiment, a light-emitting module includes a module substrate, a light-reflecting layer, and a light-emitting element. The light-reflecting layer is superposed on the module substrate and has a reflection ratio higher than the reflection ratio of the module substrate. The light-emitting element is mounted on the module substrate. The light-reflecting layer includes a copper layer, a copper plating layer which covers the copper layer, and a metal layer which is superposed on the copper plating layer and reflects light emitted from the light-emitting element. | 2012-01-05 |
20120001216 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package is provided comprising a light emitting device including at least one light emitting diode and a body including a first lead frame on which the light emitting device is mounted and a second lead frame spaced apart from the first lead frame, wherein at least one of the first and second lead frames is extending to a bending region in a first direction by a predetermined length on the basis of an outer surface of the body and is bent in a second direction intersecting the first direction. | 2012-01-05 |
20120001217 | COMPOSITION FOR LIGHT-EMITTING PARTICLE-POLYMER COMPOSITE, LIGHT-EMITTING PARTICLE-POLYMER COMPOSITE, AND DEVICE INCLUDING THE LIGHT-EMITTING PARTICLE-POLYMER COMPOSITE - A composition for manufacture of a light emitting particle-polymer composite, the composition including a light emitting particle, a first monomer including at least two thiol groups, each located at a terminal end of the first monomer, and a second monomer including at least two unsaturated carbon-carbon bonds, each located at a terminal end of the second monomer. | 2012-01-05 |
20120001218 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a light emitting device and a method of fabricating the same. The light emitting device includes a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer, the active layer being formed of a semiconductor material. Also, the light emitting device further includes a current spreading layer comprising a plurality of carbon nanotube bundles physically connected to each other on one of the first and second conductive type semiconductor layers. | 2012-01-05 |
20120001219 | LIGHT-EMITTING DEVICE AND FABRICATION METHOD THEREOF - Disclosed is a light-emitting device including a conductive support substrate, a reflective layer arranged on the conductive support substrate, a first electrode layer arranged on the reflective layer and provided with a step in at least one region of the edge thereof, a protective layer arranged on the step, and a light-emitting structure arranged on the first electrode layer and the protective layer, the light-emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer interposed between the first conductive semiconductor layer and the second conductive semiconductor layer, wherein at least one region of the reflective layer and the first electrode layer vertically overlaps the protective layer. Based on this configuration, the light-emitting device can exhibit improved adhesion between the electrode layer and the reflective layer and be provided with a wider reflective layer, thus improving brightness. | 2012-01-05 |
20120001220 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME, AND LAMP - Disclosed is a group III nitride semiconductor light-emitting device which suppresses electric current concentration in a light-transmitting electrode and a semiconductor layer directly below an electrode to enhance light emission efficiency, suppresses light absorption in the electrode or light loss due to multiple reflection therein to enhance light extraction efficiency, and has superior external quantum efficiency and electric characteristics. A semiconductor layer ( | 2012-01-05 |
20120001221 | LIGHT EMITTING DEVICE AND LIGHT UNIT - Provided are a light emitting device, a method of fabricating the light emitting device, and a light unit. The light emitting device includes a light emitting structure layer comprising a first conductive type semiconductor layer, an active layer under the first conductive type semiconductor layer, and a second conductive type semiconductor layer under the active layer, a first conductive layer under the second conductive type semiconductor layer and electrically connected to the first conductive type semiconductor layer, a second conductive layer under the second conductive type semiconductor layer and electrically connected to the second conductive type semiconductor layer, an insulation layer between the first conductive layer and the second conductive layer, and a tunnel barrier under the second conductive type semiconductor layer and disposed between the first conductive layer and the second conductive layer. | 2012-01-05 |
20120001222 | LIGHT EMITTING DEVICE, AND LIGHT EMITTING DEVICE PACKAGE - A light emitting device including a light emitting structure including a second conductive type semiconductor layer, an active layer, and a first conductive type semiconductor layer, and a first protective layer disposed on a side of the light emitting structure, wherein the first protective layer overlaps with the first conductive type semiconductor layer in a vertical direction. | 2012-01-05 |
20120001223 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND PROCESS FOR PRODUCTION THEREOF - A nitride-based semiconductor light-emitting device | 2012-01-05 |
20120001224 | IGBT TRANSISTOR WITH PROTECTION AGAINST PARASITIC COMPONENT ACTIVATION AND MANUFACTURING PROCESS THEREOF - An IGBT transistor includes a drift region, at least one body region housed in the drift region and having a first type of conductivity, and a conduction region, which crosses the body region in a direction perpendicular to a surface of the drift region and has the first type of conductivity and a lower resistance than the body region. The conduction region includes a plurality of implant regions, arranged at respective depths from the surface of the drift region. | 2012-01-05 |
20120001225 | INSULATED GATE BIPOLAR TRANSISTOR (IGBT) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P | 2012-01-05 |
20120001226 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device 10 includes forming a plurality of second conductive second semiconductor regions at specific intervals on one main surface of a first conductive first semiconductor region, the plurality of second conductive second semiconductor regions being opposite to the first conductive first semiconductor region, forming a plurality of the first conductive third semiconductor regions on a main surface of the second semiconductor region, the plurality of the first conductive third regions being separated from each other, forming a plurality of holes at specific intervals on an another main surface which faces the one main surface of the first semiconductor region, the plurality of holes being separated from each other, forming a pair of adjacent second conductive fourth semiconductor regions which are alternately connected at a bottom part of the hole within the first semiconductor region, and burying an electrode within the hole. | 2012-01-05 |
20120001227 | Power semiconductor module - A power semiconductor module includes a plurality of sets of semiconductor switching elements, a molded resin casing containing the semiconductor switching elements, screw holders for receiving mounting screws formed at bottom regions of four corners of the molded resin casing, first terminal blocks having main circuit terminals, and arranged on a central region of a top surface of the molded resin casing, and second terminal blocks having control terminals arranged at a side edge of the molded resin casing apart. Insulating separation walls having a configuration of a rib erect from a surface of the second terminal blocks, and are interposed between groups of the control terminals corresponding to the sets of semiconductor switching elements, and between the screw holder including the mounting screw therein on the molded resin casing and the control terminal at a high voltage side adjacent to the screw holder. | 2012-01-05 |
20120001228 | METHOD TO CONTROL SOURCE/DRAIN STRESSOR PROFILES FOR STRESS ENGINEERING - An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile. | 2012-01-05 |
20120001229 | Semiconductor Device and Method for Forming the Same - A semiconductor device comprises a semiconductor substrate on an insulating layer; and a second gate, the second gate is located on the insulating layer and is embedded at least partially in the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a void within the semiconductor substrate, with the insulating layer being exposed by the void; and forming a second gate, with the void being filled with at least one part of the second gate. It facilitates the reduction of the short channel effects, resistances of source and drain regions, and parasitic capacitances. | 2012-01-05 |
20120001230 | Multi-gate semiconductor devices - A multi-gate semiconductor device with inter-gate conductive regions being connected to balance resistors is provided. The multi-gate semiconductor device comprises a substrate, a multilayer structure formed upon the substrate, a first ohmic electrode, a second ohmic electrode, a plural of gate electrodes, at least one conductive region, and at least one resistive component. When put into practice, the multi-gate semiconductor device is advantageous in reducing the voltage drop along the conductive region with a minimal change in device layout, improving the | 2012-01-05 |
20120001231 | Electrical Fuse - An electrical fuse comprises first, second, and third thick oxide NMOS transistors and a thin oxide NMOS transistor. The first thick oxide NMOS transistor has a gate connected to a first input signal, and the thin oxide NMOS transistor has a drain connected to the source of the first thick oxide NMOS transistor and a gate shorted to its source. The second thick oxide transistor has a gate connected to a power up signal, a drain connected to the source of the thin oxide NMOS transistor, and a source connected to a reference voltage. The third thick oxide transistor has a gate connected to the second input signal, a drain connected to a high voltage, and a source connected to the drain of the thin oxide NMOS transistor. The first input signal and the second input signal are complementary. | 2012-01-05 |
20120001232 | ROM CELL CIRCUIT FOR FINFET DEVICES - The present disclosure provides a read only memory (ROM) cell array. The ROM cell array includes a plurality of fin active regions oriented in a first direction and formed on a semiconductor substrate; a plurality of gates formed on the plurality of fin active regions and oriented in a second direction perpendicular to the first direction; and a plurality of ROM cells formed by the plurality of fin active regions and the plurality of gates, the plurality of ROM cells being coded such that each cell of a first subset of ROM cells has a source electrically connected to a Vss line, and each cell of a second subset of ROM cells has a source electrically isolated. Each cell of the first subset of ROM cells includes a drain contact having a first contact area and a source contact having a second contact area at least 30% greater than the first contact area. | 2012-01-05 |
20120001233 | Novel embedded NOR flash memory process with NAND cell and true logic compatible low voltage device - An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line. | 2012-01-05 |
20120001234 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor includes first impurity regions formed in a substrate, second impurity regions formed in the first impurity regions, wherein the second impurity regions has a junction with the first impurity regions, recess patterns formed over the first impurity regions in contact with the second impurity regions, and transfer gates filling the recess patterns. | 2012-01-05 |
20120001235 | CHEMICALLY SENSITIVE SENSOR WITH LIGHTLY DOPED DRAINS - A chemically sensitive sensor with a lightly doped region that affects an overlap capacitance between a gate and an electrode of the chemical sensitive sensor. The lightly doped region extends beneath and adjacent to a gate region of the chemical sensitive sensor. Modifying the gain of the chemically sensitive sensor is achieved by manipulating the lightly doped region under the electrodes. | 2012-01-05 |
20120001236 | ONE-TRANSISTOR PIXEL ARRAY WITH CASCODED COLUMN CIRCUIT - To reduce the pixel size to the smallest dimensions and simplest form of operation, a pixel may be formed by using only one ion sensitive field-effect transistor (ISFET). This one-transistor, or | 2012-01-05 |
20120001237 | TWO-TRANSISTOR PIXEL ARRAY - A two-transistor (2T) pixel comprises a chemically-sensitive transistor (ChemFET) and a selection device which is a non-chemically sensitive transistor. A plurality of the 2T pixels may form an array, having a number of rows and a number of columns. The ChemFET can be configured in a source follower or common source readout mode. Both the ChemFET and the non-chemically sensitive transistor can be NMOS or PMOS device. | 2012-01-05 |
20120001238 | INTEGRATED CIRCUIT DEVICE WITH WELL CONTROLLED SURFACE PROXIMITY AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a lightly doped source and drain (LDD) region that acts as an etch stop. The LDD region may act as an etch stop during an etching process implemented to form a recess in the substrate that defines a source and drain region of the device. | 2012-01-05 |
20120001239 | Formation of III-V Based Devices on Semiconductor Substrates - A device includes a semiconductor substrate, and insulation regions in the semiconductor substrate. Opposite sidewalls of the insulation regions have a spacing between about 70 nm and about 300 nm. A III-V compound semiconductor region is formed between the opposite sidewalls of the insulation regions. | 2012-01-05 |
20120001240 | Junction field effect transistor structure - A junction field effect transistor structure includes a grid electrode, a source electrode, a drain electrode and a substrate. The grid electrode includes a polysilicon layer and a P-type implanted layer. The source electrode includes an N-type implanted layer, an N-type well layer and a heavy-implanted N-type well layer. The drain electrode includes the N-type implanted layer, the N-type well layer and the heavy-implanted N-type well layer. The substrate is connected with a substrate connecting end by the P-type implanted layer, a P-type well layer, a heavy-implanted P-type well layer and a P-type buried layer. The junction field effect transistor structure of the present invention can be manufactured without adding any masking step based on the existing technologies, and has the high-voltage resistant characteristic to meet the requirements in practical applications. Furthermore, it has the compact structure and compatible technology. | 2012-01-05 |
20120001241 | CMOS Image Sensor Including PNP Triple Layer And Method Of Fabricating The CMOS Image Sensor - A CMOS image sensor (CIS) for sensing visible light and infrared (IR) light, capable of effectively preventing increase in electrical crosstalk that is caused when photodiodes are formed deeply and the thickness of an epitaxial layer is increased due to deep permeation of IR light, and a method of fabricating the CIS. The CIS includes a substrate; the PNP triple layer including a P-type lower layer, an N-type intermediate layer, and a P-type upper layer that are sequentially stacked on the substrate; a plurality of photodiodes formed in the P-type upper layer and isolated from each other by isolation regions; a wiring layer formed on the P-type upper layer and the plurality of photodiodes and including a plurality of wirings; and a plurality of lenses for focusing light to transfer the light to the photodiodes. | 2012-01-05 |
20120001242 | SINGLE POLY CMOS IMAGER - More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate. | 2012-01-05 |
20120001243 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material. | 2012-01-05 |
20120001244 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREFOR - In an active matrix type liquid crystal display device, in which functional circuits such as a shift register circuit and a buffer circuit are incorporated on the same substrate, an optimal TFT structure is provided along with the aperture ratio of a pixel matrix circuit is increased. There is a structure in which an n-channel TFT, with a third impurity region which overlaps a gate electrode, is formed in a buffer circuit, etc., and an n-channel TFT, in which a fourth impurity region which does not overlap the gate electrode, is formed in a pixel matrix circuit. A storage capacitor formed in the pixel matrix circuit is formed by a light shielding film, a dielectric film formed on the light shielding film, and a pixel electrode. Al is especially used in the light shielding film, and the dielectric film is formed anodic oxidation process, using an Al oxide film. | 2012-01-05 |
20120001245 | Recessed Access Device for a Memory - Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess. | 2012-01-05 |
20120001246 | MEMORY DEVICE AND METHOD OF FABRICATING THEREOF - Subject matter disclosed herein relates to a process flow to form a gate structure of a memory device. | 2012-01-05 |
20120001247 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 2012-01-05 |
20120001248 | METHODS OF FORMING NANOSCALE FLOATING GATE - A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer. | 2012-01-05 |
20120001249 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE & METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 2012-01-05 |
20120001250 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 2012-01-05 |
20120001251 | EEPROM - An EEPROM includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. First through fifth impurity regions are formed in top layer portions of the semiconductor layer. On the first insulating film, a select gate, and first and second floating gates are respectively disposed opposite a region between the first impurity region and the second impurity region, a region between the second impurity region and the third impurity region, and a region between the third impurity region and the fourth impurity region. In the first insulating film, first and second tunnel windows are respectively formed at portions in contact with the first and second floating gates. A sixth impurity region of the second conductive type, which is connected to the second impurity region, is formed in the top layer portion of the semiconductor layer that opposes the second tunnel window. | 2012-01-05 |
20120001252 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 2012-01-05 |
20120001253 | FLATBAND VOLTAGE ADJUSTMENT IN A SEMICONDUCTOR DEVICE - Memory devices, methods for fabricating, and methods for adjusting flatband voltages are disclosed. In one such memory device, a pair of source/drain regions are formed in a semiconductor. A dielectric material is formed on the semiconductor between the pair of source/drain regions. A control gate is formed on the dielectric material. A charged species is introduced into the dielectric material. The charged species, e.g., mobile ions, has an energy barrier in a range of greater than about 0.5 eV to about 3.0 eV. A flatband voltage of the memory device can be adjusted by moving the charged species to different levels within the dielectric material, thus programming different states into the device. | 2012-01-05 |
20120001254 | Transistor With Embedded Si/Ge Material Having Reduced Offset and Superior Uniformity - In sophisticated semiconductor devices, a strain-inducing embedded semiconductor alloy may be provided on the basis of a crystallographically anisotropic etch process and a self-limiting deposition process, wherein transistors which may not require an embedded strain-inducing semiconductor alloy may remain non-masked, thereby providing superior uniformity with respect to overall transistor configuration. Consequently, superior strain conditions may be achieved in one type of transistor, while generally reduced variations in transistor characteristics may be obtained for any type of transistors. | 2012-01-05 |
20120001255 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The present invention relates to a semiconductor device and a method of manufacture thereof, particularly, to a semiconductor device including a vertical type gate and a method of forming the same. According to the present invention, a semiconductor device includes a vertical pillar which is protruded from a semiconductor substrate, has a vertical channel, and has a first width; an insulating layer which has a second width smaller than the first width, provided in both sides of the vertical pillar which is adjacent in a first direction; and a nitride film provided in a side wall of the insulating layer. | 2012-01-05 |
20120001256 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first insulator pillar surrounding an active region; a second insulator pillar with a second side surface opposed in a y direction to a first side surface of the first insulator pillar on the active region side; an insulating film covering top surfaces of first and second insulator pillars; a second gate electrode electrically connected to the first gate electrode, covering at least the first and second side surfaces; and a gate contact plug in a contact hole and electrically connected to a top surface of the second gate electrode, the insulating film and the second gate electrode being exposed in a bottom of the contact hole. A distance between first and second side surfaces | 2012-01-05 |
20120001257 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film. | 2012-01-05 |
20120001258 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a gate metal buried within a trench included in a semiconductor substrate including an active region defined by an isolation layer, a spacer pattern disposed on an upper portion of a sidewall of a gate metal, a first gate oxide layer disposed between the spacer pattern and the trench, a second gate oxide layer disposed below the first gate oxide layer and the gate metal, and a junction region disposed in the active region to overlap the first gate oxide layer. | 2012-01-05 |
20120001259 | METHOD AND APPARATUS FOR IMPROVING GATE CONTACT - A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess. | 2012-01-05 |
20120001260 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device for use in a relatively high voltage application that comprises a substrate, a first n-type well region in the substrate to serve as a high voltage n-well (HVNW) for the semiconductor device, a pair of second n-type well regions in the first n-type well region, a p-type region in the first n-type well region between the second n-type well regions, a pair of conductive regions on the substrate between the second n-type well regions, and a number of n-type regions to serve as n-type buried layers (NBLs) for the semiconductor device, wherein the NBLs are located below the first n-type region and dispersed in the substrate. | 2012-01-05 |
20120001261 | SYSTEM AND METHOD FOR INPUT PIN ESD PROTECTION WITH FLOATING AND/OR BIASED POLYSILICON REGIONS - A system and method for electrostatic discharge protection. The system includes a first transistor including a first drain, a second transistor including a second drain, and a resistor including a first terminal and a second terminal. The first terminal is coupled to the first drain and the second drain. Additionally, the system includes a third transistor coupled to the second terminal and a protected system. The third transistor includes a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a third drain. The protected system includes a fourth transistor, and the fourth transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a fourth drain. | 2012-01-05 |
20120001262 | METAL CONDUCTOR CHEMICAL MECHANICAL POLISH - The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment. | 2012-01-05 |
20120001263 | Replacement Gate Approach for High-K Metal Gate Stacks Based on a Non-Conformal Interlayer Dielectric - In replacement gate approaches for forming sophisticated high-k metal gate electrode structures in a late manufacturing stage, the exposing of the placeholder material may be accomplished on the basis of a substantially uniform interlayer dielectric material, for instance in the form of a silicon nitride material, which may have a similar removal rate compared to the dielectric cap material, the spacer elements and the like of the gate electrode structures. Consequently, a pronounced degree of recessing of the interlayer dielectric material may be avoided, thereby reducing the risk of forming metal residues upon removing any excess material of the gate metal. | 2012-01-05 |
20120001264 | ETCHANTS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME - Provided according to embodiments of the present invention are methods of fabricating semiconductor devices using an etchant. In some embodiments, the etchant may be highly selective and may act to reduce interference between wordlines in the semiconductor device. In some embodiments of the invention, provided are methods of fabricating a semiconductor device that include forming a plurality of gate patterns on a substrate; forming first insulation layers between the gate patterns; wet-etching the first insulation layers to form first insulation layer residues; and forming air gaps between the plurality of gate patterns. Related etchant solutions and semiconductor devices are also provided. | 2012-01-05 |
20120001265 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WHICH A PLURALITY OF TYPES OF TRANSISTORS ARE MOUNTED - A method of manufacturing a semiconductor device includes the steps of forming a trench on a semiconductor substrate to define a first and a second element regions; burying a first oxide film in the trench; forming a second oxide film on surfaces of the first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing the first element region and a part of the first oxide; performing a second ion doping using a second mask which is exposing a second region containing the second element region and a part of the first oxide film; and removing the second oxide film formed in the first element region and the second element region by etching, and the first oxide film is selectively thinned using the first or second mask after performing the first or second ion doping. | 2012-01-05 |
20120001266 | GATE STRUCTURES AND METHOD OF FABRICATING SAME - A method includes: forming first and second projections; forming a first structure engaging the first projection, and including: a non-metallic conductive layer, and a first opening over the conductive layer; forming a second structure engaging the second projection, and including: a second opening; and conformally depositing a pure metal in the first and second openings. A different aspect involves an apparatus including: a first device that includes a first projection and a first gate structure, the first projection extending from a substrate, and the first gate structure engaging the first projection, and including an opening, and a conformal, pure metal disposed in the opening; and a second device that includes a second projection and a second gate structure, the second projection extending from the substrate, and the second gate structure engaging the second projection, and including a silicide including a metal that is the same metal disposed in the opening. | 2012-01-05 |
20120001267 | ELECTRODE STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE INCLUDING THE ELECTRODE STRUCTURE - An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer. | 2012-01-05 |
20120001268 | ISOLATION WITH OFFSET DEEP WELL IMPLANTS - A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is removed and a second mask is prepared over the substrate. The method performs a second shallow well implant through the second mask to implant second-type impurities to the first depth of the substrate and then removes the second mask. A third mask is prepared over the substrate. The third mask has openings smaller than openings in the first mask and the second mask. A first deep well implant is performed through the third mask to implant the first-type impurities to a second depth of the substrate, the second depth of the substrate being greater than the first depth of the substrate. The third mask is removed and a fourth mask is prepared over the substrate, the fourth mask has openings smaller than the openings in the first mask and the second mask. Then, a second deep well implant is performed through the fourth mask to implant the second-type impurities to the second depth of the substrate. | 2012-01-05 |
20120001269 | Semiconductor Device - According to one embodiment, a semiconductor device including a field-effect transistor, and a resistance element connected between a gate electrode of the field effect transistor and a connection point connected between a back gate electrode of the field effect transistor and one of source-drain regions of the field effect transistor, a voltage being applied between the other of the source-drain regions and the gate electrode. | 2012-01-05 |
20120001270 | MEMORY CELLS - A method of manufacturing an integrated circuit (IC), comprising: defining a plurality of continuous active areas; forming conducting lines extending over the active areas; and using the conducting lines as a mask, introducing dopant into the active areas. Connections are provided between doped regions and conducting lines to form first and second circuit portions, at least one active area being continuous between those portions. In that active area, connections are provided between doped regions and conducting lines to form a pair of diode-connected transistors in reverse bias to one another between the first and second circuit portions, connected so as to leave a shared, unconnected doped region between the pair. The present invention also relates to a corresponding IC. | 2012-01-05 |
20120001271 | GATE ELECTRODE AND GATE CONTACT PLUG LAYOUTS FOR INTEGRATED CIRCUIT FIELD EFFECT TRANSISTORS - A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction. | 2012-01-05 |
20120001272 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR MODULE AND ELECTRONIC SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a cell area and a peripheral area, the cell area having an active region defined by an isolation region, a cell gate structure below an upper surface of the substrate in the cell area, the cell gate crossing the active region, a bit line structure above an upper surface of the substrate in the cell area, the bit line structure including bit line offset spacers on at least two side surfaces thereof, and a peripheral gate structure above an upper surface of the substrate in the peripheral area, the peripheral gate structure including peripheral gate offset spacers and peripheral gate spacers on at least two side surfaces thereof. | 2012-01-05 |
20120001273 | Micro-package for Micromachining Liquid Flow Sensor Chip - The current invention disclosed a micro-package design for packaging of micromachining liquid flow sensor. The package in present invention is fabricated with micromachining or micro-molding approach, which can greatly reduce the manufacturing cost due to the batch production. The micro-package design provides packaging solution for general micromachining liquid flow sensors that can enable various microfluidic applications while reaching the cost threshold for a disposable unit. | 2012-01-05 |
20120001274 | WAFER LEVEL PACKAGE HAVING A PRESSURE SENSOR AND FABRICATION METHOD THEREOF - A wafer level package having a pressure sensor and a fabrication method thereof are provided. A wafer having the pressure sensor is bonded to a lid, and electrical connecting pads are formed on the wafer. After the lid is cut, wire-bonding and packaging processes are performed. Ends of bonding wires are exposed and serve as an electrical connecting path. A bottom opening is formed on a bottom surface of the wafer, in order to form a pressure sensor path. | 2012-01-05 |
20120001275 | SEMICONDUCTOR DEVICE - A semiconductor device in which intrusion of the cutting water and cutting wastes in the singulation process can be prevented, and reliability is improved includes: a substrate; at least one semiconductor element having a piezoelectric conversion function and mounted on the main surface of the substrate; a casing fixed to the main surface of the substrate to cover the semiconductor element; a through hole formed in the substrate or the casing; and a predetermined substance filled into the through hole to close the through hole, wherein the predetermined substance has properties such that the predetermined substance wettably spreads by heating to open the through hole. | 2012-01-05 |
20120001276 | APPARATUS INTEGRATING MICROELECTROMECHANICAL SYSTEM DEVICE WITH CIRCUIT CHIP AND METHODS FOR FABRICATING THE SAME - One embodiment discloses an apparatus integrating a microelectromechanical system device with a circuit chip which comprises a circuit chip, a microelectromechanical system device, a sealing ring, and a lid. The circuit chip comprises a substrate and a plurality of metal bonding areas. The substrate has an active surface with electrical circuit area, and the metal bonding areas are disposed on the active surface and electrically connected to the electrical circuits. The microelectromechanical system device comprises a plurality of bases and at least one sensing element. The bases are connected to at least one of the metal bonding areas. The at least one sensing element is elastically connected to the bases. The sealing ring surrounds the bases, and is connected to at least one of the metal bonding areas. The lid is opposite to the active surface of the circuit chip, and is connected to the sealing ring to have a hermetic chamber which seals the sensing element and the active surface of the circuit chip. | 2012-01-05 |
20120001277 | METHODS FOR MAKING IN-PLANE AND OUT-OF-PLANE SENSING MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) - A device structure is made using a first conductive layer over a first wafer. An isolated conductive region is formed in the first conductive layer surrounded by a first opening in the conductive layer. A second wafer has a first insulating layer and a conductive substrate, wherein the conductive substrate has a first major surface adjacent to the first insulating layer. The insulating layer is attached to the isolated conductive region. The conductive substrate is thinned to form a second conductive layer. A second opening is formed through the second conductive layer and the first insulating layer to the isolated conductive region. The second opening is filled with a conductive plug wherein the conductive plug contacts the isolated conductive region. The second conductive region is etched to form a movable finger over the isolated conductive region. A portion of the insulating layer under the movable finger is removed. | 2012-01-05 |
20120001278 | SEMICONDUCTOR PHYSICAL QUANTITY SENSOR - A semiconductor physical quantity sensor includes a sensor chip, a support member for fixing the sensor chip to a fixing position and an adhesive bonding the sensor chip with the support member. The sensor chip includes a semiconductor substrate and a chip base supporting the semiconductor substrate. The semiconductor substrate is provided with a sensing portion for detecting a physical quantity. The chip base is bonded with the support member through the adhesive. The adhesive is provided by a mixture of an adhesive base material mainly made of a resin and a granular material mainly made of a cross-linked resin. | 2012-01-05 |
20120001279 | Hall sensor - Provided is a highly-sensitive Hall element capable of eliminating an offset voltage without increasing the chip size. At the four vertices of a square Hall sensing portion, Hall voltage output terminals and control current input terminals are respectively arranged independently from each other. The Hall voltage output terminals all have the same shape. The control current input terminals are arranged on both sides of the Hall voltage output terminals, respectively, to be spaced apart from the Hall voltage output terminals so as to prevent electrical connection to the Hall voltage output terminals, and have the same shape at the four vertices. | 2012-01-05 |
20120001280 | Hall sensor - Provided is a highly-sensitive Hall element capable of eliminating an offset voltage without increasing the chip size. The Hall element includes: a Hall sensing portion having a shape of a cross and four convex portions; Hall voltage output terminals which are arranged at the centers of the front edges of the four convex portions, respectively; and control current input terminals which are arranged on side surfaces of each of the convex portions independently of the Hall voltage output terminals. In this case, the Hall voltage output terminal has a small width and the control current input terminal has a large width. | 2012-01-05 |
20120001281 | MAGNETIC STORAGE ELEMENT AND MAGNETIC MEMORY - Disclosed herein is a magnetic storage element including: a reference layer configured to have a magnetization direction fixed to a predetermined direction; a recording layer configured to have a magnetization direction that changes due to spin injection in a direction corresponding to recording information; an intermediate layer configured to separate the recording layer from the reference layer; and a heat generator configured to heat the recording layer. A material of the recording layer is such a magnetic material that magnetization at 150° C. is at least 50% of magnetization at a room temperature and magnetization at a temperature in a range from 150° C. to 200° C. is in a range from 10% to 80% of magnetization at a room temperature. | 2012-01-05 |
20120001282 | RADIATION DETECTOR - A radiation detector of a compact size and producing almost no image defect is disclosed, comprising a first radiation-transmissive substrate, a first adhesive layer, a second radiation-transmissive substrate, a scintillator layer and an output substrate provided with a photoelectric conversion element layer which are provided sequentially in this order, wherein an arrangement region of the scintillator layer in a planar direction of the layer includes an arrangement region of the photoelectric conversion element layer in a planar direction of the layer and an arrangement region of the first substrate in a planar direction of the substrate, and the arrangement region of the first substrate includes the arrangement region of the photoelectric conversion element layer; and when the arrangement region of the scintillator layer is divided to plural areas, a coefficient of variation of filling factor is 20% or less which is defined as a standard deviation of filling factor of phosphor of the plural areas, divided by an average value of the filling factor. | 2012-01-05 |
20120001283 | Germanium Photodetector - A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, implanting n-type ions in the Ge layer, patterning the n-type Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline n-type Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer. | 2012-01-05 |
20120001284 | SILICON NITRIDE LIGHT PIPES FOR IMAGE SENSORS - Various embodiments for etching of silicon nitride (Si | 2012-01-05 |
20120001285 | SOLID STATE IMAGING APPARATUS - According to one embodiment, in the upper laminated structure, first layers and second layers are alternately laminated, the first layer and the second layer having different refractive indices. In the lower laminated structure, first layers and second layers are alternately laminated, the first layer and the second layer having different refractive indices. The upper laminated structure and the lower laminated structure are equal in number of layers laminated therein. Each of the lowermost layer of the upper laminated structure and the uppermost layer of the lower laminated structure are configured by the first layer. The upper laminated structure and the lower laminated structure are configured to be asymmetric to each other such that, within some layer sets out of a plurality of layer sets each including two layers disposed at corresponding positions in the upper and lower laminated layers, one layer of the two layers in each layer set of the some layer sets is thinner than the other layer. | 2012-01-05 |
20120001286 | IMAGE SENSOR AND PACKAGE INCLUDING THE IMAGE SENSOR - Provided are an image sensor and a package including the same. The image sensor may include an interconnection layer comprising a plurality of interconnections that are vertically stacked, a light penetration layer including color filters and microlenses, a semiconductor layer disposed between the interconnection layer and the light penetration layer and including photoelectrical transformation elements and a light shielding pattern disposed between the light penetration layer and the semiconductor layer. A surface of the semiconductor layer adjacent to the light penetration layer defines a recess region recessed toward the interconnection layer. The light shielding pattern is formed in the recess region and at least one of the photoelectrical transformation elements is formed in the semiconductor layer between the light shielding pattern and the interconnection layer. | 2012-01-05 |
20120001287 | IMAGE SENSOR AND METHOD FOR MANUFACTURING AN IMAGE SENSOR - An image sensor and a method for manufacturing an image sensor are described in which the image sensor includes at least one substrate having a plurality of light-sensitive elements forming a sensor field and first microfilter elements for wavelength-selective filtering of incident light. The first microfilter elements are attached to a transparent carrier made of glass or a transparent film, for example. A first microfilter element is situated in front of a portion of the light-sensitive elements for wavelength-selective filtering of light striking the light-sensitive element. No microfilter element is situated in front of a further portion of the light-sensitive elements. | 2012-01-05 |
20120001288 | SUB-PIXEL NBN DETECTOR - A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area. | 2012-01-05 |
20120001289 | UNIT PIXEL ARRAY OF AN IMAGE SENSOR - A unit pixel array of an image sensor includes a semiconductor substrate having a plurality of photodiodes, an interlayer insulation layer on a front-side of the semiconductor substrate, and a plurality of micro lenses on a back-side of the semiconductor substrate. The unit pixel array of the image sensor further includes a wavelength adjustment film portion between each of the micro lenses and the back-side of the semiconductor substrate such that a plurality of wavelength adjustment film portions correspond with the plurality of micro lenses. | 2012-01-05 |
20120001290 | SOLID-STATE IMAGING DEVICE MANUFACTURING METHOD, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - A solid-state imaging device that includes: a semiconductor substrate having a recess portion formed on a top surface thereof; an impurity region of a first conductivity type formed in a portion of the semiconductor substrate disposed lower than a bottom surface of the recess portion; and a semiconductor layer of the first conductivity type formed in the recess portion, wherein the impurity region and the semiconductor layer form a photoelectric conversion. | 2012-01-05 |
20120001291 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND SOLID-STATE IMAGE SENSOR - A method of manufacturing a semiconductor device includes steps of providing a substrate including a semiconductor portion, a non-porous semiconductor layer, and a porous semiconductor layer arranged between the semiconductor portion and the non-porous semiconductor layer, forming a porous oxide layer by oxidizing the porous semiconductor layer, forming a bonded substrate by bonding a supporting substrate to a surface, on a side of the non-porous semiconductor layer, of the substrate on which the porous oxide layer is formed, and separating the semiconductor portion from the bonded substrate by utilizing the porous oxide layer. | 2012-01-05 |
20120001292 | METHOD FOR PRODUCING SOLID STATE IMAGING DEVICE AND SOLID-STATE IMAGING DEVICE - Certain embodiments provide a method for producing a solid-state imaging device including the steps of forming an interconnection layer, forming a passivation film, forming a resist layer, forming a plurality of protruding portions and an opening, and forming an electrode pad. In the step of forming the interconnection layer, the interconnection layer is formed on the surface of the semiconductor substrate having a photodiode. In the step of forming the resist layer, the resist layer is formed on the passivation film such that the resist layer has a plurality of first openings above the photodiode and has a second opening above the interconnection of the interconnection layer. In the step of forming the plurality of protruding portions and the opening, the plurality of protruding portions and the opening are formed by etching the passivation film via the resist layer. | 2012-01-05 |
20120001293 | SEMICONDUCTOR ON GLASS SUBSTRATE WITH STIFFENING LAYER AND PROCESS OF MAKING THE SAME - A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film. | 2012-01-05 |
20120001294 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first metal wiring which is formed over substructure; a first contact plug which is coupled to the first metal wiring and passes through a first interlayer insulating film provided over the substructure; a second metal wiring which is provided over the first interlayer insulating film and is coupled to the first contact plug; a second contact plug which is coupled to the second metal wiring and passes through a second interlayer insulating film which is provided over the first interlayer insulating film; and a fuse pattern and a data read fuse pattern which are coupled to the second contact plug and provided over the second interlayer insulating film. | 2012-01-05 |
20120001295 | Semiconductor Device Comprising High-K Metal Gate Electrode Structures and Precision eFuses Formed in the Active Semiconductor Material - In a complex semiconductor device, electronic fuses may be formed in the active semiconductor material by using a semiconductor material of reduced heat conductivity selectively in the fuse body, wherein, in some illustrative embodiments, the fuse body may be delineated by a non-silicided semiconductor base material. | 2012-01-05 |
20120001296 | P-I-N DIODE CRYSTALLIZED ADJACENT TO A SILICIDE IN SERIES WITH A DIELECTRIC MATERIAL - A vertically oriented p-i-n diode is provided that includes semiconductor material crystallized adjacent a silicide, germanide, or silicide-germanide layer, and a dielectric material arranged electrically in series with the diode. The dielectric material has a dielectric constant greater than 8, and is adjacent a first metallic layer and a second metallic layer. Numerous other aspects are provided. | 2012-01-05 |
20120001297 | Techniques for Placement of Active and Passive Devices within a Chip - A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs). | 2012-01-05 |
20120001298 | Method for manufacturing thin film capacitor and thin film capacitor obtained by the same - A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0. | 2012-01-05 |
20120001299 | Semiconductor Constructions - Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays. | 2012-01-05 |
20120001300 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, forming a film of amorphous Si on a substrate including an insulating upper surface; injecting a first impurity of a first conductivity in a first region and a second region of the film; crystallizing the film by melting and solidifying the film and activating the first impurity by scanning a first laser light in a first direction and radiating the first laser light over the film; injecting a second impurity of a second conductivity at a higher concentration than the first impurity, the second impurity being a lighter element than the first impurity in the first region with masking the second region; and activating the second impurity. | 2012-01-05 |