01st week of 2009 patent applcation highlights part 21 |
Patent application number | Title | Published |
20090002006 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS - In one aspect of the present invention, a manufacturing method of a semiconductor device may include performing an electrical test on a plurality of electronic components on a wafer, generating a mapping data set including category information representing categories of the respective electronic components based on the electrical test result and position information representing positions of the respective electronic components in the wafer, forming bumps on the plurality of electronic components at wafer level in various bump layouts employed in accordance with the categories assigned to the respective electronic components, with reference to the mapping data set, and dicing the wafer to separate the plurality of electronic components into individual chips, after forming the bumps. | 2009-01-01 |
20090002007 | Universal cover for a burn-in socket - In one embodiment, the present invention includes a universal cover to be adapted to burn-in sockets, where at least some of the burn-in sockets have different dimensions. In this way, the universal cover enables an actuator plate of an actuator system having a fixed configuration of actuation members to open and close burn-in socket covers of different form factors. Other embodiments are described and claimed. | 2009-01-01 |
20090002008 | Inspection Method, Inspection Apparatus and Control Program | 2009-01-01 |
20090002009 | MULTI-OFFSET DIE HEAD - An upper die portion of a die head for aligning probes having different offsets in a first array of first micro-holes formed in a lower die portion of the die head. The upper die portion includes a spacer portion and a first assembly aid film. The spacer portion includes first and second surfaces. The first surface contacts the lower die portion. The first assembly aid film is attached with the second surface and has a second array of second micro-holes for receiving the probes having different offsets. The second micro-holes include at least a first micro-hole that is configured to be offset from a corresponding micro-hole of the first micro-holes by a first offset and at least a second micro-hole that is configured to be offset from a corresponding micro-hole of the first micro-holes by a second offset that is not the same as the first offset. | 2009-01-01 |
20090002010 | Active thermal control using a burn-in socket heating element - In one embodiment, the present invention includes a burn-socket for insertion into a test board, where the burn-in socket is coupled to receive a semiconductor device under test (DUT). The burn-in socket includes a substrate to support the semiconductor DUT, which includes a heating element embedded in a layer of the substrate. Other embodiments are described and claimed. | 2009-01-01 |
20090002011 | INSPECTING METHOD AND STORAGE MEDIUM FOR STORING PROGRAM OF THE METHOD - An inspecting method includes registering a pre-obtained relationship between contact time of the probes with the target object having the predetermined temperature and tip positions of the probes which vary in accordance with the contact time. The method further includes inspecting the chips by estimating the tip positions of the probes based on the relationship and the contact time of the probes with the chips upon the inspection and then correcting the tip positions of the probes from previous tip positions based on the estimated values until the probes are stable without being extended or contracted during the inspection. | 2009-01-01 |
20090002012 | Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits - Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated. | 2009-01-01 |
20090002013 | Testing circuit and testing method for liquid crystal display device - This invention discloses a testing circuit and a test method for a liquid crystal display device. The testing circuit for the liquid crystal display device comprises: a substrate, a plurality of pixels, a plurality of signal paths, and numbers of p shorting bars, wherein the plurality of pixels are formed on the substrate, and every pixel has numbers of n sub-pixels; the plurality of signal paths are formed on the substrate and connected to the sub-pixels correspondingly; and the p shorting bars are formed on the substrate and respectively connected to (p×m+1)th, (p×m+2)th, (p×m+3)th . . . , (p×m+p)th numbered signal paths of the plurality of the signal paths, wherein when n is odd, p=2×n; when n is even, p=n; and m being zero or positive integers. The testing method for the liquid crystal display device, by providing the mentioned above testing circuit for the liquid crystal display device, comprising: dividing the p shorting bars into n groups; and applying testing signals respectively to the shorting bars of every group for testing. The testing method for the liquid crystal display device also comprises: dividing the p shorting bars into 2 groups by odd-even sequence; and applying testing signals respectively to the shorting bars of every group for test, so as to effectively increase the testing efficiency of both array and cell test in fabrication of the liquid crystal display device. | 2009-01-01 |
20090002014 | Ultra fast differential transimpedance digital amplifier for superconducting circuits - Supercooled electronics often use Rapid Single Flux Quantum (RSFQ) digital circuits. The output voltages from RSFQ devices are too low to be directly interfaced with semiconductor electronics, even if the semiconductor electronics are cooled. Techniques for directly interfacing RSFQ digital circuits with semiconductor electronics are disclosed using a novel inverting transimpedance digital amplifier in conjunction with a non-inverting transimpedance digital amplifier to create a differential transimpedance digital amplifier that permits direct interfacing between RSFQ and semiconductor electronics. | 2009-01-01 |
20090002015 | ERROR CORRECTING LOGIC SYSTEM - The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system. | 2009-01-01 |
20090002016 | RETRIEVING DATA FROM A CONFIGURABLE IC - Some embodiments provide a configurable integrated circuit (IC). The IC has configurable logic circuits for performing logical operations, configurable routing circuits for routing signals between the configurable logic circuits, and a network for monitoring data. In some embodiments a method uses at least a subset of the configurable logic circuits and a first subset of the configurable routing circuits to implement a user design circuit on the configurable IC. The method uses a second subset of the configurable routing circuits to pass signals to the network. | 2009-01-01 |
20090002017 | Multiple-Mode Compensated Buffer Circuit - A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode. | 2009-01-01 |
20090002018 | Impedance adjusting circuit and semiconductor memory device having the same - An impedance adjusting circuit includes: a first calibration resistor circuit configured to be calibrated with an external resistor and generate a first calibration code; a second calibration resistor circuit configured to be calibrated with the first calibration resistor circuit and generate a second calibration code, the second calibration resistor circuit being connected to a first node; and a transmission line circuit configured to be responsive to a control signal to connect the first node to a pin of a system employing the impedance adjusting circuit. | 2009-01-01 |
20090002019 | APPARATUS FOR ADJUSTING RESISTANCE VALUE OF A DRIVER IN A SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for adjusting a resistance value of a driver of a semiconductor integrated circuit in which the resistance value of the driver is adjusted according to a code signal. The apparatus includes a control means that generates a plurality of counting mode signals such that the unit of counting is changed in a predetermined period, a counting means that counts the code signal in the unit of counting that is changed in response to the plurality of counting mode signals, according to a count up/down signal, and a comparing means that compares a voltage obtained by converting the code signal with a reference voltage to generate the count up/down signal. | 2009-01-01 |
20090002020 | DYNAMICALLY TRACKING DATA VALUES IN A CONFIGURABLE IC - Some embodiments provide a method of dynamically tracking data values in a configurable integrated circuit (IC). The method, during a run time of the configurable IC, receives a request for a data value and dynamically configures the configurable IC to monitor the data value. | 2009-01-01 |
20090002021 | RESTRUCTURING DATA FROM A TRACE BUFFER OF A CONFIGURABLE IC - Some embodiments provide a method that outputs from a configurable IC a first set of data bits from a trace buffer. Each bit of the first set of data bits is simultaneously generated in the configurable circuits and, in some embodiments, multiple data bits of the first set of data bits do not reach the traced buffer simultaneously. The method also determines a set of relative delays for the first set of data bits and arranges the first set of data bits into a second set of data bits by compensating for the relative delays. | 2009-01-01 |
20090002022 | CONFIGURABLE IC WITH DESKEWING CIRCUITS - Some embodiments provide a configurable integrated circuit (IC) comprising multiple deskew circuits for delaying data passage. Each of the deskew circuits comprises a stepwise delay circuit with multiple outputs and an input selection circuit with multiple inputs. Multiple outputs connect to multiple inputs. | 2009-01-01 |
20090002023 | Modular ASIC With Crosspoint Switch - Provided is a digital signal processing device, specifically a modular application specific integrated circuit (“ASIC”), having a programmable crosspoint switch for facilitating data transfer and processing within the circuit. A programmable matrix element is operable to perform advanced matrix operations (arithmetic operations) according to user provided commands. The crosspoint switch interconnects the programmable matrix element with various other processing or conditioning modules (i.e. down conversion, filter, pulse processing and demodulation modules) to ensure parallel processing at System Clock rates. The ASIC, which is reconfigurable at a top-level according to user requirements, facilitates design changes and bench testing. | 2009-01-01 |
20090002024 | TRANSPORT NETWORK FOR A CONFIGURABLE IC - Some embodiments provide a configurable integrated circuit (IC) with an arrangement of circuit elements, a trace buffer, a transport network separate from the arrangement of circuit elements. The transport network transports data from the arrangement of circuit elements to the trace buffer. | 2009-01-01 |
20090002025 | MEMORY UTILIZING OXIDE NANOLAMINATES - Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers. | 2009-01-01 |
20090002026 | Level conversion circuit for converting voltage amplitude of signal - In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable. | 2009-01-01 |
20090002027 | LEVEL SHIFTER HAVING LOW DUTY CYCLE DISTORTION - A level shifter includes an inverting circuit, a cross-coupled level shifting latch, and a SR logic gate latch. The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is powered by a first supply voltage VDDL, supplies a noninverted version of an input signal onto a first input of the level shifting latch and supplies an inverted version of the input signal onto a second input of the level shifting latch. A low-to-high transition of the input signal resets the SR latch, whereas a high-to-low transition sets the SR latch. Duty cycle distortion skew of the level shifter is less than fifty picoseconds over voltage, process and temperature corners, and the level shifter has a supply voltage margin of more than one quarter of a nominal value of VDDL. | 2009-01-01 |
20090002028 | MIXED-VOLTAGE I/O BUFFER TO LIMIT HOT-CARRIER DEGRADATION - A Mixed-voltage input and output (I/O) buffer including a pre-driver unit, a bulk-voltage generating unit, a first to a third transistors and an input stage unit is provided. The pre-driver unit outputs a first source/drain and a second signal. The bulk-voltage generating unit determines whether a first voltage or a pad voltage is used as a bulk voltage according to the pad voltage level. A gate of the first transistor receives the first signal, and a bulk, a first source/drain and a second source/drain of the first transistor are respectively coupled to the bulk voltage, the first voltage and the pad. A gate of the third transistor receives the second signal, and a first source/drain and a second source/drain of the third transistor are respectively coupled to the input stage unit for receiving an input signal from the pad and a second voltage. | 2009-01-01 |
20090002029 | TEST CONTROL CIRCUIT AND REFERENCE VOLTAGE GENERATING CIRCUIT HAVING THE SAME - A test control circuit according to an embodiment of the invention includes a test mode control unit that outputs a control signal according to a voltage trimming test signal, a decoding portion that receives the control signal and outputs a decoding signal, and a trimming signal adjusting portion that receives the decoding signal and outputs a trimming signal adjusted by a low level test signal. | 2009-01-01 |
20090002030 | HIGH SPEED SIGNALING SYSTEM WITH ADAPTIVE TRANSMIT PRE-EMPHASIS - A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level. | 2009-01-01 |
20090002031 | Slew rate controlled output driver for use in semiconductor device - An output driver for use in a semiconductor is capable of maintaining its slew rate constantly regardless of PVT (Process/Voltage/Temperature) variation. The output driver includes a pre-driving unit for pre-driving a data signal; a main driving unit for driving an output pad in response to the output signal of the pre-driving unit; and a slew rate modeling unit for generating a pre-driver bias signal to constantly maintain effective resistances of a pull-up path and a pull-down path of the pre-driving unit by modeling the pre-driving unit. | 2009-01-01 |
20090002032 | DATA SYNCHRONIZER - A data synchronizer is to avoid the pulse width constraint on the data while synchronizing the data between two devices operating at different clock rates. The data synchronizer may comprise one or more storage units such as the flip-flops and a clock gating logic associated with each storage unit. The clock gating logic may generate a control signal which may either allow or stall the clock reaching the storage units. The control signal may be generated by comparing the input and the output to the storage units. | 2009-01-01 |
20090002033 | Noise removal circuit and comparator circuit including same - The present invention reliably removes a signal change associated with a noise component from a comparison signal of a comparator. A comparator circuit includes a comparator and a timer circuit. After a reversal of the comparison signal, if the level of the comparator is sustained at least from a first time to a second time, an output signal is reversed and output. The timer circuit includes a memory unit that is shifted to a memory state in which the reversal of the comparison signal is stored at the first time if the reversal is verified. If the comparison signal is reversed during the interval between the first time and second time, the memory state is cleared. | 2009-01-01 |
20090002034 | Circuit Arrangement and Method for Detecting a Power Down Situation of a Voltage Supply Source - Circuit arrangement for detecting a power down situation of a second voltage comprising a first conductor, adapted the be connected to a first voltage, a second conductor, adapted the be connected to a reference voltage, an input node, adapted the be connected to the second voltage, and two output nodes, a first output node and a second output node. The output nodes are interconnected in such a manner, that (a) when the second voltage is higher than the reference voltage, the first output node is at the first voltage level and the second output node is at the reference voltage level, and (b) when the second voltage is equal to the reference voltage, the first output node is at the reference voltage level and the second output node is at the first voltage level. The circuit arrangement further comprises an inverter section arranged in between the two conductors, wherein the input node represents an inverter section input and wherein an inverter section output node is formed representing the inverter section output. | 2009-01-01 |
20090002035 | COMPARATOR CIRCUIT - A comparator circuit according to an embodiment of the present invention includes a comparator configured to compare an input signal voltage with a reference voltage obtained by smoothing the input signal by use of a resistor and a capacitor, and output a result of the comparison, a discharge circuit configured to compare a first addition signal which is obtained by adding a positive first voltage to the input signal voltage, with the reference voltage, and discharge the capacitor when the first addition signal is lower than the reference voltage, and a charge circuit configured to compare a second addition signal which is obtained by adding a negative second voltage to the input signal voltage, with the reference voltage, and charge the capacitor when the second addition signal is higher than the reference voltage. | 2009-01-01 |
20090002036 | LIQUID EJECTING APPARATUS AND LIQUID EJECTING METHOD - A liquid ejection apparatus includes an element that is charged and discharged so as to perform an operation to eject a liquid, an analog signal generating unit that generates an analog signal having a voltage change pattern for determining the operation of the element, a charging transistor that amplifies a current of the analog signal while the element is charged, and pushes the amplified current toward the element, the charging transistor having a current source terminal, to which a current source is connected, and a push terminal for pushing the current, and a current source connector that selects at least one current source from among a plurality of current sources according to a voltage of the analog signal, and connects the selected current source to the current source terminal. | 2009-01-01 |
20090002037 | Reset control method and apparatus in power management integrated circuit - A reset control apparatus may include a first reference generator adapted to output a first reference value in response to an enable signal from an external power source, a second reference generator adapted to receive the first reference value and to output a second reference value, and a set signal generator adapted to output a set signal when the second reference value exceeds a predetermined value. | 2009-01-01 |
20090002038 | Phase Locked Loop with Stabilized Dynamic Response - A hybrid phase locked loop (PLL) circuit for obtaining stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path from the output of the phase frequency detector to the voltage controlled oscillator (VCO). The hybrid PLL essentially enhances the performance of the conventional feed-forward PLL by providing the RC filter whose components can be weighted to provide a dynamic response that is significantly less sensitive to parameter variation and which allows loop bandwidth optimization without sacrificing damping. | 2009-01-01 |
20090002039 | POWER CONTROL CIRCUIT, METHOD OF CONTROLLING POWER CONTROL CIRCUIT, AND DLL CIRCUIT INCLUDING POWER CONTROL CIRCUIT - A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal. | 2009-01-01 |
20090002040 | DLL CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers. | 2009-01-01 |
20090002041 | METHOD FOR IMPROVING STABILITY AND LOCK TIME FOR SYNCHRONOUS CIRCUITS - Delay-locked loops, signal locking methods and devices and systems incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the internal test signal into the forward delay path and measures the time of traversal of the internal test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate. | 2009-01-01 |
20090002042 | System and method for conditioning differential clock signals and integrated circuit load board using same - A system and method of conditioning differential clock signals iteratively adjusts the duty cycles and phases of the clock signals. The duty cycles of the clock signals are adjusted by comparing respective voltage corresponding to the duty cycles of respective clock signals in each of the differential pairs. The result of the comparison is used to adjust the duty cycles of the clock signal until the magnitudes of the voltages are substantially equal. The phases of the clock signals are adjusted by selecting two sets of two clock signals each that are assigned relative phases that differ from each other by the same amount. The selected sets of clock signals are processed so that the duty cycles of resulting signals correspond to the phases of the clock signals. The duty cycle of these signals is measured as described above and used to adjust the phases of the clock signals. | 2009-01-01 |
20090002043 | System, Method and Apparatus Having Improved Pulse Width Modulation Frequency Resolution - Using a combination of frequency dithering of a PWM counter and a variable time delay circuit yields improved PWM frequency resolution with realizable circuit components and clock operating frequencies. A controllable time delay circuit lengthens a PWM signal during the first PWM cycle. During the second PWM cycle, the PWM period is increased beyond the desired amount, but the delay is reduced during this second PWM cycle to achieve the correct (desired) PWM signal period. The dithering of the PWM signal period enables the time delay circuit to be “reset” so that an infinite delay circuit is not required. The time delay circuit provides short term (one cycle) frequency adjustment so that the resulting PWM cycle is not dithered and has a period at the desired frequency resolution. | 2009-01-01 |
20090002044 | Master-slave type flip-flop circuit - A master-slave type flip-flop circuit consisting of a master latch and a slave latch, wherein the master latch comprises: a first clocked inverter to which data are input and a first latch circuit configuring a closed circuit with a first inverter and a second clocked inverter so that an output of the first clocked inverter is input to the first inverter and; the slave latch comprises: a transmission gate to which an output from the first latch circuit is input and a second latch circuit configuring a closed circuit with a second inverter and a third clocked inverter so that an output of the transmission gate is input to the second inverter, respective components configuring the master latch and the slave latch are configured with Sea Of Gate (hereinafter to be referred to as SOG) configuring a gate array, a basic cell of the SOG consists of triplely arrayed N-type transistors and corresponding triplely arrayed P-type transistors, the triplely arrayed N-type transistors consist of double-arrayed normally sized main transistors and one auxiliary transistor sized smaller than in a normal size and the triplely arrayed P-type transistors consist of double-arrayed normally sized main transistors and one auxiliary transistor sized smaller than in a normal size. | 2009-01-01 |
20090002045 | INTEGRATED CIRCUIT WITH DELAY SELECTING INPUT SELECTION CIRCUITRY - Some embodiments provide an integrated circuit (IC) with a delay select input selection circuit. The delay select input selection circuit comprises a first input selection circuit, a first storage element, a second storage element, and a first input line branching into multiple input lines. The multiple input lines include at least a second, third, and fourth input line. The second input line is communicably connected to a first input of the first input selection circuit. The third input line enters the first storage element. The fourth input line enters the second storage element. An output from the first storage element is communicably connected to a second input of the first input selection circuit. An output from the second storage element is communicably connected to a third input of the first input selection circuit. | 2009-01-01 |
20090002046 | Skew signal generation circuit and semiconductor memory device having the same - In a skew signal generation circuit, a pad is connected to an external resistor and a code generator compares a voltage of the pad with a reference voltage to generate a plurality of codes. A skew signal extractor extracts a skew signal from the codes, the skew signal containing information about a current characteristic of a MOS transistor. A driver calibrates a drivability in response to the skew signal. | 2009-01-01 |
20090002047 | Switching Circuit Which Is Used To Obtain A Doubled Dynamic Range - It permits switching signals with a peak level equal to the source voltage by means of a transistor, the peak to peak level being double the source. | 2009-01-01 |
20090002048 | Reference voltage generating circuit - Disclosed is a reference voltage generating circuit which includes resistors R | 2009-01-01 |
20090002049 | Voltage Output Device for an Electronic System - The present invention discloses a voltage output device for an electronic system, for transforming an input voltage for generating an output voltage for a load, which includes a first node, a second node, a third node, a first transistor, a second transistor, a first driving unit, a second driving unit, a control unit, a first diode, an inductor, a first capacitor, and a boost circuit. | 2009-01-01 |
20090002050 | Voltage Output Device for an Electronic System - The present invention discloses a voltage output device for an electronic system, for transforming an input voltage for generating an output voltage for a load, which includes a first transistor, a second transistor, a first driving unit, a second driving unit, a control unit, a diode, an inductor, a first capacitor, and a boost circuit. The boost circuit includes a level shifter, a third transistor, and a second capacitor. Whether the third transistor | 2009-01-01 |
20090002051 | INPUT CIRCUIT OF SEMICONDUCTOR INTEGRATED CIRCUIT - An input circuit is disclosed. The input circuit can include a cross voltage generating block that can be configured to perform charge-sharing on a pair of input signals whose phases are opposite to each other and generate a cross voltage, and an input buffer block that can be configured to buffer the pair of input signals at a voltage level corresponding to a voltage level of the cross voltage and generate an output signal. | 2009-01-01 |
20090002052 | SEMICONDUCTOR DEVICE - A level shifter circuit of the present invention includes a level shifter for converting a low-voltage signal to a high-voltage signal, and is provided with a unit that sets a voltage condition of an input signal to a transistor for input of the level shifter, when a high-voltage power supply is inputted to the level shifter circuit of the present invention before a low-voltage power supply. | 2009-01-01 |
20090002053 | Offset compensation using non-uniform calibration - Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset. | 2009-01-01 |
20090002054 | GATE DRIVE APPARATUS - A gate drive apparatus including a constant-current-pulse gate drive circuit which creates a gate signal for a switching device as a constant-current output, a constant-voltage-pulse gate drive circuit which creates the gate signal as a constant-voltage output, and a decision/switch circuit which switches the operation of the constant-current-pulse gate drive circuit and the operation of the constant-voltage-pulse gate drive circuit. The variance of switching speeds attributed to the variances of threshold voltages and mirror voltages in a plurality of switching devices which are driven by the gate drive apparatus can be suppressed, and the variance of losses can be minimized. | 2009-01-01 |
20090002055 | SEMICONDUCTOR DEVICE - A switching transistor has its drain and source respectively connected to a gate and a source of an output transistor for supplying output current to a load, and its gate connected to an internal grounding wire GW to be connected to a grounding terminal GND. A resistance element R | 2009-01-01 |
20090002056 | ACTIVE RESISTANCE CIRCUIT WITH CONTROLLABLE TEMPERATURE COEFFICIENT - Embodiments of the invention provide a circuit to implement an on-chip resistor with desired temperature coefficient behavior. In some embodiments, a circuit may comprise an amplifier, with a reference controlled by ratioed amounts of one or more positive temperature coefficient (TC+) and/or negative temperature coefficient (TC−) circuits, coupled to a controllable resistor device to control it as temperature changes to track the desired temperature coefficient behavior. | 2009-01-01 |
20090002057 | Temperature sensor circuit and method for controlling the same - A temperature sensor circuit includes a first reference voltage generator configured to generate a first reference voltage signal by using a first signal linearly varying with temperature, a second reference voltage generator configured to generate a second reference voltage signal with a predetermined logic level by using the first reference voltage signal, and a controller configured to compare the first signal with the second reference voltage signal and control a voltage level of the first signal according to the comparison result. | 2009-01-01 |
20090002058 | Automatic Bias Circuit for Sense Amplifier - The present invention discloses a bias circuit for a sense amplifier having a device under sensing, the device under sensing having an un-programmed state and a programmed state, the bias circuit comprises at least one first branch having at least one first device formed substantially the same as the device under sensing and remaining in the un-programmed state, and at least one second device formed also substantially the same as the device under sensing and being in the programmed state, wherein the at least one first device and the at least one second device are serially connected. A typical application of the present invention is an electrical fuse memory. | 2009-01-01 |
20090002059 | Rail to rail full complementary CMOS isolation gate - An isolation gate to provide isolation to a circuit to be isolated for a first voltage and a second voltage includes a voltage source for the first voltage and the second voltage, a first path coupled to the circuit to be isolated and a first control switch to control the first path. The first control switch isolates the circuit to be isolated while said isolation gate is subject to either the first voltage or the second voltage. | 2009-01-01 |
20090002060 | NEGATIVE N-EPI BIASING SENSING AND HIGH SIDE GATE DRIVER OUTPUT SPURIOUS TURN-ON PREVENTION DUE TO N-EPI P-SUB DIODE CONDUCTION DURING N-EPI NEGATIVE TRANSIENT VOLTAGE - A high-side driver in a driver circuit for driving a half-bridge stage having high- and low-side power switching devices series connected at a switched node, the high-side driver driving the high-side power switching device. The high-side driver including first and second complementary switched MOSFET series connected at a high-side node, driving the high-side power switching device, one of the MOSFETs having a parasitic bipolar transistor formed between the substrate, an N+ epitaxial region connected to the high-side driver supply voltage and the switched node, with the parasitic transistor having a base electrode formed by the N+ epitaxial region, an emitter electrode formed by the substrate and a collector electrode formed by the switched node, such that if a transient voltage that is negative with respect to the substrate is present at the high-side driver supply voltage, the parasitic transistor will conduct a short circuit current between the switched node and the substrate; a first circuit for controlling the conduction of the first and second MOSFETs to switch the high-side switching device ON and OFF; a diffusion in the N+ epitaxial region in which a terminal connected to the switched node is provided by the diffusion forming the collector of the parasitic transistor; and a second circuit coupled to the diffusion for sensing the high-side driver supply voltage at the epitaxial region and providing a signal to the controller circuit to prevent turn-ON of the high-side power switching device. | 2009-01-01 |
20090002061 | BIAS SUPPLY, START-UP CIRCUIT, AND START-UP METHOD FOR BIAS CIRCUIT - A bias supply, a start-up circuit, and a start-up method for a bias circuit are provided. The bias supply includes the bias circuit, an impedance unit, a charge storage unit, and a switch. The impedance unit is coupled between a first voltage and a node. The charge storage unit is coupled between the node and a second voltage. The switch decides whether or not to output a start-up voltage to the bias circuit according to the voltage of the node. In other words, charge/discharge properties of the charge storage unit are utilized for controlling whether the switch outputs a start-up voltage to the bias circuit or not. Therefore, the power consumption of the start-up circuit is decreased. | 2009-01-01 |
20090002062 | METHOD FOR SENSING INTEGRATED CIRCUIT TEMPERATURE INCLUDING ADJUSTABLE GAIN AND OFFSET - Embodiments of the invention include a temperature sensor method for providing an output voltage response that is linear to the temperature of the integrated circuit to which the temperature sensor belongs and/or the integrated circuit die on which the temperature sensor resides. The output voltage of the temperature sensor has an adjustable gain component and an adjustable voltage offset component that both are adjustable independently based on circuit parameters. The inventive temperature sensor includes an offset circuit that diverts a portion of current from the scaled PTAT current before the current is sourced through the output resistor. The offset circuit includes a bandgap circuit arrangement, a voltage to current converter arrangement, and a current mirror arrangement that are configured to provide a voltage offset adjustable based on independent circuit parameters such as resistor value ratios and transistor device scaling ratios. The gain of the temperature sensor also is based on similar independent circuit parameters. | 2009-01-01 |
20090002063 | Semiconductor Circuit - A semiconductor circuit according to an embodiment of the present invention includes a first current mirror operating between a first power supply potential and a second power supply potential, a third power supply potential generated by the first current mirror, a second current mirror operating between the first power supply potential and the second power supply potential, a fourth power supply potential generated by the second current mirror, a circuit operating between the third power supply potential and the fourth power supply potential, and a first conductive type transistor and a second conductive type transistor connected to the circuit in parallel and connected to each other in series. | 2009-01-01 |
20090002064 | CHARGE PUMP CIRCUIT - A reversal charge pump circuit generates a negative voltage from an input voltage received from an input terminal, and provides an output terminal with the negative voltage. The charge pump circuit achieves increased voltage stability and avoids breakdown voltage problems, with an uncomplicated structure. The circuit may have first and second capacitors, first through fourth switches, and a voltage control circuit. The voltage control circuit controls the voltage provided to the first capacitor. The switches are on/off controlled by signals from a control circuit. | 2009-01-01 |
20090002065 | Buffer circuit for reducing differential-mode phase noise and quadrature phase error - According to one exemplary embodiment, a buffer circuit for reducing differential-mode phase noise and quadrature phase error comprises first and second switching branches driven by an in-phase (I) signal, third and fourth switching branches driven by a quadrature-phase (Q) signal, the first and second switching branches and third and fourth switching branches being coupled to a common bias current source to reduce the differential-mode phase noise and quadrature phase error at an output of the buffer circuit. In one embodiment, the switching branches may be loaded by first, second, third, and fourth resonators formed, for example, by L-C circuits tuned to a local oscillator frequency. In one embodiment, the buffer circuit may comprise switching branches formed by FETs, and be used in conjunction with a local oscillator and mixer circuits to down-convert a radio frequency (RF) signal, in a receiving system, for example. | 2009-01-01 |
20090002066 | Multi-Tap Direct Sub-sampling Mixing System for Wireless Receivers - A multi-tap direct sub-sampling mixing system for wireless receivers is provided with a dynamically configurable passive switched capacitor filter. A front end amplifier is connected to receive a signal. The passive switched capacitor filter is connected to receive the amplified signal and has an output for providing a filtered signal. The switched capacitor filter has at least two sections that are each operable as a pole, wherein a first section of the at least two sections has sets of at least two stacked capacitors interconnected with a set of switches operable to amplify in input voltage provided to an input of the first section in response to operation of the set of switches; and a back end section connected to the output of the switched capacitor filter to receive the filtered signal. | 2009-01-01 |
20090002067 | Method and System for Signal Coupling and Direct Current Blocking - A method and class of circuit configurations for coupling low-frequency signals from one stage of an electronic apparatus to another stage, from the outside world to such a stage, or from such a stage to the outside world, through the use of a plurality of symmetrical double-layer capacitors combined with other electronic components are disclosed. The capacitors are used for signal transmission while blocking direct current, rather than for energy storage. Use of double-layer capacitors in place of more conventional capacitors permits the transmission of a much wider range of signals with far less distortion. The technology is particularly well-adapted to use in medical devices, including bioelectronic stimulators, where redundant devices are required for safety in case of single component failure while unacceptable levels of distortion may occur when conventional components are used. | 2009-01-01 |
20090002068 | Dynamic Biasing System For An Amplifier - A dynamic biasing system (“DBS”) for dynamically biasing an amplifier with an adjusted bias signal is shown. The DBS may include a first biasing circuit that produces a bias signal and a second biasing circuit in signal communication with both the first biasing circuit and the amplifier, wherein the second biasing circuit compares the bias signal to a predetermined threshold and in response produces the adjusted bias signal. | 2009-01-01 |
20090002069 | VARIABLE CIRCUIT, COMMUNICATION APPARATUS, MOBILE COMMUNICATION APPARATUS AND COMMUNICATION SYSTEM - A variable circuit that has a device that changes the mechanical state thereof and has a characteristic that is changed by a change of the mechanical state of the device, the variable circuit including: a controlling section | 2009-01-01 |
20090002070 | METHODS AND APPARATUS TO CONTROL RAIL-TO-RAIL CLASS AB AMPLIFIERS - In one example, an amplifier for providing stable output quiescent current comprising includes a number of supply rails, an output device configured for providing an output voltage, the output device coupled to the plurality of supply rails, and an output quiescent current controller coupled to the plurality of supply rails and the output device, the output quiescent current controller to regulate the voltage in the output device to provide a consistent quiescent current in the output device. | 2009-01-01 |
20090002071 | Distributed Circular Geometry Power Amplifier Architecture - The present invention discloses a distributed power amplifier topology and device that efficiently and economically enhances the power output of an RF signal to be amplified. The power amplifier comprises a plurality of push-pull amplifiers interconnected in a novel circular geometry that preferably function as a first winding of an active transformer having signal inputs of adjacent amplification devices driven with an input signal of equal magnitude and opposite phase. The topology also discloses the use of a secondary winding that matches the geometry of primary winding and variations thereof that serve to efficiently combine the power of the individual power amplifiers. The novel architecture enables the design of low-cost, fully-integrated, high-power amplifiers in the RF, microwave, and millimeter-wave frequencies. | 2009-01-01 |
20090002072 | POWER AMPLIFICATION DEVICE - A power amplification device includes a BTL amplification circuit including a first amplification circuit and a second amplification circuit, the first amplification circuit including a first output transistor, a first power detection circuit, a second output transistor, and a second power detection circuit, the second amplification circuit including a third output transistor, a third power detection circuit, a fourth output transistor, and a fourth power detection circuit, a first comparator which compares output values of the first and fourth power detection circuits, and a second comparator which compares output values of the second and third power detection circuits. | 2009-01-01 |
20090002073 | Wideband Variable Gain Amplifier With Clipping Function - The present invention relates to a variable gain amplifier. The variable gain amplifier includes an input unit including first and second input nodes and an output node, the input unit being configured to receive first and second input signals. The variable gain amplifier further includes a first clipping unit operable to clip a voltage level at the output node to be equal to or lower than a level of a first reference voltage and a second clipping unit operable to clip a voltage level at the output node to be equal to or greater than a level of a second reference voltage, wherein the second reference voltage is lower than the first reference voltage. A predetermined level of a voltage is outputted through an output unit included in the variable gain amplifier based on the clipped voltage level. | 2009-01-01 |
20090002074 | Power Supply Control Circuit - The present invention is to provide a power supply control circuit that can effectively eliminate voltage distortion of an input signal during signal amplification. A power supply control circuit which controls a power supply voltage of a direct-current power source at a constant level and supplies the power supply voltage to an amplification circuit performing a differential operation alternately in accordance with a signal level of an input signal includes: a first transistor whose collector is connected to the direct-current power source and emitter is connected to the amplification circuit, for outputting a current; an error amplifier whose output port is connected to a base of the first transistor, for performing feedback control to hold a difference between a predetermined reference potential and a potential at the emitter of the first transistor at a constant level; and a second transistor whose emitter and base are mutually connected to the first transistor and collector is grounded, for absorbing a current. | 2009-01-01 |
20090002075 | AMPLIFIER WITH CONFIGURABLE DC-COUPLED OR AC-COUPLED OUTPUT - A multi-mode amplifier with configurable DC-coupled or AC-coupled output is described. In one design, the multi-mode amplifier includes an amplifier and at least one DC level shifting circuit. The amplifier receives and amplifies an input signal and provides an output signal that is suitable for DC coupling to a load in a DC-coupled mode and for AC coupling to the load in an AC-coupled mode. The at least one DC level shifting circuit performs DC level shifting for at least one (e.g., input and/or output) common-mode voltage of the amplifier and is controlled based on whether the amplifier is operating in the DC-coupled or AC-coupled mode. The amplifier operates between V | 2009-01-01 |
20090002076 | SIGNAL WAVEFORM EQUALIZER CIRCUIT AND RECEIVER CIRCUIT - A signal waveform equalizer circuit capable of equalizing the waveform of an input signal with a center voltage of 0 V and yet small in circuit scale. An input signal (in | 2009-01-01 |
20090002077 | Monolithic flexible power amplifier using integrated tunable matching networks - A flexible power amplifier can be adapted during operation for use in connection with two or more different wireless standards. In at least one embodiment, adaptations to power transistor size, RF bias current, and matching are made when a corresponding multi-standard wireless device changes the wireless standard under which it is currently operating. | 2009-01-01 |
20090002078 | PREAMPLIFIER AND OPTICAL RECEIVING DEVICE INCLUDING THE SAME - A preamplifier includes a single-ended amplifier, a differential amplifier, an operational amplifier, and a clipping circuit. The single-ended amplifier converts an input current signal into a voltage signal, outputs an amplified voltage signal according to a preset amplification gain. The differential amplifier includes first and second differential inputs, and outputs a negative-phase signal and a positive-phase signal. The amplified voltage signal is applied to the first differential input of the differential amplifier. The operational amplifier includes first and second inputs which respectively receive the negative-phase signal and the positive-phase signal, where an output of the operational amplifier is applied to the second differential input of the differential amplifier. The clipping circuit clips an amplitude of the negative-phase signal output by the differential amplifier. | 2009-01-01 |
20090002079 | CONTINUOUS GAIN COMPENSATION AND FAST BAND SELECTION IN A MULTI-STANDARD, MULTI-FREQUENCY SYNTHESIZER - A frequency synthesizer capable of high speed, low power, wideband operation including a method of gain compensation, and a method of fast voltage controlled oscillator (VCO) band calibration. In addition, the frequency synthesizer may include two or more switchable independent loop filters to facilitate wideband operation. Such a frequency synthesizer may be used in many applications, and in one example, may be particularly suitable for use in a multi-band, multi-standard transmitter or radio transceiver. | 2009-01-01 |
20090002080 | FREQUENCY DIVIDER AND PHASE LOCKED LOOP USING THE SAME - The invention relates to a frequency divider operated digitally and capable of satisfying the Zigbee standard, and a phase locked loop system using the same. The frequency divider includes a plurality of latches in a ring structure with an output of a latter end latch is connected to an input of a former end latch. The frequency divider also includes an input end connected in common to clock ends of the latches, receiving a signal to be divided, and a plurality of output ends connected to the output ends of the latches, outputting divided signals of different phases. The phase locked loop system of the invention has a dividing means dividing an output frequency by 1/P and 1/P+0.5 using the frequency divider, thereby generating the Zigbee channel frequencies at a 5 MHz spacing. | 2009-01-01 |
20090002081 | MEASUREMENT APPARATUS FOR IMPROVING PERFORMANCE OF STANDARD CELL LIBRARY - Disclosed herein is a measurement apparatus for improving performances of standard cells in a standard cell library when verifying performance of the standard cell library through a ring oscillator among various test element groups (TEGs). A built-in circuit is used to measure and verify performance of the standard cell library through a TEG. Therefore, it is possible to effectively improve performances of the standard cells in the standard cell library. Particularly, it is possible to not only remove human errors or internal errors of equipment, but also perform the measurement more readily, rapidly and accurately. Further, it is possible to curtail the use of high-performance equipment or manpower and time required in a measurement process. | 2009-01-01 |
20090002082 | MULTIPHASE SIGNAL GENERATOR - A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage. | 2009-01-01 |
20090002083 | Oscillation Circuit, Power Supply Circuit, Display Device, and Electronic Apparatus - An oscillation circuit, power supply circuit, display device using same, and electronic apparatus which can be built in a display panel without causing an increase of cost and do not need any adjustment work, each having a pulse generation portion | 2009-01-01 |
20090002084 | Oscillator - In an oscillator of the present invention, each of field-effect transistors ( | 2009-01-01 |
20090002085 | 4Less-Xtaless, capless, indless, dioless TSOC design of SOC or 4Free-Xtalfree, capfree, indfree, diofree TSOC desigh of SOC - 4Less-Xtaless, Capless, Indless, Dioless TSOC Design of SOC or 4Free-Xtafree, Capfree, Indfree, Diofree TSOC Design of SOC is the True System On Chip Design of Security Of Community. Xtaless is Xtaless Clock Generator generating the reference clock having the superior quality of crystal clock without the on-board external crystal. Capless has the Capless Toggle and Capless LDVR. Capless Toggle is the de-bouncing circuit without the external on-board capacitor. Capless LDVR is the Low Drop Voltage Regulator having no external on-board capacitor. Indless is the Indless SM of Switch Mode Power Supply having no external on-board inductor. The Indless SM adopts the PHM of Pulse Hybrid Modulation of the PWM and PFM and making smooth load adaptive hybrid operations. Both LDVR and SM have the hybrid of the hybrid mode of digital and analog modes. Furthermore, with circuit configuration, the LDVR and SM can share the same driver. Dioless is the Dioless TRNG which the True Random Number Generator having no external Avalanche Diode. The Xtaless Clock Generator adopt the PVTNAH design which is Process, Voltage, Temperature, Noise, Aging and Humidity compensation design. The Xtaless Clock using LC resonator of which LC resonator is self-compensation LC resonator over the temperature and humidity. The Xtaless Clock using RC resonator of which RC resonator is self-compensation RC resonator over the temperature and humidity. The smart USB switch for SOC design can save the portable battery power. The Triple-Mode Camera for SOC design has the ultra-wide dynamic range for the still camera mode, video camera mode and surveillance camera mode. | 2009-01-01 |
20090002086 | Film bulk acoustic resonator calibration - Film bulk acoustic resonators (FBARS) have resonant frequencies that vary with manufacturing variations, but tend to be matched when in proximity on an integrated circuit die. FBAR resonant frequency is determined using a fractional-N synthesizer and comparing phase/frequency of an output signal from the fractional-N synthesizer to a reference. The reference may be derived from a low frequency crystal oscillator, an external signal source, or a communications signal. | 2009-01-01 |
20090002087 | LOW-POWER FAST-STARTUP OSCILLATOR WITH DIGITAL FEEDBACK CONTROL - Embodiments of the present invention provide a system for controlling a startup time of an oscillator circuit. The system includes a variable current source coupled to the oscillator circuit, wherein a startup time of the oscillator circuit is proportional to a bias current input into the oscillator circuit from the variable current source. The system also includes a control mechanism coupled to the variable current source and to the output of the oscillator circuit. Upon startup, the control mechanism is configured to adjust the variable current source to input a large startup bias current into the oscillator circuit. After the oscillator circuit outputs a predetermined number of oscillations during startup, the control mechanism is configured to adjust the variable current source to decrease its current to a smaller steady-state bias current into the oscillator circuit. | 2009-01-01 |
20090002088 | DIGITAL CONTROLLED OSCILLATOR, FREQUENCY SYNTHESIZER, RADIO COMMUNICATION APPARATUS USING THE SAME, AND CONTROL METHOD FOR THE SAME - The digital controlled oscillator includes a variable capacitance section having a first capacitor array of a plurality of first variable capacitors and a second capacitor array of a plurality of second variable capacitors, and generates a signal having an oscillation frequency corresponding to the capacitance value of the variable capacitance section. The first capacitance change amount in the individual first variable capacitors is a value obtained by multiplying the second capacitance change amount in the individual second variable capacitors by an integer equal to or more than 2, and the number of second variable capacitors is equal to or more than a value obtained by subtracting 1 from the integer equal to or more than 2. | 2009-01-01 |
20090002089 | Digital FM Transmitter with Variable Frequency Complex Digital IF - A system, method and apparatus are described for digitally synthesizing a signal for FM transmission. A complex variable frequency digital IF signal is generated for use by a digital modulator in transmission of a signal with an integrated circuit. In some examples, the integrated circuit includes various baseband processing blocks, an up-sampler, a summer, a numerically controlled oscillator (NCO) and a complex rotator, all arranged in cooperation with one another. The complex variable frequency digital IF signal can be used by a digital quadrature modulator for generation of the synthesized analog RF transmission signal, and optionally for use with an orthogonal frequency division multiplexing (OFDM) scheme. | 2009-01-01 |
20090002090 | Integrated Non-Reciprocal Component Comprising a Ferrite Substrate - The invention relates to a non-reciprocal component ( | 2009-01-01 |
20090002091 | ON DIE TERMINATION DEVICE THAT CAN CONTROL TERMINAL RESISTANCE - An on die termination controls a terminal resistance value in accordance with a test signal. The one die termination device comprises an on die termination control unit and an on die termination resistor unit and can change the terminal resistance value in accordance with the test signal, so that the terminal resistance can be easily analyzed. The one die termination control unit comprises a resistance control enable signal generating unit and a resistance control signal generating unit and generates at least one resistance increment signal and at least one resistance decrement signal. The on die termination resistor unit comprises a resistor and a plurality of switch units that are connected in parallel and is driven by a driving signal and uses the resistance increment signal and resistance decrement signal to control the on die termination resistance value. | 2009-01-01 |
20090002092 | Microwave Power Splitter/Combiner - A microwave, power splitter/combiner ( | 2009-01-01 |
20090002093 | COMPOSITE RIGHT/LEFT HANDED (CRLH) HYBRID-RING COUPLERS - High-frequency couplers and coupling techniques are described utilizing artificial composite right/left-handed transmission line (CRLH-TL). Three specific forms of couplers are described; (1) a coupled-line backward coupler is described with arbitrary tight/loose coupling and broad bandwidth; (2) a compact enhanced-bandwidth hybrid ring coupler is described with increased bandwidth and decreased size; and (3) a dual-band branch-line coupler that is not limited to a harmonic relation between the bands. These variations are preferably implemented in a microstrip fabrication process and may use lumped-element components. The couplers and coupling techniques are directed at increasing the utility while decreasing the size of high-frequency couplers, and are suitable for use with separate coupler or couplers integrated within integrated devices. | 2009-01-01 |
20090002094 | Power Line Coupling Device and Method - A power line coupler for communicating data signals over a power distribution system having a first and second overhead energized medium voltage power line conductors is provided. In one embodiment, the coupler includes a first lightening arrestor having a first end and a second end, wherein the first end of the first arrestor is connected to the first power line conductor. The coupler further includes a first high frequency impedance having a first end connected to the second end of the first lightening arrestor and the first impedance having a second end connected to a neutral conductor of the power line distribution system. The coupler may further include a second lightening arrestor having a first end and a second end, wherein the first end of the second arrestor is connected to the second power line conductor. The coupler further including a second high frequency impedance having a first end connected to the second end of the second lightening arrestor and a second end connected to the neutral conductor. The first high frequency impedance and the second high frequency impedance may each comprise an air core coil that forms an inductor. The coupler may further include a balun having a first winding and a second winding, wherein the first winding is coupled to a communication device, and wherein the second winding has a first end connected to the first end of the first high frequency impedance and a second end connected to the first end of the second high frequency impedance. | 2009-01-01 |
20090002095 | Antenna Branching Filter - In an antenna duplexer including a high band side filter, a low band side filter, and a phase shifter in a low pass configuration inserted between the high band side filter and an antenna port and taking phase matching of both filters, a resonance inductor resonating with a capacitor on the antenna port side is provided to obtain a attenuation characteristic in an optional band in an out-of-pass band of both filters by the resonance. For instance, the maximum attenuation is held at twice of the center frequency f | 2009-01-01 |
20090002096 | ANTENNA DUPLEXER, AND RF MODULE AND COMMUNICATION APPARATUS USING THE SAME - One of plurality of transmission terminals connected to a transmission filter and a receiving terminal connected to a receiving filter is a balanced type terminal, and another is an unbalanced type terminal. The transmission filter and the receiving filter includes surface acoustic wave resonators or film bulk acoustic resonators. The balanced type terminal is connected to a longitudinal mode coupled surface acoustic wave filter. | 2009-01-01 |
20090002097 | DUPLEXER - A duplexer includes a transmission filter having a ladder circuit configuration and a reception filter. The reception filter includes an input terminal connected to an antenna terminal, a first reception output terminal, and a second reception output terminal. A first filter element and a second filter element, each of which is a longitudinally coupled resonator filter element including a plurality of IDTs, are connected in parallel to the input terminal so that IDTs are connected to the input terminal. The first filter element the second filter element are connected to the first reception output terminal and the second reception output terminal, respectively. | 2009-01-01 |
20090002098 | Resonator Functioning with Acoustic Volume Waves - A resonator operating with bulk acoustic waves includes a resonator stack. The resonator stack includes a resonator area configured to allow propagation of an acoustic main mode and an acoustic secondary mode. The resonator stack also includes an acoustic mirror that includes a first partial mirror for locking in the acoustic main mode in the resonator area and a second partial mirror for locking in the secondary mode in a resonator space. | 2009-01-01 |
20090002099 | Elastic Wave Device - In an elastic wave device including an input side electrode and an output side electrode being a resonant single-phase unidirectional transducers (RSPUDT) provided with respective pairs of bus bars opposing to each other on a piezoelectric substrate and a number of excitation electrode fingers extending in a comb-teeth shape so as to respectively cross each other from the respective bus bars, the elastic waves are repeatedly reflected and amplified between the central part of the input side electrode and the central part of the output side electrode along the direction of extension of the respective bus bars by the excitation electrode fingers of the input side electrode and the output side excitation electrode, the elastic wave device includes a damper at least on either one of the input side bus bar or the output side bus bar in an area between the central part of the input side electrode in the direction of movement of the elastic waves and the central part of the output side electrode in the direction of movement of the elastic waves so that the energy leaked out into the bus bar is absorbed. | 2009-01-01 |
20090002100 | SYSTEM AND METHOD FOR TUNING MULTICAVITY FILTERS - The invention refers to a system and method to tune a multicavity filter of microwave signals, said filter comprising a filter body (CF), a removable lid (CO), n resonant cavities dug out in said filter body (CF) and n tuners (TU) susceptible of displacement under the action of movement means. Typically a sub-system to absorb the oscillations and vibrations generated in such displacements is associated to each tuner. | 2009-01-01 |
20090002101 | HIGH-PASS FILTER - A high frequency filter for filtering a frequency component from a high frequency signal includes a capacitor and a branch line. The capacitor may be disposed in series to a transmission line. The transmission line transmits the high frequency signal. The capacitor performs as capacitive component to the high frequency signal. The branch line may intersect the transmission line. The branch line may include, but is not limited to, a capacitive portion and an inductive portion. The capacitive portion performs as capacitive component to the high frequency signal. The inductive portion performs as inductive component to the high frequency signal. | 2009-01-01 |
20090002102 | ELECTRICAL FILTERS WITH IMPROVED INTERMODULATION DISTORTION - A method of constructing a band-stop filter comprises designing a band-stop filter including a signal transmission path, resonant elements disposed along the signal transmission path, and non-resonant elements coupling the resonant elements together to form a stopband having transmission zeroes corresponding to respective frequencies of the resonant elements. The method further comprises changing the order in which the resonant elements are disposed along the signal transmission path to create different filter solutions, computing a performance parameter for each filter solution, comparing the performance parameters to each other, selecting one of the filter solutions based on this comparison, and constructing the band-stop filter using the selected filter solution. Another RF band-stop filter comprises resonant elements coupled together to form a stopband, wherein at least two of the resonant elements have third order IMD components different from each other, such that the IMD components are asymmetrical about the stopband. | 2009-01-01 |
20090002103 | Tunable lambda/4 filter subassembly - The invention relates to a tunable λ/4-filter subassembly ( | 2009-01-01 |
20090002104 | VERTICAL COUPLING STRUCTURE FOR NON-ADJACENT RESONATORS - A vertical coupling structure for non-adjacent resonators is provided to have a first and a second resonators, a dielectric material layer, a first and a second high-frequency transmission lines and at least one via pole. The first and the second resonators respectively have a first and a second opposite metal surfaces. The dielectric material layer is disposed between the opposite second metal surfaces of the first and the second resonators. The first and the second transmission lines are respectively arranged at sides of the first metal surfaces of the first resonator and the second resonator. The first high-frequency transmission line is vertically connected to the second high-frequency transmission line by the via pole. | 2009-01-01 |
20090002105 | INTEGRATED SOLENOID AND IGNITION MAGNETIC SWITCH - A solenoid includes a solenoid housing defining a solenoid centerline; and an ignition magnetic switch including an ignition magnetic switch coil disposed at least partially within the housing, the ignition magnetic switch coil having a magnetic field that encompasses the solenoid centerline. | 2009-01-01 |