01st week of 2009 patent applcation highlights part 16 |
Patent application number | Title | Published |
20090001503 | SEMICONDUCTOR DEVICE HAVING FLOATING BODY ELEMENT AND BULK BODY ELEMENT AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a floating body element and a bulk body element and a manufacturing method thereof are provided. The semiconductor device includes a substrate having a bulk body element region and floating body element regions. An isolation region defining an active region of the bulk body element region of the substrate and defining first buried patterns and first active patterns, which are sequentially stacked on a first element region of the floating body element regions of the substrate is provided. A first buried dielectric layer interposed between the first buried patterns and the substrate and between the first buried patterns and the first active patterns is provided. | 2009-01-01 |
20090001504 | Method for Transferring Semiconductor Element, Method for Manufacturing Semiconductor Device, and Semiconductor Device - A transistor formed on a monocrystalline Si wafer is temporarily transferred onto a first temporary supporting substrate. The first temporarily supporting substrate is heat-treated at high heat so as to repair crystal defects generated in a transistor channel of the monocrystalline Si wafer when transferring the transistor. The transistor is then made into a chip and transferred onto a TFT substrate. In order to transfer the transistor which has been once separated from the monocrystalline Si wafer, a different method from a stripping method utilizing ion doping is employed. | 2009-01-01 |
20090001505 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING DEVICE ISOLATION FILM OF SEMICONDUCTOR DEVICE - A device isolation film in a semiconductor device and a method for forming the same are provided. The method includes etching a middle portion of a device isolation film having a deposition structure including a Spin-On-Dielectric (SOD) oxide film and a High Density Plasma (HDP) oxide film to form a hole and filling an upper portion of the hole with an oxide film having poor step coverage characteristics to form a second hole extending along the middle portion of the device isolation film. The second hole serves as a buffer for stress generated at the interface between an oxide film, which can be a device isolation film, and a silicon layer, which can be a semiconductor substrate, thereby increasing the operating current of a transistor and improving the electrical characteristics of the resulting device. | 2009-01-01 |
20090001506 | DUAL STRESS LINER EFUSE - A semiconductor fuse structure comprises an anode connected to a first end of a fuse link, a cathode connected to a second end of the fuse link opposite the first end of the fuse link, a compressive (nitride) liner covering the anode, and a tensile (nitride) liner covering the cathode. The compressive liner and the tensile liner are positioned to cause a net stress gradient between the cathode and the anode, wherein the net stress gradient promotes electromigration from the cathode and the fuse link to the anode. | 2009-01-01 |
20090001507 | SEMICONDUCTOR DEVICE - A semiconductor device that includes a metal fuse which may be used for redundancy or trimming, allowing for adjustment in the characteristics of a circuit. The fuse includes a disconnecting metal, a plurality of metal-vias that are connected under respective ends of the disconnecting metal, and a plurality of interconnections that connect to the disconnecting metal through respective metal-vias. The disconnecting metal is disconnected by a laser exposure and the metal-vias are located inside of the spot diameter of the laser used for the laser exposure, and are spaced apart from a side surface of the disconnecting metal. The disconnecting metal is formed of a material having a melting point and a boiling point that is lower than the melting point and boiling point of the metal-vias. | 2009-01-01 |
20090001508 | Semiconductor device including fuse elements and bonding pad - A semiconductor device includes a lower-layer substrate, a fuse above the lower-layer substrate and blown by radiation with light, a silicon oxide film on the fuse and on an exposed portion of the surface of the lower-layer substrate, and a silicon nitride film on the silicon oxide film. The portion of the silicon oxide film on the surface of the lower-layer substrate is thicker than the fuse, and the silicon oxide film has an opening opposite the fuse. | 2009-01-01 |
20090001509 | CIRCUIT SYSTEM WITH CIRCUIT ELEMENT - A circuit system includes: forming a first electrode over a substrate; applying a dielectric layer over the first electrode and the substrate; forming a second electrode over the dielectric layer; and forming a dielectric structure from the dielectric layer with the dielectric structure within a first horizontal boundary of the first electrode. | 2009-01-01 |
20090001510 | AIR GAP IN INTEGRATED CIRCUIT INDUCTOR FABRICATION - In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via. | 2009-01-01 |
20090001511 | High performance system-on-chip using post passivation process - The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface. | 2009-01-01 |
20090001512 | Providing a moat capacitance - In one embodiment, the present invention includes an apparatus having core logic formed on a die, input/output (IO) buffers surrounding the core logic, and a moat capacitance surrounding the IO buffers and extending to an edge of the die. Other embodiments are described and claimed. | 2009-01-01 |
20090001513 | Semiconductor structure - The present invention discloses a structure of a buried word line, which comprises a semiconductor substrate having a U-shape trench, a U-shape gate dielectric layer in the U-shape trench, a polysilicon layer on the U-shape gate dielectric layer, a conducting layer on the polysilicon layer, and a cover dielectric layer on the conducting layer. The semiconductor structure may have a minimized size and when recess channels are formed thereby, the integration is accordingly improved without suffering from the short channel effect. | 2009-01-01 |
20090001514 | METAL INSULATOR METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A metal-insulator-metal (MIM) capacitor may include a lower metal layer including a lower metal layer including a first lower metal layer and a second lower metal layer formed on a semiconductor substrate, an upper metal layer including a first upper metal layer and a second upper metal layer formed on the lower metal layer, a capacitor dielectric layer formed between the lower metal layer and the upper metal layer, a first bonding metal layer formed on the upper metal layer and a second bonding metal layer formed on the lower metal layer, a first connection wiring formed between the upper metal layer and the first bonding metal layer for directly connect the upper metal layer to the first bonding metal layer, and a second connection wiring formed between the lower metal layer and the second bonding metal layer for directly connecting the lower metal layer to the second bonding metal layer. | 2009-01-01 |
20090001515 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device includes a capacitor | 2009-01-01 |
20090001516 | Semiconductor device and method of fabricating the same - A method of fabricating a semiconductor device includes forming an interlayer insulating pattern over a semiconductor substrate. The interlayer insulating pattern defines a plurality of storage node regions. A lining conductive film is formed over the interlayer insulating pattern including the storage node region. A capping insulating film is formed over the lining conductive film. The capping insulating film over the interlayer insulating film and the lining conductive film are selectively etched between two neighboring storage node regions to form a recess exposing the interlayer insulating pattern on the bottom of the recess and the lining conductive film on sidewalls of the recess. The capping insulating film and the lining conductive film is shaped to be planar so that the lining conductive layer is electrically separated from each other to form a respective lower storage electrode. A supporting pattern is formed to fill the recess. The capping insulating film and the interlayer insulating pattern are removed to expose the lower storage node. | 2009-01-01 |
20090001517 | THERMALLY ENHANCED SEMICONDUCTOR DEVICES - One embodiment relates to a circuit. In this circuit, a first semiconductor device with a first geometry is associated with a first region of a semiconductor body within a first isolation structure. A second semiconductor device with a geometry that matches the first geometry is associated with a second region of the semiconductor body within a second isolation structure. A member, which spans the semiconductor body between the first region and the second region, thermally couples the first region to the second region while retaining electrical isolation therebetween. Other circuits and methods are also disclosed. | 2009-01-01 |
20090001518 | Varactor - A varactor comprising a first layer separated from a second layer by an insulating layer, wherein the first layer is a first type of semiconductor material and the second layer is a second type of semiconductor material and the insulation layer is arranged to allow an accumulation region to be formed in the first layer and second layer when a positive bias is applied to the first layer and the second layer and a depletion region to be formed in the first layer and second layer when a negative bias is applied to the first layer and the second layer. | 2009-01-01 |
20090001519 | GROWTH OF PLANAR, NON-POLAR, GROUP-III NITRIDE FILMS - Growth methods for planar, non-polar, Group-III nitride films are described. The resulting films are suitable for subsequent device regrowth by a variety of growth techniques. | 2009-01-01 |
20090001520 | THINNED WAFER HAVING STRESS DISPERSION PARTS AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME - A thinned wafer having stress dispersion parts that make the wafer resistant to warpage and a method for manufacturing a semiconductor package using the same is described. The wafer includes a wafer body having a semiconductor chip forming zone and a peripheral zone located around the semiconductor chip forming zone; and the stress dispersion parts are located in the peripheral zone so as to disperse stress induced in the peripheral zone and the semiconductor chip forming zone. | 2009-01-01 |
20090001521 | Semiconductor wafer - A semiconductor wafer includes an insulation substrate with transparency; a silicon semiconductor layer formed on the insulation substrate; a chip forming area defined on the silicon semiconductor layer; a scribe line area defined on the silicon semiconductor layer for dividing the chip forming area; and an opaque pattern layer formed in the scribe line area. A plurality of opaque pattern portions is arranged apart from each other in the opaque pattern layer. | 2009-01-01 |
20090001522 | DIE SEAL RING AND WAFER HAVING THE SAME - A die seal ring disposed in a die and surrounding an integrated circuit region of the die is described. The die seal ring has at least two different local widths. | 2009-01-01 |
20090001523 | Systems and Methods for Processing a Film, and Thin Films - In some embodiments, a method of processing a film is provided, the method comprising defining a plurality of spaced-apart regions to be pre-crystallized within the film, the film being disposed on a substrate and capable of laser-induced melting; generating a laser beam having a fluence that is selected to form a mixture of solid and liquid in the film and where a fraction of the film is molten throughout its thickness in an irradiated region; positioning the film relative to the laser beam in preparation for at least partially pre-crystallizing a first region of said plurality of spaced-apart regions; directing the laser beam onto a moving at least partially reflective optical element in the path of the laser beam, the moving optical element redirecting the beam so as to scan a first portion of the first region with the beam in a first direction at a first velocity, wherein the first velocity is selected such that the beam irradiates and forms the mixture of solid and liquid in the first portion of the first region, wherein said first portion of the first region upon cooling forms crystalline grains having predominantly the same crystallographic orientation in at least a single direction; and crystallizing at least the first portion of the first region using laser-induced melting. | 2009-01-01 |
20090001524 | GENERATION AND DISTRIBUTION OF A FLUORINE GAS - Molecular fluorine may be generated and distributed on-site at a fabrication facility. A molecular fluorine generator may come in a variety of sizes to fit better the needs of the particular fabrication facility. The generator may service one process tool, a plurality of process tool along a process bay, the entire fabrication facility, or nearly any other configuration within the facility. The process can obviate the need and inherent risks with transporting or handling gas cylinders. The process can be used in conjunction with a cleaning or fabrication operation used in the electronics fabrication industry. | 2009-01-01 |
20090001525 | HIGH-K DUAL DIELECTRIC STACK - The present invention discloses a method including: providing a Group III-V component semiconductor material; forming a first layer over a surface of the Group III-V component semiconductor material, the first layer to unpin a Fermi level at the surface; forming a second layer over the first layer, the second layer for scaling an equivalent oxide thickness (EOT); and annealing the first layer before or after forming the second layer to remove bulk trap defects in the first layer. | 2009-01-01 |
20090001526 | TECHNIQUE FOR FORMING AN INTERLAYER DIELECTRIC MATERIAL OF INCREASED RELIABILITY ABOVE A STRUCTURE INCLUDING CLOSELY SPACED LINES - By removing excess material of an interlayer dielectric material deposited by SACVD, the gap filling capabilities of this deposition technique may be exploited, while, on the other hand, negative effects of this material may be reduced. In other aspects, a buffer material, such as silicon dioxide, may be formed prior to depositing the interlayer dielectric material on the basis of SACVD, thereby creating enhanced uniformity during the deposition process when depositing the interlayer dielectric material on dielectric layers having different high intrinsic stress levels. Consequently, the reliability of the interlayer dielectric material may be enhanced while nevertheless maintaining the advantages provided by an SACVD deposition. | 2009-01-01 |
20090001527 | Series-shunt switch with thermal terminal - A series-shunt switch is provided. The switch includes a PIN diode having an input electrical terminal, an output electrical terminal and a thermal terminal. The thermal terminal is configured to provide continuity of diode thermal ground with respect to a circuit thermal ground node. | 2009-01-01 |
20090001528 | Lowering resistance in a coreless package - In one embodiment, the present invention includes a coreless substrate to provide a power net connection and a ground net connection to a semiconductor die, which is electrically coupled to the substrate, and a stiffener surrounding the semiconductor die and electrically coupled to the substrate to provide a lateral current path to the semiconductor die. Other embodiments are described and claimed. | 2009-01-01 |
20090001529 | PACKAGE STACKING USING UNBALANCED MOLDED TSOP - A semiconductor package assembly is disclosed including a pair of stacked leadframe-based semiconductor packages. The first package is encapsulated in a mold compound so that the electrical leads emanate from the sides of the package, near a bottom surface of the package. The first package may be stacked atop the second package by aligning the exposed leads of the first package with the exposed leads of the second package and affixing the respective leads of the two packages together. The vertical offset of leads toward a bottom of the first package provides a greater overlap with leads of the second package, thus allowing a secure bonding of the leads of the respective packages. | 2009-01-01 |
20090001530 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lead frame including inner lead portion having inner leads connected to outer leads and relay inner leads not connected to the outer leads. A semiconductor element is mounted on a lower surface of the lead frame. Electrode pads of the semiconductor element are connected to the inner lead portion via metal wire. One end of the relay inner lead is connected to the electrode pad via the metal wire, and the other end is connected to the outer lead via a relay metal wire disposed to step over the inner lead. | 2009-01-01 |
20090001531 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRAL INNER LEAD AND PADDLE - An integrated circuit package system includes: fabricating a lead frame including: providing inner leads having an inner lead pitch of progressive length, forming a lead shoulder, on the inner leads, having a shoulder height of a progressive height, and forming outer leads coupled to the lead shoulder and the inner leads; mounting an integrated circuit die on the lead frame; and molding a package body on the lead frame and the integrated circuit die. | 2009-01-01 |
20090001532 | Plastic-Encapsulated Semiconductor Device with an Exposed Radiator at the Top and Manufacture Thereof - A plastic-encapsulated semiconductor device is provided which comprises a plastic-encapsulant | 2009-01-01 |
20090001533 | MULTI-CHIP PACKAGING IN A TSOP PACKAGE - A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include a leadframe having one or more semiconductor die and one or more passive components affixed thereon. The one or more passive components may be affixed by soldering with a solder material. In embodiments, in order to prevent bleeding of the solder material during a solder reflow process, barricades are formed on the surface of the leadframe, at least partially surrounding the one or more passive components. | 2009-01-01 |
20090001534 | TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe. | 2009-01-01 |
20090001535 | Semiconductor Module for a Switched-Mode Power Supply and Method for Its Assembly - Semiconductor module for a Switched-Mode Power Supply comprises at least one semiconductor power switch, a control semiconductor chip and a leadframe comprising a die pad and a plurality of leads disposed on one side of the die pad. The die pad comprises at least two mechanically isolated regions wherein the semiconductor power switch is mounted on a first region of the die pad and the control semiconductor chip is mounted on a second region of the die pad. Plastic housing material electrically isolates the first region and the second region of the die pad and electrically isolates the semiconductor power switch from the control semiconductor chip. | 2009-01-01 |
20090001536 | Electronic Component and a Method of Fabricating an Electronic Component - An electronic component includes a lead frame assembly, an insert, a semiconductor chip and an encapsulation compound. The lead frame assembly includes a mounting hole, a die pad, a plurality of bonding fingers and a plurality of lead fingers. The insert includes a hollow center and is provided at the mounting hole of the lead frame assembly. The semiconductor chip is arranged on the die pad and includes contact areas on its surface. A plurality of electrical contacts respectively links the contact areas of the semiconductor chip to the bonding fingers of the lead frame assembly. An encapsulating compound encloses the insert, the semiconductor chip, and the electrical contacts, however, leaves the hollow center of the insert uncovered. | 2009-01-01 |
20090001537 | Gettering material for encapsulated microdevices and method of manufacture - A method for providing improved gettering in a vacuum encapsulated microdevice is described. The method includes designing a getter alloy to more closely approximate the coefficient of thermal expansion of a substrate upon which the getter alloy is deposited. Such a getter alloy may have a weight percentage of less than about 8% iron (Fe) and greater than about 50% zirconium, with the balance being vanadium and titanium, which may better match the coefficient of thermal expansion of a silicon substrate. In one exemplary embodiment, the improved getter alloy is deposited on a silicon substrate prepared with a plurality of indentation features, which increase the surface area of the substrate exposed to the vacuum. Such a getter alloy is less likely to delaminate from the indented surface of the substrate material during heat-activated steps, such as activating the getter material and bonding a lid wafer to the device wafer supporting the microdevice. | 2009-01-01 |
20090001538 | PRINTED WIRING BOARD STRUCTURE, ELECTRONIC COMPONENT MOUNTING METHOD AND ELECTRONIC APPARATUS - According to one embodiment, a printed wiring board structure comprises a printed wiring board having first and second component mounting surfaces at front and back sides thereof, respectively, each for mounting a semiconductor package loading a semiconductor chip loaded on a substrate as a mounting component, a first semiconductor package mounted on the first component mounting surface, and a second semiconductor package mounted on the second component mounting surface, wherein the first and second semiconductor packages have a positional relationship such that the substrates are partially overlapped via the printed wiring board, and the semiconductor chips are not overlapped. | 2009-01-01 |
20090001539 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH TOP AND BOTTOM TERMINALS - An integrated circuit package system includes a die pad with leads; attaching an integrated circuit over the die pad; attaching a connector to the integrated circuit and the leads; and forming an encapsulant, over the integrated circuit, having a connection cavity over the leads leaving an exposed portion of the leads. | 2009-01-01 |
20090001540 | Stackable Package by Using Internal Stacking Modules - A semiconductor package has a substrate with solder balls. A first semiconductor die is disposed on the substrate. A first double side mold (DSM) internal stackable module (ISM) is in physical contact with the first semiconductor die through a first adhesive, such as a film on wire adhesive. A second DSM ISM is in physical contact with the first DSM ISM through a second adhesive. The arrangement of the first and second DSM ISM reduce headroom requirements for the package and increase device packing density. Each DSM ISM has semiconductor die disposed in cavities. An interposer is disposed above the top DSM ISM. Wire bonds connect the semiconductor die and DSM ISMs to the solder balls. An encapsulant surrounds the first semiconductor die and first DSM ISM with an exposed mold area in the encapsulant above the interposer. | 2009-01-01 |
20090001541 | Method and apparatus for stackable modular integrated circuits - Systems and methods for vertically stacking integrated circuit (IC) modules on a motherboard to conserve motherboard space and reduce power consumption are disclosed. IC modules can comprise processor circuitry, memory elements, communication circuitry, etc. Pins on each IC module can be directly inserted into lower IC module or into a socket layer that couples the IC modules. Heat generated by the IC modules can be dissipated by inserting heat dissipation layers into the vertical stack, between IC modules, or by placing a heat-dissipating sleeve around the stack. The IC modules themselves and/or heat-generating regions therein may be misaligned on their respective socket layers to further facilitate dissipating heat. Module stacks are scalable in that a user may add memory and/or processor modules as desired to increase device capability. | 2009-01-01 |
20090001542 | SEMICONDUCTOR PACKAGE AND MULTI-CHIP SEMICONDUCTOR PACKAGE USING THE SAME - Disclosed is a semiconductor package and a multi-chip semiconductor package. The semiconductor package includes a semiconductor chip having bonding pads located at a center portion thereof; redistribution patterns extending from the bonding pads toward one edge of the semiconductor chip; and dummy bump pads located adjacent to another edge of the semiconductor chip which is opposite the one edge. | 2009-01-01 |
20090001543 | LIGHTWEIGHT AND COMPACT THROUGH-SILICON VIA STACK PACKAGE WITH EXCELLENT ELECTRICAL CONNECTIONS AND METHOD FOR MANUFACTURING THE SAME - A through-silicon via stack package contains package units. Each package unit includes a semiconductor chip; a through-silicon via formed in the semiconductor chip; a first metal line formed on an upper surface and contacting a portion of a top surface of the through-silicon via; and a second metal line formed on a lower surface of the semiconductor chip and contacting a second portion of a lower surface of the through-silicon via. When package units are stacked, the second metal line formed on the lower surface of the top package unit and the first metal line formed on the upper surface of the bottom package unit are brought into contact with the upper surface of the through-silicon via of the bottom package unit and the lower surface of the through-silicon via of the top package unit, respectively. The stack package is lightweight and compact, and can form excellent electrical connections. | 2009-01-01 |
20090001544 | CHIP STACKED STRUCTURE AND METHOD OF FABRICATING THE SAME - A chip stacked structure and a method of fabrication the same that may include a first chip having first semiconductor devices and a first connection pad electrically connected to the first semiconductor devices, a second chip stacked on the first chip, the second chip having second semiconductor devices and a second connection pad electrically connected to the second semiconductor devices, and a connection member interposed between the first connection pad and the second connection pad to electrically connect the first connection pad and the second connection pad. The connection member has lower electric resistance than when the chips are unstacked, and thus, offers high reliability and performance. | 2009-01-01 |
20090001545 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SIDE SUBSTRATE - An integrated circuit package system comprising: providing a package substrate; attaching an integrated circuit over the package substrate; and attaching a side substrate adjacent the integrated circuit over the package substrate. | 2009-01-01 |
20090001546 | Ultra-thick thick film on ceramic substrate - An electrically isolated and thermally conductive double-sided pre-packaged integrated circuit component exhibiting excellent heat dissipative properties, durability and strength, and which can be manufactured at a low cost includes electrically insulated and thermally conductive substrate members having outer surfaces, ultra-thick thick film materials secured to the outer surfaces of the substrate members and a lead member and a transistor member positioned between the substrate members. | 2009-01-01 |
20090001547 | High-Density Fine Line Structure And Method Of Manufacturing The Same - A high-density fine line structure mainly includes: two packaged semiconductor devices installed on a circuit layer and a power/ground layer formed therebetween, to realize the objective of high-density and ground connection. On an outer circuit, the part, which is not covered by a solder mask, can be made into a pad for electrically connecting with one of the semiconductor devices. The other semiconductor device may be installed on the fine line circuit layer. The fine line circuit layer, which is exposed, is to be a tin ball pad where a tin ball is filled. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density. | 2009-01-01 |
20090001548 | Semiconductor package - A semiconductor package which includes: a semiconductor chip which includes a signal terminal for inputting and outputting electrical signals and a ground terminal; and a package substrate which includes a semiconductor chip mounting surface on which the semiconductor chip is mounted, and a terminal electrode forming surface on which a signal terminal electrode electrically connected to the signal terminal and a ground terminal electrode electrically connected to the ground terminal are arranged in an array pattern, wherein: on the semiconductor chip mounting surface, there is provided a first signal wiring connected to the signal terminal, a ground wiring connected to the ground terminal, and a ground conductive layer connected to the ground wiring and is provided in a planar pattern in an area excluding the forming area of the first signal wiring; on the terminal electrode forming surface, there is provided a second signal wiring connected to the signal terminal electrode, and a ground fine wiring connected to the ground terminal electrode; and the first signal wiring and the second signal wiring are connected via a conductor filled in a signal through hole penetrating the package substrate, and the ground conductive layer and the ground fine wiring are connected via a conductor filled in a ground through hole penetrating the package substrate. | 2009-01-01 |
20090001549 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SYMMETRIC PACKAGING - An integrated circuit package system comprising: providing a substrate having a first substrate surface and a second substrate surface; forming a first package connector and a second package connector over substantially opposite locations of the first substrate surface and the second substrate surface; and attaching a first integrated circuit and a second integrated circuit adjacent the first package connector over the first substrate surface and the second package connector over the second substrate surface. | 2009-01-01 |
20090001550 | Method of Forming a Multilayer Substrate Core Structure Using Sequential Microvia Laser Drilling And Substrate Core Structure Formed According to the Method - A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof. | 2009-01-01 |
20090001551 | NOVEL BUILD-UP-PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME - A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body. | 2009-01-01 |
20090001552 | SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES FOR MOLDING BACK SIDE OF PACKAGE - A portable memory card and methods of manufacturing same are disclosed. The portable memory includes a substrate having a plurality of holes formed therein. During the encapsulation process, mold compound flows over the top surface of the substrate, through the holes, and down into a recessed section formed in the bottom mold cap plate to form a projection of mold compound on the bottom surface of the substrate. | 2009-01-01 |
20090001553 | Mems Package and Method for the Production Thereof - A micro electro-mechanical systems (MEMS) package is described herein. The package includes a carrier substrate having a top side, a MEMS chip mounted on the top side of the carrier substrate, and at least one chip component on or above the top side of the carrier substrate or embedded in the carrier substrate. The package also includes a thin metallic shielding layer covering the MEMS chip and the chip component and forming a seal with the top side of the carrier substrate. | 2009-01-01 |
20090001554 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer arranged over the carrier and a first semiconductor chip arranged over the electrically insulating layer, wherein the first semiconductor chip has a first contact element on a first surface and a second contact element on a second surface. | 2009-01-01 |
20090001555 | SEMICONDUCTOR DEVICE HAVING METAL CAP - In order to reduce a thermal stress applied by a metal cap to a semiconductor chip: a semiconductor chip ( | 2009-01-01 |
20090001556 | LOW TEMPERATURE THERMAL INTERFACE MATERIALS - A method may provide thermal interface material. The method comprises providing a first coating layer on a top side of a base metal layer and a second coating layer on a bottom side of the base metal layer, wherein the coating layer has a melting point lower than a melting point of the base metal layer; attaching the base metal layer to a die and a heat spreader; and melting the first coating layer and the second coating layer to bond to the die and the heat spreader. | 2009-01-01 |
20090001557 | Forming a semiconductor package including a thermal interface material - In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed. | 2009-01-01 |
20090001558 | Lamp Seat for a Light Emitting Diode and Capable of Heat Dissipation, and Method of Manufacturing the Same - A lamp seat includes a metal substrate having opposite first and second surfaces, first and second conductive patterns formed on the first surface, and third and fourth conductive patterns formed on the second surface and connected respectively and integrally to the first and second conductive patterns. A heat-conductive first insulating layer is disposed between the metal substrate and each of the first, second, third and fourth conductive patterns. A heat-conductive second insulating layer is formed over the first insulating layer such that corresponding parts of the first and second conductive patterns are exposed outwardly of the second insulating layer for electrical connection with positive and negative electrodes of a light emitting diode, respectively. | 2009-01-01 |
20090001559 | Semiconductor device, a method of manufacturing the same and an electronic device - A novel semiconductor device high in both heat dissipating property and connection reliability in mounting is to be provided. The semiconductor device comprises a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member. | 2009-01-01 |
20090001560 | Embedded Heat Pipe In A Hybrid Cooling System - One embodiment of a system for cooling a heat-generating device includes a base adapted to be coupled to the heat-generating device, a housing coupled to the base, a liquid channel formed between the base and the housing, where a heat transfer liquid may be circulated through the liquid channel to remove heat generated by the heat-generated device, and a heat pipe disposed within the liquid channel, where the heat pipe increases the heat transfer surface area to which the heat transfer liquid is exposed. Among other things, the heat pipe advantageously increases the heat transfer surface area to which the heat transfer liquid is exposed and efficiently spreads the heat generated by the heat-generating device over that heat transfer surface area. The result is enhanced heat transfer through the liquid channel relative to prior art cooling systems. | 2009-01-01 |
20090001561 | High Thermal Performance Packaging for Circuit Dies - A circuit die is disposed into a region defined by a mold. A molding material is then introduced into the region to encapsulate the circuit die. Prior to substantial curing of the molding material, at least a portion of the molding material is removed from over a surface of the circuit die, creating a recessed region in the encapsulating material. A heat spreader may then be disposed within the recessed region, as well as over the top surface of the encapsulating material. The heat spreader may have a downset that substantially aligns with the recessed region and reduces the distance between the heat spreader and the spacer for better heat dissipation. | 2009-01-01 |
20090001562 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides a module including a first carrier having a first mounting surface and a second mounting surface, a first semiconductor chip mounted onto the first mounting surface of the first carrier and having a first surface facing away from the first carrier, a first connection element connected to the first surface of the first semiconductor chip, a second semiconductor chip having a first surface facing away from the first carrier, a second connection element connected to the first surface of the second semiconductor chip, and a mold material covering the first connection element and the second connection element only partially. | 2009-01-01 |
20090001563 | INTEGRATED CIRCUIT PACKAGE IN PACKAGE SYSTEM WITH ADHESIVELESS PACKAGE ATTACH - An integrated circuit package in package system includes a package in package lead with a package in package lead surface substantially planar, attaching a first integrated circuit package having a first encapsulant surface substantially coplanar with the package in package lead surface, attaching a second integrated circuit near the first integrated circuit package, and forming a package in package encapsulant over the first integrated circuit package and the second integrated circuit. | 2009-01-01 |
20090001564 | PACKAGE SUBSTRATE DYNAMIC PRESSURE STRUCTURE - Devices and methods for their formation, including electronic assemblies having a shape memory material structure, are described. In one embodiment, a device includes a package substrate and an electronic component coupled to the package substrate. The device also includes a shape memory material structure coupled to the package substrate. In one aspect of certain embodiments, the shape memory material structure is formed from a material selected to have a martensite to austenite transition temperature in the range of 50-300 degrees Celsius. In another aspect of certain embodiments, the shape memory material structure is positioned to extend around a periphery of the electronic component. Other embodiments are described and claimed. | 2009-01-01 |
20090001565 | MEMS DEVICE FORMED INSIDE HERMETIC CHAMBER HAVING GETTER FILM - A MEMS device including a getter film formed inside a hermetic chamber provides stable performance of the MEMS device by electrically stabilizing the getter film. | 2009-01-01 |
20090001566 | Semiconductor Device Having Improved Gate Electrode Placement and Decreased Area Design - In one aspect provides a semiconductor device that includes gate electrodes having ends that overlap isolation regions, wherein each gate electrode] is located over an active region located within a semiconductor substrate. A gate oxide is located between each of the gate electrodes and the active region, and source/drains are located adjacent each of the gate electrodes and within the active region. An etch stop layer is located over each of the gate electrodes and each of the gate electrodes has at least one electrical contact that extends through the etch stop layer and contacts a portion of the gate electrode that overlies the active region. | 2009-01-01 |
20090001567 | IC chip with finger-like bumps - A bumped chip has a plurality of finger-like bumps bonded on multiple openings of a chip. The chip primarily comprises a plurality of bonding pads and a passivation layer having a plurality of opening thereon. In one embodiment, the openings on each bonding pad are plural and disposed in linear, in parallel, or in an array. The finger-like bumps are protrusively disposed on the chip and each has a bump core and an extension finger. The bump cores are disposed within the corresponding bonding pads and cover the openings, and the extension fingers are disposed outside the corresponding bonding pads to maintain the bonding strengths of the bumps even at fine pitches. In an embodiment, the extension fingers overlap at least a trace of the chip. | 2009-01-01 |
20090001568 | Wafer-level solder bumps - In one embodiment, the present invention includes a semiconductor package having a support substrate coupled to a first semiconductor die, where the first semiconductor die includes first conductive bumps, and a second semiconductor die includes second conductive bumps, and where the first and second die are coupled by joints formed of the first and second conductive bumps and a solder material therebetween. Other embodiments are described and claimed. | 2009-01-01 |
20090001569 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor chip is characterized by a structure including a semiconductor chip on which electrode pads are formed, bumps which are formed on the respective electrode pads and which have projection sections, an insulating layer formed on the semiconductor chip, and a conductive pattern to be connected to the bumps, wherein extremities of the projection sections are inserted into the conductive pattern and the inserted extremities are flattened. | 2009-01-01 |
20090001570 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - The present disclosure relates to a method of manufacturing an electronic device in which a plurality of first bumps serving as external connection terminals are formed on a conductive pattern. The method includes: (a) forming a second bump having a projection portion on an electrode pad formed on a substrate; (b) forming an insulating layer on the substrate; (c) exposing a portion of the projection portion from an upper surface of the insulating layer; (d) forming a flat stress absorbing layer in a bump providing area, in which the first bumps are provided, on the insulating layer; (e) forming a first conductive layer on the insulating layer and the stress absorbing layer and the exposed portion of the projection portion; (f) forming a second conductive layer by an electroplating using the first conductive layer as a power feeding layer; (g) forming the conductive pattern by patterning the second conductive layer; and (h) forming the first bumps on the conductive pattern formed on the stress absorbing layer. | 2009-01-01 |
20090001571 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device in which a semiconductor element | 2009-01-01 |
20090001572 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of the present invention includes a chip which has a pad; a bump electrode formed on the pad; and a wire whose stitch bonding is made on the bump electrode. The wire satisfies a condition: (modulus-of-elasticity/breaking strength per unit area)≧400. | 2009-01-01 |
20090001573 | Structure and method for wire bond integrity check on BGA substrates using indirect electrical interconnectivity pathway between wire bonds and ground - An invention providing improvement in integrity testing of wire bonds between an IC die and a BGA substrate. | 2009-01-01 |
20090001574 | Multi-chips Stacked package structure - A multi-chips Stacked package structure, wherein a plurality of chips are stacked on the substrate with a rotation so that a plurality of metallic ends and the metal pad on each chip on the substrate can all be exposed; a plurality of metal wires are provided for electrically connecting the plurality of metal pads on the plurality of chips with the plurality metallic ends on the substrate in one wire bonding process; then an encapsulate is provided for covering the plurality of stacked chips, a plurality of metal wires and the plurality of metallic ends on the substrate. | 2009-01-01 |
20090001575 | Printed Circuit Board, Mounting Method of Electronic Component, and Electronic Apparatus - According to one embodiment, there is provided a printed circuit board includes a printed wiring board having a component mounting surface, a semiconductor package which is mounted on the component mounting surface of the printed wiring board by solder bonding using solder balls, and reinforcement portions which locally reinforce portions of the solder bonding of the semiconductor package at a plurality of locations on the component mounting surface of the printed wiring board, the reinforcement portions being formed of a resin material having parts entering the solder balls of the portions of the solder bonding. | 2009-01-01 |
20090001576 | INTERCONNECT USING LIQUID METAL - A semiconductor package comprises a substrate that has a first protruding interconnect and a semiconductor die that has a second protruding interconnect that faces the first protruding interconnect. The package further comprises a spacer provided between the substrate and the die, wherein the spacer comprises a hole filled with liquid metal to couple the first protruding interconnect to the second protruding interconnect. | 2009-01-01 |
20090001577 | METAL LINE OF SEMICONDUCTOR DEVICE WITH A TRIPLE LAYER DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME - A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region and a metal line is formed to fill the metal line forming region of the insulation layer. The diffusion barrier is formed between the metal line and the insulation layer. The diffusion barrier has a structure in which a TaSi | 2009-01-01 |
20090001578 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER WITH AN AMORPHOUS TaBN LAYER AND METHOD FOR FORMING THE SAME - A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A metal line is formed to fill the metal line forming region of the insulation layer. And a diffusion barrier that includes an amorphous TaBN layer is formed between the metal line and the insulation layer. The amorphous TaBN layer prevents a copper component from diffusing into the semiconductor substrate, thereby improving upon the characteristics and the reliability of a device. | 2009-01-01 |
20090001579 | MULTI-LAYERED METAL LINE HAVING AN IMPROVED DIFFUSION BARRIER OF A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A multi-layered metal line of a semiconductor device and a process of forming the same are described. The multi-layered metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is subsequently formed on the semiconductor substrate including the lower metal line and has an upper metal line forming region that exposes a portion of the lower metal line. A diffusion barrier formed on a surface of the upper metal line forming region of the insulation layer. The diffusion barrier includes a W—B—N ternary layer. An upper metal line is finally formed on the diffusion barrier to fill the upper metal line forming region of the insulation layer. | 2009-01-01 |
20090001580 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER INCLUDING CRxBy AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device having a diffusion barrier including Cr | 2009-01-01 |
20090001581 | METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A metal line of a semiconductor device includes an insulating layer in which damascene patterns have been formed, a first metal layer formed on sidewalls and bottom surfaces of the damascene patterns, a second metal layer formed on the first metal layer within the damascene patterns and having a lower resistance than the first metal layer, and a third metal layer formed on the second metal layer. | 2009-01-01 |
20090001582 | SEMICONDUCTOR DEVICE WITH METAL GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate, a gate dielectric layer over the substrate, a silicon electrode over the gate dielectric layer, wherein the silicon electrode comprises a damascene pattern, a diffusion barrier layer on a bottom and a sidewall of the damascene pattern, and a metal electrode over the diffusion barrier layer, wherein the metal electrode fills the damascene pattern. | 2009-01-01 |
20090001583 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention relates to a semiconductor device and a method of fabricating the same. In an embodiment of the present invention, an insulating layer in which contact holes are formed is formed over a semiconductor substrate in which lower metal lines are formed. A barrier metal layer, having a stack structure of a first tungsten (W) layer and a tungsten nitride (WN) layer, is formed within the contact holes. Contact plugs are formed within the contact holes. | 2009-01-01 |
20090001584 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method of fabricating a semiconductor device that may include at least one of the following steps: Forming a lower metal wiring on and/or over a semiconductor substrate. Forming an interlayer insulating film having a damascene hole on and/or over the semiconductor substrate and the lower metal wiring. Forming an anti-diffusion film on and/or over the exposed lower metal wiring below the damascene hole and/or on side surfaces of the damascene hole. Selectively removing the anti-diffusion film formed on and/or over the exposed lower metal wiring at the bottom of the damascene hole using a plasma process that uses an inert gas. | 2009-01-01 |
20090001585 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory that can include forming a titanium nitride (TiN) layer on the pre-metal dielectric having the via hole and then forming a TiSiN layer by injecting silane (SiH | 2009-01-01 |
20090001586 | INTEGRATED CIRCUIT AND SEED LAYERS - Structures are provided that include a conducting layer disposed on a layered arrangement of a diffusion barrier layer and a seed layer in an integrated circuit. Apparatus and systems having such structures and methods of forming these structures for apparatus and systems are disclosed. | 2009-01-01 |
20090001587 | Ta-TaN SELECTIVE REMOVAL PROCESS FOR INTEGRATED DEVICE FABRICATION - Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor. | 2009-01-01 |
20090001588 | Metal and alloy silicides on a single silicon wafer - Methods and apparatus relating to a single silicon wafer having metal and alloy silicides are described. In one embodiment, two different silicides may be provided on the same wafer. Other embodiments are also disclosed. | 2009-01-01 |
20090001589 | NOR FLASH DEVICE AND METHOD FOR FABRICATING THE DEVICE - An NOR flash memory device having a back end of line (BEOL) structure, the BEOL structure including a substrate having a conductive region, a first intermetal dielectric layer formed on the substrate, a first metal line formed on the conductive region, a second intermetal dielectric layer formed on the first metal line and the first inter metal dielectric, a first contact extending through the second intermetal dielectric layer, and a second metal line connected to the first metal line through the first contact. At least one of the first contact and the first and second metal lines is composed of copper and at least one of the first and second intermetal dielectric layers is composed of a low diectrice material. The use of copper metal lines and intermetal dielectric layers composed of a low-k (k=3.0) material makes it possible to improve 40% or more in the time constant delay. | 2009-01-01 |
20090001590 | WIRING STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A wiring structure includes a first wiring, a first interlayer dielectric film having a first opening, a second wiring formed with a first recess portion on a region corresponding to the first opening, a second interlayer dielectric film having a second opening and a third wiring so formed as to cover the second interlayer dielectric film, wherein an inner side surface of the second opening is arranged on a region corresponding to the first recess portion and formed such that an opening width of a portion in the vicinity of an upper end increases from a lower portion toward an upper portion. | 2009-01-01 |
20090001591 | REDUCING RESISTIVITY IN METAL INTERCONNECTS BY COMPRESSIVE STRAINING - Techniques for reducing resistivity in metal interconnects by compressive straining are generally described. In one example, an apparatus includes a dielectric substrate, a thin film of metal coupled with the dielectric substrate, and an interconnect metal coupled to the thin film of metal, the thin film of metal having a lattice parameter that is smaller than the lattice parameter of the interconnect metal to compressively strain the interconnect metal. | 2009-01-01 |
20090001592 | METAL INTERCONNECT FORMING METHODS AND IC CHIP INCLUDING METAL INTERCONNECT - Methods of forming a metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect. | 2009-01-01 |
20090001593 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OVERHANGING CONNECTION STACK - An integrated circuit package system comprising: providing a first conductive line adjacent to a second conductive line; forming a first connection stack over the first conductive line with the first connection stack overhanging the second conductive line; connecting an integrated circuit device and the first connection stack; and encapsulating the integrated circuit device and the first connection stack. | 2009-01-01 |
20090001594 | AIRGAP INTERCONNECT SYSTEM - A method may comprise assembling a first dielectric ensemble that comprises a first dielectric layer exhibiting a first porosity, a second dielectric layer exhibiting a second porosity and a third dielectric layer exhibiting a third porosity, and fabricating a first metal line in the dielectric ensemble. A chemical may be applied on the third layer to pass through and dissolve a portion of the second layer. The third layer acts to prevent a via that is partially landed on the dielectric from exposing the air gap underneath. | 2009-01-01 |
20090001595 | Integrated Circuit, Intermediate Structure and a Method of Fabricating a Semiconductor Structure - In a method of fabricating a semiconductor structure, a carbon containing mask is fabricated over a dielectric layer. The mask exposes the surface of the dielectric layer at least partly in a region between two adjacent conducting lines. A contact hole is etched into the dielectric layer in the region between the two adjacent conducting lines. | 2009-01-01 |
20090001596 | CONDUCTIVE LINE STRUCTURE - A conductive line structure is defined with an OPC photomask and is suitably applied to a semiconductor device. The conductive line structure includes a first conductive line and a second conductive line. The first conductive line includes a first line body oriented in the X-direction of a plane coordinate system, a first end portion at one end of the first line body slanting toward the Y-direction of the plane coordinate system, and a second end portion at the other end of the first line body also slanting toward the Y-direction. The second conductive line arranged in an end-to-end manner with the first conductive line includes a second line body oriented in the X-direction, a third end portion at one end of the second line body slanting toward the Y-direction, and a fourth end portion at the other end of the second line body also slanting toward the Y-direction. | 2009-01-01 |
20090001597 | SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT ELECTRICALLY CONNECTING A FRONT AND BACKSIDE THEREOF AND A METHOD OF MANUFACTURE THEREFOR - The disclosure provides a semiconductor device and method of manufacture. The method for manufacturing the semiconductor device includes providing a substrate having circuitry located thereover. The surface of the substrate is subjected to a first anisotropic etch, the first anisotropic etch forming an opening that extends only partially into the substrate. An opposing surface of the substrate is subjected to a second anisotropic etch, the second anisotropic etch forming an opposing opening that extends only partially into the substrate. Additionally, a first conductive layer is formed in electrical contact with the circuitry and lining sidewalls of the opening. A second conductive layer is formed along at least a portion of the second opposing surface and lining sidewalls of the opposing opening. The first conductive layer and the second conductive layer electrically contact one another. | 2009-01-01 |
20090001598 | Formation of Through Via before Contact Processing - The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads. | 2009-01-01 |
20090001599 | DIE ATTACHMENT, DIE STACKING, AND WIRE EMBEDDING USING FILM - Systems, methods, and/or devices that facilitate stacking dies in a multi-die stack using film over wire and attaching a die to a substrate are presented. Film over wire (FOW) techniques can be employed to facilitate stacking dies that are the same or similar in size such that the wires bonded onto the lower die can be embedded in film used to attach the two dies. FOW techniques can also be employed to embed a smaller die and wires attached thereto in film underneath a larger die stacked on top of the lower die such that the larger die can be supported by the film in areas where the larger die would otherwise overhang. Die attach film can be utilized to facilitate attaching a die to a substrate such that all areas between the die and substrate are filled thereby reducing or eliminating delamination. | 2009-01-01 |
20090001600 | ELECTRONIC DEVICE INCLUDING A PLURALITY OF SINGULATED DIE AND METHODS OF FORMING THE SAME - An electronic device can include a first die having a first terminal at a first front side, and a second die having a second terminal at a second front side and a through via. In one aspect, a process of forming the electronic device includes supplying a second substrate including a die location of the second die. The process can also include attaching the second substrate to a handling substrate and singulating the second die from the second substrate before removing the handling substrate. In another aspect, the handling substrate can include a rigid substrate. The process can include orienting the front side of the first die and a back side of the second substrate front-to-back with respect to each other. In yet another aspect, the first terminal is electrically connected to the through via and the second terminal. In one embodiment, the electronic device can include a third die. | 2009-01-01 |
20090001601 | MEMORY ARRAY ON MORE THAN ONE DIE - For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed. | 2009-01-01 |
20090001602 | STACK PACKAGE THAT PREVENTS WARPING AND CRACKING OF A WAFER AND SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING THE SAME - A stack package and a method for manufacturing the same. The stack package includes first and second semiconductor chips placed such that surfaces thereof, on which bonding pads are formed, face each other; a plurality of through-silicon vias formed in the first and second semiconductor chips; and a plurality of redistribution layers formed on the surfaces of the first and second semiconductor chips to connect the through-silicon vias to the corresponding bonding pad, wherein the redistribution layers of the first and second semiconductor chips contact each other. By forming the stack package in this manner, it is possible to prevent pick-up error and cracks from forming during the manufacturing process, and therefore the stack package can be reliable formed. | 2009-01-01 |