Class / Patent application number | Description | Number of patent applications / Date published |
324762090 | Field effect transistor | 34 |
20110006801 | Circuit Arrangement for Overtemperature Detection - A method and system is provided for retrieving information about operational data from a plurality of building systems and service and maintenance information for a plurality of building sites. A customer web portal is provided with a database for storing the operational data and the service information allowing users to more readily generate reports and obtain service related information for a plurality of sites without having to maintain separate database systems at remote locations. | 01-13-2011 |
20110215827 | Method and Apparatus for Testing a Memory Device - In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data. | 09-08-2011 |
20110279144 | METHOD FOR EVALUATING SEMICONDUCTOR DEVICE - To provide a simple method for evaluating reliability of a transistor, a simple test which correlates with a bias-temperature stress test (BT test) is performed instead of the BT test. Specifically, a gate current value is measured in the state where a voltage lower than the threshold voltage of an n-channel transistor whose channel region includes an oxide semiconductor is applied between a gate and a source of the transistor and a potential applied to a drain is higher than a potential applied to the gate. The evaluation of the gate current value can be simply performed compared to the case where the BT test is performed; for example, it takes short time to measure the gate current value. That is, reliability of a semiconductor device including the transistor can be easily evaluated. | 11-17-2011 |
20110304350 | Mask Alignment, Rotation and Bias Monitor Utilizing Threshold Voltage Dependence - The present invention provides a method and apparatus for measuring alignment, rotation and bias of mask layers in semiconductor manufacturing by examining threshold voltage variation. | 12-15-2011 |
20120062271 | Methods and System for Electrostatic Discharge Protection of Thin-Film Transistor Backplane Arrays - The present invention provides devices and methods for testing the electrical performance of thin-film transistor backplane arrays and protecting thin-films during testing and handling. | 03-15-2012 |
20120074981 | METHOD AND APPARATUS FOR DEVICE PARAMETER MEASUREMENT - A method of measuring a parameter of a device in a circuit includes providing a device under test (DUT). The DUT includes a metal oxide semiconductor (MOS) transistor having a gate, a source, and a drain coupled to a first voltage supply node. The method further includes coupling a constant current source to the source of the transistor, coupling an operational amplifier to the transistor, and measuring a parameter of the transistor. | 03-29-2012 |
20120105095 | SILICON-ON-INSULATOR (SOI) BODY-CONTACT PASS GATE STRUCTURE - A circuit for testing a floating body field-effect transistor (FET), and a related method, are provided. Embodiments of this invention include a circuit including a contacted-body FET structure that can be operated in a floating body mode or a body-contacted mode, and a passgate FET. A body of the contacted-body FET structure is connected to the drain of the passgate FET. Voltage can be applied to the passgate FET to either allow or restrict current flow through the passgate FET, to operate the contacted-body FET structure in body contacted mode or floating body mode. Data can be taken in each mode and compared to extract a floating body voltage. | 05-03-2012 |
20120119778 | POST SILICIDE TESTING FOR REPLACEMENT HIGH-K METAL GATE TECHNOLOGIES - A test structure for testing transistor gate structures in an IC device includes one or more probe pads formed at an active area of the IC device; one or more first conductive lines formed at the active area of the IC device, in electrical contact with the one or more probe pads; one or more second conductive lines formed at a gate conductor level of the IC device, in electrical contact with the one or more first conductive lines; and a gate electrode structure to be tested in electrical contact with the one or more second conductive lines; wherein the electrical contact between the one or more second conductive lines and the one or more first conductive lines is facilitated by a localized dielectric breakdown of a gate dielectric material disposed between the one or more second conductive lines and the one or more first conductive lines. | 05-17-2012 |
20120206161 | CIRCUIT HAVING AN EXTERNAL TEST VOLTAGE - A circuit having an external test voltage includes an amplifier, a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, at least one reference resistor, at least one test resistor, a first upper resistor, a second upper resistor and a lower resistor. The second P-type metal-oxide-semiconductor transistor is the same as the first P-type metal-oxide-semiconductor transistor. A difference between a voltage of a test output terminal of each test resistor and a voltage of a reference output terminal of a corresponding reference resistor is kept at a predetermined value by duplicating a current flowing through the first P-type metal-oxide-semiconductor transistor to the second P-type metal-oxide-semiconductor transistor, and feeding an external test voltage to a second terminal of the second upper resistor. | 08-16-2012 |
20120319721 | CLOSED LOOP FEEDBACK CONTROL OF INTEGRATED CIRCUITS - Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior. | 12-20-2012 |
20130033285 | METHODS FOR RELIABILITY TESTING OF SEMICONDUCTOR DEVICES - In accordance with a exemplary embodiments, methods for performing reliability testing of a plurality of transistors formed on a substrate includes simultaneously stressing the plurality of transistors by applying a voltage potential from each of a plurality of voltage sources to respective drain contacts of a like plurality of row groups and to gate contacts of a like plurality of column groups for a time interval, while applying a reference potential to the substrate and source contacts of the plurality of transistors. After stressing the plurality of transistors for a time interval, the transistors are each measured individually to collect reliability data. | 02-07-2013 |
20130076388 | TRANSISTOR ARRAY FOR TESTING - A transistor array for testing is provided. The transistor array includes a plurality of tested units. Each of the tested unit includes a tested transistor and a first to third switches. The tested transistor has a control terminal, a first and a second terminals and a bulk. The first switch is coupled between the first terminal and a leakage transporting line. The second switch is coupled between the second terminal and the leakage transporting line. The third switch is coupled between the control terminal and a bias providing line. The first to third switches are turned on or turned off according to a control signal. When the tested transistor is selected to be tested, the first to third switches are turned on according to the control signal. | 03-28-2013 |
20130162284 | METHOD AND APARATUS FOR HIGH SIDE TRANSISTOR PROTECTION - A method and apparatus for detecting a high energy event in a transistor includes performing the steps of: monitoring a gate to source voltage of a transistor during transistor start up, continuously determining a derivative of the monitored gate to source voltage with respect to time, and detecting a high energy event when the derivative of the gate to source voltage exceeds a predetermined threshold. | 06-27-2013 |
20130278281 | SEMICONDUCTOR DEVICE INCLUDING BODY CONNECTED FETS - A semiconductor includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET. | 10-24-2013 |
20130293256 | Method and Apparatus for Reading a Programmable Anti-Fuse Element in a High-Voltage Integrated Circuit - A semiconductor device comprises an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which comprises the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET. This abstract is provided to allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 11-07-2013 |
20140021979 | CIRCUIT AND METHOD FOR OVERCURRENT DETECTION OF POWER SWITCH - An overcurrent detection circuit for a power switch comprises a sampling circuit and a comparing circuit. The sampling circuit is configured to perform current sampling on the power switch using a sampling Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and an amplifier, convert a sample current into a sample voltage and transmit the sample voltage to the comparing circuit, and clamp operating voltages of the comparing circuit and of an output circuit of the amplifier by a serially connected clamping MOSFET. The comparing circuit is configured to compare the sample voltage with a reference voltage and to output a result of overcurrent detection. | 01-23-2014 |
20140035612 | Method and Measuring Device for Determining a State of a Semiconductor Material of a Chemosensitive Field-Effect Transistor that has been Tested and Delivered by a Manufacturer - The disclosure relates to a method for determining a state of a semiconductor material of a chemosensitive field-effect transistor that has been tested and delivered by a manufacturer. The chemosensitive field-effect transistor includes a source contact, a drain contact, a gate contact of a chemosensitive gate electrode, and a substrate contact. The method includes applying a voltage between the gate contact and a reference potential to the field-effect transistor that has been tested and delivered by the manufacturer. The method further includes detecting a current between the source contact and the substrate contact, and determining the state using the voltage and the current. | 02-06-2014 |
20140062524 | JFET HAVING WIDTH DEFINED BY TRENCH ISOLATION - A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a second-type formed in the semiconductor surface. A first-type drain and a first-type source are formed on opposing sides of the top gate. A first deep trench isolation region has an inner first trench wall and an outer first trench wall surrounding the top gate, the drain and the source, and extends vertically to a deep trench depth from the topside surface. A second-type sinker formed in semiconductor surface extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and laterally inside the inner first trench wall to provide a bottom gate. | 03-06-2014 |
20140111244 | Electrical Device With A Pulsed Power Supply And Method For Testing The Power Supply Of The Electrical Device - An electrical device having a clocked circuitry, and a method for testing the power supply unit of the electrical device. The electrical device comprises an electrical load, a clocked power supply unit, at least one pulse transformer and an evaluation device. The power supply unit comprises a power stack having at least one power semiconductor switch and is configured for generating a clocked voltage for the electrical load from an electric voltage based on an alternating on/off switching of the power semiconductor switch. The power stack exhibits at least one current path, through which an electric current flows during operation. The pulse transformer generates a signal assigned to the change in the charge and/or the direction of the electric current flowing through the current path. The evaluation device evaluates the signal coming from the pulse transformer and draws a conclusion regarding the operational reliability of the power semiconductor switch. | 04-24-2014 |
20140218064 | SMU RF TRANSISTOR STABILITY ARRANGEMENT - An RF testing method and system by which a DC measurement pathway can also act like a properly terminated RF pathway. Achieving this requires that the output HI, LO, and Sense HI conductors are terminated in a frequency selective manner such that the terminations do not affect the SMU DC measurements. Once all SMU input/output impedances are controlled, as well as properly terminated to eliminate reflections, the high-speed devices will no longer oscillate during device testing, so long as the instruments maintain a high isolation from instrument-to-instrument (separate instruments are used on the gate and drain, or on the input and output of the device). The output of HI, LO and Sense HI conductors are coupled to various nodes of the DUT via three triaxial cables, the outer shieldings of which are coupled to each other and to an SMU ground. | 08-07-2014 |
20140247067 | TESTING STRUCTURE AND METHOD FOR INTERFACE TRAP DENSITY OF GATE OXIDE - The present invention discloses a testing structure and method for interface trap density of gate oxide, relating to the field of quality and reliability researches of MOS devices. The present invention makes the interface traps density tests for gate oxide layers of n-type and p-type MOS devices completed on a same testing structure, this does not only shorten the measurement period by half but also decrease the costs for testing instruments, because the present testing method is based on a simple current-voltage scanning test without using equipments such as pulse generator required in conventional method. The testing results obtained according to the present invention are featured with spectral peak, which facilitates the data analysis and computation. | 09-04-2014 |
20140354325 | SEMICONDUCTOR LAYOUT STRUCTURE AND TESTING METHOD THEREOF - A semiconductor layout structure and a testing method thereof are disclosed. The semiconductor layout structure includes a device under test (DUT), a first testing pad, a second testing pad and a plurality of third testing pads. The DUT includes a plurality of metal-oxide-semiconductor (MOS) transistors. Each of the MOS transistors includes a first terminal, a second terminal and a third terminal. The first testing pad is coupled to the first terminals for being applied a first voltage. The second testing pad is coupled to the second terminals for being applied a second voltage. The third testing pads are respectively coupled to the third testing pads for being applied a third voltage. The third testing pads are electrical insulated from each other. The third voltage is larger than the first voltage and the second voltage. | 12-04-2014 |
20150015300 | DETECTING FAULTS IN HOT-SWAP APPLICATIONS - Circuitry for detecting faults in a system for supplying power from an input node to an output node and having at least one switch coupled between the input node and the output node. The fault detecting circuitry is configured for indicating a fault condition of the switch when the switch is commanded to turn on and at least one of the following conditions is detected: a voltage across the switch exceeds a predetermined value or a value of the switch control signal is insufficient to turn the switch on. The fault condition is indicated only if the detected condition is present for a predetermined period of time. | 01-15-2015 |
20150061726 | NEGATIVE BIAS THERMAL INSTABILITY STRESS TESTING OF TRANSISTORS - A circuit is powered through a P-type transistor whose thermal instability behavior is to be evaluated. The threshold of the P-type transistor under evaluation and consequently the saturation current of the transistor are reflected in the frequency of the circuit, which in one embodiment is a ring oscillator. Additional circuitry is connected to the P-type transistor and the ring oscillator to ensure the proper stress conditions for the transistor and consequently to the evaluation of the P-type transistor. | 03-05-2015 |
20150301091 | Duty Cycle Independent Comparator - Disclosed are methods and circuits to measure independently of duty cycles a pulsed current of a pass transistor of a switched circuit. Methods and circuits of one embodiment may be applied to precisely operate DC-to-DC converters such as buck converters in the most efficient operation modes. Another embodiment can be used to measure the pulsed current independently of duty cycle over a wide range of current values. | 10-22-2015 |
20150338455 | TEST METHOD AND SYSTEM FOR CUT-IN VOLTAGE - A test method and system for cut-in voltage. The method comprises: coarse scanning of the cut-in voltage: a grid voltage, i.e., the cut-in voltage, is quickly determined when a drain terminal current is greater than a target current for the first time ( | 11-26-2015 |
20150369854 | CIRCUIT AND METHOD FOR DETECTING SHORT CIRCUIT FAILURE OF A SWITCHING TRANSISTOR - A circuit and method are provided detecting a persistent short circuit in a power MOSFET for the purpose of protecting a load from over-current. | 12-24-2015 |
20150369855 | EVALUATION OF THERMAL INSTABILITY STRESS TESTING - A circuit is powered through a transistor whose thermal instability behavior is to be evaluated in a stress test. The transistor is stressed during a stress phase of the stress test with a sensor circuit powered off and the Vds of the transistor is zero. The sensor circuit is powered on through the transistor during an evaluate phase of the stress test. | 12-24-2015 |
20160005828 | GATE DIELECTRIC PROTECTION FOR TRANSISTORS - At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge. | 01-07-2016 |
20160061898 | WETTING CURRENT DIAGNOSTICS - A method of providing wetting current diagnostics for a load control switch includes changing test switch settings of a detection circuit from an operational configuration to a testing configuration. The test switch settings specify respective states of first and second test switches of the detection circuit. The first and second test switches are connected to a node of the detection circuit through which, in the operational configuration, a wetting current for the load control switch flows. The method includes determining whether a voltage at the node becomes no longer indicative of the operational configuration as a result of the changed test switch settings, returning the test switch settings to the operational configuration, and providing a wetting current fault indication if the voltage at the node fails to return to a level indicative of the operational configuration after returning the test switch settings to the operational configuration. | 03-03-2016 |
20160069946 | SEMICONDUCTOR INSPECTION APPARATUS - The semiconductor inspection apparatus according to an embodiment includes a first detecting unit capable of being electrically connected to a source electrode of a field effect transistor to be evaluated, the first detecting unit used for detecting voltage, a first diode including a first anode electrode and a first cathode electrode, the first cathode electrode capable of being electrically connected to a drain electrode of the field effect transistor, a second detecting unit electrically connected to the first anode electrode, the second detecting unit used for detecting voltage, a first resistance element of which a first end is electrically connected to the first anode electrode, and a first electric power source electrically connected to a second end of the first resistance element. | 03-10-2016 |
20160109505 | DEVICE TESTING - A device may include a plurality of cells. Each cell may include a field-effect transistor and a switch configured to selectively connect a second contact of the respective field-effect transistor with a common test line of the device. A controller of the device is configured to control the switch to be in a closed position. At least one pin is provided which is configured to apply a stress voltage to a common power line connected to a first contact with the field-effect transistor and to the common test line. | 04-21-2016 |
20160187415 | DISPLAY APPARATUS INCLUDING DUMMY DISPLAY ELEMENT FOR TFT TESTING - This disclosure provides systems, methods and apparatus for a display apparatus including dummy display elements that can be switched between being coupled to a test bus and a drive bus. When connected to the drive bus, the circuit components, including thin-film transistors, of the dummy display element experience exposure to typical operating signals. When connected to the test bus, the display apparatus can test the operating parameters of the dummy display element circuit components. | 06-30-2016 |
20160252565 | NON-CONTACT METHOD TO MONITOR AND QUANTIFY EFFECTIVE WORK FUNCTION OF METALS | 09-01-2016 |