Class / Patent application number | Description | Number of patent applications / Date published |
324762050 | Semiconductor wafer | 35 |
20100327900 | POLISHING HEAD TESTING WITH MOVABLE PEDESTAL - A polishing head is tested in a test station having a pedestal for supporting a test wafer and a controllable pedestal actuator to move a pedestal central wafer support surface and a test wafer toward the polishing head. In another aspect of the present description, the test wafer may be positioned using a positioner having a first plurality of test wafer engagement members positioned around the pedestal central wafer support surface. In another aspect, the wafer position may have a second plurality of test wafer engagement members positioned around an outer wafer support surface disposed around the pedestal central wafer support surface and adapted to support a test wafer. The second plurality of test wafer engagement members may be distributed about a second circumference of the ring member, the second circumference having a wider diameter than the first circumference. Additional embodiments and aspects are described and claimed. | 12-30-2010 |
20110018576 | METHOD AND DEVICE FOR TESTING SEMICONDUCTOR - A semiconductor testing device of the prevent invention includes a current detecting circuit, an electric current drawing circuit, and a determining device. The electric current drawing circuit is connected to a semiconductor device under test, and draws a branched electric current branched from a measured electric current output from a second terminal based on predetermined electric voltage. The current detecting circuit is connected to the semiconductor device, and detects a detection current obtained by subtracting the branched electric current from the measured electric current. The determining device determines a quality of the semiconductor device based on the detection current. | 01-27-2011 |
20110018577 | TEST CIRCUIT, WAFER, MEASURING APPARATUS, MEASURING METHOD, DEVICE MANUFACTURING METHOD AND DISPLAY APPARATUS - There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section. | 01-27-2011 |
20110050273 | FAST TESTABLE WAFER AND WAFER TEST METHOD - A fast testable wafer includes a die group, testing points located on dies, a scribe line located between the dies, and a plurality of testing pads disposed in the scribe line area. The testing points comprise bonding pads or electrodes of internal circuits within the dies. The testing pads and bonding pads may be electrically connected and arranged suitably such that testing probes may be electrically connected to the testing pads and bonding pads easily so as to test the plurality of dies at about the same time. Through suitable circuits on the wafer, different circuit routes may be selected to connect the testing pads and different testing points on the dies so as to test a plurality of dies without moving the testing probes and thereby accelerating the test. | 03-03-2011 |
20110050274 | Maintaining A Wafer/Wafer Translator Pair In An Attached State Free Of A Gasket Disposed Therebetween - A wafer translator and a wafer, removably attached to each other, provides the electrical connection to electrical contacts on integrated circuits on a wafer in such a manner that the electrical contacts are substantially undamaged in the process of making such electrical connections. Various embodiments of the present invention provide a gasketless sealing means for facilitating the formation by vacuum attachment of the wafer/wafer translator pair. In this way, no gasket is required to be disposed between the wafer and the wafer translator. Air, or gas, is evacuated from between the wafer and wafer translator through one or more evacuation pathways in the gasketless sealing means. | 03-03-2011 |
20110050275 | SEMICONDUCTOR WAFER HAVING TEST MODULES INCLUDING PIN MATRIX SELECTABLE TEST DEVICES - A semiconductor wafer includes a plurality of die areas including circuit elements, and at least one test module (TM) on the wafer outside the die areas. The TMs include a test circuit including plurality of test transistors arranged in a plurality of rows and columns. The plurality of test transistors include at least three terminals (G, S, D and B). The TMs each include a plurality of pads. The pads include a first plurality of locally shared first pads each coupled to respective ones of a first of the three terminals, a second plurality of locally shared second pads each coupled to respective ones of a second of the three terminals, and at least one of the plurality of pads coupled to a third of the three terminals. The TM provides at least 2 pin transistor selection for uniquely selecting from the plurality of test transistors for testing. | 03-03-2011 |
20110050276 | METHOD AND PROGRAM FOR OPERATING TEST APPARATUS - Disclosed is a method for operating a test apparatus in which the testing efficiency is drastically increased. The test apparatus has a plurality of stages for testing wafers by using operation buttons displayed on the operating screens of each of a plurality of monitors. Exclusion condition buttons for excluding operation buttons are set in at least one monitor using exclusion condition data prepared by combining data required to perform various functions of the test apparatus and an exclusion condition pattern prepared by combining the exclusion condition of the exclusion condition data into data for deciding whether the operating button configured to operate each function can be pressed or not. Also, display of the screen that satisfies the exclusion condition for at least one monitor is prevented. | 03-03-2011 |
20110095780 | WAFER INSPECTION DEVICE AND SEMICONDUCTOR WAFER INSPECTION METHOD USING THE SAME - A wafer inspection device, which inspects the electrical properties of a semiconductor wafer on which a semiconductor integrated circuit is formed, and the wafer inspection device has: a holding mechanism for holding a probe card; a wafer stage that holds the semiconductor wafer on the upper surface and is movably provided; and a pressing mechanism that are held and press the wafer stage against the probe card. The wafer stage is provided on the outer periphery with a seal ring. The seal ring forms a sealed space in a state where the wafer and the probe card are brought close to each other by contacting the probe card and is provided in such a manner as to reduce the pressure of the sealed space. | 04-28-2011 |
20110109343 | SEMICONDUCTOR WAFER DEVICE AND METHOD FOR TESTING THE SAME - In an embodiment, a plurality of semiconductor chip portions is provided with respect to each reticle unit in a semiconductor wafer. Each of the semiconductor chip portions is provided with a first identification code generation circuit to generate a first identification code, and a switching circuit. The switching circuit controls connection with outside. Each of second identification code generation circuits is provided on dicing line areas within each reticle unit, and generates a second identification code to select the corresponding reticle unit. Coincidence detection circuits are provided on the dicing line areas. Each of the coincidence detection circuits determines whether or not the corresponding first and second identification codes and a chip select signal coincide with each other. Bus lines are provided on the dicing line areas. One ends of the bus lines are connected to the circuits, and the other ends are connected to test pads. | 05-12-2011 |
20110115519 | TEST SYSTEM AND WRITE WAFER - A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel. | 05-19-2011 |
20110227602 | PROBE STATION FOR ON-WAFER-MEASUREMENT UNDER EMI-SHIELDING - An arrangement is provided for testing DUTs with a chuck that has a support surface for supporting of a DUT as well as for supplying the support surface with a defined potential, or for connecting the DUT. The arrangement further includes a positioning device for positioning the chuck as well as an electromagnetic shielding housing enclosing at least the chuck. Inside the housing and adjacent to the chuck, a signal preamplifier is arranged whose signal port facing the chuck is electrically connected with the support surface, wherein the signal preamplifier is moveable together with the chuck by the positioning device in a way that it holds its position constant relative to the chuck during positioning. The signal preamplifier is connected to a measurement unit outside of the housing via a measurement cable. | 09-22-2011 |
20110254580 | METHOD FOR AN IMPROVED CHECKING OF REPEATABILITY AND REPRODUCIBILITY OF A MEASURING CHAIN FOR SEMICONDUCTOR DEVICE TESTING - A method provides an improved checking of repeatability and reproducibility of a measuring chain, in particular for quality control by semiconductor device testing. The method includes testing steps provided for multiple and different devices to be subjected to measurement or control through a measuring system that includes at least one chain of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement or control. Advantageously, the method comprises checking repeatability and reproducibility of each type of unit that forms part of the measuring chain and, after the checking, making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement or control. | 10-20-2011 |
20110279143 | SEMICONDUCTOR WAFER TESTING APPARATUS - Disclosed is a semiconductor wafer testing apparatus that resolves the following problems which arise when semiconductor wafers become larger: (1) complexity of stage acceleration/deceleration control; (2) throughput reduction; and (3) increased vibration of the stage support platform during the stage inversion operation (deterioration in resolution). In the semiconductor wafer testing apparatus for resolving these problems, a wafer is rotated, an electro beam is irradiated onto the rotating wafer from a scanning electron microscope, and secondary electrons emitted from the wafer are detected. The detected secondary electrons are A/D converted by an image processing unit, realigned by an image data realignment unit, and then image-processed for display. As a result, image information of all dies of a wafer can be acquired without a large amount of movement of the stage in the X and the Y directions. | 11-17-2011 |
20120013359 | Method and System for Wafer Level Testing of Semiconductor Chips - A system and method for wafer level testing of semiconductor chips are provided. In one embodiment, the system comprises a plurality of semiconductor chips disposed in a wafer, each semiconductor chip having at least one port for receiving test data and at least one connection disposed in a kerf region of the wafer between at least one port of a first semiconductor chip and at least one port of at least one second semiconductor chip in the plurality of semiconductor chips, wherein the first semiconductor chip is configured to send the test data to the at least one second semiconductor chip via the at least one connection. Additionally, the plurality of semiconductor chips may comprise at least one core logic configured to pass the test data to the at least one second semiconductor chip via the at least one connection. | 01-19-2012 |
20120032699 | METHOD OF MEASURING ELECTRICAL CHARACTERISTICS OF SEMICONDUCTOR WAFER - There is provided a method of measuring a leakage current or a dielectric breakdown voltage of a semiconductor wafer that has a base wafer and a buffer layer formed on the base wafer. The method includes providing, on the buffer layer, a plurality of electrodes including a hole injection electrode made of a material that injects a hole into the buffer layer when an electric field is applied thereto, measuring an electric current flowing through a pair of electrodes or a voltage between the electrodes when a voltage or an electric current is applied to the pair of electrodes, the electrodes including at least one hole injection electrode, and measuring a leakage current or a dielectric breakdown voltage caused by hole migration in the semiconductor wafer based on the current flowing through the pair of electrodes or the voltage generated between the pair of the electrodes. | 02-09-2012 |
20120062269 | INSPECTION TOOL AND METHODOLOGY FOR THREE DIMENSIONAL VOLTAGE CONTRAST INSPECTION - A system and method for improved voltage contrast inspection is disclosed. In one embodiment the temporal response to voltage contrast is considered to find an optimal acquisition time. In another embodiment, multiple optimal acquisition times are identified. The identified acquisition times are used in voltage contrast inspection of semiconductor fabrication, and are well-suited to SOI technology. | 03-15-2012 |
20120062270 | COMPLIANT PRINTED CIRCUIT WAFER PROBE DIAGNOSTIC TOOL - Diagnostic tools for testing wafer-level IC devices, and a method of making the same. The first diagnostic tool can include a first compliant printed circuit with a plurality of contact pads configured to form an electrical interconnect at a first interface between distal ends of probe members in the wafer probe and contact pads on a wafer-level IC device. A plurality of printed conductive traces electrically couple to a plurality of the contact pads on the first compliant printed circuit. A plurality of electrical devices are printed on the first compliant printed circuit at a location away from the first interface. The electrical devices are electrically coupled to the conductive traces and are configured to provide one or more of continuity testing or functionality of the wafer-level IC devices. A second diagnostic tool includes a second compliant printed circuit electrically coupled to a dedicated IC testing device. A plurality of electrical devices are printed on the second compliant printed circuit and electrically coupled to the dedicated IC device. | 03-15-2012 |
20120286819 | MOS TEST STRUCTURE, METHOD FOR FORMING MOS TEST STRUCTURE AND METHOD FOR PERFORMING WAFER ACCEPTANCE TEST - A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together. | 11-15-2012 |
20130135005 | METHOD FOR TESTING GROUP III-NITRIDE WAFERS AND GROUP III-NITRIDE WAFERS WITH TEST DATA - The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control. | 05-30-2013 |
20130141135 | APPARATUS FOR TESTING ELECTRONIC DEVICES - An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer. | 06-06-2013 |
20130234750 | SEMICONDUCTOR WAFER AND METHOD FOR TESTING THE SAME - A semiconductor wafer includes semiconductor chips divided by a dicing line, one of the semiconductor chips including terminals of an identical potential; a wiring located on the dicing line, and electrically connecting the terminals to each other; and a pad electrically connected through the wiring to the terminals, wherein the pad is located entirely on the semiconductor chip and is not present on the dicing line. | 09-12-2013 |
20130285695 | Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate - In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions. | 10-31-2013 |
20130300451 | EVALUATING TRANSISTORS WITH E-BEAM INSPECTION - A test structure of a semiconductor wafer includes a series of electrical units connected electrically in series output-to-input in an open loop configuration. The series of electrical units is configured to have alternating output voltages, such that each electrical unit is configured to output a voltage opposite an output voltage of a preceding electrical unit. Each electrical unit is configured to have an output voltage that alternates when an input voltage applied to a first electrical unit in the series of electrical units alternates. | 11-14-2013 |
20140125374 | METHOD FOR EVALUATING WAFER DEFECTS - Provided is a method for evaluating defects in a wafer. The method for evaluating the wafer defects includes preparing a wafer sample, forming an oxidation layer on the wafer sample, measuring a diffusion distance of a minority carrier using a surface photovoltage (SPV), and determining results of a contamination degree. | 05-08-2014 |
20140139258 | BUILT OFF TESTING APPARATUS - A built off testing apparatus coupled between a semiconductor device and an external testing apparatus to test a semiconductor device. The built off testing apparatus can include a frequency multiplying unit to generate a test clock frequency by multiplying the frequency of a clock input by the external testing apparatus according to the operation speed of the semiconductor device, an instruction decoding unit to generate test information by decoding test signals input by the external testing apparatus according to the test clock frequency, and a test execution unit to test the semiconductor device according to the test information, and can determine whether the semiconductor device is failed or not based on test data output by the semiconductor device, and can transmit resulting data to the external testing apparatus. | 05-22-2014 |
20140145749 | METHOD AND APPARATUS OF RFID TAG CONTACTLESS TESTING - A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands. | 05-29-2014 |
20140152337 | STRUCTURE AND METHOD FOR IN-LINE DEFECT NON-CONTACT TESTS - A system, method and apparatus may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral test structure may comprise a spiral connected at either end by a capacitor to allow the spiral test structure to resonate. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus. | 06-05-2014 |
20140210506 | In-Situ Charging Neutralization - Some embodiments relate to a method for semiconductor processing. In this method, a semiconductor wafer is provided. A surface region of the semiconductor wafer is probed to determine whether excess charge is present on the surface region. Based on whether excess charge is present, selectively inducing a corona discharge to reduce the excess charge. Other techniques are also provided. | 07-31-2014 |
20140266292 | SEMICONDUCTOR TEST WAFER AND METHODS FOR USE THEREOF - A test wafer is disclosed with a first side configured to have integrated circuits formed thereon and a second side with a test structure formed thereon. The test wafer can include electrical test structures embedded in the second side of the wafer. An electrical test of the test wafer can be performed after handling by a tool used in a wafer manufacturing process to determine if the tool caused a defect on the second side of the wafer. The test structure can include a blanket layer disposed on the second side of the wafer. The test wafer can then be exposed to a wet etch and inspected thereafter for the presence of an ingress path caused from the etch chemistry. The presence of an ingress path is an indication that the tool used prior to the wet etch caused a defect in the wafer. | 09-18-2014 |
20150015299 | TRANSLATORS COUPLEABLE TO OPPOSING SURFACES OF MICROELECTRONIC SUBSTRATES FOR TESTING, AND ASSOCIATED SYSTEMS AND METHODS - Translators coupleable to opposing surfaces of microelectronic substrates for testing, and associated systems and methods are disclosed. An arrangement in accordance with one embodiment includes a microelectronic substrate having a first major surface, a second major face facing opposite from the first major surface, and electrically conductive through-substrate vias extending through the substrate and electrically accessible from both the first and second surfaces. The arrangement further includes a first translator releasably connected to the substrate and positioned in a first region extending outwardly from the first surface, the first translator including first electrical signal paths that access the vias from the first surface, and a second translator releasably connected to the substrate simultaneously with the first translator, the second translator being positioned in a second region extending outwardly from the second surface, the second translator including second electrical signal paths that access the vias from the second surface. | 01-15-2015 |
20150048862 | DETECTING ARCING USING PROCESSING CHAMBER DATA - A method and apparatus for detecting substrate arcing and breakage within a processing chamber is provided. A controller monitors chamber data, e.g., parameters such as RF signals, voltages, and other electrical parameters, during operation of the processing chamber, and analyzes the chamber data for abnormal spikes and trends. Using such data mining and analysis, the controller can detect broken substrates without relying on glass presence sensors on robots, but rather based on the chamber data. | 02-19-2015 |
20150084668 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a test control unit suitable for activating an on-die termination signal in response to a control signal activated in a test mode, and a data mask pad suitable for pull-down driving a data mask signal when the on-die termination signal is activated. | 03-26-2015 |
20150115994 | OPTIMIZATION OF INTEGRATED CIRCUIT RELIABILITY - A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate. | 04-30-2015 |
20150377951 | METHOD FOR TESTING SPECIAL PATTERN AND PROBE CARD DEFECT IN WAFER TESTING - Methods for testing a special pattern and testing a probe card defect in wafer testing are provided. In the method for testing the special pattern, a wafer is divided into multiple testing partitions, in which each of the testing partitions includes multiple dies. The dies in each testing partition of the wafer are respectively tested by multiple sites of the probe card to obtain a testing map. Then, a number of the dies having defects and a number of the dies without defect within each of the testing partitions in the testing map are accumulated to construct chi-square test and calculate a maximum P-value. Finally, it is determined whether a minimum of the maximum P-values of all of the testing partitions is smaller than a certain predetermined threshold. If the minimum is smaller than the threshold, it is determined that the testing map of the wafer contains the special pattern. | 12-31-2015 |
20220137132 | Apparatus and Method for Testing Semiconductor Devices - The invention is a test system for testing silicon wafers or packaged devices. The system includes a tester having multiple testing stacks that each hold a vertical stack of test engines, data buffers, pin drivers, and other resources, which are electrically connected on one side to a wafer or DUT and on the other side to a test host computer via fast data links. Each testing stack is disposed on a top side of a wafer contactor electrically connected to a wafer or a load board electrically connected to a DUT. The system includes a cooling system to remove heat during operation. The system minimizes the data signal path between the pads of the devices being tested and the pin drivers of the tester, the test engines, and the test host computer. High performance is possible by the connection of bottom of each testing stack directly to the wafer contactor. | 05-05-2022 |