Class / Patent application number | Description | Number of patent applications / Date published |
324754070 | Probe or probe card with build-in circuit element | 39 |
20100301885 | HIGH IMPEDANCE, HIGH PARALLELISM, HIGH TEMPERATURE MEMORY TEST SYSTEM ARCHITECTURE - An electronic device for use with a probe head in automated test equipment includes first and second pluralities of semiconductor devices. The first plurality of semiconductor devices is arranged to form at least one driver arranged to couple to a device under test. The at least one driver is configured to transmit a signal to the at least one device under test. The second plurality of semiconductor devices is arranged to form at least one receiver arranged to couple to the device under test. The at least one receiver is configured to receive a signal from the at least one device under test. Each of the second plurality of semiconductor devices has a thickness less than about 300 μm exclusive of any electrical interconnects. The at least one receiver is adapted to mount directly to the probe head. | 12-02-2010 |
20100321054 | SEMICONDUCTOR INSPECTING DEVICE AND SEMICONDUCTOR INSPECTING METHOD - A semiconductor inspecting device comprises a probe card for transmitting a signal or power supply to semiconductor wafers having one or more subject chips formed therein, and is constituted such that the first semiconductor wafer faces the first face of the probe card and such that the second semiconductor wafer faces the second face of the probe card on the opposite side of the first face. The probe card includes one or more inspecting chips, which can perform non-contact transmissions with the first subject chip in the first semiconductor wafer and the second subject chip in the second semiconductor wafer. | 12-23-2010 |
20100327893 | Probing Structure for Evaluation of Slow Slew-Rate Square Wave Signals in Low Power Circuits - An integrated circuit probing structure ( | 12-30-2010 |
20110012633 | APPARATUS AND METHOD FOR TESTING OF STACKED DIE STRUCTURE - An integrated circuit device is described that includes a stacked die and a base die having probe pads that directly couple to test logic of the base die so as to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. In addition, the base die includes a first probe pad configured to couple test input, a second probe pad configured to couple test output and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die so as to implement a scan chain for testing of the integrated circuit device. In accordance with aspects of the present invention, the first probe pad, the second probe pad and the third probe pad are coupled directly to the test logic such that configuration of the programmable logic is not required for coupling the test input, the test output and the control signal between the base die and the stacked die so as to implement the scan chain. | 01-20-2011 |
20110018566 | TEMPORARY PLANAR ELECTRICAL CONTACT DEVICE AND METHOD USING VERTICALLY-COMPRESSIBLE NANOTUBE CONTACT STRUCTURES - A wafer-scale probe card for temporary electrical contact to a sample wafer or other device, for burn-in and test. The card includes a plurality of directly metallized single-walled or multi-walled nanotubes contacting a pre-arranged electrical contact pattern on the probe card substrate. The nanotubes are arranged into bundles for forming electrical contacts between areas of the device under test and the probe card. The bundles are compressible along their length to allow a compressive force to be used for contacting the probe card substrate to the device under test. A strengthening material may be disposed around and/or infiltrate the bundles. The nanotubes forming the bundles may be patterned to provide a pre-determined bundle profile. Tips of the bundles may be metallized with a conductive material to form a conformal coating on the bundles; or metallized with a conductive material to form a continuous, single contact surface. | 01-27-2011 |
20110037489 | SILICON CHICKLET PEDESTAL - A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another. | 02-17-2011 |
20110193583 | METHODS FOR PLANARIZING A SEMICONDUCTOR CONTACTOR - A planarizer for a probe card assembly. A planarizer includes a first control member extending from a substrate in a probe card assembly. The first control member extends through at least one substrate in the probe card assembly and is accessible from an exposed side of an exterior substrate in the probe card assembly. Actuating the first control member causes a deflection of the substrate connected to the first control member. | 08-11-2011 |
20110199109 | SILICON CHICKLET PEDESTAL - A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another. | 08-18-2011 |
20110204912 | TEST APPARATUS HAVING A PROBE CORE WITH A TWIST LOCK MECHANISM - A probe core includes a frame, a wire guide connected to the frame, a probe tile, and a plurality of probe wires supported by the wire guide and probe tile. Each probe wire includes an end configured to probe a device, such as a semiconductor wafer. Each probe wire includes a signal transmitting portion and a guard portion. The probe core further includes a lock mechanism supported by the frame. The lock mechanism is configured to allow the probe core to be connected and disconnected to another test equipment or component, such as a circuit board. As one example, the probe core is configured to connect and disconnect from the test equipment or component in a rotatable lock and unlock operation or twist lock/unlock operation, where the frame is rotated relative to remainder of the core to lock/unlock the probe core. | 08-25-2011 |
20110267085 | METHOD AND APPARATUS FOR TESTING DEVICES USING SERIALLY CONTROLLED INTELLIGENT SWITCHES - Methods and apparatus for testing devices using serially controlled intelligent switches have been described. In some embodiments, a probe card assembly can be provided that includes a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to at least one serial control line, the plurality of ICs including switches coupled to test probes, each of the switches being programmable responsive to a control signal on the at least one serial control line. | 11-03-2011 |
20110291682 | PIN CARD AND TEST APPARATUS USING THE SAME - A first switch is arranged such that a first terminal thereof is connected to an AC test unit and a second terminal thereof is connected to an I/O terminal and a DC test unit. A first switch is configured so as to be capable of switching states between a connection state in which the first terminal and the second terminal are connected to each other, and a disconnection state in which they are disconnected from each other. A bypass capacitor is arranged between the first terminal and the second terminal, and is configured to bypass the frequency component which is cut off by the first switch. | 12-01-2011 |
20110316573 | LOADING CARD - A loading card includes a printed circuit board, first and second connection portions. The first connection portion includes first and second voltage pins, and a first ground pin. The second connection portion includes third and fourth voltage pins, and a second ground pin. The loading card also includes a first voltage signal test point connected to the first and third voltage pins, a second voltage signal test point connected to the second and fourth voltage pins, a first ground signal test point connected to the first and second ground signal test points, and a second ground signal test point connected to the first and second ground signal test points. | 12-29-2011 |
20120038380 | ELECTRICAL TESTING APPARATUS - A test apparatus is described that can be useful as test equipment in various applications, including for example testing a semiconductor device. The test apparatus has a circuit board, a probe card, and a card holder. The circuit board includes a contact layout that electrically connects with a probe card at one portion and electrically connects with a probe card holder at another portion. The probe card has probes for electrically contacting a device to be tested, and has a contact configuration that electrically connects with the circuit board. The apparatus allows for electrical signals to be sent to and from the probe card, through the probe card holder and circuit board, in testing a device such as for example a semiconductor device. The circuit board and probe card holder have an attachment structure, configured for example as a notch and catch finger attachment arrangement. | 02-16-2012 |
20120112778 | METHODS AND APPARATUS FOR MULTI-MODAL WAFER TESTING - Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer. A first set of pads of at least one integrated circuit is electrically coupled to the first set of wafer-side contact terminals, and a second set of pads of the integrated circuit is electrically coupled to the second set of wafer-side contact terminals. The edge-extended wafer translator may be shaped such that its edge-extended portion is not coplanar with the central portion thereof. | 05-10-2012 |
20120133382 | TEST APPARATUS - A test apparatus that test a device under test, comprising a test head that is arranged facing the device under test and that includes a test module for testing the device under test, and a probe assembly that transmits a signal and that is arranged between the test head and the device under test. The probe assembly includes a plurality of low voltage pins arranged at prescribed intervals from each other, and a plurality of high voltage pins that are arranged such that distance between each high voltage pin and each low voltage pin is greater than the prescribed interval, and that transmit a signal with a higher voltage than a signal transmitted by the low voltage pins. All of the high voltage pins are arranged in only one of two regions formed by dividing a surface of the probe assembly in half. | 05-31-2012 |
20120133383 | PROBE, PROBE CARD AND ELECTRONIC DEVICE TESTING APPARATUS - A probe includes: a single base portion; a plurality of beam portions whose rear end sides are supported by the base portion and whose front end sides protrude from the base portion; and a plurality of conductive patterns formed on surfaces of the beam portions. At least a part of the plurality of beam portions has a beam bent portion which is bent in a direction inclined to or substantially perpendicular to a protruding direction of the beam portions. | 05-31-2012 |
20120139572 | Tester and Test Apparatus Including the Same - A tester may include a test head with a movable coupler, a probe card with a connector unit that is coupled with the coupler, and a needle block disposed on the probe card. In one example, the tester may test respective subsets of semiconductor devices on a wafer via a one-touch operation by moving a coupler on the test head, while the wafer remains in continuous and uninterrupted electrical contact with the tester during testing. | 06-07-2012 |
20120161805 | DISPLAY DEVICE AND METHOD OF TESTING THE SAME - A display device and a method of testing the display device. The display device includes a substrate including both a display region on which pixel cells are located and a peripheral region; test pads, main pins connected to the pixel cells, and dummy pins that are respectively connected to the test pads, the test pads, the main pins, and the dummy pins being on the peripheral region of the substrate, and visual test lines on the peripheral region of the substrate. The visual test lines include a first portion connected to the main pins and a second portion connected to the test pads, and the first and second portions are disconnected from each other. | 06-28-2012 |
20120194210 | PROBE CARD WIRING STRUCTURE - The present disclosure provides a probe card for wafer level testing. The probe card includes a space transformer having first power/ground lines and first signal lines embedded therein, wherein the first power/ground and signal lines are configured to have a first wiring pitch on a first surface and a second wiring pitch on a second surface, the second wiring pitch being substantially less than the first wiring pitch; a printed circuit board bonded to the first surface of the space transformer, wherein the printed circuit board includes second power/ground lines and second signal lines embedded in the printed circuit board and coupled to the first power/ground and signal lines; and conductive lines configured to a surface of the printed circuit board remote to the first surface of the space transformer, wherein each of the conductive lines includes a first end coupled to one of the second signal lines and a second end coupled to a different location of the printed circuit board. | 08-02-2012 |
20120212248 | Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies - Enhanced microfabricated spring contact structures and associated methods, e.g. such as for electrical contactors and interposers, comprise improvements to spring structures that extend from the substrate surface, and/or improvements to structures on or within the support substrate. Improved spring structures and processes comprise embodiments having selectively formed and etched, coated and/or plated regions, which are optionally further processed through planarization and/or annealment. Enhanced solder connections and associated processes provide a gap between substrates for componentry, and or improved manufacturing techniques using distributed spacers. Enhanced probe card assembly structures and processes provide improved planarization adjustment and thermal stability. | 08-23-2012 |
20130002282 | Test Structures and Testing Methods for Semiconductor Devices - Test structures, methods of manufacturing thereof, and testing methods for semiconductors are disclosed. In one embodiment, a test structure for semiconductor devices includes a printed circuit board (PCB), a probe region, and a compliance mechanism disposed between the PCB and the probe region. A plurality of wires is coupled between the PCB and the probe region. End portions of the plurality of wires proximate the probe region are an integral part of the probe region. | 01-03-2013 |
20130015872 | Test Schemes and Apparatus for Passive InterposersAANM Lee; Yun-HanAACI Baoshan TownshipAACO TWAAGP Lee; Yun-Han Baoshan Township TWAANM Wang; Mill-JerAACI Hsin-ChuAACO TWAAGP Wang; Mill-Jer Hsin-Chu TWAANM Chou; Tan-LiAACI Zhubei CityAACO TWAAGP Chou; Tan-Li Zhubei City TW - A probe card includes a plurality of probe pins, and a switch network connected to the plurality of probe pins. The switch network is configured to connect the plurality of probe pins in a first pattern, and reconnect the plurality of probe pins in a second pattern different from the first pattern. | 01-17-2013 |
20130069681 | TEST CARD FOR MOTHERBOARDS - A test card includes a power interface, a controller, a test interface, and a test point. The test interface includes a power pin, a start pin, and a data signal pin. The power interface is connected to the controller and the power pin, and also connected to an external power to receive a work voltage. The controller transmits a turn-on signal to the start pin. The test point is connected to the data signal pin. When an interface of a motherboard is connected to the test interface, the power pin, the start pin, and the data signal pin are connected to corresponding pins of the interface of the motherboard. The motherboard outputs a data signal to the test point through the motherboard interface and the test interface after the controller receives the turn-on signal. | 03-21-2013 |
20130162276 | PROBE CARD AND METHOD FOR MANUFACTURING SAME - Provided is a probe card including a plurality of unit plates including pad areas and contact probe areas, a plurality of electrode pads formed in the pad areas, a plurality of contact probes formed in the contact probe areas, and a plurality of interconnecting layers electrically connecting the electrode pads and the contact probes. The plurality of unit plates has different sizes and are arranged and laminated so as to expose all the pad areas of each unit plate. | 06-27-2013 |
20130241589 | WIRING BASE PLATE AND METHOD FOR MANUFACTURING THE SAME - In a method for manufacturing a circuit board, as a photomask adapted to form an etching mask for selective removal of a seed layer covering a conductive portion exposed on an insulating film, a photomask whose opening area has an outline having two sides along two straight lines approaching to each other as the two straight lines extend from a center portion of the opening area in an extending direction of a wiring path is used. | 09-19-2013 |
20130265073 | Probe Card And Manufacturing Method Therefor - The present invention provides a ST board | 10-10-2013 |
20140070831 | SYSTEM AND METHOD OF PROTECTING PROBES BY USING AN INTELLIGENT CURRENT SENSING SWITCH - An apparatus and method for protecting probes used in automated testing is disclosed. The apparatus comprises a probe operable to provide power to a device under test (DUT) from a device power source (DPS), wherein the probe is coupled to a contact point on the DUT and a probe protector circuit connected to the probe in series between the DPS and the DUT. The probe protector circuit further comprises a current sense module operable to monitor a flow of current from the DPS to the DUT to determine if the current flow is below a predetermined threshold current level and a switch for controlling the connection from the DPS to the DUT. The switch is coupled to the current sense module and is operable to be used in conjunction with the current sense module to limit the current flow if it exceeds the predetermined threshold current level. | 03-13-2014 |
20140145741 | PROBE CARD AND INSPECTION DEVICE - A probe card comes in touch with a test object to perform an inspection. The probe card contains: a probe substrate provided with a plurality of probes on the first surface and a plurality of anchor receiving portions on the second surface; and a supporting body disposed to support the periphery of the probe substrate, with at least a plurality of anchor receiving portions located within a probe existence region being arranged regularly and at an equal distance from each other on the second surface of the probe substrate. | 05-29-2014 |
20140176173 | PROBE CARD FOR POWER DEVICE - A probe card | 06-26-2014 |
20140184259 | METHOD AND DEVICE FOR TESTING WAFERS - Circuits and methods for testing wafers are disclosed herein. An embodiment of a method includes electrically contacting a first probe and a second probe to a wafer. A gas is blown in the areas proximate the first probe and the second probe. An electric potential is then applied between the first probe and the second probe while the gas is being blown. | 07-03-2014 |
20140306731 | METHOD OF TESTING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR TESTING SYSTEM - A method of testing semiconductor devices is provided includes: exposing one end of the device contact on the surface of the semiconductor; using a scanning probe microscopy apparatus to scan a diagnostic area on the semiconductor; applying a direct current bias between the conductive probe and a substrate of the semiconductor; directing a testing radiation at the diagnostic area to increase amount of free carriers in the device contacts and in the semiconductor layer under the device contacts; and detecting the current flowing through the conductive probe and the substrate, wherein a defect current signal is measured when the probe is in contact with a defective device contact and a normal current signal is measured when the probe is in contact with a normal device contact, wherein the testing radiation increases the current measured to increase the difference between the defect signal and the normal signal. | 10-16-2014 |
20150015290 | PROBE MODULE SUPPORTING LOOPBACK TEST - A probe module, which supports loopback test and is provided between a PCB and a DUT, includes a substrate, a probe base, two probes, two signal path switchers, and a capacitor. The substrate has two first connecting circuits and two second connecting circuits, wherein an end of each first connecting circuit is connected to the PCB. The probe base is provided between the substrate and the DUT with the probes provided thereon, wherein an end of each probe is exposed and electrically connected to one second connecting circuit, while another end thereof is also exposed to contact the DUT. Each signal path switcher is provided on the probe base, and respectively electrically connected to another end of one first and one second connecting circuits. The capacitor is provided on the probe base with two ends electrically connected to the two signal path switchers. | 01-15-2015 |
20150054539 | WIRING BOARD FOR TESTING LOADED PRINTED CIRCUIT BOARD - A wiring board for transmission of test signals between test point locations on a circuit board under test and an external analyzer having compliant contacts making electrical contact with a pad positioned on a conductive surface circuit layer having a trace extending to a second pad having a hole for receipt of an interface pin having a swaged head electrically connected to the external analyzer. | 02-26-2015 |
20150070038 | POGO PIN AND PROBE CARD, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - A pogo pin may include a housing, a resilient connecting member and a switching unit. The housing may be arranged between a printed circuit board (PCB) and a probing head. The resilient connecting member may be arranged in the housing to electrically connect the PCB with the probing head. The switching unit may be provided in the housing to selectively cut off an electrical connection between the PCB and the probing head. Thus, because the PCB may not require additional switching substrates, the PCB may have a small size so that the probe card may also have a small size. A semiconductor device may be manufactured using the probe card. | 03-12-2015 |
20150323566 | CONVERSION CARD FOR USE WITH PROBE CARD - A conversion card is provided for use with a probe card and includes a board and first transmission units, second transmission units, and a DC/AC conversion circuit formed on the board. The first transmission units are electrically connected to test instruments. The second transmission units are electrically connected to a POGO tower. The DC/AC conversion circuit is electrically connected to the first and second transmission units. The first transmission unit is fed with an AC signal that is transmitted through the DC/AC conversion circuit, the second transmission units, and the POGO tower to the probe card. Through the use of AC circuit and transmission line theory, in combination with AC signal test instruments, an AC based process can be used to conduct error analysis tests and improvement of the probe card to prevent mistakenly determine the error rate of the probe card. | 11-12-2015 |
20160103172 | CIRCUIT BOARD TESTING APPARATUS AND CIRCUIT BOARD TESTING METHOD - In a circuit board testing apparatus for performing a four-terminal measurement method on a wiring pattern formed of a plurality of wires on a circuit board, a control part connects in series contact probes to be connected to upstream-side voltage detection terminals or downstream-side voltage detection terminals, via connection terminals, allows a power supply part to apply power between the test points with which the contact probes connected in series are in contact, allows a voltage detection part to detect a voltage between the test points, and makes a determination as to conductive contact states of the contact probes with the test points, based on the detected voltage. | 04-14-2016 |
20160109482 | ELECTRONICS TESTER WITH OUTPUT CIRCUITS OPERABLE IN VOLTAGE COMPENSATED POWER MODE, DRIVER MODE OR CURRENT COMPENSATED POWER MODE - A tester is described having output circuits that are operable in either power mode or driver mode. A switching circuit connects force and sense lines to one of the output circuits when in power mode, or connects the same lines separately to the output circuits when in driver mode. A further configuration allows for power to be provided through the lines separately while detecting a measure of power through each line and correcting for unknown resistances of leads connected to the lines. | 04-21-2016 |
20190146004 | TESTING INTERPOSER METHOD AND APPARATUS | 05-16-2019 |
20220137095 | BOARD-LIKE CONNECTOR, DUAL-RING BRIDGE OF BOARD-LIKE CONNECTOR, AND WAFER TESTING ASSEMBLY - A board-like connector, a dual-ring bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-ring bridges spaced apart from each other and an insulating layer. Each of the dual-ring bridges includes two carrying rings, two cantilevers respectively extending from and being coplanar with the two carrying rings, two abutting columns respectively extending from the two cantilevers along two opposite directions, and a bridging segment that connects the two carrying rings. The insulating layer connects the two carrying rings of the dual-ring bridges, and the two abutting columns of the dual-ring bridges respectively protrude from two opposite sides of the insulating layer. The two abutting columns of each of the dual-ring bridges are configured to be respectively abutted against two boards. | 05-05-2022 |