Class / Patent application number | Description | Number of patent applications / Date published |
324750020 | Calibration of test equipment | 52 |
20100308851 | TESTING DEVICE AND METHOD FOR DETERMINING A COMMON MODE SIGNAL OF AN ELECTRICAL TELECOMMUNICATION - A testing device including: a first terminal configured to be connected to an equipment under test; a common-mode detector configured to detect a common-mode part of a signal emitted from the equipment under test; and a first impedance unit connected in series between the first terminal and the common-mode detector. The first impedance unit is configured to adjust a longitudinal conversion loss of the testing device to a predetermined value. A corresponding method determines a common mode signal of an electrical telecommunication. | 12-09-2010 |
20110012630 | DEVICE FOR CHECKING THE OPERABILITY OF A SENSOR ELEMENT - The invention relates to a device for checking the operability of a sensor element ( | 01-20-2011 |
20110133764 | APPARATUS AND METHOD FOR DETECTING ABNORMALITY IN SOLAR CELL POWER GENERATION SYSTEM - The present invention provides an apparatus for easily detecting an abnormal status of power generation of a solar cell panel in a solar cell power generation system having the power generation of 1 MW or higher. | 06-09-2011 |
20110156730 | CHIP-BASED PROBER FOR HIGH FREQUENCY MEASUREMENTS AND METHODS OF MEASURING - A chip-based prober for measuring a device-under-test is provided. The prober includes a probe tip, a voltage and control connector, a chip carrier, and a programmable termination chip. The probe tip is configured to contact the device-under-test. The voltage and control connector is in electrical communication with the probe tip. The programmable termination chip has a plurality of terminations interconnected with the voltage and control connector and the chip carrier through controlled collapsed chip connections. | 06-30-2011 |
20110181308 | TEST APPARATUS AND TESTING METHOD - A main power supply supplies a power supply voltage to a power supply terminal of a DUT. A control pattern generator generates a control pattern including a pulse sequence. A compensation circuit intermittently injects a compensation current to the power supply terminal of the DUT via a path different from that of the main power supply. A switch is arranged between an output terminal of a voltage source and the power supply terminal of the DUT, and is turned on and off according to the control pattern. | 07-28-2011 |
20110199107 | METHOD AND APPARATUS FOR CALIBRATING A TEST SYSTEM FOR MEASURING A DEVICE UNDER TEST - Methods and apparatus for calibrating a vector network analyzer (VNA) and characterizing a device under test. In one example, a device fixture including a pair of embedded device adapters provides an interface between a device under test (DUT) with non-coaxial connectors and the coaxial connectors of the VNA, and moves the calibration reference plane from the coaxial connectors of the VNA to a DUT reference plane at the leads/connectors of the DUT. A through fixture having a pair of similar through adapters is used to establish the DUT reference plane and to facilitate characterizing the device adapters such that they can be de-embedded from measurements of the device fixture. | 08-18-2011 |
20110291680 | CHUCK FOR SUPPORTING AND RETAINING A TEST SUBSTRATE AND A CALIBRATION SUBSTRATE - A chuck for supporting and retaining a test substrate includes a device for supporting and retaining a calibration substrate. The chuck comprises a first support surface for supporting a test substrate and a second support surface, which is laterally offset to the first support surface, for supporting a calibration substrate. The calibration substrate has planar calibration standards for calibration of a measuring unit of a prober, and dielectric material or air situated below the calibration substrate at least in the area of the calibration standard. In order to be able to take the actual thermal conditions on the test substrate and in particular also on known and unknown calibration standards and thus the thermal influence on the electrical behavior of the calibration standard used into consideration, the second support surface is equipped for temperature control of the calibration substrate. | 12-01-2011 |
20120032695 | METHOD OF AND CIRCUIT FOR BROWN-OUT DETECTION - A circuit and method for detecting a brown-out condition and providing a feed-forward transfer function in a power supply circuit. A comparison circuit is coupled to a delay element through a latch. A second delay element is connected between the first delay element and an input of the latch. The output of the first delay element is connected to a clamping circuit via a logic circuit. A first voltage is compared with a reference voltage to generate a comparison voltage, which is transmitted through the latch and the first delay element. The comparison voltage is monitored at an output of the first delay element. A brown-out condition occurs if the comparison voltage being monitored at the output of the first delay element results from the first voltage being less than the reference voltage. | 02-09-2012 |
20120062256 | TEST APPARATUS, CALIBRATION METHOD AND RECORDING MEDIUM - A test apparatus that tests a device under test, comprising first and second terminal groups including a plurality of drivers that output signals to the device under test; a first common setting section that sets a common delay amount for the signals output from one driver in the first terminal group and one driver in the second terminal group; and an inter-group adjusting section that causes reference phases of the signals output from the drivers in the first terminal group and reference phases of the signals output from the drivers in the second terminal group to draw near each other, based on a delay amount setting value set by the first common setting section when the reference phases in the first terminal group were adjusted and a delay amount setting value set by the first common setting section when the reference phases in the second terminal group were adjusted. | 03-15-2012 |
20120062257 | Semiconductor Device With A Test Circuit And A Reference Circuit - Implementations are presented herein that include a test circuit and a reference circuit. | 03-15-2012 |
20120119766 | PROBE APPARATUS AND METHOD FOR CORRECTING CONTACT POSITION - A probe apparatus includes a movable mounting table for supporting an object to be tested; a probe card disposed above the mounting table and having a plurality of probes to come into contact with electrodes of the object; a support body for supporting the probe card; and a control unit for controlling the mounting table. Electrical characteristics of the object are tested based on a signal from a tester by bringing the object and the probes into electrical contact with each other by overdriving the mounting table in a state where a test head is electrically connected with the probe card by a predetermined load. Further, one or more distance measuring devices for measuring a current overdriving amount of the mounting table are provided at one or more locations of the test head or the probe card. | 05-17-2012 |
20120161803 | APPARATUS AND METHOD FOR NEAR FIELD SCAN CALIBRATION - Disclosed are a method and an apparatus of near field scan calibration, and more particularly, a method and an apparatus for near field scan calibration for calibrating a characteristic of an antenna for near field scan measurement of a semiconductor chip. The apparatus for near field scan calibration includes: a plane-type text fixture having a plane shape; an antenna positioned spaced apart from the plane-type test fixture by a set spacing distance and acquiring data including a magnetic field; and a spectrum analyzer analyzing the data acquired by the antenna. | 06-28-2012 |
20130002275 | SYSTEM AND METHOD FOR MEASURING NEAR FIELD INFORMATION OF DEVICE UNDER TEST - A system and method for measuring near field information of a device under test (DUT) uses a reference probe and a measurement probe that are configured to sense a field. A probe calibration factor is used to determine corresponding field values for signals from the measurement probe at sampling locations about the DUT. The probe calibration factor is derived from measured signals about a conductive trace using a probe and simulated field information for the conductive trace when subjected to a simulated reference signal. | 01-03-2013 |
20130057306 | METHOD AND APPARATUS FOR TESTING A SEMICONDUCTOR DEVICE - The present disclosure provides a method for testing a semiconductor device. The method includes providing a test unit and an electronic circuit that is electrically coupled to the test unit. The method includes performing a multi-dimensional sweeping process. The multi-dimensional sweeping process includes sweeping a plurality of different electrical parameters across their respective ranges. The method includes monitoring a performance of the electronic circuit during the multi-dimensional sweeping process. The monitoring includes identifying optimum values of the different electrical parameters that yield a satisfactory performance of the electronic circuit. The method includes testing the test unit using the optimum values of the different electrical parameters. | 03-07-2013 |
20130069678 | EFFICIENT METHODS AND APPARATUS FOR MARGIN TESTING INTEGRATED CIRCUITS - Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails. | 03-21-2013 |
20130099809 | METHODS AND SYSTEMS FOR PROBING SEMICONDUCTOR WAFERS - A wafer probing method includes calibrating a wafer probing system, checking continuity between probe pins of the wafer probing system and respective conductors of a wafer under test, and identifying at least an interconnect structure in the wafer under test to determine whether a fault exists. | 04-25-2013 |
20130134999 | Signal Acquisition System Having Reduced Probe Loading of a Device Under Test - A signal acquisition system has a signal acquisition probe having probe tip circuitry coupled to a resistive center conductor signal cable. The resistive center conductor signal cable of the signal acquisition probe is coupled to a compensation system in a signal processing instrument via an input node and input circuitry in the signal processing instrument. The signal acquisition probe and the signal processing instrument have mismatched time constants at the input node with the compensation system having an input amplifier with feedback loop circuitry and a shunt pole-zero pair coupled to the input circuitry providing pole-zero pairs for maintaining flatness over the signal acquisition system frequency bandwidth. | 05-30-2013 |
20130187674 | TEST STATION FOR WIRELESS DEVICES AND METHODS FOR CALIBRATION THEREOF - A test station for wireless devices and methods for calibration thereof. The test station includes a signal generator, a calibrator, a scanner having receiving and transmitting antennas, a signal analyzer, and a computer. Under the direction of the computer, the signal generator generates a calibration signal in accordance with a programmable calibration signal script. The calibrator may be used to emulate either a wireless device in transmit mode by transmitting the calibration signal to the scanner for analysis by the signal analyzer, or a wireless device in receive mode by receiving the calibration signal from the scanner for analysis by the signal analyzer. The behavior of the test station is calibrated by correlating signal parameters of the calibration signal as specified by the calibration signal script and as measured at the signal analyzer. | 07-25-2013 |
20130234743 | METHOD FOR TESTING COMPARATOR AND DEVICE THEREFOR - An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal. | 09-12-2013 |
20130271167 | CURRENT TESTS FOR I/O INTERFACE CONNECTORS - Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data communications bus of an integrated circuit on a die, sensing the energy caused by the forced energy at a second pin of the interface, and comparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface. | 10-17-2013 |
20130293249 | Methods for Modeling Tunable Radio-Frequency Elements - A test system for characterizing an antenna tuning element is provided. The test system may include a test host, a radio-frequency tester, and a test fixture. The test system may calibrate the radio-frequency tester using known coaxial standards. The test system may then calibrate transmission line effects associated with the test fixture using a THRU-REFLECT-LINE calibration algorithm. The antenna tuning element may be mounted on a test socket that is part of the test fixture. While the antenna tuning element is mounted on the test socket, scattering parameter measurements may be obtained using the radio-frequency tester. An equivalent circuit model for the test socket can be obtained based on the measured scattering parameters and known characteristics of the antenna tuning element. Once the test socket has been characterized, an equivalent circuit model for the antenna tuning element can be obtained by extracting suitable modeling parameters from the measured scattering parameters. | 11-07-2013 |
20130321012 | Methods and Apparatus for Testing Small Form Factor Antenna Tuning Elements - A test system for testing a device under test (DUT) is provided. The test system may include a DUT receiving structure configured to receive the DUT during testing and a DUT retention structure that is configured to press the DUT against the DUT receiving structure so that DUT cannot inadvertently shift around during testing. The DUT retention structure may include a pressure sensor operable to detect an amount of pressure that is applied to the DUT. The DUT retention structure may be raised and lowered vertically using a manually-controlled or a computer-controlled positioner. The positioner may be adjusted using a coarse tuning knob and a fine tuning knob. The positioner may be calibrated such that the DUT retention structure applies a sufficient amount of pressure on the DUT during production testing. | 12-05-2013 |
20130328582 | Methods and Apparatus for Performing Wafer-Level Testing on Antenna Tuning Elements - A test system for testing an antenna tuning element is provided. The test system may include a tester, a test fixture, and a probing structure. The probing structure may include probe tips configured to mate with corresponding solder bumps formed on a device under test (DUT) containing an antenna tuning element. The DUT may be tested in a shunt or series configuration. The tester may be electrically coupled to the test probe via first and second connectors on the test fixture. An adjustable load circuit that is coupled to the second connector may be configured in a selected state so that a desired amount of electrical stress may be presented to the DUT during testing. The tester may be used to obtain measurement results on the DUT. Systematic effects associated with the test structures may be de-embedded from the measured results to obtain calibrated results. | 12-12-2013 |
20140002119 | METHOD, SYSTEM, AND CONTROL APPARATUS FOR SETTING OVER-CURRENT PROTECTION POINT OF ELECTRONIC DEVICE | 01-02-2014 |
20140021970 | PROBE CARD ANALYSIS SYSTEM AND METHOD - A system and method for evaluating wafer test probe cards under real-world wafer test cell condition integrates wafer test cell components into the probe card inspection and analysis process. Disclosed embodiments may utilize existing and/or modified wafer test cell components such as, a head plate, a test head, a signal delivery system, and a manipulator to emulate wafer test cell dynamics during the probe card inspection and analysis process. | 01-23-2014 |
20140070828 | METHOD AND APPARATUS FOR MASSIVELY PARALLEL MULTI-WAFER TEST - Disclosed herein is a cost effective, efficient, massively parallel multi-wafer test cell. Additionally, this test cell can be used for both single-touchdown and multiple-touchdown applications. The invention uses a novel “split-cartridge” design, combined with a method for aligning wafers when they are separated from the probe card assembly, to create a cost effective, efficient multi-wafer test cell. A “probe-card stops” design may be used within the cartridge to simplify the overall cartridge design and operation. | 03-13-2014 |
20140125363 | SYSTEMS AND METHODS FOR TESTING ELECTRONIC DEVICES THAT INCLUDE LOW POWER OUTPUT DRIVERS - Systems and methods for testing a device under test (DUT) that includes a low power output driver. The methods include providing an input signal to the DUT. The low power output driver is configured to generate a data signal responsive to receipt of the input signal by the DUT and provide the data signal to a signal analyzer via a data signal transmission line. The methods further include determining an expected data signal to be received from the low power output driver and charging at least a portion of the data signal transmission line with a co-drive output signal that is based, at least in part, on the expected data signal. The methods further include receiving a composite data signal with the signal analyzer. The systems include probe heads with a plurality of data signal transmission lines and a plurality of co-drive conductors. | 05-08-2014 |
20140152334 | SEMICONDUCTOR DEVICE - If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit | 06-05-2014 |
20140167794 | Methods for Validating Radio-Frequency Test Stations - A manufacturing system for assembling wireless electronic devices is provided. The manufacturing system may include test stations for testing the radio-frequency performance of components that are to be assembled within the electronic devices. A reference test station may be calibrated using calibration coupons having known radio-frequency characteristics. The calibration coupons may include transmission line structures. The reference test station may measure verification standards to establish baseline measurement data. The verification standards may include circuitry having electrical components with given impedance values. Many verification coupons may be measured to enable testing for a wide range of impedance values. Test stations in the manufacturing system may subsequently measure the verification standards to generate test measurement data. The test measurement data may be compared to the baseline measurement data to characterize the performance of the test stations to ensure consistent test measurements across the test stations. | 06-19-2014 |
20140184253 | In-tool ESD Events Monitoring Method And Apparatus - In one embodiment of the invention, an apparatus for electrostatic discharges (ESD) events monitoring incorporating a charged device model event simulator (CDMES) unit comprises: at least one antenna positioned in a process area; an ESD detector coupled to said at least one antenna; said ESD detector wirelessly coupled to said CDMES unit; and said ESD detector calibrated for different discharge energies generated by said CDMES unit. | 07-03-2014 |
20140203828 | LAYOUT STRUCTURE OF ELECTRONIC ELEMENT AND TESTING METHOD OF THE SAME THEREOF - A layout structure of an electronic element comprising an electronic matrix, a first load and a second load is disclosed. The first load couples to a first end of the electronic matrix and comprises a first testing pad and a second testing pad coupling to the first testing pad. The second load couples to a second end of the electronic matrix and comprises a third testing pad and a fourth testing pad coupling to the third testing pad. | 07-24-2014 |
20140361798 | CALIBRATION DEVICE - An example apparatus is for use in calibration of a test system having multiple channels and a socket for receiving a device under test. The example apparatus includes a device interface that is connectable to the socket; and multiple circuit paths, where each circuit path is connectable, through the device interface, to a corresponding channel of the test system and being connected to a common node. The example apparatus is configured so that, during calibration, signals either (i) each pass from the test system, through one of the multiple circuit paths, and back to the test system through others of the multiple circuit paths, or (ii) each pass from the test system, through the others of the multiple circuit paths, and back to the test system through the one of the multiple circuit paths. | 12-11-2014 |
20140375343 | SOLAR CELL MODULE EFFICACY MONITORING SYSTEM AND MONITORING METHOD THEREFOR - A solar cell module efficacy monitoring system includes a reference module which includes a solar power generation module and is to be maintained in a clean condition, an evaluation module which includes a solar power generation module and is to be covered by dust in an environment, maximum power point tracking devices which track powers of the reference module and the evaluation module and maintain power outputs at maximum points by connected to the reference module and the evaluation module, respectively, and, a PV communication recording device which records power generation results of the reference module and the evaluation module by connected to the reference module and the evaluation module, and a calculation display device which calculates power loss due to accumulation of dust on the evaluation module by connected to the PV communication recording device. | 12-25-2014 |
20150028899 | SYSTEMS AND METHODS MITIGATING TEMPERATURE DEPENDENCE OF CIRCUITRY IN ELECTRONIC DEVICES - Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system. | 01-29-2015 |
20150028900 | SYSTEMS AND METHODS MITIGATING TEMPERATURE DEPENDENCE OF CIRCUITRY IN ELECTRONIC DEVICES - Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system. | 01-29-2015 |
20150028901 | SYSTEMS AND METHODS MITIGATING TEMPERATURE DEPENDENCE OF CIRCUITRY IN ELECTRONIC DEVICES - Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system. | 01-29-2015 |
20150028902 | SYSTEMS AND METHODS MITIGATING TEMPERATURE DEPENDENCE OF CIRCUITRY IN ELECTRONIC DEVICES - Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system. | 01-29-2015 |
20150028903 | SYSTEMS AND METHODS MITIGATING TEMPERATURE DEPENDENCE OF CIRCUITRY IN ELECTRONIC DEVICES - Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system. | 01-29-2015 |
20150028904 | SYSTEMS AND METHODS MITIGATING TEMPERATURE DEPENDENCE OF CIRCUITRY IN ELECTRONIC DEVICES - Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system. | 01-29-2015 |
20150028905 | SYSTEMS AND METHODS MITIGATING TEMPERATURE DEPENDENCE OF CIRCUITRY IN ELECTRONIC DEVICES - Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system. | 01-29-2015 |
20150028906 | SYSTEMS AND METHODS MITIGATING TEMPERATURE DEPENDENCE OF CIRCUITRY IN ELECTRONIC DEVICES - Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system. | 01-29-2015 |
20150054534 | METHOD OF MEASURING AND ASSESSING A PROBE CARD WITH AN INSPECTION DEVICE - A method of assessing functionality of a probe card includes providing a probe card analyzer without a probe card interface, removably coupling a probe card having probes to a support plate of the probe card analyzer, aligning a sensor head of the probe card analyzer with the probe card, and measuring a component of the probes with the sensor head. | 02-26-2015 |
20150061708 | Detection Method of Current Sensor Faults in the E-Drive System By Using the Voltage Command Error - Systems, apparatus, and methods detect a current sensor error in an FOC electric machine system. A voltage command is monitored to detect the presence of an ac component can indicate that an error has occurred at a current sensor. By way of example, a sensor fault detection module can be configured to determine the deviation between an actual voltage command and an ideal voltage command to provide a complex deviation vector. By transforming the deviation vector to a reference frame rotating at the fundamental frequency of the command voltage, a dc component of the positive and negative sequences can be filtered, and their amplitudes determined. Error detection can be based on the total amplitude of the fundamental component, determined by positive and negative component amplitudes. The invention enables an FOC system to operate with two current sensors, rather than three, and provides a dedicated fault diagnostic for a current sensor. | 03-05-2015 |
20150130485 | MODULATED TEST MESSAGING FROM DEDICATED TEST CIRCUITRY TO POWER TERMINAL - The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals. | 05-14-2015 |
20150301109 | Synchronous Sampling of Internal State for Investigation of Digital Systems - Methods and apparatus are provided for sampling an indicator of the internal state of an embedded system or integrated circuit, where the indicator is sampled in a manner synchronous to the internal clock of the embedded system or integrated circuit. The resulting samples can be used for determining secret data within the embedded system or integrated circuit, detecting failures, or detecting counterfeit devices. | 10-22-2015 |
20150338494 | WORK FUNCTION CALIBRATION OF A NON-CONTACT VOLTAGE SENSOR - A method and a system for calibrating the work function or surface potential of a non-contact voltage sensor probe tip are provided. The method includes preparing one or more reference sample surfaces and a reference non-contact voltage sensor probe tip to have stable surface potentials, measuring the voltage between the reference samples and the reference sensor probe tip, measuring the voltage between a point on a non-reference sample surface and the reference sensor probe tip, measuring the voltage between the same point on the non-reference sample surface and a non-reference non-contact voltage sensor probe tip, and determining a surface potential correction factor for the non-reference, non-contact voltage sensor. | 11-26-2015 |
20150369898 | PHASE NOISE CORRECTION SYSTEM FOR DISCRETE TIME SIGNAL PROCESSING - Embodiments of the invention include a test and measurement instrument including a test signal input and a sampler coupled to the test signal input to generate a sampled test signal. The instrument also includes a noise reduction system that includes an additional oscillator coupled to the sampler and structured to generate a sampled oscillating signal, as well as a phase detector coupled to the sampled oscillating signal for measuring noise introduced by the sampler. The noise reduction system further includes a phase corrector coupled to the phase detector for removing the measured amount of noise from the sampled test signal. Methods of noise detection are also described. | 12-24-2015 |
20150369899 | METHOD FOR CHARACTERISING AN ELECTRICAL CONNECTION DEVICE INTENDED TO BE HYBRIDIZED TO AN ELECTRONIC DEVICE - Method for characterizing an electrical connection device intended to be hybridized to an electronic device and comprising electrical connection elements each intended to be in electrical contact with at least one of a plurality of contact pads of the electronic device which are electrically connected together, including at least one step of selection of a reference electrical connection element from among said electrical connection elements, then, for the or each of the electrical connection elements other than the reference electrical connection element, the implementation of the following steps:
| 12-24-2015 |
20160069930 | STATIC ELECTRICITY NEUTRALIZING DEVICE AND STATIC ELECTRICITY NEUTRALIZING METHOD - To neutralize static electricity in a charged coaxial cable with a decreased installation space. The first base member | 03-10-2016 |
20160124066 | CALIBRATION BOARD AND TIMING CALIBRATION METHOD THEREOF - A calibration board and a timing calibration method thereof are provided. The calibration board for calibrating signal delays of test channels in an automatic test equipment is pluggably disposed in the automatic test equipment and includes calibration groups, a first common node, and a switching module. Each calibration group includes a second common node and conductive pads electrically connecting to the second common node. Each conductive pad selectively and electrically connects to one test channel. The switching module electrically connects to the first common node and each second common node. When a first delay calibration procedure is performed, the connection between the first common node and each second common node is disabled. When a second delay calibration procedure is performed, the connection between the first common node and each second common node is built. | 05-05-2016 |
20160169962 | Automated Test Equipment for Testing a Device Under Test and Method for Testing a Device Under Test | 06-16-2016 |
20190146013 | CURRENT-SENSE RATIO CALIBRATION | 05-16-2019 |