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DESIGN OF SEMICONDUCTOR MASK

Subclass of:

716 - Data processing: design and analysis of circuit or semiconductor mask

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
716021000 Pattern exposure 78
716020000 Mesh generation 21
Entries
DocumentTitleDate
20090193385Method of checking and correcting mask pattern - The present invention provides a method of checking and correcting a mask pattern. The method includes inputting a mask pattern, wherein the mask pattern includes at least a segment; inputting a process rule; selecting an edge, which fits in with an orientation model, as a target edge, wherein two ends of the target edge are an ahead direction and a behind direction, and the ahead direction and the behind direction each further comprise at least a checking point; identifying an interacting edge from the mask pattern along the checking directions; performing a process rule check to provide a correcting value; performing a first correction to provide a first bias to the target edge; and performing a second correction to provide a second bias to the interacting edge, wherein a sum of the first bias and the second bias equals the correcting value.07-30-2009
20100011335GRID-BASED FRAGMENTATION FOR OPTICAL PROXIMITY CORRECTION IN PHOTOLITHOGRAPHY MASK APPLICATIONS - An optical proximity correction (OPC) method for photolithography applications can be utilized to reduce the processing time, cost, and post-OPC file size associated with conventional methods. The OPC method provides a target layout pattern that represents a corresponding mask pattern for a photolithography mask, and aligns the target layout pattern relative to a suitably dimensioned fragmentation grid. Then, at least one feature of the target layout pattern is fragmented using the fragmentation grid. Thereafter, a fragment data set is generated in response to the grid-based fragmentation of the target layout pattern.01-14-2010
20100115489METHOD AND SYSTEM FOR PERFORMING LITHOGRAPHY VERIFICATION FOR A DOUBLE-PATTERNING PROCESS - One embodiment of the present invention provides a system that performs lithography verification for a double-patterning process on a mask layout without performing a full contour simulation of the mask layout. During operation, the system starts by receiving a first mask which is used in a first lithography step of the double-patterning process, and a second mask which is used in a second lithography step of the double-patterning process. Note that the first mask and the second mask are obtained by partitioning the mask layout. Next, the system receives an evaluation point on the mask layout. The system then determines whether the evaluation point is exclusively located on a polygon of the first mask, exclusively located on a polygon of the second mask, or located elsewhere. The system next computes a printing indicator at the evaluation point for the mask layout based on whether the evaluation point is exclusively located on a polygon of the first mask or exclusively located on a polygon of the second mask.05-06-2010
20100037199RECORDING MEDIUM STORING ORIGINAL DATA GENERATION PROGRAM, ORIGINAL DATA GENERATION METHOD, ORIGINAL FABRICATING METHOD, EXPOSURE METHOD, AND DEVICE MANUFACTURING METHOD - To calculate data of an original, a computer is caused to execute the following steps of converting data regarding an intended pattern to be formed on a substrate into frequency-domain data, calculating a two-dimensional transmission cross coefficient using a function representing an effective light source that an illumination device forms on a pupil plane of a projection optical system when the original is absent on an object plane of the projection optical system and using a pupil function of the projection optical system, calculating a diffracted light distribution from a pattern that is formed on the object plane using both the frequency-domain data and data of at least one component of the calculated two-dimensional transmission cross coefficient, and converting data of the calculated diffracted light distribution into spatial-domain data to determine the data of the original.02-11-2010
20100042967MEEF REDUCTION BY ELONGATION OF SQUARE SHAPES - A method that purposely relaxes OPC algorithm constraints to allow post OPC mask shapes to elongate along one direction (particularly lowering the 1-dimensional MEEF in this direction with the result of an effectively overall lowered MEEF) to produce a pattern on wafer that is circular to within an acceptable tolerance.02-18-2010
20090187876STEINER TREE BASED APPROACH FOR POLYGON FRACTURING - Roughly described, a method for mask data preparation is described, for use with a preliminary mask layout that includes a starting polygon, the vertices of the starting polygon including I-points (vertices of the starting polygon having an interior angle greater than 90 degrees), including steps of developing a rectilinear partition tree on at least the I-points of the starting polygon, and using the edges of the partition tree to define the partition of the starting polygon into sub-polygons for mask writing.07-23-2009
20100023914Use Of Graphs To Decompose Layout Design Data - Techniques are disclosed for determining if the decomposition of layout design data is feasible, and for optimizing the segmentation of polygons in decomposable layout design data. Layout design data is analyzed to identify the edges of polygons that should be imaged by separate lithographic masks. In addition, proposed cut paths are generated to cut the polygons in the layout design data into a plurality of polygon segments. Once the separated edges and cut paths have been selected, a conflict graph is constructed that reflects these relationships. Next, a dual of the conflict graph is constructed. This dual graph will have a corresponding separation dual graph edge for each separated polygon edge pair in the layout design data. The dual graph also will have a corresponding cut path dual graph edge for each proposed cut path generated for the layout design data. After the dual graph has been constructed, it is analyzed to determine which of the proposed cut paths should be kept and which should be discarded. The layout design data is then modified to include the cut paths corresponding to the selected cut path dual graph edges. Alternately or additionally, separate sets of layout design data may be decomposed from original layout design data using the selected cut paths.01-28-2010
20090125864SYSTEM AND METHOD FOR MAKING PHOTOMASKS - The present application is directed a method for preparing a mask pattern database for proximity correction. The method comprises receiving data from a design database. Mask pattern data describing a first photomask pattern for forming first device features is generated. The first photomask pattern is to be corrected for proximity effects in a proximity correction process. A second set of data is accessed comprising information about second device features, wherein at least a portion of the second set of data is relevant to the proximity correction process. The second set of data is manipulated so as to improve the proximity correction process, as compared with the same proximity correction process in which the second set of data was included in the mask pattern database without being manipulated. At least a portion of the mask pattern data and at least a portion of the manipulated second set of data is included in the mask pattern database.05-14-2009
20090125863TREATMENT OF TRIM PHOTOMASK DATA FOR ALTERNATING PHASE SHIFT LITHOGRAPHY - In accordance with the invention, there is a method of designing a lithography mask. The method can comprise generating initial phase photomask data and initial trim photomask data from a first set of data from a first drawn layer and/or layout and a second set of data from a second drawn layer, combining the initial phase photomask data with the first set of data to form a combined layer, inspecting for gaps in the combined layer, and processing the gaps in the combined layer.05-14-2009
20090125868MULTILAYER OPC FOR DESIGN AWARE MANUFACTURING - A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.05-14-2009
20090125865SYSTEM AND METHOD FOR MAKING PHOTOMASKS - The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.05-14-2009
20100095264METHOD AND APPARATUS FOR DETERMINING A PHOTOLITHOGRAPHY PROCESS MODEL WHICH MODELS THE INFLUENCE OF TOPOGRAPHY VARIATIONS - One embodiment provides a system for determining a process model for a photolithography process. The photolithography process can use multiple exposure-and-development steps to create features on a wafer. When the photolithography process exposes the wafer to a layout, the wafer can include topography variations which were caused by previous exposure-and-development steps. The process model can be used to predict patterns that are created on the wafer when the wafer is exposed to a second layout, wherein the wafer includes topography variations that were caused by resist features that were created when the wafer was exposed to a first layout. The process model can include a first term and a second term, wherein the first term is convolved with a sum of the first layout and the second layout, and wherein the second term is convolved with the second layout.04-15-2010
20100064273Method for Compensating for Variations in Structures of an Integrated Circuit - A method of for compensating for variations in structures of an integrated circuit. The method includes (a) selecting a mask design shape and selecting a region of the mask design shape; (b) applying a model-based optical proximity correction to all of the mask design shape; and after (b), (c) applying a rules-based optical proximity correction to the selected region of the mask design shape.03-11-2010
20090044166EXPOSING MASK AND PRODUCTION METHOD THEREFOR AND EXPOSING METHOD - An exposure mask forms a three-dimensional shape in simple structure and obtainable sufficient number of gray scales by exposure. In an exposure mask (M) for use in an exposure apparatus (S), the present invention is provided such that a plurality of pattern blocks constituted by a pair of a light blocking pattern blocking light emitted from the exposure apparatus (S) and a transmissive pattern transmitting the light are continuously arranged while a pitch of the continuous pattern blocks is constant and a ratio of the light blocking pattern to the transmissive pattern is varied gradually.02-12-2009
20090307649SYSTEM AND METHOD FOR MODIFYING A DATA SET OF A PHOTOMASK - The present invention provides a method for compensating, infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.12-10-2009
20090271759CONTRAST-BASED RESOLUTION ENHANCEMENT FOR PHOTOLITHOGRAPHIC PROCESSING - A contrast-based resolution enhancing technology (RET) determines a distribution of contrast values for edge fragments in a design layout or portion thereof. Resolution enhancement is applied to the edge fragments in a way that increases the number of edge fragments having a contrast value that exceeds a predetermined threshold.10-29-2009
20090271758METHODS FOR FORMING ARRAYS OF SMALL, CLOSELY SPACED FEATURES - Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed patterns of crossing elongate features with pillars at the intersections. Spacers are simultaneously applied to sidewalls of both sets of crossing lines to produce a pitch-doubled grid pattern. The pillars facilitate rows of spacers bridging columns of spacers.10-29-2009
20090271757DATA CORRECTING HIERARCHICAL INTEGRATED CIRCUIT LAYOUT ACCOMMODATING COMPENSATE FOR LONG RANGE CRITICAL DIMENSION VARIATION - A solution for performing a data correction on a hierarchical integrated circuit layout is provided. A method includes: receiving a CD compensation map for the long range critical dimension variation prior to the data correction; grouping compensation amounts of the CD compensation into multiple compensation ranges; generating multiple target layers corresponding to the multiple compensation ranges; super-imposing a region of the CD compensation map having a compensation amount falling into a compensation range over a respective target layer to generate a target shape; performing the data correction on the layout to generate a data corrected layout; performing the data correction on the target shape separately to generate a data corrected target shape; and combining the data corrected layout and the data corrected target shape based on the CD compensation map.10-29-2009
20080201684SIMULATION SITE PLACEMENT FOR LITHOGRAPHIC PROCESS MODELS - A method and system for performing the method are provided for designing a mask layout that includes selecting simulation sites for optical proximity correction (OPC) or mask verification, prior to fragmentation of shape edges. The primary simulation sites are selected based upon the influence of adjacent shapes, and then fragmentation is performed based on the primary simulation sites. Preferably, the simulation sites are selected by initial simulation within a region of influence of the vertices of mask shapes. The extrema of the resulting simulations are identified, and the intersection of a projection from the extrema to shape edges is used to define the primary simulation sites. Fragmentation of the edges may then be performed as long as the primary simulation sites thus selected are retained. The resulting simulation sites will allow the OPC engine to more effectively correct the shapes where the greatest influences will occur.08-21-2008
20080256504MASK PATTERN DESIGN METHOD AND SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR DESIGN PROGRAM - A mask pattern design method includes: dividing design layout data for a pattern into multiple regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of the pattern from the plurality of regions exceeds a predetermined allowance range; setting a process window of which multiple transfer conditions of the pattern data from the region extracted by the process are each changed, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; and extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with the process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition.10-16-2008
20090013303METHOD OF CREATING MASK LAYOUT IMAGE AND IMAGING SYSTEM - Provided are a method of creating a mask layout image from a target image, a computer readable storage medium having stored thereon a computer program for executing the method, and an imaging system. The method includes reading all or a part of a target image to be transcribed on a substrate; defining a mask data set including a plurality of pixels having a predetermined transmittance characteristic; defining a weighting function having a non-zero value within a critical range; defining a convolution kernel determined by an illumination meter; and creating the mask layout image that minimizes an image fitting function by using the weighting function and the convolution kernel.01-08-2009
20090013302METHODS OF ARRANGING MASK PATTERNS RESPONSIVE TO ASSIST FEATURE CONTRIBUTION TO IMAGE INTENSITY AND ASSOCIATED APPARATUS - Methods and apparatus are disclosed that arrange mask patterns in response to the contribution of an assist feature to image intensity. In some methods of arranging mask patterns, a distribution of functions h(ξ−x) is obtained which represents the contribution of an assist feature to image intensity on a main feature. Neighboring regions of the main feature are discretized into finite regions, and the distribution of the functions h(ξ−x) is replaced with representative values 01-08-2009
20090007051SELECTABLE DEVICE OPTIONS FOR CHARACTERIZING SEMICONDUCTOR DEVICES - A system, method and program product that allows multiple devices to be placed between pads such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system is disclosed for implementing a testsite for characterizing devices in an integrated circuit technology, and includes: a system for designing a plurality of device options for a set of chip pads; a system for designing a pseudo wiring layout for each of the plurality of device options; a system for selecting one of the device options; a system for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and a system for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option.01-01-2009
20080295060Method for Forming a Semiconductor Device Using Optical Proximity Correction for the Optical Lithography - A method for forming a semiconductor device includes performing a first optimization of a first edge location of a feature fragment, wherein the first optimization has a first speed per fragment, and performing a second optimization of a second edge location of the feature fragment, wherein the second optimization has a second speed per fragment that is slower than the first speed per fragment. Next, a result of the second optimization is used to form a reticle pattern; and a layer on a semiconductor wafer is patterned using the reticle pattern.11-27-2008
20080295059Method for Correcting Optical Proximity Effect - A method of correcting an optical proximity effect may include the steps of: fabricating a test mask having test patterns; projecting patterns on a wafer using the test mask; measuring line widths of the patterns formed on the wafer; and executing a model calibration using the measured line widths and writing a correction recipe. The entire area of the wafer chip may be divided into a plurality of templates. An optical proximity correction may be executed on one of the templates and it may be verified that the optical proximity correction was executed properly on another template. The data for the templates that pass a verification may be merged and final data may be written using the merged data. A photomask may be fabricated using the final data.11-27-2008
20080216047Intermediate Layout for Resolution Enhancement in Semiconductor Fabrication - Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.09-04-2008
20090293039METHOD FOR MANUFACTURING A PHOTOMASK - A method for manufacturing a photomask based on design data includes the steps of forming a figure element group including a figure element in a layout pattern on the photomask and a figure element affecting the figure element due to the optical proximity effect, adding identical identification data to a data group indicating an identical figure element group, estimating an influence of the optical proximity effect on the figure element group, generating correction data indicating a corrected figure element in which the influence of the optical proximity effect is compensated for at the time of exposure, creating figure data by associating data having the identical identification data with correction data having the identical identification data, and forming a mask pattern on the photomask using figure data. Thus, the computation time for correction of the layout can be reduced, thereby reducing the production time of the photomask.11-26-2009
20090150850METHOD AND APPARATUS FOR IDENTIFYING AND CORRECTING PHASE CONFLICTS - One embodiment of the present invention provides a system that identifies a substantially minimal set of phase conflicts in a PSM-layout that when corrected renders the layout phase-assignable. During operation, the system constructs a phase-conflict graph from a PSM-layout. Next, the system removes a first set of edges from the phase-conflict graph to make the graph planar, and then removes a second set of edges to make the graph bipartite. The system then adds zero or more edges of the first set of edges, and determines a set of phase conflicts in the PSM-layout based on the remaining edges in the first set of edges and the second set of edges. Next, the system identifies a set of lines in the layout, such that adding space along the set of lines results in a phase-assignable PSM-layout.06-11-2009
20100122231ELECTRICALLY-DRIVEN OPTICAL PROXIMITY CORRECTION TO COMPENSATE FOR NON-OPTICAL EFFECTS - A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.05-13-2010
20080282217METHOD FOR CREATING MASK LAYOUT DATA, APPARATUS FOR CREATING MASK LAYOUT DATA, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to mask layout data created for a particular factory facility, transistors constituting a semiconductor device are classified into multiple groups depending on the gate length. Thereafter, the concentration of impurity introduced into a channel layer is set for each group, and thereby the gate length-threshold characteristics of a transistor are controlled. An overlapping area of a gate electrode and an element region of a certain group is extracted from mask layout data. The overlapping area is expanded to determine the shape of a mask used in injecting impurity in a channel layer. The data on the mask shape is then added to the mask layout data.11-13-2008
20090089736FACILITATING PROCESS MODEL ACCURACY BY MODELING MASK CORNER ROUNDING EFFECTS - An embodiment provides systems and techniques for determining an improved process model which models mask corner rounding (MCR) effects. During operation, the system may receive a mask layout and process data which was generated by applying a photolithography process to the mask layout. The system may also receive an uncalibrated process model which may contain a set of MCR components. Next, the system may identify a set of corners in the mask layout. The system may then modify the mask layout in proximity to the set of corners to obtain a modified mask layout. Alternatively, the system may determine a set of mask layers. Next, the system may determine an improved process model by calibrating the uncalibrated process model using the modified mask layout and/or the set of mask layers, and the process data.04-02-2009
20090276750METHOD FOR ESTABLISHING SCATTERING BAR RULE - A method for establishing a scattering bar rule for a mask pattern for fabricating a device is provided. The method is described as follows. First, at least one image simulation model is established according to the mask pattern and a process reference set used for fabricating the device based on the mask pattern. Next, a plurality of scattering bar reference sets is applied to the image simulation model so as to generate a plurality of simulation images, respectively. Further, a portion of the simulation images are selected to be a plurality of candidate layouts according to a screening criterion. Next, one of the candidate layouts is determined to be a pattern layout according to a selection rule, and the scattering bar reference set corresponding to the pattern layout is determined to be a scattering bar rule of the mask pattern.11-05-2009
20080216048Yield Profile Manipulator - A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.09-04-2008
20080216046PATTERN MANAGEMENT METHOD AND PATTERN MANAGEMENT PROGRAM - A pattern management method includes extracting patterns having process margins equal to or below a predetermined value from a chip layout of an integrated circuit, screening a plurality of types of representative patterns from the extracted pattern, extracting patterns closest to the most outer periphery of the chip from the representative patterns, and representatively managing the extracted patterns which is closest to the most outer periphery of the chip.09-04-2008
20090119634Method and System for Implementing Controlled Breaks Between Features Using Sub-Resolution Assist Features - Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems.05-07-2009
20100005440CALIBRATION AND VERIFICATAION STRUCTURES FOR USE IN OPTICAL PROXIMITY CORRECTION - A method of training an Optical Proximity Correction (OPC) model comprises symmetrizing a complex design to be a test pattern having orthogonal symmetry. Symmetrizing may comprise establishing a axis of symmetry passing through the design, thereby dividing the design into two portions; deleting one of the two portions; and mirror-imaging the other of the two portions about the axis of symmetry. The design may be centered.01-07-2010
20080250381PARAMETER ADJUSTMENT METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND RECORDING MEDIUM - A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device so as to fall within a range of a predetermined permissible variation and defining the adjusted parameter as a reference parameter of the reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate using the reference manufacturing device from a mask to form the pattern on the substrate when the reference parameter is set to the reference manufacturing device and defining the obtained first shape as a reference finished shape; defining an adjustable parameter of another to-be-adjusted manufacturing device as a to-be-adjusted parameter of the to-be-adjusted manufacturing device; obtaining a second shape of the pattern formed on the substrate using the to-be-adjusted manufacturing device from the mask when the defined to-be-adjusted parameter is set to the to-be-adjusted manufacturing device and defining the obtained second shape as a to-be-adjusted finished shape; calculating a difference amount between the reference finished shape and the to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter having the difference amount equal to or less than the predetermined reference value or the to-be-adjusted parameter having the difference amount which becomes equal to or less than the predetermined reference value through the repeated calculation.10-09-2008
20080288912METHOD OF INSPECTING MASK USING AERIAL IMAGE INSPECTION APPARATUS - A method of precisely inspecting the entire surface of a mask at a high speed in consideration of optical effects of the mask. The method includes designing a target mask layout for a pattern to be formed on a wafer, and extracting an effective mask layout using an inspection image measured from the target mask layout using an aerial image inspection apparatus as a mask inspection apparatus. The effective mask layout is input to a wafer simulation tool for calculating a wafer image to be formed on the wafer. Optical effects of the mask are detected by comparing the target mask layout with the effective mask layout.11-20-2008
20080270969METHOD FOR CORRECTING PHOTOMASK PATTERN - A method for correcting a photomask pattern is provided. The correcting method performs a verification of a focus-exposure matrix (FEM) and an overlay variation on a layout area having contact holes or vias in a layout pattern so as to generate a hint information. The layout pattern of the photomask is corrected according to the hint information to prevent the contact holes or vias from being exposed in arrangement to corresponding metal layer, poly layer, or diffusion layer.10-30-2008
20080270970Method for processing pattern data and method for manufacturing electronic device - A method for processing data for a mask pattern. The method includes analyzing data of the mask pattern and specifying a pattern region having a predetermined shape and a predetermined dimension from the mask pattern. The pattern region functions as an alignment mark.10-30-2008
20100146476MODELING MASK CORNER ROUNDING EFFECTS USING MULTIPLE MASK LAYERS - An embodiment provides systems and techniques for determining an improved process model which models mask corner rounding (MCR) effects. During operation, the system may receive a mask layout and process data which was generated by applying a photolithography process to the mask layout. The system may also receive an uncalibrated process model which may contain a set of MCR components. Next, the system may identify a set of corners in the mask layout. The system may then determine a set of mask layers, wherein at least some of the mask layers correspond to the MCR components. Next, the system may determine an improved process model by calibrating the uncalibrated process model using the set of mask layers, and the process data.06-10-2010
20100146475METHODS AND SYSTEM FOR MODEL-BASED GENERIC MATCHING AND TUNING - The present invention relates to a method for tuning lithography systems so as to allow different lithography systems to image different patterns utilizing a known process that does not require a trial and error process to be performed to optimize the process and lithography system settings for each individual lithography system. According to some aspects, the present invention relates to a method for a generic model-based matching and tuning which works for any pattern. Thus it eliminates the requirements for CD measurements or gauge selection. According to further aspects, the invention is also versatile in that it can be combined with certain conventional techniques to deliver excellent performance for certain important patterns while achieving universal pattern coverage at the same time.06-10-2010
20090049420Dummy pattern placement apparatus, method and program and semiconductor device - The load of OPC processing (especially, the load of bias processing) has been increasing due to optical effects involved in the placement of a dummy pattern. A pattern placement apparatus places dummy patterns in a layout region where a plurality of wiring patterns is placed. The pattern placement apparatus comprises: a placement region setting section that sets a placement region, where each of the dummy patterns should be placed, in an intermediate region between the adjacent wiring patterns at substantially constant intervals to the adjacent writing patterns; and a pattern placement section that places the dummy pattern in the placement region.02-19-2009
20090144691Enhanced Process Yield Using a Hot-Spot Library - The invention provides apparatus and methods for processing substrates using a hot-spot library.06-04-2009
20090024978SEMICONDUCTOR DEVICE MASK, METHOD OF FORMING THE SAME AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - Embodiments relate to a semiconductor device mask in which an optical proximity correction (OPC) process is performed to compensate for varying degrees of planarization of a lower layer and a method of forming a mask pattern. In embodiments, a method of forming a semiconductor device mask includes dividing a semiconductor substrate into a plurality of local regions. Densities of patterns of the local regions are determined. A degree of dishing of the local regions is also determined. The local regions are classified into a first group in case where the degree dishing of the local regions are within an error range and a second group in case where the degree of dishing of the local regions exceed the error range. A mask data preparation process is performed with a size retrieved from a basic database in the first group. A mask data preparation sizing rule different from the mask data preparation process is applied to the second group. An optical proximity correction process is performed using a database of the first group and the second group. A semiconductor device mask according to an embodiment is formed using a semiconductor device mask formation process.01-22-2009
20090199150Step-Walk Relaxation Method for Global Optimization of Masks - A set of candidate global optima is identified, one of which is a global solution for making a mask for printing a lithographic pattern. A solution space is formed from dominant joint eigenvectors that is constrained for bright and dark areas of the printed pattern. The solution space is mapped to identify regions each containing at most one local minimum intensity. For each selected region, stepped intensity contours are generated for intensity of the dark areas and stepped constraint surfaces are generated for a target exposure dose at an individual test point. An individual test point is stepped toward a lowest intensity contour along the stepped constraint surfaces of each selected region. Further lowering of the intensities of these points is also detailed, where possible in adjacent regions, to yield final test points. The set of candidate global optima is the final test points at their respective lowest intensity contour of the respective selected regions.08-06-2009
20090100400Phase-shifting masks with sub-wavelength diffractive optical elements - The present invention discloses a method of designing a set of two tiled masks, as well as, a mask including: a first tile, the first tile being transparent to a light, the first tile having a first characteristic linear dimension that is 15% or less of a wavelength of the light; a second tile, the second tile being transparent to the light, the second tile having a second characteristic linear dimension that is 15% or less of the wavelength of the light; and a third tile, the third tile being opaque to the light, the third tile having a third characteristic linear dimension that is 15% or less of the wavelength of the light.04-16-2009
20100199256PERFORMING OPTICAL PROXIMITY CORRECTION BY INCORPORATING CRITICAL DIMENSION CORRECTION - A solution for performing an optical proximity correction (OPC) process on a layout by incorporating a critical dimension (CD) correction is provided. A method may include separating the layout into a first portion and a second portion corresponding to the two exposures; creating a model for calculating a CD correction for a site on the first portion, the model corresponding to a topography change on the site due to the double exposures; implementing an OPC iteration for the fragment based on the model to generate an OPC solution for the first portion; and combining the OPC solution for the first portion with an OPC solution for the second portion to generate an OPC solution for the layout to generate a mask for fabricating a structure using the layout.08-05-2010
20090222785METHOD FOR SHAPE AND TIMING EQUIVALENT DIMENSION EXTRACTION - An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.09-03-2009
20100162196STRUCTURE AND METHODOLOGY FOR FABRICATION AND INSPECTION OF PHOTOMASKS - A photomask, method of designing, of fabricating, of designing, a method of inspecting and a system for designing the photomask. The photomask, includes: a cell region, the cell region comprising one or more chip regions, each chip region comprising a pattern of opaque and clear sub-regions corresponding to features of an integrated circuit chip and one or more kerf regions, each kerf region comprising a pattern of opaque and clear sub-regions corresponding to features of an integrated circuit kerf; a clear region formed adjacent to a side of a copy region, the copy region comprising opaque and clear sub-regions that are copies of at least a part of the cell region; and an opaque region between the clear region and the cell region.06-24-2010
20100185998METHOD FOR OPC CORRECTION - An optical proximity correction method is disclosed, comprising establishing an optical proximity correction (OPC) model, and performing an OPC correction step to correct segments of a layout pattern. The OPC correction comprises the step of defining an edge of the layout pattern neighboring a hot-spot location on a mask to locate a target point and a dissection point. The step of locating the target point and the dissection point includes setting a plurality of pre-target points and pre-dissection points, and electing a target point and a dissection point for correcting the segments of the layout pattern from the pre-target points and pre-dissection points according to image quality of the pre-target points and pre-dissection points.07-22-2010
20100262946Model-based assist feature placement using inverse imaging approach - Some embodiments provide techniques and systems to identify locations in a target mask layout for placing assist features. During operation, an embodiment can determine a spatial sampling frequency to sample the target mask layout, wherein sampling the target mask layout at the spatial sampling frequency prevents spatial aliasing in a gradient of a cost function which is used for computing an inverse mask field. Next, the system can generate a grayscale image by sampling the target mask layout at the spatial sampling frequency. The system can then compute the inverse mask field by iteratively modifying the grayscale image. The system can use the gradient of the cost function to guide the iterative modification process. Next, the system can filter the inverse mask field using a morphological operator, and use the filtered inverse mask field to identify assist feature locations in the target mask layout.10-14-2010
20100229147SYSTEM AND METHOD FOR CREATING A FOCUS-EXPOSURE MODEL OF A LITHOGRAPHY PROCESS - A system and a method for creating a focus-exposure model of a lithography process are disclosed. The system and the method utilize calibration data along multiple dimensions of parameter variations, in particular within an exposure-defocus process window space. The system and the method provide a unified set of model parameter values that result in better accuracy and robustness of simulations at nominal process conditions, as well as the ability to predict lithographic performance at any point continuously throughout a complete process window area without a need for recalibration at different settings. With a smaller number of measurements required than the prior-art multiple-model calibration, the focus-exposure model provides more predictive and more robust model parameter values that can be used at any location in the process window.09-09-2010
20090077524METHOD OF MANUFACTURING PHOTOMASK - A technique for quantitatively expressing a manufacturing difficulty level of a photomask and for efficiently manufacturing the photomask is provided. A mask manufacturing difficulty level different for each mask layout, product, and mask layer is relatively recognized with a mask manufacturing load index calculated by a mask manufacturing load prediction system, and when layout correction is possible, the final layout is corrected to a layout with a low difficulty level, and a mask ordering party provides a mask manufacturer with information regarding the mask manufacturing difficulty level in an early stage. The mask manufacturing load index is expressed with a defect guarantee load index and a lithography load index.03-19-2009
20100162195METHOD FOR DETECTING A WEAK POINT - A weak point detecting method of the present invention designs a target layout, and compensates an optical proximity effect for the target layout, thereafter, verifies the target layout in which the optical proximity effect is compensated by using an NILS of the target layout, thereby, enabling to reduce the time and cost in detecting a weak point for a full chip regardless of the size and form of a pattern.06-24-2010
20100218159Data Flow Branching in Mask Data Preparation - Branching of the data-flow in a mask data preparation processes is described herein. In various implementations, the output stream from a first mask data processing operation is branched. Subsequently, the branched output stream may be connected to the input stream of a first independent mask data preparation operation and a second independent mask data preparation operation. This provides that the first and the second independent mask data preparation operations may operate in parallel. Furthermore, this provides that the first and the second independent mask data preparation operations may operate upon discrete “portions” of the data processed by the first mask data preparation operation.08-26-2010
20100242011METHOD FOR VERIFICATION OF MASK LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT - In a semiconductor integrated circuit mask layout verification method, a layout pattern division condition 09-23-2010
20100235805SYSTEM AND METHOD FOR EVALUATING ERROR SOURCES ASSOCIATED WITH A MASK - Evaluating error sources associated with a mask involves: (i) receiving data representative of multiple images of the mask that were obtained at different exposure conditions; (ii) calculating, for multiple sub-frames of each image of the mask, values of a function of intensities of pixels of each sub-frame to provide multiple calculated values; and (iii) detecting error sources in response to calculated values and in response to sensitivities of the function to each error source.09-16-2010
20090037867METHOD FOR OPTIMIZATION OF OPTICAL PROXIMITY CORRECTION - A method of designing and forming a mask used for projecting an image of an integrated circuit design. After providing a mask element corresponding to a portion of a design of an integrated circuit layout, the method includes correcting the mask element using OPC techniques, and fracturing the OPC-corrected mask element into a plurality of polygonal segments. The method then includes identifying along an edge of the mask element a polygon edge having a thickness less than that which can be normally reproduced by a mask writer, and modifying configuration of the identified mask element segment to add or subtract length to an end of the polygon to create a corrected mask element having increased resolution by the mask writer. The method then includes using an electron beam or other mask writer to form a mask having the mask element with modified configuration.02-05-2009
20090265679SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN - A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.10-22-2009
20090187877MULTI-PASS, CONSTRAINED PHASE ASSIGNMENT FOR ALTERNATING PHASE-SHIFT LITHOGRAPHY - Generating two-tone phase shift photomasks that satisfy lithography and photomask constraints is accomplished using an iterative algorithm which successively identifies violations of the constraints, relaxes or removes constraints, and alters layout polygons associated with the violations, to produce a phase assignment configuration which meets the lithography and photomask constraints or identifies a subset of the layout polygons for which no viable solution can be found.07-23-2009
20090144692METHOD AND APPARATUS FOR MONITORING OPTICAL PROXIMITY CORRECTION PERFORMANCE - A method includes specifying a plurality of optical proximity correction metrology sites on a wafer. Metrology data is collected from at least a subset of the metrology sites. Data values are predicted for the subset of the metrology sites using an optical proximity correction design model. The collected metrology data is compared to the predicted data values to generate an optical proximity correction metric. A problem condition associated with the optical proximity correction design model is identified based on the optical proximity correction metric.06-04-2009
20090113376Apparatus for OPC Automation and Method for Fabricating Semiconductor Device Using the Same - An OPC automation apparatus and manufacturing method of a semiconductor device using the same, being capable of improving the fabrication yield of a semiconductor device by establishing a system and an OPC automation apparatus in which an engineer computer and a work station are connected to one database such that all OPC tasks are monitored in the engineer computer and the OPC task is automatically performed. An OPC automation apparatus may include a first computer that receives a first OPC information from outside to store; and a second computer that receives the first OPC information from the first computer to perform an OPC process, generates a second OPC information from the result of the performance of an OPC process, and delivers the second OPC information to the first computer, wherein the second computer delivers the second OPC information to the first computer such that the first computer is able to compare and analyze the first OPC information with the second OPC information.04-30-2009
20100223590Mask Decomposition for Double Dipole Lithography - Method and apparatus for generating a pair of layouts suitable for forming exposure mask to use in a double dipole lithographic process are disclosed. With some implementations, a y-dipole layout and an x-dipole layout are generated by decomposing a target layout. Subsequently, an optical proximity correction process is implemented on the y-dipole layout and the x-dipole layout. The decomposition may designate ones of the edge segments in the target layout at major edge segments and other ones of the edge segments as minor edge segments. A higher feedback value may then be assigned to the minor edges than the major edges. Subsequently, a few iterations of an optical proximity correction process that utilizes a smaller than intended mask rule constraint value and the assigned feedback values is implemented on the target layout. The minor edges separated by a distance of less than the intended mask rule constraint distance are then collapsed. After which, a few iterations of the optical proximity correction process are allowed to iterate. In further implementations, once the y-dipole and x-dipole layouts have been generated. An additional optical proximity correction process is implemented on the layouts. During this optical proximity correction process, a higher feedback values is again assigned to the minor edge segments. At a point during the optical proximity correction process, minor edges within portions of the layouts that have a bias value larger than a predetermined value are expanded back from their collapsed position.09-02-2010
20080263501System, Method, and Computer-Readable Medium for Performing Data Preparation for a Mask Design - A method, computer-readable medium, and system for performing data preparation are provided. An integrated circuit design is received, and a plurality of pre-optical proximity correction processes are invoked such that the plurality of pre-optical proximity correction processes are performed in parallel. An optical proximity correction process is invoked in response to a determination that each of the plurality of pre-optical proximity correction processes have completed. A post-optical proximity correction process is invoked in response to a determination that the optical proximity correction process has completed10-23-2008
20090037866ALTERNATING PHASE SHIFT MASK OPTIMIZATION FOR IMPROVED PROCESS WINDOW - A method for designing alternating phase shift masks is provided, in which narrow phase shapes located between densely spaced design shapes are colored to allow a maximum amount of light transmission. After assigning and ensuring binary legalization of the phase shapes, the narrow phase shapes are assigned a color, such as 0° phase shift, that allows the more light transmission than the alternate or opposite color (e.g. 180° phase shift), which helps avoid printing errors such as resist scumming between closely spaced shapes, and maximizes the lithographic process window.02-05-2009
20090070730METHOD AND APPARATUS FOR MODELING A VECTORIAL POLARIZATION EFFECT IN AN OPTICAL LITHOGRAPHY SYSTEM - One embodiment of the present invention provides a system that accurately models polarization effects in an optical lithography system for manufacturing integrated circuits. During operation, the system starts by receiving a polarization-description grid map for a lens pupil in the optical lithography system. The system then constructs a pupil-polarization model by defining a vectorial matrix at each grid point in the grid map, wherein the vectorial matrix specifies a pupil-induced polarization effect on an incoming optical field at the grid point. Next, the system enhances a lithography model for the optical lithography system by incorporating the pupil-polarization model into the lithography/OPC model. The system then uses the enhanced lithography model to perform convolutions with circuit patterns on a mask in order to simulate optical lithography pattern printing.03-12-2009
20100242012FORMATION OF MASKS/RETICLES HAVING DUMMY FEATURES - A method of forming a mask. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features. The method further includes (i) creating a cluster of P representative dummy features, P being a positive integer less than N, (ii) performing OPC for the cluster of the P representative dummy features but not for the N original dummy features, resulting in P OPC-applied representative dummy features, and (iii) forming the mask including N mask dummy features. The N mask dummy features are identical. Each mask dummy feature of the N mask dummy features of the mask has an area which is a function of at least an area of an OPC-applied representative dummy feature of the P OPC-applied representative dummy features. The N mask dummy features have the same relative positions as the N original dummy features.09-23-2010
20100138806RESOLUTION ENHANCING TECHNOLOGY USING PHASE ASSIGNMENT BRIDGES - In one embodiment, a spacing is determined for each edge of a number of features in a photolithographic design. The edges have at least a partially predictable layout. Based on the spacing and the predictable layout, a bridge structure is generated. Each bridge of the bridge structure connects one of the edges to an edge of a neighboring feature. Then, the features and the bridge structure are provided for a phase assignment. The phase assignment assigns features at opposite ends of each bridge in the bridge structure to opposite phases. In another embodiment, a sub-resolution assist feature (SRAF) is introduced for an edge of a feature and a bridge is generated from the feature to the SRAF. Then, the feature and the SRAF are assigned to opposite phases based on the relationship defined by the bridge.06-03-2010
20100058279Method and System for Design of a Reticle to be Manufactured Using Variable Shaped Beam Lithography - A method for fracturing or mask data preparation or proximity effect correction of a desired pattern to be formed on a reticle is disclosed in which a plurality of variable shaped beam (VSB) shots are determined which can form the desired pattern. Shots within the plurality of VSB shots are allowed to overlap each other. Dosages of the shots may also be allowed to vary with respect to each other. The union of the plurality of shots may deviate from the desired pattern. The plurality of shots may be determined such that a pattern on the surface calculated from the plurality of shots is within a predetermined tolerance of the desired pattern. In some embodiments, an optimization technique may be used to minimize shot count. In other embodiments, the plurality of shots may be optionally selected from one or more pre-computed VSB shots or groups of VSB shots.03-04-2010
20090100399DESIGN STRUCTURE FOR PARTITIONED DUMMY FILL SHAPES FOR REDUCED MASK BIAS WITH ALTERNATING PHASE SHIFT MASKS - A design structure, method, and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim mask. A design structure is embodied in a machine readable medium used in a design process, the design structure comprising regions in a finished semiconductor design that do not contain as-designed shapes. The design structure additionally includes dummy fill shapes in the regions at a predetermined final density, wherein the generated dummy shapes are sized so that their local density is increased to a predetermined value. Moreover, corresponding trim shapes act to expose an oversized portion of the dummy shape, effectively trimming each dummy shape back to the predetermined final density.04-16-2009
20080244503System for Coloring a Partially Colored Design in an Alternating Phase Shift Mask - A method of designing an alternating phase shifting mask for projecting an image of an integrated circuit design. Phase units are binary colorable within each unit of the hierarchical circuit design, e.g., cell, an array, a net, or array of nets and/or cells, the phase shapes. The assignment of phases or colors within a hierarchical unit will be correctly binary colored to satisfy the lithographic, manufacturability and other design rules, referred to collectively as coloring rules. During assembly with other units, the coloring of phases in a hierarchical unit may change (e.g., be reversed or flipped), but the correct binary colorability of a hierarchical unit is preserved, which simplifies assembly of the integrated circuit layout.10-02-2008
20100005441Method of Designing a Mask Layout - In a method of designing a mask layout, a wiring region for forming a metal wire is established, the wiring region having at least a standard width. Contact regions for forming contacts electrically connected to the metal wire are established in the wiring region. The contact regions adjacent to each other are grouped to divide the wiring region into a first region and a second region including the contact regions. First dummy regions are established in the first region, the first dummy regions corresponding to regions for forming first dummy patterns. Second dummy regions are established among the contact regions in the second region, the second dummy regions corresponding to regions for forming second dummy patterns.01-07-2010
20090241086METHOD OF MAKING PATTERN DATA, AND MEDIUM FOR STORING THE PROGRAM FOR MAKING THE PATTERN DATA - A method of making pattern data of a photomask pattern includes: the processes of adding, to each of first cells, information of the first cell higher than the first cell on the basis of a hierarchical structure; selecting, from the first cells included in one level of the hierarchical structure, the first cell identical to one of the first cells included in a level higher than the one level and the first cell placed inside two or more of the first cells included in a level immediately higher than the one level, and forming a cell group with the selected first cells; making pattern data of the first cells not included in the cell group in consideration of the optical proximity effect and forming a fourth cell group with second cells including the pattern data; and replacing the first cells with the corresponding second cells in input data.09-24-2009
20090241085SYSTEM AND METHOD FOR IMPLEMENTING OPTICAL RULE CHECKING TO IDENTIFY AND QUANTIFY CORNER ROUNDING ERRORS - A method for implementing optical rule checking to identify and quantify corner rounding errors includes receiving corner rounding data based on established ground rules; determining a simulated shape for a semiconductor device feature produced on a wafer, the simulated shape based on a designed shape for the semiconductor device feature; selecting a corner feature associated with the designed shape, and drawing one or more triangles at the selected corner feature. For each triangle, the presence or absence of an intersection between the triangle and the simulated shape is determined, wherein a degree of corner rounding is determined by a pair of successively sized triangles for which one of the pair intersects with the simulated shape and the other does not; and comparing the determined corner rounding with the corner rounding data for the designed shape to determine whether the simulated shape results in a rule violation.09-24-2009
20090125867Handling Of Flat Data For Phase Processing Including Growing Shapes Within Bins To Identify Clusters - Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then the phase shifting process can be performed more rapidly. If the shapes on the layout are enlarged, then the overlapping shapes can be grouped together to identify shapes that should be processed together. For large layouts, growing and grouping the shapes can be time consuming. Therefore, an approach that uses bins can speed up the clustering process, thereby allowing the phase shifting to be performed in parallel on multiple computers. Additional efficiencies result if identical clusters are identified and processing time saved so that repeated clusters of shapes only undergo the computationally expensive phase shifter placement and assignment process a single time.05-14-2009
20080250382SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A yielding percentage is calculated based on a first relationship, a probability distribution and a second relationship. The first relationship is a relationship between measurement values of a transfer pattern formed on a semiconductor substrate provided in the semiconductor device in the semiconductor lithographic process and number of sections on the semiconductor substrate where the measurement values are set. The probability distribution is a probability distribution showing variation of manufacturing parameters in the semiconductor lithographic process. The second relationship is a relationship between the manufacturing parameters and the measurement values.10-09-2008
20100180251METHOD FOR PROCESS WINDOW OPTIMIZED OPTICAL PROXIMITY CORRECTION - One embodiment of a method for process window optimized optical proximity correction includes applying optical proximity corrections to a design layout, simulating a lithography process using the post-OPC layout and models of the lithography process at a plurality of process conditions to produce a plurality of simulated resist images. A weighted average error in the critical dimension or other contour metric for each edge segment of each feature in the design layout is determined, wherein the weighted average error is an offset between the contour metric at each process condition and the contour metric at nominal condition averaged over the plurality of process conditions. A retarget value for the contour metric for each edge segment is determined using the weighted average error and applied to the design layout prior to applying further optical proximity corrections.07-15-2010
20090300575Optimizing Layout of Irregular Structures in Regular Layout Context - Within a dynamic array architecture, an irregular wire layout region within a portion of a chip level layout is bracketed by placing first and second regular wire layout shapes on a first and second sides, respectively, of the irregular wire layout region. One or more irregular wire layout shapes are placed within the irregular wire layout region. A first edge spacing is maintained between the first regular wire layout shape and a first outer irregular wire layout shape within the irregular wire layout region nearest to the first regular wire layout shape. A second edge spacing is maintained between the second regular wire layout shape and a second outer irregular wire layout shape within the irregular wire layout region nearest to the second regular wire layout shape. The first and second edge spacings are defined to optimize lithography of the regular and irregular wire layout shapes.12-03-2009
20090300574Methods for Defining and Utilizing Sub-Resolution Features in Linear Topology - Regular layout shapes are placed in accordance with a virtual grate. A determination is made as to whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape, is large enough to support placement of a sub-resolution shape. Upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape, the sub-resolution shape is placed so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space. Also, one or more sub-resolution shapes are placed between and parallel with neighboring regular layout shapes when windows of lithographic reinforcement associated with each of the neighboring regular layout shapes permit. The sub-resolution shapes may be placed according to a virtual grate, or may be placed based on proximity to edges of the neighboring regular layout shapes.12-03-2009
20090300573MODEL-BASED PROCESS SIMULATION SYSTEMS AND METHODS - Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.12-03-2009
20090300572Method of Correcting Etch and Lithographic Processes - System and method of correcting etch and lithographic processes on a photo mask provides for performing an etch proximity correction on a layout design pattern. A first and a second intermediate layout pattern each being based on the etch proximity corrected layout design pattern are provided. An optical proximity correction on the first intermediate layout pattern is performed so as to generate a modified first intermediate layout pattern. Scatterbar generation on the second intermediate layout pattern is performed so as to generate a modified second intermediate layout pattern including scatterbars. Generating a mask layout pattern being based on the first and the second modified intermediate layout pattern is performed.12-03-2009
20090293038METHOD AND CORRECTION APPARATUS FOR CORRECTING PROCESS PROXIMITY EFFECT AND COMPUTER PROGRAM PRODUCT - A process proximity effect (PPE) correction method includes providing corrected cells arranged in a place/route arrangement, the corrected cells being obtained by correcting design data of a semiconductor device based on correction value for correcting PPE correction, determining whether a cell arrangement of the corrected cells is registered or not based on environmental profiles, conducting lithography verification if the corrected cells includes the cell arrangement not registered in the environmental profiles, the verification being performed on the corrected cells, wherein the corrected cell to be conducted the verification corresponds to the cell arrangement not registered, determining whether error is found or not in the verification, correcting the corrected cell to which the verification is conducted if the error is found and registering the cell arrangement in the environmental profiles, and registering the cell arrangement of the corrected cell if the error is not found.11-26-2009
20090293037Technique for Correcting Hotspots in Mask Patterns and Write Patterns - Embodiments of a method for determining a mask pattern to be used on a photo-mask in a lithography process are described. This method may be performed by a computer system. During operation, this computer system receives at least a portion of a first mask pattern including first regions that violate pre-determined rules associated with the photo-mask. Next, the computer system determines a second mask pattern based on at least the portion of the first mask pattern, where the second mask pattern includes second regions that are estimated to comply with the pre-determined rules. Note that the second regions correspond to the first regions, and the second mask pattern is determined using a different technique than that used to determine the first mask pattern.11-26-2009
20100031223SYSTEMS FOR REAL-TIME CONTAMINATION, ENVIRONMENTAL, OR PHYSICAL MONITORING OF A PHOTOMASK - Systems for real-time contamination, environmental, or physical monitoring of a photomask. The system includes an electronics package physically mounted to the photomask and a processing device in communication with the electronics package. The electronics package includes a sensor configured to monitor the attribute and generate sensor data. The processing device is configured to analyze the sensor data communicated from the electronics package to the processing device.02-04-2010
20100023917TOOL FOR MODIFYING MASK DESIGN LAYOUT - An embodiment of the invention provides a tool for modifying a mask design layout to be printed. The tool is executed by a computer system, and includes code for establishing a first level of correction for a mask design layout for a predetermined parametric yield without cost of correction to area of the mask design layout. The tool also includes code for correcting the mask design layout at said first level of correction based on a correction algorithm, the correction algorithm selecting a cell of the mask design layout having an edge placement error (EPE) for each gate feature in the cell. The correction algorithm selects the cell without loss to parametric yield as established by the predetermined parametric yield.01-28-2010
20100023916Model Based Hint Generation For Lithographic Friendly Design - In various implementations of the invention, a model of an optical proximity correction process is employed to determine potential adjustments to a layout design for a mask that might resolve potential errors an image resulting from application of the mask in an optical lithographic process. In various implementations of the invention, corrected mask shapes, such as for example optical proximity corrected mask shapes, and associated printed image contours are generated through use of a model. Subsequently, the associated printed image contour and a desired printed image contour may be used to determine various edge segment adjustments to the corrected mask shapes that would realize the desired printed image contour. In various implementations of the present invention, the model for generation of the corrected mask shapes and the associated printed image contour is a square kernel model. With various implementations of the invention, the kernel represents a grey scale map wherein each pixel of the map is generated based on the desired displacement relative to the displacement to be modeled. For example by application of linear regression techniques. As a result, printed image contours and corrected mask shapes may be generated based upon an input layout design, wherein potential adjustments to the mask may be determined based upon a desired printed image contour.01-28-2010
20100023915Calculation System For Inverse Masks - A system for calculating mask data to create a desired layout pattern on a wafer reads all or a portion of a desired layout pattern. Mask data having pixels with transmission values is defined along with corresponding optimal mask data pixel transmission values. An objective function is defined that compares image intensities as would be generated on a wafer with an optimal image intensity at a point corresponding to a pixel. The objective function is minimized to determine the transmission values of the mask pixels that will reproduce the desired layout pattern on a wafer.01-28-2010
20100017778METHODS FOR DEFINING EVALUATION POINTS FOR OPTICAL PROXIMITY CORRECTION AND OPTICAL PROXIMITY CORRECTION METHODS INCLUDING SAME - Methods are disclosed for defining evaluation points for use in optical proximity correction of a rectangular target geometry. A method for defining evaluation points for use in optical proximity correction of a rectangular target geometry may comprise predicting a contour of an image to be produced in an optical proximity correction simulation of a target geometry. The target geometry may comprise a plurality of line segments, each line segment of the plurality having one evaluation point defined thereon. The method may further comprise shifting at least one evaluation point to an associated point on the predicted contour of the image.01-21-2010
20090125866METHOD FOR PERFORMING PATTERN DECOMPOSITION FOR A FULL CHIP DESIGN - A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph.05-14-2009
20080222597PHOTO MASK, EXPOSURE METHOD USING THE SAME, AND METHOD OF GENERATING DATA - A photo mask formed with patterns to be transferred to a substrate using an exposure apparatus, the photo mask comprising a pattern row having three or more hole patterns surrounded by a shielding portion or a semitransparent film and arranged along one direction, and an assist pattern surrounded by the shielding portion or semitransparent film and having a longitudinal direction and a latitudinal direction, the assist pattern being located at a specified distance from the pattern row in a direction orthogonal to the one direction, the longitudinal direction of the assist pattern being substantially parallel with the one direction, the longitudinal length of the assist pattern being equivalent to or larger than the longitudinal length of the pattern row, the assist pattern being not transferred to the substrate.09-11-2008
20080216045MASK DATA PROCESSING METHOD FOR OPTIMIZING HIERARCHICAL STRUCTURE - Disclosed is a mask data processing method of correcting a hierarchical structure. In the case that in design data having a hierarchical structure including a plurality of cells each having a design pattern, when the total number of graphic forms or the total edge length of a design pattern on which the calculation of mask data processing is to be executed, the amount of calculation to be executed, or the expansion degree presumably becomes equal to or larger than a predetermined threshold value if the calculation of the mask data processing is executed on the design data having the initial hierarchical structure, the hierarchical structure is corrected. This correction is performed to reduce the total number of graphic forms or the total edge length of the design pattern on which the calculation is to be executed, the amount of calculation to be executed, of the expansion degree.09-04-2008
20090150849Methods for Measuring Mean-to-Target (MTT) Based on Pattern Area Measurements and Methods of Correcting Photomasks Using the Same - Methods of measuring a mean-to-target (MTT) based on pattern area measurements are provided including providing a design pattern. A plurality of design pattern measurements are measured for calculating an area of the design pattern based on a shape of the design pattern. A series of calculation measurements are calculated by continuously substituting a same variation into the design pattern measurements, and calculating a series of calculation areas corresponding respectively to the calculation measurements to generate a database including the calculation measurements and the calculation areas. An actual pattern is formed using the design pattern and an area of the actual pattern is measured. A calculation area corresponding to the area of the actual pattern is selected from the database and calculation measurements corresponding to the calculation area are selected. A difference between the design pattern measurements and the calculation measurements is calculated and the difference is set as an MTT. Related methods of correcting a photomask are also provided herein.06-11-2009
20100175040METHODOLOGY OF PLACING PRINTING ASSIST FEATURE FOR RANDOM MASK LAYOUT - Embodiments of the present invention provide a method of placing printing assist features in a mask layout. The method includes providing a design layout having one or more designed features; generating a set of parameters, the set of parameters being associated with one or more printing assist features (PrAFs); adding the one or more PrAFs of the set of parameters to the design layout to produce a modified design layout; performing simulation of the one or more PrAFs and the one or more designed features on the modified design layout; verifying whether the one or more PrAFs are removable based on results of the simulation; and creating a set of PrAF placement rules based on the set of parameters, if the one or more PrAFs are verified as removable. The set of PrAF placement rules may be used in creating a final set of PrAF features to be used for creating the mask layout.07-08-2010
20090064083COMPUTER AUTOMATED METHOD FOR DESIGNING AN INTEGRATED CIRCUIT, A COMPUTER AUTOMATED SYSTEM FOR DESIGNING AN INTEGRATED CIRCUIT, AND A METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - A computer automated method for designing an integrated circuit includes placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group; determining one of the groups as a candidate hot spot based on a total number of marks included in each of the groups; and modifying the corresponding pattern in the candidate hot spot.03-05-2009
20090019418Lithography simulation method, mask pattern preparation method, semiconductor device manufacturing method and recording medium - A lithography simulation method includes: taking in design data of a pattern to be formed on a substrate and mask data to prepare a mask pattern used in forming a latent image of the pattern on the substrate by transmission of an energy ray; obtaining the latent image of the pattern by calculation of an intensity of the energy ray; locally changing, at least in a portion corresponding to a pattern to be interested, a relative position in a direction of the intensity of the energy ray between a latent image curve and a reference intensity line in accordance with a distance between the pattern to be interested and a pattern of a neighboring region, the latent image curve being an intensity distribution curve of the energy ray constituting the latent image, the reference intensity line being defined to specify a position of an edge of the pattern to be interested; and calculating a distance between intersections of a portion of the latent image curve corresponding to the pattern to be interested and the reference intensity line in the changed relative position to define an interested line width of the pattern to be interested.01-15-2009
20080301621MASK PATTERN CORRECTING METHOD - In a model-based OPC which makes a suitable mask correction for each mask pattern using an optical image intensity simulator, a mask pattern is divided into subregions and the model of optical image intensity simulation is changed according to the contents of the pattern in each subregion. When the minimum dimensions of the mask pattern are smaller than a specific threshold value set near the exposure wavelength, the region is calculated using a high-accuracy model and the other regions are calculated using a high-speed model.12-04-2008
20080301622METHOD OF DETERMINING DEFECTS IN PHOTOMASK - A method of determining defects in photomasks according to the present invention is designed to increase the yield of the manufacture of photomasks and to decrease the cost of inspecting the photomasks. In the method, circuit data 12-04-2008
20080301620SYSTEM AND METHOD FOR MODEL-BASED SUB-RESOLUTION ASSIST FEATURE GENERATION - Methods are disclosed to create efficient model-based Sub-Resolution Assist Features (MB-SRAF). An SRAF guidance map is created, where each design target edge location votes for a given field point on whether a single-pixel SRAF placed on this field point would improve or degrade the aerial image over the process window. In one embodiment, the SRAF guidance map is used to determine SRAF placement rules and/or to fine tune already-placed SRAFs. In another embodiment the SRAF guidance map is used directly to place SRAFs in a mask layout.12-04-2008
20100100865METHOD FOR MODIFYING PHOTOMASK LAYOUT - A method for modifying a photomask layout includes the following steps. First, a photomask layout having at least an edge is provided. A plurality of evaluation points are positioned on the edge. Then, the photomask layout is interpreted to have an interpreted photomask layout and an interpreted edge pattern. The interpreted edge pattern is formed by interpreting the above-mentioned edge. After that, a shift between the edge and the interpreted edge and corresponding to each of the evaluation points is calculated. Afterwards, a shift gradient between two evaluation points can be derived from the shift. Finally, a number of segments between each two evaluation points can be estimated.04-22-2010
20100229146Variable Overlap Method and Device for Stitching Together Lithographic Stripes - The technology disclosed relates to variable tapers to resolve varying overlaps between adjacent strips that are lithographically printed. Technology disclosed combines an aperture taper function with the variable overlap taper function to transform data and compensate for varying overlaps. The variable taper function varies according to overlap variation, including variation resulting from workpiece distortions, rotor arm position, or which rotor arm printed the last stripe. Particular aspects of the present invention are described in the claims, specification and drawings.09-09-2010
20100229145Use Of Graphs To Decompose Layout Design Data - Techniques are disclosed for determining if the decomposition of layout design data is feasible, and for optimizing the segmentation of polygons in decomposable layout design data. Layout design data is analyzed to identify the edges of polygons that should be imaged by separate lithographic masks. In addition, proposed cut paths are generated to cut the polygons in the layout design data into a plurality of polygon segments. Once the separated edges and cut paths have been selected, a conflict graph is constructed that reflects these relationships. Next, a dual of the conflict graph is constructed. This dual graph will have a corresponding separation dual graph edge for each separated polygon edge pair in the layout design data. The dual graph also will have a corresponding cut path dual graph edge for each proposed cut path generated for the layout design data. After the dual graph has been constructed, it is analyzed to determine which of the proposed cut paths should be kept and which should be discarded. The layout design data is then modified to include the cut paths corresponding to the selected cut path dual graph edges. Alternately or additionally, separate sets of layout design data may be decomposed from original layout design data using the selected cut paths.09-09-2010
20100199255METHOD AND APPARATUS FOR CORRECTING ASSIST-FEATURE-PRINTING ERRORS IN A LAYOUT - One embodiment of the present invention provides a system that adjusts assist features in a layout to prevent assist features from printing. During operation, the system receives a layout. The system then identifies an assist-feature (AF)-printing hotspot in the layout, wherein the AF-printing hotspot includes a set of assist features and one or more target patterns in proximity to the set of assist features. At least one assist feature in the set of assist features is expected to print during a lithography process. Next, the system modifies the AF-printing hotspot by: (1) modifying the set of assist features; and (2) performing optical-proximity-correction (OPC) on the one or more target patterns. The system then performs a lithography simulation on the modified AF-printing hotspot to determine if: (1) a through-process-window associated with the modified AF-printing hotspot is acceptable; and (2) no assist feature in the modified set of assist features is expected to print. If so, the system replaces the AF-printing hotspot with the modified AF-printing hotspot.08-05-2010
20100153901Determining manufacturability of lithographic mask by reducing target edge pairs used in determining a manufacturing penalty of the lithographic mask - The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic mask to determine a manufacturing penalty in making the lithographic mask. The mask layout data includes polygons, where each polygon has edges, and where each target edge pair is defined by two of the edges of one or more of the polygons. The number of the target edge pairs is reduced to decrease computational volume in determining the manufacturing penalty in making the lithographic mask. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined based on the target edge pairs as reduced in number. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.06-17-2010
20100131914METHOD TO DETERMINE PROCESS WINDOW - A method to determine a process window is disclosed. First, a pattern data is provided. Second, a bias set is determined. Then, a resizing procedure is performed on the pattern data in accordance with the bias set to obtain a usable final resized pattern to be a target pattern of changed area. The final resized pattern is consistent with a minimum spacing rule, a contact to poly rule and a contact to metal rule. Accordingly, the target pattern is output.05-27-2010
20080235650PATTERN CREATION METHOD, MASK MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A pattern creation method, including laying out data of a most extreme end pattern of integrated circuit patterns on a first layer and laying out data of the integrated circuit patterns excluding the most extreme end pattern on a second layer, extracting data of a first most proximate pattern being most proximate to the most extreme end pattern from the second layer and converting the extracted data to a third layer, generating data of a contacting pattern which contacts both the first most proximate pattern and the most extreme end pattern in a fourth layer, generating data of a non-overlapping pattern of the contacting pattern excluding overlapping portions with the most extreme end pattern and the first most proximate pattern in a fifth layer, extracting data of a second most proximate pattern being most proximate to the non-overlapping pattern and converting the extracted data to the first layer.09-25-2008
20080235649METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, APPARATUS FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, RECORDING MEDIUM, AND MASK MANUACTURING METHOD - A method of designing a semiconductor integrated circuit includes a cell arranging and wiring step of arranging and wiring cells for creating a physical layout, a design-rule checking step of verifying a shape of a second physical layout including the cells of the physical layout with reference to a rule library for design rule check, a mask-data creating step of creating mask data corresponding to the physical layout using the second physical layout when the design rule is satisfied in the design-rule checking step, a mask-data processing step of performing, when the design rule is not satisfied in the design-rule checking step, mask data processing for the verification-object second physical layout, and a mask-data creating step for creating mask data corresponding to the physical layout using the second physical layout subjected to the mask data processing in the mask-data processing data.09-25-2008
20080229273SYSTEMS AND METHODS FOR UV LITHOGRAPHY - A method of designing a lithographic mask for use in lithographic processing of a substrate is disclosed. The lithographic processing comprises irradiating mask features of a lithographic mask using a predetermined irradiation configuration. In one aspect, the method comprises obtaining an initial design for the lithographic mask comprising a plurality of initial design features having an initial position. The method further comprises applying at least one shift to at least one initial design feature and deriving there from an altered design so as to compensate for shadowing effects when irradiating the substrate using a lithographic mask corresponding to the altered design in the predetermined irradiation configuration. Also disclosed herein are a corresponding design, a method of setting up lithographic processing, a system for designing a lithographic mask, a lithographic mask, and a method of manufacturing it.09-18-2008
20080222596Method of shrinking semiconductor mask features for process improvement - Provided is a method to design an integrated circuit. The method reduces a time delay between introduction of a new lithography process and a start of production. A first semiconductor mask is designed at a first process feature size. The first process feature size can be based on an anticipated process feature size of the new lithography process. A second semiconductor mask is created by enlarging the first semiconductor mask to a second process feature size for which production is available. Thus, the second process feature size is larger than the first process feature size. An integrated circuit (IC) is fabricated with the second semiconductor mask. After the new semiconductor process has been developed and is available for production, another IC is fabricated with the first semiconductor mask.09-11-2008
20100281449Method For Forming Arbitrary Lithographic Wavefronts Using Standard Mask Technology - A desired set of diffracted waves using mask features whose transmissions are chosen from a set of supported values are generated. A representation of the mask as a set of polygonal elements is created. Constraints which require that the ratio of the spatial frequencies in the representation take on the amplitude ratios of the desired set of diffracted waves are defined. An optimization algorithm is used to adjust the transmission discontinuities at the edges of the polygons to substantial equality with the discontinuity values allowed by the set of supported transmissions while maintaining the constraints.11-04-2010
20080201686METHOD AND APPARATUS FOR PERFORMING TARGET-IMAGE-BASED OPTICAL PROXIMITY CORRECTION - A system that performs target-image-based optical proximity correction on masks that are used to generate an integrated circuit is presented. The system operates by first receiving a plurality of masks that are used to expose features on the integrated circuit. Next, the system computes a target image for a target feature defined by the plurality of masks, wherein mask features from different masks define the target image. The system dissects the feature into a plurality of segments, wherein dissecting the mask feature involves using dissection parameters associated with geometric characteristics of the target image, instead of using dissection parameters associated with geometric characteristics of the mask feature. The system then performs an optical proximity correction (OPC) operation on the plurality of masks, wherein the OPC operation uses parameters associated with geometric characteristics of the target image to perform optical proximity correction on the mask features that define the target image.08-21-2008
20080201685Minimizing Number of Masks to be Changed When Changing Existing Connectivity in an Integrated Circuit - A method and apparatus for fabricating integrated circuits providing a desired operation using a plurality of masks, wherein each of said plurality of masks is used to control a corresponding one of a plurality of layers to form said integrated circuits. Said method includes incorporating a plurality of dummy stacks along with a functional block, said functional block providing said desired operation, each of said dummy stack providing a point of common connectivity on a plurality of metal layers comprised in said plurality of layers.08-21-2008
20100293516MASK SYSTEM EMPLOYING SUBSTANTIALLY CIRCULAR OPTICAL PROXIMITY CORRECTION TARGET AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a mask system includes: providing design data; generating a substantially circular optical proximity correction target from the design data; biasing a segment of the substantially circular optical proximity correction target; and generating mask data based on the shape produced by biasing the segment of the substantially circular optical proximity correction target.11-18-2010
20090125869CALCULATION SYSTEM FOR INVERSE MASKS - A system for calculating mask data to create a desired layout pattern on a wafer reads all or a portion of a desired layout pattern. Mask data having pixels with transmission values is defined along with corresponding optimal mask data pixel transmission values. An objective function is defined that compares image intensities as would be generated on a wafer with an optimal image intensity at a point corresponding to a pixel. The objective function is minimized to determine the transmission values of the mask pixels that will reproduce the desired layout pattern on a wafer.05-14-2009
20090070731Distributed Mask Data Preparation - Layout data is divided into segments of data, and each segment of data is distributed to a computing node in a parallel processing fracturing tool. During the fracturing process, the fracturing tool generates one or more global parameter values for each segment of data. After the fracturing process is completed, the fracturing tool will merge the segments back together using the global parameter values to ensure that the merger of the data segments does not exceed a constraint of the reticle or mask writer in which the fractured data will be employed.03-12-2009

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