Class / Patent application number | Description | Number of patent applications / Date published |
716017000 | Programmable integrated circuit (e.g., basic cell, standard cell, macrocell) | 24 |
20080282215 | METHOD OF DESIGNING A DIGITAL INTEGRATED CIRCUIT FOR A MULTI-FUNCTIONAL DIGITAL PROTECTIVE RELAY - This invention relates to a method of designing a digital integrated circuit for a multi-functional digital protective relay, emphasizing a digital module part, and input voltage and current signals are processed by a digital signal processor module to calculate the fundamental wave of the input voltage and current of protective relay, prevent the harmonic components in the input voltage or current from affecting the protective relay in operation; calculate for a root mean square value of voltage and current, being offered to a protective module next to determine a precise value, and the result is sent to the over voltage, under voltage, over current, and under current protective relay, the DSP using a pipeline-based structure, frequency-division fast Fourier transformation, and matrix spin digital algorithm to speed up the operation and reduce the occupied hardware area, which is a design for calculation and protection of the multi-functional digital protective relay. | 11-13-2008 |
20080282216 | Method for designing structured ASICs in silicon processes with three unique masking steps - A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules. | 11-13-2008 |
20080288910 | STRUCTURE FOR ESTIMATING POWER CONSUMPTION OF INTEGRATED CIRCUITRY - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software. | 11-20-2008 |
20080295056 | System and Method for Building Configurable Designs with Hardware Description and Verification Languages - An invention is provided for building configurable designs synthesizable to gates. The invention includes creating a configurable design using an HDL. The configurable design has a plurality of instantiated configurable constructs that can be optionally included in a design. Basically, the configurable design is an all-inclusive design having a large set of features, including varying interfaces, FIFO depths, and other features. Then, a derived design is generated by removing configurable constructs from the configurable design based on a specification, typically a customer specification received from a customer for a particular design. The specification indicates which configurable constructs are to be included in a derived design. Thereafter, the derived design is synthesizable in logic. | 11-27-2008 |
20080295057 | METHOD FOR DETERMINING A STANDARD CELL FOR IC DESIGN - IC design flow includes RTL design, synthesis, APR, and layout. An IC designer can choose a suitable standard cell for an integrated circuit according to the timing, area, and BCI (best cell index) of each standard cell. Further, the BCI of a standard cell can be generated by generating critical dimensions of a standard cell in a plurality of surroundings, generating a plurality of circuit parameters corresponding to the plurality of surroundings, calculating the differences of the plurality of circuit parameters and the ideal circuit parameter of the standard cell, and analyzing the distribution of the differences. | 11-27-2008 |
20080301619 | SYSTEM AND METHOD FOR PERFORMING NEXT PLACEMENTS AND PRUNING OF DISALLOWED PLACEMENTS FOR PROGRAMMING AN INTEGRATED CIRCUIT - A system and method for graphically displaying modules and resources within a chip design software application. The system and method provide a data driven model for matching the hardware resource requirements for an associated user module and the available hardware resources on an underlying chip. Databases are utilized to describe the hardware resource requirements which are dictated by the particular user module and the available hardware resources of a particular chip. The user module descriptive database can be updated in response to additional user modules being added or changes to the hardware resource requirements of existing user modules. The hardware description database can be updated in response to additional chips being added. Further, the graphical interface relates both a user module and the possible hardware resource. This graphical interface utilizes highlights of both the module and the associated resource in patterns, grayscales, or colors to graphically illustrate the relationship between the module and the associated resource. | 12-04-2008 |
20090070729 | METHOD AND SOFTWARE TOOL FOR DESIGNING AN INTEGRATED CIRCUIT - A method of designing an integrated circuit for use in an application having standards having a plurality of primitives, wherein each of the primitives has a corresponding response. The method includes generating a macros description of each of the primitives and the response corresponding to each of the primitives, generating a template relating to the response corresponding to each of the primitives, receiving information specifying a behavior of the integrated circuit in response to the primitives based on the template, and generating a hardware description language representation for the integrated circuit based on the macros description and the information. | 03-12-2009 |
20090094571 | Method and system for outputting a sequence of commands and data described by a flowchart - The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x | 04-09-2009 |
20090138840 | CELL, STANDARD CELL, STANDARD CELL LIBRARY, A PLACEMENT METHOD USING STANDARD CELL, AND A SEMICONDUCTOR INTEGRATED CIRCUIT - A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area. | 05-28-2009 |
20090138841 | SYSTEM AND APPARATUS FOR IN-SYSTEM PROGRAMMING - Embodiments of the present invention relate to machines that perform in-system programming of programmable devices that are attached to assembled printed circuit boards. In accordance with one aspect, multiple nonvolatile devices may be programmed in a single session at their normal maximum programming speeds. Different nonvolatile devices on a board can receive different data. Data variables can be inserted so that not all boards receive identical data. A master controller sends image files and algorithm information to a subsidiary controller. The subsidiary controller executes a device algorithm, and an FPGA executes a bus algorithm. Embodiments of the present invention can be designed as stand-alone systems or to operate cooperatively with an automatic tester, so that testing and device programming can take place in a single operation using a single fixture to hold the circuit board. | 05-28-2009 |
20090144689 | Structure for a Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal - A design structure for an integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level. | 06-04-2009 |
20090158234 | VERTICAL SOI TRENCH SONOS CELL - A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing. | 06-18-2009 |
20090183135 | Method and Device for Identifying and Implementing Flexible Logic Block Logic for Easy Engineering Changes - A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). | 07-16-2009 |
20090183136 | Structure for a Programmable Interpolative Voltage Controlled Oscillator with Adjustable Range - A design structure for a programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. Programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable. | 07-16-2009 |
20090265678 | System and Method of Resistance Based Memory Circuit Parameter Adjustment - Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory circuit includes selecting a first parameter based on a first predetermined design constraint of the resistance based memory circuit and selecting a second parameter based on a second predetermined design constraint of the resistance based memory circuit. The method further includes performing an iterative methodology to adjust at least one circuit parameter of a sense amplifier portion of the resistance based memory circuit by selectively assigning and adjusting a physical property of the at least one circuit parameter to achieve a desired sense amplifier margin value without changing the first parameter or the second parameter. | 10-22-2009 |
20090271756 | Minimal Leakage-Power Standard Cell Library - A minimal leakage power Standard Cell Library is provided. The minimal leakage power Standard Cell Library provides minimal leakage power cells with improved speed characteristics. The minimal leakage power Standard Cell Library includes cells from an existing Standard Cell Library and a set of minimal leakage power cells for a selected set of logic functions. The minimal leakage power Standard Cell Library is formed by identifying a set of logic functions. For each logic function in the identified set, a base case for an unfolded implementation of the logic function is determined. Widths for transistors in a transistor topology used in the unfolded implementation of the logic function are determined based on the non-linear leakage power characteristics for the transistor topology to achieve minimal leakage power. The determined widths are then assigned to the transistors and the minimal leakage cell is added to the library. | 10-29-2009 |
20100005439 | DESIGNING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT - A designing method of a semiconductor integrated circuit is provided, the method including a preparation step of preparing first design data having a power gating circuit for supplying a power supply voltage to a logic circuit according to a power gating control signal and a first clamp circuit for clamping an output signal from the logic circuit according to a clamp control signal; and a generation step of generating, in order to verify the first design data, second design data in which a first mask circuit for masking the output signal from the logic circuit according to the power gating control signal is added in place of the power gating circuit to the first design data. | 01-07-2010 |
20100037198 | PORT ASSIGNMENT IN HIERARCHICAL DESIGNS BY ABSTRACTING MACRO LOGIC - A method to reduce the problem complexity maintains a relatively high quality port assignment by abstracting local connections in the macro when performing the port assignment. This is done for netlength, congestion as well as timing. The internal netlist of the macro is abstracted in such a way that the optimization of the external interconnect can be done in an efficient manner. Three levels of abstractions are described. A first level optimizes the top level interconnect, a second level optimizes the top level and macro interconnects, while a third level optimizes the top level timing. | 02-11-2010 |
20100050147 | METHOD AND DEVICE PROVIDING INTEGRATED CIRCUIT DESIGN ASSISTANCE - The invention relates to a method and device providing integrated circuit design assistance. Independently of a design flow, the inventive method comprises the following steps, namely: a step ( | 02-25-2010 |
20100058275 | Top Level Hierarchy Wiring Via 1xN Compiler - Embodiments that route 1×N building blocks using higher-level wiring information for a 1×N compiler are disclosed. Some embodiments comprise determining higher-level coordinates for a blockage of a 1×N building block, determining intra-1×N coordinates for a shape of the blockage via the higher-level coordinates, and creating routes of intra-1×N wires of the 1×N building block that avoid the intra-1×N coordinates. Further embodiments comprise an apparatus having a higher-level wiring examiner to examine higher-level wiring of an area near a 1×N building block of a physical design representation. The apparatus may also have a blockage determiner to determine a blockage that affects intra-1×N wiring for the 1×N building block and a coordinate calculator to calculate coordinates of a shape of the blockage, wherein the calculated coordinates may enable a routing tool to avoid the shape when creating intra-1×N wiring for the 1×N building block. | 03-04-2010 |
20100058276 | Method for the integration of an integrated circuit into a standardized software architecture for embedded systems - A method is disclosed for the integration of an integrated circuit into a standardized software architecture for embedded systems. The method includes a definition of a computer readable standardized data structure which is completed with the properties of the integrated circuit. The completed standardized data structure is then used for the definition of a hardware module which includes the integrated circuit. The hardware module definition thus generated is exported in a form which can be imported by the standardized software architecture for embedded systems for further processing. | 03-04-2010 |
20100077374 | Automatic Alignment of Macro Cells - In a particular embodiment, a method is disclosed that includes detecting a first pitch between at least two lines (e.g. a power line and a ground line) of a first reference macro. The method also includes generating a virtual grid based on the first pitch and aligning at least a second macro to the virtual grid. | 03-25-2010 |
20100199254 | Programmable analog tile programming tool - A programmable analog tile integrated circuit programming tool communicates a power management control characteristic query soliciting control requirement information for a novel power management integrated circuit (PMIC) tile in a multi-tile power management integrated circuit (MTPMIC). The programming tool receives a user response to the query indicating control requirements across a network. The novel PMIC tiles have a pre-defined physical structure including all memory structures required for configuration of each tile and a bus portion. When combined in a multi-tile power management integrated circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. The memory structure of each tile is individually addressable via the standardized bus. Thus, in response to control requirements, the programming tool programs a PMIC tile that is part of a MTPMIC to meet the control requirements. | 08-05-2010 |
20100242010 | Propagation delay time balancing in chained inverting devices - A circuit comprising a plurality of semiconductor inverting devices arranged in series is disclosed. Each of the semiconductor inverting devices comprise at least one NMOS transistor and at least one PMOS transistor and alternate ones of the inverting devices in the series comprise transistors having a first ratio of a width of the at least one PMOS transistor and the at least one NMOS transistor; and alternate ones of said inverting devices in the series comprise transistors having a second ratio of a width of the at least one PMOS transistor and the at least one NMOS transistor; wherein the first ratio and the second ratio are not equal and in some case, the first and second ratios are such that a sum of a delay in a rise time of a signal propagated by a first inverting device and a fall time of a signal propagated by a second inverting device is substantially equal to a delay in a fall time of a signal propagated by the first inverting device. | 09-23-2010 |