Class / Patent application number | Description | Number of patent applications / Date published |
716015000 | PCB wiring | 18 |
20080222593 | DESIGN METHOD, RECORDING MEDIUM, AND DESIGN SUPPORT SYSTEM - A design method includes creating power supply planes in each layer of a circuit board, from CAD data of the circuit boards whereby the power supply planes form one power supply conductor interconnect and supply power or connect to ground, expanding the shape of the power supply planes by a predetermined width, creating power supply pairs which are formed by opposing portions wherein two power supply planes existing in different layers are separated by an insulator and correcting the parameter by use of the mesh area. | 09-11-2008 |
20080235646 | Spacers for Reducing Crosstalk and Maintaining Clearances - In one aspect of the invention is a method for reducing crosstalk and maintaining clearances between traces on a printed circuit board design. Crosstalk caused by placing traces a virtual printed circuit board are reduced by placing artificial obstructs, called spacers, between traces and/or between traces and nets to create a user-specified clearance between the traces and/or nets. As additional traces and/or nets are added to the virtual printed circuit board, the spacers are dynamic and adjust accordingly to maintain the specified clearances. | 09-25-2008 |
20080244498 | NETLIST SYNTHESIS AND AUTOMATIC GENERATION OF PC BOARD SCHEMATICS - A computer implemented method and system for automatically generating a net list for a printed circuit board are described. Selection of one or more pins on a first and second component to be connected is based on one or more of a logical definition, an electrical definition, a distance property, and a programmable constraint. Once pins of the first and second connections are selected and connected, a net list is automatically generated. The net list includes information associated with the first component, information associated with the second component and at least one pin of the second component. | 10-02-2008 |
20080244499 | APPARATUS AND DESIGN METHOD FOR CIRCUIT OF SEMICONDUCTOR DEVICE ETC - A design apparatus comprises a unit generating a new-via-formable overlapped area between a first wiring pattern and a second wiring pattern by extending, in a predetermined direction, at least one of the first wiring pattern included in a first wiring layer and the second wiring pattern connected by a via to the first wiring pattern and included in a second wiring layer thereof, and a unit determining whether or not there is a predetermined interval between the first extended wiring pattern and a wiring pattern existing in the periphery of the first wiring pattern in each of the first wiring layer including the first extended wiring pattern and the second wiring layer including the second extended wiring pattern, and determining whether or not there is a predetermined interval between the second extended wiring pattern and a wiring pattern existing in the periphery of the second wiring pattern. | 10-02-2008 |
20080250377 | CONDUCTIVE DOME PROBES FOR MEASURING SYSTEM LEVEL MULTI-GHZ SIGNALS - Methods and apparatus for accessing a high speed signal routed on a conductive trace on an internal layer of a printed circuit board (PCB) using high density interconnect (HDI technology) are provided. The conductive trace may be coupled to a microvia (μVia) having a conductive dome disposed above the outer layer pad of the μVia. In-circuit test (ICT) fixtures or high speed test probes may interface with the conductive dome to test the high speed signal with decreased reflection loss and other parasitic effects when compared to conventional test points utilizing plated through-hole (PTH) technology. | 10-09-2008 |
20080270968 | APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING VERTICALLY COUPLED NOISE CONTROL THROUGH A MESH PLANE IN AN ELECTRONIC PACKAGE DESIGN - A method, apparatus and computer program product are provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package physical design data are identified. The identified instances of vertically coupled noise are quantified. Then the electronic package physical design data are modified to limit the vertically coupled noise. | 10-30-2008 |
20080276214 | METHOD AND COMPUTER PROGRAM FOR AUTOMATED ASSIGNMENT AND INTERCONNECTION OF DIFFERENTIAL PAIRS WITHIN AN ELECTRONIC PACKAGE - Connection assignments of differential signals within an integrated circuit (IC) package are automatically made in the design and manufacturing process of the IC package, for use in automated computing systems. Either predefined pairs of pins at both ends or pairs of pins automatically paired or a combination of both are used in the creation of an imaginary pin or midpoint between the pair. Then the point-to-point connections of the pair are automatically detangled. Once the imaginary midpoint-to-midpoint connections are created, the real differential connections can then be assigned. | 11-06-2008 |
20080288908 | SIMULTANEOUS DESIGN OF INTEGRATED CIRCUIT AND PRINTED CIRCUIT BOARD - A printed circuit board (PCB) circuit assembly is designed utilizing software to create the best performing “total design” by selecting component layout locations, optimizing the circuit routing of the PCB copper (or other metallic) traces, and simultaneously optimizing the interconnections between a “standard” die inside an integrated circuit (IC) package and an interposer substrate of the IC package. | 11-20-2008 |
20090007049 | AUTOMATIC TRACE DESIGN METHOD - An automatic trace design method comprises: a tentative passing point setting step of setting, on a virtual plane corresponding to a substrate surface, tentative passing points through which a trace subject to route determination should pass; a triangle setting step of setting triangles, each of which is formed by one of the tentative passing points and two points on either side of such tentative passing point among a starting point, an end point and the other of the tentative passing points; and a determination step of determining points in the neighborhood of respective obstacles that are located inside the respective triangles mentioned above and most adjacent to the respective tentative passing points as final passing points through which the trace subject to route determination should pass, wherein the route that passes through the final passing points is determined as the optimal route of the trace subject to route determination. | 01-01-2009 |
20090125860 | Auto-Routing Small Jog Eliminator - In a method of routing a wire to a shape in an integrated circuit for minimizing undesirable jog creation during a masking process, a plurality of possible placements of the wire relative to a selected edge of the shape resulting in the wire being connected to the shape are determined. A cost is assigned to each placement, the cost indicating an amount of jog that would be created in the masking process corresponding to the placement, wherein a greater cost indicates that a greater jog would be created in the masking process than would be created by a placement assigned a lesser cost. A placement having a lowest cost of the plurality of possible placements is selected. | 05-14-2009 |
20090125861 | Wiring design processing method and wiring design processing apparatus - A wiring design processing method is for designing an automatic wiring processing process as an execution sequence of various processing in automatic wiring processing for printed circuit boards by using a computer. The wiring design processing method includes storing, in a storage unit, printed circuit board information including various physical information regarding the printed circuit boards, for each of the printed circuit boards; creating an automatic wiring processing process automatically according to a result of analyzing setting, wiring progress, and wiring situation at present regarding each of the printed circuit boards, after reading the printed circuit board information, stored in the storage unit at the storing, for each of the printed circuit boards; and executing the automatic wiring processing according to the automatic wiring processing process created at the creating, for each of the printed circuit boards. | 05-14-2009 |
20090125862 | Wiring path information creating method and wiring path information creating apparatus - A wiring processing apparatus decides each group formed by sorting signals that flow between component pins. Then, the wiring processing apparatus reads printed circuit board data and identifies a net cluster that belongs to each group. After a net cluster that belongs to each group is identified, the wiring processing apparatus refers to the printed circuit board data about the identified net cluster, and automatically creates each wiring route that indicates a wiring scanning area of the signal cluster in each group. Thus the wiring processing apparatus displays them on the printed board data. After the wiring route is automatically created, the wiring processing apparatus automatically creates wiring route information that corresponds to each wiring route, and controls them according to each wiring route. | 05-14-2009 |
20090178017 | SYSTEM AND METHOD FOR I/O SYNTHESIS AND FOR ASSIGNING I/O TO PROGRAMMABLE DEVICES - A method for connecting a programmable device (PD) and an electronic component (EC) based on a protocol, including: obtaining a signal group of the protocol having a group constraint, a first pin definition including an electrical constraint and a logical constraint, and a second pin definition; mapping the first pin definition to a first pin of the PD based on the electrical constraint, the logical constraint, and the group constraint; identifying a first pin of the EC to connect with the first pin of the PD based on the electrical constraint, the logical constraint, the group constraint, and a connection preference; generating a first connection between the first pin of the EC and a second pin of the PD based on the electrical constraint, the logical constraint, the group constraint, and the connection preference; and storing the first connection in an edge list. | 07-09-2009 |
20090187874 | CIRCUIT AND CIRCUIT DESIGN METHOD - A circuit and a circuit design method are provided. The circuit operates between a first power source voltage and a ground voltage. The circuit comprises at least one low speed circuit path and at least one high speed circuit path. The low speed circuit path adjusts voltage level at the first power source voltage or the ground voltage. The low speed circuit path provides a first return path and isolates unwanted noise signals for a signal on the high speed circuit path. | 07-23-2009 |
20090199149 | METHODS AND APPARATUS FOR LAYOUT OF MULTI-LAYER CIRCUIT SUBSTRATES - Methods and apparatus are provided for designing and laying out multi-layer circuit substrates, such as multi-layer PCBs. Dynamic vias are proviuded on intermediate PCB layers. Each dynamic via has features that adjust based on the trace layout of the corresponding intermediate layer. In particular, each dynamic via has a second radius R | 08-06-2009 |
20090259984 | METHOD OF PRINTED CIRCUIT BOARDS - A design method of printed circuit boards includes the following steps. First, simulate a printed circuit board including power layers, and vias connected to all the power layers. Then, change connections of the vias that tend to draw too much current to be connected to fewer power layers, than the vias that tend to draw less current. Repeat adjusting connections of the vias until all vias draw a similar amount of current such that no via draws more current than an upper limit the vias are designed for. Finally, according to the results, design/fabricate a PCB with vias respectively insulated, as needed, from the power layers that do not need to be connected to the vias. | 10-15-2009 |
20100235804 | WIRING DESIGN APPARATUS AND METHOD - A wiring design apparatus for designing a plurality of wiring lines of a printed circuit board including a plurality of connection posts arranged in a matrix, includes a processor, the processor providing an orthogonal grid including a plurality of rows and columns running over and between the connection posts, providing a plurality of diagonal paths each connecting at least one of the rows with at least one of the columns each running between each of adjacent pairs of the connection posts, and determining a route for each of the wiring lines by exclusively allocating to each of the wiring lines a selected part of the rows, the columns and the paths so that the selected part connects both ends of each of the wiring lines. | 09-16-2010 |
20100251200 | VIA DESIGN APPARATUS AND VIA DESIGN METHOD - A via design apparatus for designing a via providing connections between a plurality of layers inside a multilayer board includes: a determination section that determines a value of a shape parameter indicating a shape of a via in the multilayer board, the via having a hole passing through the plurality of layers and a conductive section on a side wall of the hole; and a calculation section that calculates a value of impedance of the via according to the value of the shape parameter. | 09-30-2010 |