Class / Patent application number | Description | Number of patent applications / Date published |
716003000 | Translation (e.g., conversion, equivalence) | 37 |
20080222578 | SYSTEM AND METHOD FOR CIRCUIT DESIGN SCALING - A system and method for scaling a circuit design to a new technology includes designating a first set of components including design scaled elements having a designed scaling in two dimensions to render the first set of components inactive for scaling of a second set of components. The second set of components includes pitch-matched circuits. The second set of components is scaled. Then, the second set of components is designated to render the second set of components inactive for scaling of the first set of components. The first set of components is scaled in accordance with a plurality of scale factors including scaling the design scaled elements in accordance with reference scale factors and scaling other components in the first set of components in accordance with one of the reference scale factors. | 09-11-2008 |
20080256497 | Scan compression circuit and method of design therefor - A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap. | 10-16-2008 |
20080256498 | Method and apparatus for logic equivalence verification, and computer product - A verification apparatus that verifies whether a reference circuit and an implemented circuit are logically equivalent deletes, respectively therefrom, all buffers and an even number of inverters between flip-flops. On each of the circuits, the apparatus further deletes and merges a flip-flop to another flip-flop that is logically equivalent. The name of the deleted flip-flip is added to the name of the flip-flop to which it is merged. The apparatus compares all of the names of the flip-flops and pairs the flip-flops by name. From the input pin of each of the paired flip-flops, logic cones are defined and using these logic cones, comparison of and verification between the reference circuit and the implemented circuit is performed. | 10-16-2008 |
20080288900 | DETERMINATION OF SINGLE-FIX RECTIFICATION FUNCTION - Some aspects provide determination of a function to rectify functional differences between netlist G | 11-20-2008 |
20080295043 | Automatic Error Diagnosis and Correction for RTL Designs - A computer executable tool facilitates integrated circuit design and debugging by working directly at the Register Transfer Level, where most design activities take place. The tool determines when an integrated circuit design produces incorrect output responses for a given set of input vectors. The tool accesses the expected responses and returns the signal paths in the integrated circuit that are responsible for the errors along with suggested changes for fixing the errors. The tool may operate at the RTL, which is above the gate-level abstraction which means that the design errors will be much more readily understood to the designer, and may improve scalability and efficiency. | 11-27-2008 |
20080295044 | METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRCUIT LAYOUT - A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory. | 11-27-2008 |
20080313578 | Techniques For Use With Automated Circuit Design and Simulations - Various techniques involving snapshots of the contents of registers are described and claimed. In some embodiments, a method includes receiving descriptions of design circuitry including design registers to receive register input signals. The method also includes generating additional descriptions through at least one computer program including descriptions of additional registers (snapshot registers) to receive snapshots of the register input signals, wherein the additional registers provide register initial condition signals for use in a simulation of at least a portion of the design circuitry. Other embodiments are described. | 12-18-2008 |
20080313579 | Techniques For Use With Automated Circuit Design and Simulations - Various techniques related to clocking for use with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving descriptions of design circuitry including logic to receive input signals. The method further includes generating additional descriptions through at least one computer program including descriptions of a multiplexer to multiplex the input signals and delayed input signals, and provide them to the logic, and a demultiplexer to demultiplex output signals and delayed output signals from the logic. Other embodiments are described. | 12-18-2008 |
20080313580 | Methodology for Hierarchy Separation at Asynchronous Clock Domain Boundaries for Multi-Voltage Optimization Using Design Compiler - This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and isolation cell insertion. The level shifter and isolation cell inserted are tested for proper location. The transformed circuit design is suitable for power consumption control by independent control of separate voltage domains. | 12-18-2008 |
20090044157 | Acyclic Modeling of Combinational Loops - Aspects of the present invention are directed to converting non-oscillatory combinational loops into acyclic circuits. Combinational loops may be modeled as state-holding elements where non-oscillatory loops are broken using edge-sensitive latches. In addition to providing a way to model combinational loops originally consisting only of gates (i.e., without originally including any state-holding elements), loops that have paths through user latches may also be converted. The presented methodology may be used with both small and large loops. | 02-12-2009 |
20090049415 | METHOD AND SOFTWARE TOOL FOR AUTOMATIC GENERATION OF SOFTWARE FOR INTEGRATED CIRCUIT - A method of generating software code for a processor of an IC based on a simple input description of the IC's standards. The method includes generating a macros description of each of the primitives from the standards and the response corresponding to each of the primitives, wherein the macros description includes information relating to a number of first fields for each of the primitives and a number of second fields for each response. The method further includes generating a blank version of a template that includes each of the second fields and receiving a completed version of the template, wherein the completed template specifies a behavior of the integrated circuit in response to the primitives. Finally, the method includes compiling the software code based on the macros description and the completed version of the template. Also, a software tool implementing the method is provided. | 02-19-2009 |
20090055781 | Circuit design device, circuit design program, and circuit design method - A circuit design device according to an embodiment of the present invention includes a processor performing operations of: extracting flip-flops each receiving a first clock and a control signal, from flip-flops represented in a first hardware description representing a circuit; generating a second hardware description by replacing the first clock received by each of the extracted flip-flops with a second clock; and generating a third hardware description by inserting, into the second hardware description, data of a control circuit to stop supply of the second clock based on the first clock and the control signal. | 02-26-2009 |
20090083680 | MODEL-BUILDING OPTIMIZATION - A method and system for performing multi-objective optimization of a multi-parameter design having several variables and performance metrics. The optimization objectives include the performance values of surrogate models of the performance metrics and the uncertainty in the surrogate models. The uncertainty is always maximized while the performance metrics can be maximized or minimized in accordance with the definitions of the respective performance metrics. Alternatively, one of the optimization objectives can be the value of a user-defined cost function of the multi-parameter design, the cost function depending from the performance metrics and/or the variables. In this case, the other objective is the uncertainty of the cost function, which is maximized. The multi-parameter designs include electrical circuit designs such as analog, mixed-signal, and custom digital circuits. | 03-26-2009 |
20090094566 | DESIGN STRUCTURE FOR CHIP IDENTIFICATION SYSTEM - Disclosed is a design structure for an on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key. | 04-09-2009 |
20090119622 | Variability-Aware Asynchronous Scheme Based on Two-Phase Protocols - A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained. | 05-07-2009 |
20090178015 | METHOD AND SYSTEM FOR REDUCING TURN AROUND TIME OF COMPLICATED ENGINEERING CHANGE ORDERS AND ASIC DESIGN REUTILIZATION - Reducing turn around time of engineering change orders in ASIC re-spin design includes finding, on the fly, all corresponding boundary points of storage gate elements indicated by engineering change orders to be either added, deleted or renamed. Boolean equivalence tools are used between an old spin ASIC design and a new ASIC design netlist, as well as between the new ASIC design netlist and a new re-spin ASIC design to obtain failing boundary storage gate elements and perform one or more of adding, deleting or modifying or renaming all failing boundary storage gate elements, so they pass correspondence tests. Engineering change order scripts are automatically generated to indicate which storage logic gate elements are to be added, deleted or modified and the scripts are applied to the old ASIC design to obtain the new re-spin ASIC design, after which ASIC flow gate level fixes are applied to synthesized storage gate elements. | 07-09-2009 |
20090241074 | EQUIVALENCE CHECKING METHOD, EQUIVALENCE CHECKING PROGRAM, AND GENERATING METHOD FOR EQUIVALENCE CHECKING PROGRAM - To provide a checking method that utilizes a test bench for a circuit model, which will serve as a fundamental for equivalence checking of a circuit to be newly developed for the fundamental circuit model. In order to check the equivalence of a model to be verified using a sample model a circuit of which has been described in a predetermined language and a test vector generation model for the sample model, a process for writing an output from the sample model test vector generation model into an input FIFO group for each signal of the sample model with the same timing as that of the sample model while the sample model is inputting/outputting a signal from/to the sample model test vector generation model with cycle accuracy and a process for reading data from the input FIFO group with the same operation timing as that of the model to be verified and outputting the data to the model to be verified are carried out. The output of the sample model and the output of the model to be verified are written into an output FIFO pair group for each corresponding signal name and coincidence judgment is carried out for a pair output for each written signal name. | 09-24-2009 |
20090249264 | ANALYZING DEVICE FOR CIRCUIT DEVICE, CIRCUIT DEVICE ANALYZING METHOD, ANALYZING PROGRAM, AND ELECTRONIC MEDIUM - A circuit board analyzing method and a circuit board analyzer are provided which can greatly reduce analyzing time. The circuit board analyzer includes a computing unit | 10-01-2009 |
20090271748 | METHOD AND APPARATUS FOR SIMULATING BEHAVIORAL CONSTRUCTS USING INDETERMINATE VALUES - One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different portions of code based on the value of a control expression, or it may store data in different storage locations based on the value of an index expression, etc. In response to determining that the expression's value is indeterminate, the system can execute two or more alternatives that are controlled by the expression, and then merge the results in some prescribed way. An embodiment of the present invention can enable a user to reduce the discrepancy between the results generated by a register transfer level simulation and the results generated by the associated gate level simulation. | 10-29-2009 |
20090288045 | Design-For-Test-Aware Hierarchical Design Planning - Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. The modified cost function can take into account penalty parameters. The penalty parameters can include at least one of: membership in a plan group or a top-level physical hierarchy, size of a plan group, FLOATING/ORDERED scan element in scan data, location of endpoints of an ORDERED list, location of endpoints of a macro, and membership in a plan group containing a STOP point. Scan data, at the block-level and at the top-level, can be automatically updated to reflect the plan groups and optimized scan chains. | 11-19-2009 |
20090319961 | Method of Verification of Address Translation Mechanisms - Device, system and method of verification of address translation mechanisms. For example, an apparatus for testing an address translation mechanism of a design-under-test, the apparatus including: a test generator to receive a specification of at least one address translation table, and to generate one or more constraint-satisfaction-problem projectors over a plurality of attributes of said address translation table. | 12-24-2009 |
20090319962 | AUTOMATED CONVERSION OF SYNCHRONOUS TO ASYNCHRONOUS CIRCUIT DESIGN REPRESENTATIONS - Methods and systems for performing automated conversion of synchronous circuit design to asynchronous circuit design representations are described. A synchronous netlist may be generated from a synchronous circuit design. The synchronous netlist may include combinational logic gates and state-holding elements. The synchronous netlist may be converted to an asynchronous circuit design. The converting may include grouping the combinational logic gates by operations into functions. | 12-24-2009 |
20100005430 | DDCC and FDCCII-Grounded Resistor and Capacitor Filter Structures - A voltage-mode nth-order differential difference current conveyor (DDCC) and fully differential current conveyor (FDCCII)-resistor and capacitor filter structures are proposed using a new effective analytical synthesis method (ASM), a succession of innovative algebra operations until a set of simple equations are produced, which are then realized using n integrators and a constraint sub-circuitry, A new ASM can effectively carry out (i) use of all the grounded capacitors and grounded resistors, and (ii) employment of the minimum number of active and passive components and then enjoys the low sensitivities, lower parasitics, power consumption, noise, and smaller chip area leading to simultaneously achieving two important features: (i) higher output performance and (ii) lower cost, without tradeoff. Moreover, the component value variations of all the relative sensitivities have the same incremental percentage or decrement. | 01-07-2010 |
20100005431 | CONVERTING A SYNCHRONOUS CIRCUIT DESIGN INTO AN ASYNCHRONOUS DESIGN - Methods and systems for converting synchronous circuit designs to asynchronous circuit designs are described. A method may include converting a synchronous circuit design to an asynchronous dataflow design. Functional characteristics of the synchronous circuit design may be determined. The synchronous circuit design may include multiple synchronous logic blocks and a number of connection boxes. Each synchronous logic block may be converted, based on functional characteristics, to corresponding asynchronous dataflow logic blocks. The corresponding asynchronous dataflow logic blocks may provide corresponding asynchronous dataflow logic functions that may use protocol signals. Each connection box, based on the functional characteristics, may be converted to programmable switch points and programmable switches. | 01-07-2010 |
20100017761 | DATA CONVERSION APPARATUS, DATA CONVERSION METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM - A data conversion apparatus for converting circuit description related to a dynamically-reconfigurable circuit to circuit configuration information, the data conversion apparatus includes a first generation section that generates a data flow graph from the circuit description; a segment count determining section that determines a number of segments for segmenting the data flow graph generated by the first generation section; a virtual circuit creating section that creates a virtual circuit that has as many resources of the dynamically-reconfigurable circuit as the number of the resources multiplied by the number of segments determined by the segment count determining section; a second generation section that generates, from the circuit description, a data flow graph corresponding to the virtual circuit created by the virtual circuit creating section; and a conversion section that allocates and adjusts the resources of the virtual circuit in accordance with the data flow graph. | 01-21-2010 |
20100131906 | Design Method for Transmission Lines Using Meta-Materials - High frequency circuits for wireless, digital and microwave applications place requirements upon the impedance of their signal lines, interconnects and packaging. In designing and implementing the substrates for these signal lines it is beneficial to employ meta-materials to provide the desired impedance. Such meta-materials providing a means to provide modified permittivity and permeability for the substrate, these being different than the real permittivity and permeability of the insulator used. In an example embodiment, a substrate is configured as a meta-material. It is desirable therefore to have a means to model these meta-material aspects of the signal lines rapidly and accurately allowing the circuits, interconnects and packages to be designed and implemented without expensive and exhaustive iterative experimental characterization. Within the cited invention design parameters for the meta-material structure are determined in dependence upon input parameters characterising the conductive medium, dielectric medium enveloping the conductive material, and the pre-determined shapes of the conductive medium. | 05-27-2010 |
20100162188 | METHOD AND SYSTEM PERFORMING BLOCK-LEVEL RC EXTRACTION - A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as thickness and topography. | 06-24-2010 |
20100162189 | SYSTEM AND METHOD FOR SYNTHESIS REUSE - A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints. | 06-24-2010 |
20100169848 | Method of Migrating Electronic Devices Operating in Current Mode to a Target Technology - A novel and useful method of migrating an analog or mixed signal electronic circuit from a source technology to a target technology. Devices operating in current mode and their respective voltage tuning nodes are first identified in the source technology electronic circuit. Since a device operating in current mode is less sensitive to the voltage applied to its voltage tuning node, the voltage at the voltage tuning node can be changed to achieve better current mode device performance without interfering with the biasing conditions of other devices in the circuit. This enables a circuit designer to fully exploit the two available degrees of freedom (typically width and length) when migrating the electronic device operating in current mode from a source technology to a target technology. | 07-01-2010 |
20100199236 | METHOD AND APPARATUS FOR PERFORMING RLC MODELING AND EXTRACTION FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT (3D-IC) DESIGNS - One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file. The system then combines the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description. | 08-05-2010 |
20100199237 | TRANSFORMING VARIABLE DOMAINS FOR LINEAR CIRCUIT ANALYSIS - Embodiments in the present disclosure pertain to domain translators. A domain translator converts a variable from one domain to a different domain. Domains include, but are not limited to, voltage, current, frequency, phase, delay, and duty-cycle. In particular, domain translators enable conversion between standard voltage and current domains commonly used by circuit simulators to other domains such as frequency, phase, delay, duty-cycle, etc., so that linear analysis can be performed on a wide range of circuits that exhibit linear behavior in domains other than voltage and current. | 08-05-2010 |
20100205570 | Method For Reading Polygon Data Into An Integrated Circuit Router - An approach is provided for converting a polygon described as an ordered list of perimeter points into a set of connected quadrilaterals suitable for use in an advanced integrated circuit router. Edges are constructed between the points of the polygon. Then, one or more edges are selected as starting locations. Pairs of edges or portions of pairs of edges are matched to form sequences of quadrilaterals. Methods are provided to determine when edges should be split or skipped to ensure that all quadrilaterals are convex or meet other criteria. Other methods are provided to determine when the matching process should be terminated and restarted at another location. Finally, the sequences of quadrilaterals are joined together to form a data structure suitable for use within an integrated circuit router. | 08-12-2010 |
20100205571 | SYNCHRONOUS TO ASYNCHRONOUS LOGIC CONVERSION - Apparatus, systems, and methods may operate to generate a synchronous netlist from a synchronous circuit design representation, automatically substitute asynchronous components taken from an asynchronous standard cell component library for corresponding standard cell synchronous components in the synchronous netlist to form an asynchronous core, and convert the synchronous netlist to an asynchronous circuit design representation. Additional apparatus, systems, and methods are disclosed. | 08-12-2010 |
20100218145 | Multilayer finite difference methods for electrical modeling of packages and printed circuit boards - Disclosed are exemplary finite difference methods for electromagnetically simulating planar multilayer structures. The exemplary finite difference methods simulate multilayer planes by combining the admittance matrices of single plane pairs and equivalent circuit models for such single plane pairs based on multilayer finite difference approximation. Based on the methods, coupling between different layers through electrically large apertures can be modeled very accurately and efficiently. | 08-26-2010 |
20100275169 | ADAPTIVE STATE-TO-SYMBOLIC TRANSFORMATION IN A CANONICAL REPRESENTATION - Some embodiments provide a system for adaptively performing state-to-symbolic transformation in a canonical representation which is used for generating random stimulus for a constrained-random simulation. The system can construct a canonical representation for a set of constraints using the set of random variables and the subset of the state variables in the constraints. Next, the system can use the canonical representation to generate random stimulus for the constrained-random simulation, and monitor parameters associated with the constrained-random simulation. Next, the system can add state variables to or remove state variables from the canonical representation based at least on the monitored parameters. The system can then use the modified canonical representation which has a different set of state variables to generate random stimulus for the constrained-random simulation. | 10-28-2010 |
20100275170 | Porting Analog Circuit Designs - A computer-based method of converting an analog integrated circuit design from a source technology to a target technology, by providing a computer readable source schematic file and a computer readable source layout file for the analog integrated circuit design in the source technology, providing a computer readable technology transfer file that includes conversion tables between properties of the source technology and properties of the target technology, converting the source schematic file in the source technology to a target schematic file in the target technology with the computer using the technology transfer file, and converting the source layout file in the source technology to a target layout file in the target technology with the computer using the technology transfer file. | 10-28-2010 |
20100293513 | Method and System for Design Simplification Through Implication-Based Analysis - Methods and systems are provided for reducing an original circuit design into a simplified circuit design by merging gates that may not be equivalent but can be demonstrated to preserve target assertability with respect to the original circuitry design. A composite netlist is created from the simplified netlist and the original netlist. The composite netlist includes a number of targets that imply the existence of a target in the simplified netlist and a corresponding target in the original netlist. The implications are verified and then validated to ensure the simplied circuit design is a suitable replacement for the original circuit design. | 11-18-2010 |